xref: /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td (revision ba3c1f5972d7b90feb6e6da47905ff2757e0fe57) 
1//===-- RISCVInstrInfoXVentana.td --------------------------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the vendor extensions defined by Ventana Micro Systems.
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14// XVentanaCondOps
15//===----------------------------------------------------------------------===//
16
17let Predicates = [IsRV64, HasVendorXVentanaCondOps], hasSideEffects = 0,
18  mayLoad = 0, mayStore = 0, isCodeGenOnly = 0, DecoderNamespace = "Ventana" in
19class VTMaskedMove<bits<3> funct3, string opcodestr>
20    : RVInstR<0b0000000, funct3, OPC_CUSTOM_3, (outs GPR:$rd),
21              (ins GPR:$rs1, GPR:$rs2), opcodestr,
22              "$rd, $rs1, $rs2"> {
23}
24
25def VT_MASKC : VTMaskedMove<0b110, "vt.maskc">,
26           Sched<[WriteIALU, ReadIALU, ReadIALU]>;
27
28def VT_MASKCN : VTMaskedMove<0b111, "vt.maskcn">,
29           Sched<[WriteIALU, ReadIALU, ReadIALU]>;
30
31let Predicates = [IsRV64, HasVendorXVentanaCondOps] in {
32// Directly use MASKC/MASKCN in case of any of the operands being 0.
33def : Pat<(select GPR:$rc, GPR:$rs1, (i64 0)),
34          (VT_MASKC $rs1, $rc)>;
35def : Pat<(select GPR:$rc, (i64 0), GPR:$rs1),
36          (VT_MASKCN $rs1, $rc)>;
37
38def : Pat<(select (i64 (setne GPR:$rc, (i64 0))), GPR:$rs1, (i64 0)),
39          (VT_MASKC GPR:$rs1, GPR:$rc)>;
40def : Pat<(select (i64 (seteq GPR:$rc, (i64 0))), GPR:$rs1, (i64 0)),
41          (VT_MASKCN GPR:$rs1, GPR:$rc)>;
42def : Pat<(select (i64 (setne GPR:$rc, (i64 0))), (i64 0), GPR:$rs1),
43          (VT_MASKCN GPR:$rs1, GPR:$rc)>;
44def : Pat<(select (i64 (seteq GPR:$rc, (i64 0))), (i64 0), GPR:$rs1),
45          (VT_MASKC GPR:$rs1, GPR:$rc)>;
46
47def : Pat<(select (i64 (setne GPR:$x, simm12_plus1:$y)), GPR:$rs1, (i64 0)),
48          (VT_MASKC GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)))>;
49def : Pat<(select (i64 (seteq GPR:$x, simm12_plus1:$y)), GPR:$rs1, (i64 0)),
50          (VT_MASKCN GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)))>;
51def : Pat<(select (i64 (setne GPR:$x, simm12_plus1:$y)), (i64 0), GPR:$rs1),
52          (VT_MASKCN GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)))>;
53def : Pat<(select (i64 (seteq GPR:$x, simm12_plus1:$y)), (i64 0), GPR:$rs1),
54          (VT_MASKC GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)))>;
55
56def : Pat<(select (i64 (setne GPR:$x, (i64 -2048))), GPR:$rs1, (i64 0)),
57          (VT_MASKC GPR:$rs1, (XORI GPR:$x, -2048))>;
58def : Pat<(select (i64 (seteq GPR:$x, (i64 -2048))), GPR:$rs1, (i64 0)),
59          (VT_MASKCN GPR:$rs1, (XORI GPR:$x, -2048))>;
60def : Pat<(select (i64 (setne GPR:$x, (i64 -2048))), (i64 0), GPR:$rs1),
61          (VT_MASKCN GPR:$rs1, (XORI GPR:$x, -2048))>;
62def : Pat<(select (i64 (seteq GPR:$x, (i64 -2048))), (i64 0), GPR:$rs1),
63          (VT_MASKC GPR:$rs1, (XORI GPR:$x, -2048))>;
64
65def : Pat<(select (i64 (setne GPR:$x, GPR:$y)), GPR:$rs1, (i64 0)),
66          (VT_MASKC GPR:$rs1, (XOR GPR:$x, GPR:$y))>;
67def : Pat<(select (i64 (seteq GPR:$x, GPR:$y)), GPR:$rs1, (i64 0)),
68          (VT_MASKCN GPR:$rs1, (XOR GPR:$x, GPR:$y))>;
69def : Pat<(select (i64 (setne GPR:$x, GPR:$y)), (i64 0), GPR:$rs1),
70          (VT_MASKCN GPR:$rs1, (XOR GPR:$x, GPR:$y))>;
71def : Pat<(select (i64 (seteq GPR:$x, GPR:$y)), (i64 0), GPR:$rs1),
72          (VT_MASKC GPR:$rs1, (XOR GPR:$x, GPR:$y))>;
73
74// Conditional AND operation patterns.
75def : Pat<(i64 (select GPR:$rc, (and GPR:$rs1, GPR:$rs2), GPR:$rs1)),
76          (OR (AND $rs1, $rs2), (VT_MASKCN $rs1, $rc))>;
77def : Pat<(i64 (select GPR:$rc, GPR:$rs1, (and GPR:$rs1, GPR:$rs2))),
78          (OR (AND $rs1, $rs2), (VT_MASKC $rs1, $rc))>;
79
80// Basic select pattern that selects between 2 registers.
81def : Pat<(i64 (select GPR:$rc, GPR:$rs1, GPR:$rs2)),
82          (OR (VT_MASKC $rs1, $rc), (VT_MASKCN $rs2, $rc))>;
83
84def : Pat<(i64 (select (i64 (setne GPR:$rc, (i64 0))), GPR:$rs1, GPR:$rs2)),
85          (OR (VT_MASKC GPR:$rs1, GPR:$rc), (VT_MASKCN GPR:$rs2, GPR:$rc))>;
86def : Pat<(i64 (select (i64 (seteq GPR:$rc, (i64 0))), GPR:$rs2, GPR:$rs1)),
87          (OR (VT_MASKC GPR:$rs1, GPR:$rc), (VT_MASKCN GPR:$rs2, GPR:$rc))>;
88
89def : Pat<(i64 (select (i64 (setne GPR:$x, simm12_plus1:$y)), GPR:$rs1, GPR:$rs2)),
90          (OR (VT_MASKC GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y))),
91              (VT_MASKCN GPR:$rs2, (ADDI GPR:$x, (NegImm simm12_plus1:$y))))>;
92def : Pat<(i64 (select (i64 (seteq GPR:$x, simm12_plus1:$y)), GPR:$rs2, GPR:$rs1)),
93          (OR (VT_MASKC GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y))),
94              (VT_MASKCN GPR:$rs2, (ADDI GPR:$x, (NegImm simm12_plus1:$y))))>;
95
96def : Pat<(i64 (select (i64 (setne GPR:$x, (i64 -2048))), GPR:$rs1, GPR:$rs2)),
97          (OR (VT_MASKC GPR:$rs1, (XORI GPR:$x, -2048)),
98              (VT_MASKCN GPR:$rs2, (XORI GPR:$x, -2048)))>;
99def : Pat<(i64 (select (i64 (seteq GPR:$x, (i64 -2048))), GPR:$rs2, GPR:$rs1)),
100          (OR (VT_MASKC GPR:$rs1, (XORI GPR:$x, -2048)),
101              (VT_MASKCN GPR:$rs2, (XORI GPR:$x, -2048)))>;
102
103def : Pat<(i64 (select (i64 (setne GPR:$x, GPR:$y)), GPR:$rs1, GPR:$rs2)),
104          (OR (VT_MASKC GPR:$rs1, (XOR GPR:$x, GPR:$y)),
105              (VT_MASKCN GPR:$rs2, (XOR GPR:$x, GPR:$y)))>;
106def : Pat<(i64 (select (i64 (seteq GPR:$x, GPR:$y)), GPR:$rs2, GPR:$rs1)),
107          (OR (VT_MASKC GPR:$rs1, (XOR GPR:$x, GPR:$y)),
108              (VT_MASKCN GPR:$rs2, (XOR GPR:$x, GPR:$y)))>;
109
110} // Predicates = [IsRV64, HasVendorXVentanaCondOps]
111