1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the PPC specific subclass of TargetSubtargetInfo. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "PPCSubtarget.h" 14 #include "GISel/PPCCallLowering.h" 15 #include "GISel/PPCLegalizerInfo.h" 16 #include "GISel/PPCRegisterBankInfo.h" 17 #include "PPC.h" 18 #include "PPCRegisterInfo.h" 19 #include "PPCTargetMachine.h" 20 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" 21 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" 22 #include "llvm/CodeGen/MachineFunction.h" 23 #include "llvm/CodeGen/MachineScheduler.h" 24 #include "llvm/IR/Attributes.h" 25 #include "llvm/IR/Function.h" 26 #include "llvm/IR/GlobalValue.h" 27 #include "llvm/MC/TargetRegistry.h" 28 #include "llvm/Support/CommandLine.h" 29 #include "llvm/Target/TargetMachine.h" 30 #include <cstdlib> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "ppc-subtarget" 35 36 #define GET_SUBTARGETINFO_TARGET_DESC 37 #define GET_SUBTARGETINFO_CTOR 38 #include "PPCGenSubtargetInfo.inc" 39 40 static cl::opt<bool> 41 UseSubRegLiveness("ppc-track-subreg-liveness", 42 cl::desc("Enable subregister liveness tracking for PPC"), 43 cl::init(true), cl::Hidden); 44 45 static cl::opt<bool> 46 EnableMachinePipeliner("ppc-enable-pipeliner", 47 cl::desc("Enable Machine Pipeliner for PPC"), 48 cl::init(false), cl::Hidden); 49 50 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU, 51 StringRef TuneCPU, 52 StringRef FS) { 53 initializeEnvironment(); 54 initSubtargetFeatures(CPU, TuneCPU, FS); 55 return *this; 56 } 57 58 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU, 59 const std::string &TuneCPU, const std::string &FS, 60 const PPCTargetMachine &TM) 61 : PPCGenSubtargetInfo(TT, CPU, TuneCPU, FS), TargetTriple(TT), 62 IsPPC64(TargetTriple.getArch() == Triple::ppc64 || 63 TargetTriple.getArch() == Triple::ppc64le), 64 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, TuneCPU, FS)), 65 InstrInfo(*this), TLInfo(TM, *this) { 66 CallLoweringInfo.reset(new PPCCallLowering(*getTargetLowering())); 67 Legalizer.reset(new PPCLegalizerInfo(*this)); 68 auto *RBI = new PPCRegisterBankInfo(*getRegisterInfo()); 69 RegBankInfo.reset(RBI); 70 71 InstSelector.reset(createPPCInstructionSelector( 72 *static_cast<const PPCTargetMachine *>(&TM), *this, *RBI)); 73 } 74 75 void PPCSubtarget::initializeEnvironment() { 76 StackAlignment = Align(16); 77 CPUDirective = PPC::DIR_NONE; 78 HasPOPCNTD = POPCNTD_Unavailable; 79 } 80 81 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU, 82 StringRef FS) { 83 // Determine default and user specified characteristics 84 std::string CPUName = std::string(CPU); 85 if (CPUName.empty() || CPU == "generic") { 86 // If cross-compiling with -march=ppc64le without -mcpu 87 if (TargetTriple.getArch() == Triple::ppc64le) 88 CPUName = "ppc64le"; 89 else if (TargetTriple.getSubArch() == Triple::PPCSubArch_spe) 90 CPUName = "e500"; 91 else 92 CPUName = "generic"; 93 } 94 95 // Determine the CPU to schedule for. 96 if (TuneCPU.empty()) TuneCPU = CPUName; 97 98 // Initialize scheduling itinerary for the specified CPU. 99 InstrItins = getInstrItineraryForCPU(CPUName); 100 101 // Parse features string. 102 ParseSubtargetFeatures(CPUName, TuneCPU, FS); 103 104 // If the user requested use of 64-bit regs, but the cpu selected doesn't 105 // support it, ignore. 106 if (IsPPC64 && has64BitSupport()) 107 Use64BitRegs = true; 108 109 if ((TargetTriple.isOSFreeBSD() && TargetTriple.getOSMajorVersion() >= 13) || 110 TargetTriple.isOSNetBSD() || TargetTriple.isOSOpenBSD() || 111 TargetTriple.isMusl()) 112 IsSecurePlt = true; 113 114 if (HasSPE && IsPPC64) 115 report_fatal_error( "SPE is only supported for 32-bit targets.\n", false); 116 if (HasSPE && (HasAltivec || HasVSX || HasFPU)) 117 report_fatal_error( 118 "SPE and traditional floating point cannot both be enabled.\n", false); 119 120 // If not SPE, set standard FPU 121 if (!HasSPE) 122 HasFPU = true; 123 124 StackAlignment = getPlatformStackAlignment(); 125 126 // Determine endianness. 127 IsLittleEndian = TM.isLittleEndian(); 128 } 129 130 bool PPCSubtarget::enableMachineScheduler() const { return true; } 131 132 bool PPCSubtarget::enableMachinePipeliner() const { 133 return getSchedModel().hasInstrSchedModel() && EnableMachinePipeliner; 134 } 135 136 bool PPCSubtarget::useDFAforSMS() const { return false; } 137 138 // This overrides the PostRAScheduler bit in the SchedModel for each CPU. 139 bool PPCSubtarget::enablePostRAScheduler() const { return true; } 140 141 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const { 142 return TargetSubtargetInfo::ANTIDEP_ALL; 143 } 144 145 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { 146 CriticalPathRCs.clear(); 147 CriticalPathRCs.push_back(isPPC64() ? 148 &PPC::G8RCRegClass : &PPC::GPRCRegClass); 149 } 150 151 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, 152 unsigned NumRegionInstrs) const { 153 // The GenericScheduler that we use defaults to scheduling bottom up only. 154 // We want to schedule from both the top and the bottom and so we set 155 // OnlyBottomUp to false. 156 // We want to do bi-directional scheduling since it provides a more balanced 157 // schedule leading to better performance. 158 Policy.OnlyBottomUp = false; 159 // Spilling is generally expensive on all PPC cores, so always enable 160 // register-pressure tracking. 161 Policy.ShouldTrackPressure = true; 162 } 163 164 bool PPCSubtarget::useAA() const { 165 return true; 166 } 167 168 bool PPCSubtarget::enableSubRegLiveness() const { 169 return UseSubRegLiveness; 170 } 171 172 bool PPCSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const { 173 // Large code model always uses the TOC even for local symbols. 174 if (TM.getCodeModel() == CodeModel::Large) 175 return true; 176 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) 177 return false; 178 return true; 179 } 180 181 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); } 182 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); } 183 184 bool PPCSubtarget::isUsingPCRelativeCalls() const { 185 return isPPC64() && hasPCRelativeMemops() && isELFv2ABI() && 186 CodeModel::Medium == getTargetMachine().getCodeModel(); 187 } 188 189 // GlobalISEL 190 const CallLowering *PPCSubtarget::getCallLowering() const { 191 return CallLoweringInfo.get(); 192 } 193 194 const RegisterBankInfo *PPCSubtarget::getRegBankInfo() const { 195 return RegBankInfo.get(); 196 } 197 198 const LegalizerInfo *PPCSubtarget::getLegalizerInfo() const { 199 return Legalizer.get(); 200 } 201 202 InstructionSelector *PPCSubtarget::getInstructionSelector() const { 203 return InstSelector.get(); 204 } 205