xref: /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/PPCScheduleP9.td (revision e17f5b1d307b7b8910d67883e57a9604305906d5)
1//===-- PPCScheduleP9.td - PPC P9 Scheduling Definitions ---*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the itinerary class data for the POWER9 processor.
10//
11//===----------------------------------------------------------------------===//
12include "PPCInstrInfo.td"
13
14def P9Model : SchedMachineModel {
15  // The maximum number of instructions to be issued at the same time.
16  // While a value of 8 is technically correct since 8 instructions can be
17  // fetched from the instruction cache. However, only 6 instructions may be
18  // actually dispatched at a time.
19  let IssueWidth = 8;
20
21  // Load latency is 4 or 5 cycles depending on the load. This latency assumes
22  // that we have a cache hit. For a cache miss the load latency will be more.
23  // There are two instructions (lxvl, lxvll) that have a latencty of 6 cycles.
24  // However it is not worth bumping this value up to 6 when the vast majority
25  // of instructions are 4 or 5 cycles.
26  let LoadLatency = 5;
27
28  // A total of 16 cycles to recover from a branch mispredict.
29  let MispredictPenalty = 16;
30
31  // Try to make sure we have at least 10 dispatch groups in a loop.
32  // A dispatch group is 6 instructions.
33  let LoopMicroOpBufferSize = 60;
34
35  // As iops are dispatched to a slice, they are held in an independent slice
36  // issue queue until all register sources and other dependencies have been
37  // resolved and they can be issued. Each of four execution slices has an
38  // 11-entry iop issue queue.
39  let MicroOpBufferSize = 44;
40
41  let CompleteModel = 1;
42
43  // Do not support QPX (Quad Processing eXtension) or SPE (Signal Procesing
44  // Engine) on Power 9.
45  let UnsupportedFeatures = [HasQPX, HasSPE];
46
47}
48
49let SchedModel = P9Model in {
50
51  // ***************** Processor Resources *****************
52
53  // Dispatcher slots:
54  // x0, x1, x2, and x3 are the dedicated slice dispatch ports, where each
55  // corresponds to one of the four execution slices.
56  def DISPx02 : ProcResource<2>;
57  def DISPx13 : ProcResource<2>;
58  // The xa and xb ports can be used to send an iop to either of the two slices
59  // of the superslice, but are restricted to iops with only two primary sources.
60  def DISPxab : ProcResource<2>;
61  // b0 and b1 are dedicated dispatch ports into the branch slice.
62  def DISPb01 : ProcResource<2>;
63
64  // Any non BR dispatch ports
65  def DISP_NBR
66      : ProcResGroup<[ DISPx02, DISPx13, DISPxab]>;
67  def DISP_SS : ProcResGroup<[ DISPx02, DISPx13]>;
68
69  // Issue Ports
70  // An instruction can go down one of two issue queues.
71  // Address Generation (AGEN) mainly for loads and stores.
72  // Execution (EXEC) for most other instructions.
73  // Some instructions cannot be run on just any issue queue and may require an
74  // Even or an Odd queue. The EXECE represents the even queues and the EXECO
75  // represents the odd queues.
76  def IP_AGEN : ProcResource<4>;
77  def IP_EXEC : ProcResource<4>;
78  def IP_EXECE : ProcResource<2> {
79    //Even Exec Ports
80    let Super = IP_EXEC;
81  }
82  def IP_EXECO : ProcResource<2> {
83    //Odd Exec Ports
84    let Super = IP_EXEC;
85  }
86
87  // Pipeline Groups
88  // Four ALU (Fixed Point Arithmetic) units in total. Two even, two Odd.
89  def ALU : ProcResource<4>;
90  def ALUE : ProcResource<2> {
91    //Even ALU pipelines
92    let Super = ALU;
93  }
94  def ALUO : ProcResource<2> {
95    //Odd ALU pipelines
96    let Super = ALU;
97  }
98
99  // Two DIV (Fixed Point Divide) units.
100  def DIV : ProcResource<2>;
101
102  // Four DP (Floating Point) units in total. Two even, two Odd.
103  def DP : ProcResource<4>;
104  def DPE : ProcResource<2> {
105    //Even DP pipelines
106    let Super = DP;
107  }
108  def DPO : ProcResource<2> {
109    //Odd DP pipelines
110    let Super = DP;
111  }
112
113  // Four LS (Load or Store) units.
114  def LS : ProcResource<4>;
115
116  // Two PM (Permute) units.
117  def PM : ProcResource<2>;
118
119  // Only one DFU (Decimal Floating Point and Quad Precision) unit.
120  def DFU : ProcResource<1>;
121
122  // Only one Branch unit.
123  def BR : ProcResource<1> {
124    let BufferSize = 16;
125  }
126
127  // Only one CY (Crypto) unit.
128  def CY : ProcResource<1>;
129
130  // ***************** SchedWriteRes Definitions *****************
131
132  // Dispatcher
133  // Dispatch Rules: '-' or 'V'
134  // Vector ('V') - vector iops (128-bit operand) take only one decode and
135  // dispatch slot but are dispatched to both the even and odd slices of a
136  // superslice.
137  def DISP_1C : SchedWriteRes<[DISP_NBR]> {
138    let NumMicroOps = 0;
139    let Latency = 1;
140  }
141  // Dispatch Rules: 'E'
142  // Even slice ('E')- certain operations must be sent only to an even slice.
143  // Also consumes odd dispatch slice slot of the same superslice at dispatch
144  def DISP_EVEN_1C : SchedWriteRes<[ DISPx02, DISPx13 ]> {
145    let NumMicroOps = 0;
146    let Latency = 1;
147  }
148  // Dispatch Rules: 'P'
149  // Paired ('P') - certain cracked and expanded iops are paired such that they
150  // must dispatch together to the same superslice.
151  def DISP_PAIR_1C : SchedWriteRes<[ DISP_SS, DISP_SS]> {
152    let NumMicroOps = 0;
153    let Latency = 1;
154  }
155  // Tuple Restricted ('R') - certain iops preclude dispatching more than one
156  // operation per slice for the super- slice to which they are dispatched
157  def DISP_3SLOTS_1C : SchedWriteRes<[DISPx02, DISPx13, DISPxab]> {
158    let NumMicroOps = 0;
159    let Latency = 1;
160  }
161  // Each execution and branch slice can receive up to two iops per cycle
162  def DISP_BR_1C : SchedWriteRes<[ DISPxab ]> {
163    let NumMicroOps = 0;
164    let Latency = 1;
165  }
166
167  // Issue Ports
168  def IP_AGEN_1C : SchedWriteRes<[IP_AGEN]> {
169    let NumMicroOps = 0;
170    let Latency = 1;
171  }
172
173  def IP_EXEC_1C : SchedWriteRes<[IP_EXEC]> {
174    let NumMicroOps = 0;
175    let Latency = 1;
176  }
177
178  def IP_EXECE_1C : SchedWriteRes<[IP_EXECE]> {
179    let NumMicroOps = 0;
180    let Latency = 1;
181  }
182
183  def IP_EXECO_1C : SchedWriteRes<[IP_EXECO]> {
184    let NumMicroOps = 0;
185    let Latency = 1;
186  }
187
188  //Pipeline Groups
189
190  // ALU Units
191  // An ALU may take either 2 or 3 cycles to complete the operation.
192  // However, the ALU unit is only ever busy for 1 cycle at a time and may
193  // receive new instructions each cycle.
194  def P9_ALU_2C : SchedWriteRes<[ALU]> {
195    let Latency = 2;
196  }
197
198  def P9_ALUE_2C : SchedWriteRes<[ALUE]> {
199    let Latency = 2;
200  }
201
202  def P9_ALUO_2C : SchedWriteRes<[ALUO]> {
203    let Latency = 2;
204  }
205
206  def P9_ALU_3C : SchedWriteRes<[ALU]> {
207    let Latency = 3;
208  }
209
210  def P9_ALUE_3C : SchedWriteRes<[ALUE]> {
211    let Latency = 3;
212  }
213
214  def P9_ALUO_3C : SchedWriteRes<[ALUO]> {
215    let Latency = 3;
216  }
217
218  // DIV Unit
219  // A DIV unit may take from 5 to 40 cycles to complete.
220  // Some DIV operations may keep the unit busy for up to 8 cycles.
221  def P9_DIV_5C : SchedWriteRes<[DIV]> {
222    let Latency = 5;
223  }
224
225  def P9_DIV_12C : SchedWriteRes<[DIV]> {
226    let Latency = 12;
227  }
228
229  def P9_DIV_16C_8 : SchedWriteRes<[DIV]> {
230    let ResourceCycles = [8];
231    let Latency = 16;
232  }
233
234  def P9_DIV_24C_8 : SchedWriteRes<[DIV]> {
235    let ResourceCycles = [8];
236    let Latency = 24;
237  }
238
239  def P9_DIV_40C_8 : SchedWriteRes<[DIV]> {
240    let ResourceCycles = [8];
241    let Latency = 40;
242  }
243
244  // DP Unit
245  // A DP unit may take from 2 to 36 cycles to complete.
246  // Some DP operations keep the unit busy for up to 10 cycles.
247  def P9_DP_5C : SchedWriteRes<[DP]> {
248    let Latency = 5;
249  }
250
251  def P9_DP_7C : SchedWriteRes<[DP]> {
252    let Latency = 7;
253  }
254
255  def P9_DPE_7C : SchedWriteRes<[DPE]> {
256    let Latency = 7;
257  }
258
259  def P9_DPO_7C : SchedWriteRes<[DPO]> {
260    let Latency = 7;
261  }
262
263  def P9_DP_22C_5 : SchedWriteRes<[DP]> {
264    let ResourceCycles = [5];
265    let Latency = 22;
266  }
267
268  def P9_DPO_24C_8 : SchedWriteRes<[DPO]> {
269    let ResourceCycles = [8];
270    let Latency = 24;
271  }
272
273  def P9_DPE_24C_8 : SchedWriteRes<[DPE]> {
274    let ResourceCycles = [8];
275    let Latency = 24;
276  }
277
278  def P9_DP_26C_5 : SchedWriteRes<[DP]> {
279    let ResourceCycles = [5];
280    let Latency = 22;
281  }
282
283  def P9_DPE_27C_10 : SchedWriteRes<[DP]> {
284    let ResourceCycles = [10];
285    let Latency = 27;
286  }
287
288  def P9_DPO_27C_10 : SchedWriteRes<[DP]> {
289    let ResourceCycles = [10];
290    let Latency = 27;
291  }
292
293  def P9_DP_33C_8 : SchedWriteRes<[DP]> {
294    let ResourceCycles = [8];
295    let Latency = 33;
296  }
297
298  def P9_DPE_33C_8 : SchedWriteRes<[DPE]> {
299    let ResourceCycles = [8];
300    let Latency = 33;
301  }
302
303  def P9_DPO_33C_8 : SchedWriteRes<[DPO]> {
304    let ResourceCycles = [8];
305    let Latency = 33;
306  }
307
308  def P9_DP_36C_10 : SchedWriteRes<[DP]> {
309    let ResourceCycles = [10];
310    let Latency = 36;
311  }
312
313  def P9_DPE_36C_10 : SchedWriteRes<[DP]> {
314    let ResourceCycles = [10];
315    let Latency = 36;
316  }
317
318  def P9_DPO_36C_10 : SchedWriteRes<[DP]> {
319    let ResourceCycles = [10];
320    let Latency = 36;
321  }
322
323  // PM Unit
324  // Three cycle permute operations.
325  def P9_PM_3C : SchedWriteRes<[PM]> {
326    let Latency = 3;
327  }
328
329  // Load and Store Units
330  // Loads can have 4, 5 or 6 cycles of latency.
331  // Stores are listed as having a single cycle of latency. This is not
332  // completely accurate since it takes more than 1 cycle to actually store
333  // the value. However, since the store does not produce a result it can be
334  // considered complete after one cycle.
335  def P9_LS_1C : SchedWriteRes<[LS]> {
336    let Latency = 1;
337  }
338
339  def P9_LS_4C : SchedWriteRes<[LS]> {
340    let Latency = 4;
341  }
342
343  def P9_LS_5C : SchedWriteRes<[LS]> {
344    let Latency = 5;
345  }
346
347  def P9_LS_6C : SchedWriteRes<[LS]> {
348    let Latency = 6;
349  }
350
351  // DFU Unit
352  // Some of the most expensive ops use the DFU.
353  // Can take from 12 cycles to 76 cycles to obtain a result.
354  // The unit may be busy for up to 62 cycles.
355  def P9_DFU_12C : SchedWriteRes<[DFU]> {
356    let Latency = 12;
357  }
358
359  def P9_DFU_23C : SchedWriteRes<[DFU]> {
360    let Latency = 23;
361    let ResourceCycles = [11];
362  }
363
364  def P9_DFU_24C : SchedWriteRes<[DFU]> {
365    let Latency = 24;
366    let ResourceCycles = [12];
367  }
368
369  def P9_DFU_37C : SchedWriteRes<[DFU]> {
370    let Latency = 37;
371    let ResourceCycles = [25];
372  }
373
374  def P9_DFU_58C : SchedWriteRes<[DFU]> {
375    let Latency = 58;
376    let ResourceCycles = [44];
377  }
378
379  def P9_DFU_76C : SchedWriteRes<[DFU]> {
380    let Latency = 76;
381    let ResourceCycles = [62];
382  }
383
384  // 2 or 5 cycle latencies for the branch unit.
385  def P9_BR_2C : SchedWriteRes<[BR]> {
386    let Latency = 2;
387  }
388
389  def P9_BR_5C : SchedWriteRes<[BR]> {
390    let Latency = 5;
391  }
392
393  // 6 cycle latency for the crypto unit
394  def P9_CY_6C : SchedWriteRes<[CY]> {
395    let Latency = 6;
396  }
397
398  // ***************** WriteSeq Definitions *****************
399
400  // These are combinations of the resources listed above.
401  // The idea is that some cracked instructions cannot be done in parallel and
402  // so the latencies for their resources must be added.
403  def P9_LoadAndALUOp_6C : WriteSequence<[P9_LS_4C, P9_ALU_2C]>;
404  def P9_LoadAndALUOp_7C : WriteSequence<[P9_LS_5C, P9_ALU_2C]>;
405  def P9_LoadAndALU2Op_7C : WriteSequence<[P9_LS_4C, P9_ALU_3C]>;
406  def P9_LoadAndALU2Op_8C : WriteSequence<[P9_LS_5C, P9_ALU_3C]>;
407  def P9_LoadAndPMOp_8C : WriteSequence<[P9_LS_5C, P9_PM_3C]>;
408  def P9_LoadAndLoadOp_8C : WriteSequence<[P9_LS_4C, P9_LS_4C]>;
409  def P9_IntDivAndALUOp_18C_8 : WriteSequence<[P9_DIV_16C_8, P9_ALU_2C]>;
410  def P9_IntDivAndALUOp_26C_8 : WriteSequence<[P9_DIV_24C_8, P9_ALU_2C]>;
411  def P9_IntDivAndALUOp_42C_8 : WriteSequence<[P9_DIV_40C_8, P9_ALU_2C]>;
412  def P9_StoreAndALUOp_3C : WriteSequence<[P9_LS_1C, P9_ALU_2C]>;
413  def P9_ALUOpAndALUOp_4C : WriteSequence<[P9_ALU_2C, P9_ALU_2C]>;
414  def P9_ALU2OpAndALU2Op_6C : WriteSequence<[P9_ALU_3C, P9_ALU_3C]>;
415  def P9_ALUOpAndALUOpAndALUOp_6C :
416    WriteSequence<[P9_ALU_2C, P9_ALU_2C, P9_ALU_2C]>;
417  def P9_DPOpAndALUOp_7C : WriteSequence<[P9_DP_5C, P9_ALU_2C]>;
418  def P9_DPOpAndALU2Op_10C : WriteSequence<[P9_DP_7C, P9_ALU_3C]>;
419  def P9_DPOpAndALU2Op_25C_5 : WriteSequence<[P9_DP_22C_5, P9_ALU_3C]>;
420  def P9_DPOpAndALU2Op_29C_5 : WriteSequence<[P9_DP_26C_5, P9_ALU_3C]>;
421  def P9_DPOpAndALU2Op_36C_8 : WriteSequence<[P9_DP_33C_8, P9_ALU_3C]>;
422  def P9_DPOpAndALU2Op_39C_10 : WriteSequence<[P9_DP_36C_10, P9_ALU_3C]>;
423  def P9_BROpAndALUOp_7C : WriteSequence<[P9_BR_5C, P9_ALU_2C]>;
424
425  // Include the resource requirements of individual instructions.
426  include "P9InstrResources.td"
427
428}
429
430