1//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the subset of the 32-bit PowerPC instruction set, as used 10// by the PowerPC instruction selector. 11// 12//===----------------------------------------------------------------------===// 13 14include "PPCInstrFormats.td" 15 16//===----------------------------------------------------------------------===// 17// PowerPC specific type constraints. 18// 19def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 20 SDTCisVT<0, f64>, SDTCisPtrTy<1> 21]>; 22def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x 23 SDTCisVT<0, f64>, SDTCisPtrTy<1> 24]>; 25def SDT_PPCLxsizx : SDTypeProfile<1, 2, [ 26 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 27]>; 28def SDT_PPCstxsix : SDTypeProfile<0, 3, [ 29 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 30]>; 31def SDT_PPCcv_fp_to_int : SDTypeProfile<1, 1, [ 32 SDTCisFP<0>, SDTCisFP<1> 33 ]>; 34def SDT_PPCstore_scal_int_from_vsr : SDTypeProfile<0, 3, [ 35 SDTCisFP<0>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 36]>; 37def SDT_PPCVexts : SDTypeProfile<1, 2, [ 38 SDTCisVT<0, f64>, SDTCisVT<1, f64>, SDTCisPtrTy<2> 39]>; 40 41def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, 42 SDTCisVT<1, i32> ]>; 43def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 44 SDTCisVT<1, i32> ]>; 45def SDT_PPCvperm : SDTypeProfile<1, 3, [ 46 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 47]>; 48 49def SDT_PPCVecSplat : SDTypeProfile<1, 2, [ SDTCisVec<0>, 50 SDTCisVec<1>, SDTCisInt<2> 51]>; 52 53def SDT_PPCSpToDp : SDTypeProfile<1, 1, [ SDTCisVT<0, v2f64>, 54 SDTCisInt<1> 55]>; 56 57def SDT_PPCVecShift : SDTypeProfile<1, 3, [ SDTCisVec<0>, 58 SDTCisVec<1>, SDTCisVec<2>, SDTCisPtrTy<3> 59]>; 60 61def SDT_PPCVecInsert : SDTypeProfile<1, 3, [ SDTCisVec<0>, 62 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3> 63]>; 64 65def SDT_PPCxxpermdi: SDTypeProfile<1, 3, [ SDTCisVec<0>, 66 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3> 67]>; 68 69def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 70 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 71]>; 72 73def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 74 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 75]>; 76 77def SDT_PPCFtsqrt : SDTypeProfile<1, 1, [ 78 SDTCisVT<0, i32>]>; 79 80def SDT_PPClbrx : SDTypeProfile<1, 2, [ 81 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 82]>; 83def SDT_PPCstbrx : SDTypeProfile<0, 3, [ 84 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 85]>; 86def SDT_StoreCond : SDTypeProfile<0, 3, [ 87 SDTCisPtrTy<0>, SDTCisInt<1>, SDTCisPtrTy<2> 88]>; 89 90def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ 91 SDTCisPtrTy<0>, SDTCisVT<1, i32> 92]>; 93 94def tocentry32 : Operand<iPTR> { 95 let MIOperandInfo = (ops i32imm:$imm); 96} 97 98def SDT_PPCqvfperm : SDTypeProfile<1, 3, [ 99 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3> 100]>; 101def SDT_PPCqvgpci : SDTypeProfile<1, 1, [ 102 SDTCisVec<0>, SDTCisInt<1> 103]>; 104def SDT_PPCqvaligni : SDTypeProfile<1, 3, [ 105 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3> 106]>; 107def SDT_PPCqvesplati : SDTypeProfile<1, 2, [ 108 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2> 109]>; 110 111def SDT_PPCqbflt : SDTypeProfile<1, 1, [ 112 SDTCisVec<0>, SDTCisVec<1> 113]>; 114 115def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [ 116 SDTCisVec<0>, SDTCisPtrTy<1> 117]>; 118 119def SDT_PPCextswsli : SDTypeProfile<1, 2, [ // extswsli 120 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisInt<2> 121]>; 122 123def SDT_PPCFPMinMax : SDTypeProfile<1, 2, [ 124 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 125]>; 126 127//===----------------------------------------------------------------------===// 128// PowerPC specific DAG Nodes. 129// 130 131def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>; 132def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>; 133def PPCfsqrt : SDNode<"PPCISD::FSQRT", SDTFPUnaryOp, []>; 134def PPCftsqrt : SDNode<"PPCISD::FTSQRT", SDT_PPCFtsqrt,[]>; 135 136def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>; 137def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>; 138def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>; 139def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>; 140def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 141def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 142def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>; 143def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>; 144 145def PPCstrict_fcfid : SDNode<"PPCISD::STRICT_FCFID", 146 SDTFPUnaryOp, [SDNPHasChain]>; 147def PPCstrict_fcfidu : SDNode<"PPCISD::STRICT_FCFIDU", 148 SDTFPUnaryOp, [SDNPHasChain]>; 149def PPCstrict_fcfids : SDNode<"PPCISD::STRICT_FCFIDS", 150 SDTFPRoundOp, [SDNPHasChain]>; 151def PPCstrict_fcfidus : SDNode<"PPCISD::STRICT_FCFIDUS", 152 SDTFPRoundOp, [SDNPHasChain]>; 153 154def PPCany_fcfid : PatFrags<(ops node:$op), 155 [(PPCfcfid node:$op), 156 (PPCstrict_fcfid node:$op)]>; 157def PPCany_fcfidu : PatFrags<(ops node:$op), 158 [(PPCfcfidu node:$op), 159 (PPCstrict_fcfidu node:$op)]>; 160def PPCany_fcfids : PatFrags<(ops node:$op), 161 [(PPCfcfids node:$op), 162 (PPCstrict_fcfids node:$op)]>; 163def PPCany_fcfidus : PatFrags<(ops node:$op), 164 [(PPCfcfidus node:$op), 165 (PPCstrict_fcfidus node:$op)]>; 166 167def PPCstore_scal_int_from_vsr: 168 SDNode<"PPCISD::ST_VSR_SCAL_INT", SDT_PPCstore_scal_int_from_vsr, 169 [SDNPHasChain, SDNPMayStore]>; 170def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, 171 [SDNPHasChain, SDNPMayStore]>; 172def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx, 173 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 174def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx, 175 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 176def PPClxsizx : SDNode<"PPCISD::LXSIZX", SDT_PPCLxsizx, 177 [SDNPHasChain, SDNPMayLoad]>; 178def PPCstxsix : SDNode<"PPCISD::STXSIX", SDT_PPCstxsix, 179 [SDNPHasChain, SDNPMayStore]>; 180def PPCVexts : SDNode<"PPCISD::VEXTS", SDT_PPCVexts, []>; 181 182// Extract FPSCR (not modeled at the DAG level). 183def PPCmffs : SDNode<"PPCISD::MFFS", 184 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, 185 [SDNPHasChain]>; 186 187// Perform FADD in round-to-zero mode. 188def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>; 189def PPCstrict_faddrtz: SDNode<"PPCISD::STRICT_FADDRTZ", SDTFPBinOp, 190 [SDNPHasChain]>; 191 192def PPCany_faddrtz: PatFrags<(ops node:$lhs, node:$rhs), 193 [(PPCfaddrtz node:$lhs, node:$rhs), 194 (PPCstrict_faddrtz node:$lhs, node:$rhs)]>; 195 196def PPCfsel : SDNode<"PPCISD::FSEL", 197 // Type constraint for fsel. 198 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 199 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 200def PPCxsmaxc : SDNode<"PPCISD::XSMAXC", SDT_PPCFPMinMax, []>; 201def PPCxsminc : SDNode<"PPCISD::XSMINC", SDT_PPCFPMinMax, []>; 202def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 203def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 204def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, 205 [SDNPMayLoad, SDNPMemOperand]>; 206 207def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>; 208 209def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>; 210def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp, 211 [SDNPMayLoad]>; 212def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>; 213def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>; 214def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>; 215def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>; 216def PPCgetTpointer : SDNode<"PPCISD::GET_TPOINTER", SDTIntLeaf, []>; 217def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR", 218 SDTypeProfile<1, 3, [ 219 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 220 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; 221def PPCTlsgdAIX : SDNode<"PPCISD::TLSGD_AIX", SDTIntBinOp>; 222def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>; 223def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>; 224def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>; 225def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR", 226 SDTypeProfile<1, 3, [ 227 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 228 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; 229def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>; 230def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>; 231def PPCpaddiDtprel : SDNode<"PPCISD::PADDI_DTPREL", SDTIntBinOp>; 232 233def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 234def PPCxxsplt : SDNode<"PPCISD::XXSPLT", SDT_PPCVecSplat, []>; 235def PPCxxspltidp : SDNode<"PPCISD::XXSPLTI_SP_TO_DP", SDT_PPCSpToDp, []>; 236def PPCvecinsert : SDNode<"PPCISD::VECINSERT", SDT_PPCVecInsert, []>; 237def PPCxxpermdi : SDNode<"PPCISD::XXPERMDI", SDT_PPCxxpermdi, []>; 238def PPCvecshl : SDNode<"PPCISD::VECSHL", SDT_PPCVecShift, []>; 239 240def PPCcmpb : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>; 241 242// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 243// amounts. These nodes are generated by the multi-precision shift code. 244def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; 245def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; 246def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; 247 248def PPCfnmsub : SDNode<"PPCISD::FNMSUB" , SDTFPTernaryOp>; 249 250def PPCextswsli : SDNode<"PPCISD::EXTSWSLI" , SDT_PPCextswsli>; 251 252def PPCstrict_fctidz : SDNode<"PPCISD::STRICT_FCTIDZ", 253 SDTFPUnaryOp, [SDNPHasChain]>; 254def PPCstrict_fctiwz : SDNode<"PPCISD::STRICT_FCTIWZ", 255 SDTFPUnaryOp, [SDNPHasChain]>; 256def PPCstrict_fctiduz : SDNode<"PPCISD::STRICT_FCTIDUZ", 257 SDTFPUnaryOp, [SDNPHasChain]>; 258def PPCstrict_fctiwuz : SDNode<"PPCISD::STRICT_FCTIWUZ", 259 SDTFPUnaryOp, [SDNPHasChain]>; 260 261def PPCany_fctidz : PatFrags<(ops node:$op), 262 [(PPCstrict_fctidz node:$op), 263 (PPCfctidz node:$op)]>; 264def PPCany_fctiwz : PatFrags<(ops node:$op), 265 [(PPCstrict_fctiwz node:$op), 266 (PPCfctiwz node:$op)]>; 267def PPCany_fctiduz : PatFrags<(ops node:$op), 268 [(PPCstrict_fctiduz node:$op), 269 (PPCfctiduz node:$op)]>; 270def PPCany_fctiwuz : PatFrags<(ops node:$op), 271 [(PPCstrict_fctiwuz node:$op), 272 (PPCfctiwuz node:$op)]>; 273 274// Move 2 i64 values into a VSX register 275def PPCbuild_fp128: SDNode<"PPCISD::BUILD_FP128", 276 SDTypeProfile<1, 2, 277 [SDTCisFP<0>, SDTCisSameSizeAs<1,2>, 278 SDTCisSameAs<1,2>]>, 279 []>; 280 281def PPCbuild_spe64: SDNode<"PPCISD::BUILD_SPE64", 282 SDTypeProfile<1, 2, 283 [SDTCisVT<0, f64>, SDTCisVT<1,i32>, 284 SDTCisVT<1,i32>]>, 285 []>; 286 287def PPCextract_spe : SDNode<"PPCISD::EXTRACT_SPE", 288 SDTypeProfile<1, 2, 289 [SDTCisVT<0, i32>, SDTCisVT<1, f64>, 290 SDTCisPtrTy<2>]>, 291 []>; 292 293// These are target-independent nodes, but have target-specific formats. 294def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, 295 [SDNPHasChain, SDNPOutGlue]>; 296def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, 297 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 298 299def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 300def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall, 301 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 302 SDNPVariadic]>; 303def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall, 304 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 305 SDNPVariadic]>; 306def PPCcall_notoc : SDNode<"PPCISD::CALL_NOTOC", SDT_PPCCall, 307 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 308 SDNPVariadic]>; 309def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 310 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 311def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone, 312 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 313 SDNPVariadic]>; 314def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC", 315 SDTypeProfile<0, 1, []>, 316 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 317 SDNPVariadic]>; 318 319// Call nodes for strictfp calls (that define RM). 320def PPCcall_rm : SDNode<"PPCISD::CALL_RM", SDT_PPCCall, 321 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 322 SDNPVariadic]>; 323def PPCcall_nop_rm : SDNode<"PPCISD::CALL_NOP_RM", SDT_PPCCall, 324 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 325 SDNPVariadic]>; 326def PPCcall_notoc_rm : SDNode<"PPCISD::CALL_NOTOC_RM", SDT_PPCCall, 327 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 328 SDNPVariadic]>; 329def PPCbctrl_rm : SDNode<"PPCISD::BCTRL_RM", SDTNone, 330 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 331 SDNPVariadic]>; 332def PPCbctrl_load_toc_rm : SDNode<"PPCISD::BCTRL_LOAD_TOC_RM", 333 SDTypeProfile<0, 1, []>, 334 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 335 SDNPVariadic]>; 336 337def retglue : SDNode<"PPCISD::RET_GLUE", SDTNone, 338 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 339 340def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, 341 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 342 343def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP", 344 SDTypeProfile<1, 1, [SDTCisInt<0>, 345 SDTCisPtrTy<1>]>, 346 [SDNPHasChain, SDNPSideEffect]>; 347def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP", 348 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 349 [SDNPHasChain, SDNPSideEffect]>; 350 351def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 352def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc, 353 [SDNPHasChain, SDNPSideEffect]>; 354 355def PPCclrbhrb : SDNode<"PPCISD::CLRBHRB", SDTNone, 356 [SDNPHasChain, SDNPSideEffect]>; 357def PPCmfbhrbe : SDNode<"PPCISD::MFBHRBE", SDTIntBinOp, [SDNPHasChain]>; 358def PPCrfebb : SDNode<"PPCISD::RFEBB", SDT_PPCsc, 359 [SDNPHasChain, SDNPSideEffect]>; 360 361def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 362def PPCvcmp_rec : SDNode<"PPCISD::VCMP_rec", SDT_PPCvcmp, [SDNPOutGlue]>; 363 364def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 365 [SDNPHasChain, SDNPOptInGlue]>; 366 367// PPC-specific atomic operations. 368def PPCatomicCmpSwap_8 : 369 SDNode<"PPCISD::ATOMIC_CMP_SWAP_8", SDTAtomic3, 370 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 371def PPCatomicCmpSwap_16 : 372 SDNode<"PPCISD::ATOMIC_CMP_SWAP_16", SDTAtomic3, 373 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 374def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, 375 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 376def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, 377 [SDNPHasChain, SDNPMayStore]>; 378def PPCStoreCond : SDNode<"PPCISD::STORE_COND", SDT_StoreCond, 379 [SDNPHasChain, SDNPMayStore, 380 SDNPMemOperand, SDNPOutGlue]>; 381 382// Instructions to set/unset CR bit 6 for SVR4 vararg calls 383def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone, 384 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 385def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone, 386 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 387 388// Instructions to support dynamic alloca. 389def SDTDynOp : SDTypeProfile<1, 2, []>; 390def SDTDynAreaOp : SDTypeProfile<1, 1, []>; 391def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 392def PPCdynareaoffset : SDNode<"PPCISD::DYNAREAOFFSET", SDTDynAreaOp, [SDNPHasChain]>; 393def PPCprobedalloca : SDNode<"PPCISD::PROBED_ALLOCA", SDTDynOp, [SDNPHasChain]>; 394 395// PC Relative Specific Nodes 396def PPCmatpcreladdr : SDNode<"PPCISD::MAT_PCREL_ADDR", SDTIntUnaryOp, []>; 397def PPCtlsdynamatpcreladdr : SDNode<"PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR", 398 SDTIntUnaryOp, []>; 399def PPCtlslocalexecmataddr : SDNode<"PPCISD::TLS_LOCAL_EXEC_MAT_ADDR", 400 SDTIntUnaryOp, []>; 401 402//===----------------------------------------------------------------------===// 403// PowerPC specific transformation functions and pattern fragments. 404// 405 406// A floating point immediate that is not a positive zero and can be converted 407// to a single precision floating point non-denormal immediate without loss of 408// information. 409def nzFPImmAsi32 : PatLeaf<(fpimm), [{ 410 APFloat APFloatOfN = N->getValueAPF(); 411 return convertToNonDenormSingle(APFloatOfN) && !N->isExactlyValue(+0.0); 412}]>; 413 414// A floating point immediate that is exactly an integer (for example 3.0, -5.0) 415// and can be represented in 5 bits (range of [-16, 15]). 416def nzFPImmExactInti5 : PatLeaf<(fpimm), [{ 417 APFloat FloatValue = N->getValueAPF(); 418 bool IsExact; 419 APSInt IntResult(16, false); 420 FloatValue.convertToInteger(IntResult, APFloat::rmTowardZero, &IsExact); 421 return IsExact && IntResult <= 15 && IntResult >= -16 && !FloatValue.isZero(); 422}]>; 423 424def getFPAs5BitExactInt : SDNodeXForm<fpimm, [{ 425 APFloat FloatValue = N->getValueAPF(); 426 bool IsExact; 427 APSInt IntResult(32, false); 428 FloatValue.convertToInteger(IntResult, APFloat::rmTowardZero, &IsExact); 429 return CurDAG->getTargetConstant(IntResult, SDLoc(N), MVT::i32); 430}]>; 431 432// Convert the floating point immediate into a 32 bit floating point immediate 433// and get a i32 with the resulting bits. 434def getFPAs32BitInt : SDNodeXForm<fpimm, [{ 435 APFloat APFloatOfN = N->getValueAPF(); 436 convertToNonDenormSingle(APFloatOfN); 437 return CurDAG->getTargetConstant(APFloatOfN.bitcastToAPInt().getZExtValue(), 438 SDLoc(N), MVT::i32); 439}]>; 440 441// Check if the value can be converted to be single precision immediate, which 442// can be exploited by XXSPLTIDP. Ensure that it cannot be converted to single 443// precision before exploiting with XXSPLTI32DX. 444def nzFPImmAsi64 : PatLeaf<(fpimm), [{ 445 APFloat APFloatOfN = N->getValueAPF(); 446 return !N->isExactlyValue(+0.0) && !checkConvertToNonDenormSingle(APFloatOfN); 447}]>; 448 449// Get the Hi bits of a 64 bit immediate. 450def getFPAs64BitIntHi : SDNodeXForm<fpimm, [{ 451 APFloat APFloatOfN = N->getValueAPF(); 452 bool Unused; 453 APFloatOfN.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven, 454 &Unused); 455 uint32_t Hi = (uint32_t)((APFloatOfN.bitcastToAPInt().getZExtValue() & 456 0xFFFFFFFF00000000LL) >> 32); 457 return CurDAG->getTargetConstant(Hi, SDLoc(N), MVT::i32); 458}]>; 459 460// Get the Lo bits of a 64 bit immediate. 461def getFPAs64BitIntLo : SDNodeXForm<fpimm, [{ 462 APFloat APFloatOfN = N->getValueAPF(); 463 bool Unused; 464 APFloatOfN.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven, 465 &Unused); 466 uint32_t Lo = (uint32_t)(APFloatOfN.bitcastToAPInt().getZExtValue() & 467 0xFFFFFFFF); 468 return CurDAG->getTargetConstant(Lo, SDLoc(N), MVT::i32); 469}]>; 470 471def imm34 : PatLeaf<(imm), [{ 472 return isInt<34>(N->getSExtValue()); 473}]>; 474 475def getImmAs64BitInt : SDNodeXForm<imm, [{ 476 return getI64Imm(N->getSExtValue(), SDLoc(N)); 477}]>; 478 479def SHL32 : SDNodeXForm<imm, [{ 480 // Transformation function: 31 - imm 481 return getI32Imm(31 - N->getZExtValue(), SDLoc(N)); 482}]>; 483 484def SRL32 : SDNodeXForm<imm, [{ 485 // Transformation function: 32 - imm 486 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N)) 487 : getI32Imm(0, SDLoc(N)); 488}]>; 489 490def LO16 : SDNodeXForm<imm, [{ 491 // Transformation function: get the low 16 bits. 492 return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N)); 493}]>; 494 495def HI16 : SDNodeXForm<imm, [{ 496 // Transformation function: shift the immediate value down into the low bits. 497 return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N)); 498}]>; 499 500def HA16 : SDNodeXForm<imm, [{ 501 // Transformation function: shift the immediate value down into the low bits. 502 int64_t Val = N->getZExtValue(); 503 return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N)); 504}]>; 505def MB : SDNodeXForm<imm, [{ 506 // Transformation function: get the start bit of a mask 507 unsigned mb = 0, me; 508 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 509 return getI32Imm(mb, SDLoc(N)); 510}]>; 511 512def ME : SDNodeXForm<imm, [{ 513 // Transformation function: get the end bit of a mask 514 unsigned mb, me = 0; 515 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 516 return getI32Imm(me, SDLoc(N)); 517}]>; 518def maskimm32 : PatLeaf<(imm), [{ 519 // maskImm predicate - True if immediate is a run of ones. 520 unsigned mb, me; 521 if (N->getValueType(0) == MVT::i32) 522 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 523 else 524 return false; 525}]>; 526 527def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{ 528 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit 529 // sign extended field. Used by instructions like 'addi'. 530 return (int32_t)Imm == (short)Imm; 531}]>; 532def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{ 533 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit 534 // sign extended field. Used by instructions like 'addi'. 535 return (int64_t)Imm == (short)Imm; 536}]>; 537def immZExt16 : PatLeaf<(imm), [{ 538 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 539 // field. Used by instructions like 'ori'. 540 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 541}], LO16>; 542def immNonAllOneAnyExt8 : ImmLeaf<i32, [{ 543 return (isInt<8>(Imm) && (Imm != -1)) || (isUInt<8>(Imm) && (Imm != 0xFF)); 544}]>; 545def i32immNonAllOneNonZero : ImmLeaf<i32, [{ return Imm && (Imm != -1); }]>; 546def immSExt5NonZero : ImmLeaf<i32, [{ return Imm && isInt<5>(Imm); }]>; 547 548// imm16Shifted* - These match immediates where the low 16-bits are zero. There 549// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 550// identical in 32-bit mode, but in 64-bit mode, they return true if the 551// immediate fits into a sign/zero extended 32-bit immediate (with the low bits 552// clear). 553def imm16ShiftedZExt : PatLeaf<(imm), [{ 554 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 555 // immediate are set. Used by instructions like 'xoris'. 556 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0; 557}], HI16>; 558 559def imm16ShiftedSExt : PatLeaf<(imm), [{ 560 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 561 // immediate are set. Used by instructions like 'addis'. Identical to 562 // imm16ShiftedZExt in 32-bit mode. 563 if (N->getZExtValue() & 0xFFFF) return false; 564 if (N->getValueType(0) == MVT::i32) 565 return true; 566 // For 64-bit, make sure it is sext right. 567 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); 568}], HI16>; 569 570def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{ 571 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit 572 // zero extended field. 573 return isUInt<32>(Imm); 574}]>; 575 576// This is a somewhat weaker condition than actually checking for 4-byte 577// alignment. It is simply checking that the displacement can be represented 578// as an immediate that is a multiple of 4 (i.e. the requirements for DS-Form 579// instructions). 580// But some r+i load/store instructions (such as LD, STD, LDU, etc.) that require 581// restricted memrix (4-aligned) constants are alignment sensitive. If these 582// offsets are hidden behind TOC entries than the values of the lower-order 583// bits cannot be checked directly. As a result, we need to also incorporate 584// an alignment check into the relevant patterns. 585 586def DSFormLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 587 return isOffsetMultipleOf(N, 4) || cast<LoadSDNode>(N)->getAlign() >= 4; 588}]>; 589def DSFormStore : PatFrag<(ops node:$val, node:$ptr), 590 (store node:$val, node:$ptr), [{ 591 return isOffsetMultipleOf(N, 4) || cast<StoreSDNode>(N)->getAlign() >= 4; 592}]>; 593def DSFormSextLoadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 594 return isOffsetMultipleOf(N, 4) || cast<LoadSDNode>(N)->getAlign() >= 4; 595}]>; 596def DSFormPreStore : PatFrag< 597 (ops node:$val, node:$base, node:$offset), 598 (pre_store node:$val, node:$base, node:$offset), [{ 599 return isOffsetMultipleOf(N, 4) || cast<StoreSDNode>(N)->getAlign() >= 4; 600}]>; 601 602def NonDSFormLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 603 return cast<LoadSDNode>(N)->getAlign() < 4 && !isOffsetMultipleOf(N, 4); 604}]>; 605def NonDSFormStore : PatFrag<(ops node:$val, node:$ptr), 606 (store node:$val, node:$ptr), [{ 607 return cast<StoreSDNode>(N)->getAlign() < 4 && !isOffsetMultipleOf(N, 4); 608}]>; 609def NonDSFormSextLoadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 610 return cast<LoadSDNode>(N)->getAlign() < 4 && !isOffsetMultipleOf(N, 4); 611}]>; 612 613// This is a somewhat weaker condition than actually checking for 16-byte 614// alignment. It is simply checking that the displacement can be represented 615// as an immediate that is a multiple of 16 (i.e. the requirements for DQ-Form 616// instructions). 617def quadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 618 return isOffsetMultipleOf(N, 16); 619}]>; 620def quadwOffsetStore : PatFrag<(ops node:$val, node:$ptr), 621 (store node:$val, node:$ptr), [{ 622 return isOffsetMultipleOf(N, 16); 623}]>; 624def nonQuadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 625 return !isOffsetMultipleOf(N, 16); 626}]>; 627def nonQuadwOffsetStore : PatFrag<(ops node:$val, node:$ptr), 628 (store node:$val, node:$ptr), [{ 629 return !isOffsetMultipleOf(N, 16); 630}]>; 631 632// PatFrag for binary operation whose operands are both non-constant 633class BinOpWithoutSImm16Operand<SDNode opcode> : 634 PatFrag<(ops node:$left, node:$right), (opcode node:$left, node:$right), [{ 635 int16_t Imm; 636 return !isIntS16Immediate(N->getOperand(0), Imm) 637 && !isIntS16Immediate(N->getOperand(1), Imm); 638}]>; 639 640def add_without_simm16 : BinOpWithoutSImm16Operand<add>; 641def mul_without_simm16 : BinOpWithoutSImm16Operand<mul>; 642 643//===----------------------------------------------------------------------===// 644// PowerPC Flag Definitions. 645 646class isPPC64 { bit PPC64 = 1; } 647class isRecordForm { bit RC = 1; } 648 649class RegConstraint<string C> { 650 string Constraints = C; 651} 652class NoEncode<string E> { 653 string DisableEncoding = E; 654} 655 656 657// Define PowerPC specific addressing mode. 658 659// d-form 660def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; // "stb" 661// ds-form 662def iaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std" 663// dq-form 664def iaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrImmX16", [], []>; // "stxv" 665// 8LS:d-form 666def iaddrX34 : ComplexPattern<iPTR, 2, "SelectAddrImmX34", [], []>; // "pstxvp" 667 668// Below forms are all x-form addressing mode, use three different ones so we 669// can make a accurate check for x-form instructions in ISEL. 670// x-form addressing mode whose associated displacement form is D. 671def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; // "stbx" 672// x-form addressing mode whose associated displacement form is DS. 673def xaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrIdxX4", [], []>; // "stdx" 674// x-form addressing mode whose associated displacement form is DQ. 675def xaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrIdxX16", [], []>; // "stxvx" 676 677def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 678 679// The address in a single register. This is used with the SjLj 680// pseudo-instructions. 681def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>; 682 683/// This is just the offset part of iaddr, used for preinc. 684def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 685 686// Load and Store Instruction Selection addressing modes. 687def DForm : ComplexPattern<iPTR, 2, "SelectDForm", [], [SDNPWantParent]>; 688def DSForm : ComplexPattern<iPTR, 2, "SelectDSForm", [], [SDNPWantParent]>; 689def DQForm : ComplexPattern<iPTR, 2, "SelectDQForm", [], [SDNPWantParent]>; 690def XForm : ComplexPattern<iPTR, 2, "SelectXForm", [], [SDNPWantParent]>; 691def ForceXForm : ComplexPattern<iPTR, 2, "SelectForceXForm", [], [SDNPWantParent]>; 692def PCRelForm : ComplexPattern<iPTR, 2, "SelectPCRelForm", [], [SDNPWantParent]>; 693def PDForm : ComplexPattern<iPTR, 2, "SelectPDForm", [], [SDNPWantParent]>; 694 695//===----------------------------------------------------------------------===// 696// PowerPC Instruction Predicate Definitions. 697def In32BitMode : Predicate<"!Subtarget->isPPC64()">; 698def In64BitMode : Predicate<"Subtarget->isPPC64()">; 699def IsBookE : Predicate<"Subtarget->isBookE()">; 700def IsNotBookE : Predicate<"!Subtarget->isBookE()">; 701def HasOnlyMSYNC : Predicate<"Subtarget->hasOnlyMSYNC()">; 702def HasSYNC : Predicate<"!Subtarget->hasOnlyMSYNC()">; 703def IsPPC4xx : Predicate<"Subtarget->isPPC4xx()">; 704def IsPPC6xx : Predicate<"Subtarget->isPPC6xx()">; 705def IsE500 : Predicate<"Subtarget->isE500()">; 706def HasSPE : Predicate<"Subtarget->hasSPE()">; 707def HasICBT : Predicate<"Subtarget->hasICBT()">; 708def HasPartwordAtomics : Predicate<"Subtarget->hasPartwordAtomics()">; 709def HasQuadwordAtomics : Predicate<"Subtarget->hasQuadwordAtomics()">; 710def NoNaNsFPMath 711 : Predicate<"Subtarget->getTargetMachine().Options.NoNaNsFPMath">; 712def NaNsFPMath 713 : Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">; 714def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">; 715def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">; 716def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">; 717def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">; 718def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">; 719def HasFPU : Predicate<"Subtarget->hasFPU()">; 720def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">; 721def IsNotISA3_1 : Predicate<"!Subtarget->isISA3_1()">; 722 723// AIX assembler may not be modern enough to support some extended mne. 724def ModernAs: Predicate<"!Subtarget->isAIXABI() || Subtarget->HasModernAIXAs">, 725 AssemblerPredicate<(any_of (not AIXOS), FeatureModernAIXAs)>; 726def IsAIX : Predicate<"Subtarget->isAIXABI()">; 727def NotAIX : Predicate<"!Subtarget->isAIXABI()">; 728def IsISAFuture : Predicate<"Subtarget->isISAFuture()">; 729def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">; 730 731//===----------------------------------------------------------------------===// 732// PowerPC Multiclass Definitions. 733multiclass XForm_base_r3xo_r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 734 string asmbase, string asmstr, list<dag> pattern> { 735 let BaseName = asmbase in { 736 def NAME : XForm_base_r3xo<opcode, xo, OOL, IOL, 737 !strconcat(asmbase, !strconcat(" ", asmstr)), 738 NoItinerary, pattern>, RecFormRel; 739 let Defs = [CR1] in 740 def _rec : XForm_base_r3xo<opcode, xo, OOL, IOL, 741 !strconcat(asmbase, !strconcat(". ", asmstr)), 742 NoItinerary, []>, isRecordForm, RecFormRel; 743 } 744} 745 746multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 747 string asmbase, string asmstr, InstrItinClass itin, 748 list<dag> pattern> { 749 let BaseName = asmbase in { 750 def NAME : XForm_6<opcode, xo, OOL, IOL, 751 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 752 pattern>, RecFormRel; 753 let Defs = [CR0] in 754 def _rec : XForm_6<opcode, xo, OOL, IOL, 755 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 756 []>, isRecordForm, RecFormRel; 757 } 758} 759 760multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 761 string asmbase, string asmstr, InstrItinClass itin, 762 list<dag> pattern> { 763 let BaseName = asmbase in { 764 let Defs = [CARRY] in 765 def NAME : XForm_6<opcode, xo, OOL, IOL, 766 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 767 pattern>, RecFormRel; 768 let Defs = [CARRY, CR0] in 769 def _rec : XForm_6<opcode, xo, OOL, IOL, 770 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 771 []>, isRecordForm, RecFormRel; 772 } 773} 774 775multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 776 string asmbase, string asmstr, InstrItinClass itin, 777 list<dag> pattern> { 778 let BaseName = asmbase in { 779 let Defs = [CARRY] in 780 def NAME : XForm_10<opcode, xo, OOL, IOL, 781 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 782 pattern>, RecFormRel; 783 let Defs = [CARRY, CR0] in 784 def _rec : XForm_10<opcode, xo, OOL, IOL, 785 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 786 []>, isRecordForm, RecFormRel; 787 } 788} 789 790multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 791 string asmbase, string asmstr, InstrItinClass itin, 792 list<dag> pattern> { 793 let BaseName = asmbase in { 794 def NAME : XForm_11<opcode, xo, OOL, IOL, 795 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 796 pattern>, RecFormRel; 797 let Defs = [CR0] in 798 def _rec : XForm_11<opcode, xo, OOL, IOL, 799 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 800 []>, isRecordForm, RecFormRel; 801 } 802} 803 804multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 805 string asmbase, string asmstr, InstrItinClass itin, 806 list<dag> pattern> { 807 let BaseName = asmbase in { 808 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 809 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 810 pattern>, RecFormRel; 811 let Defs = [CR0] in 812 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 813 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 814 []>, isRecordForm, RecFormRel; 815 } 816} 817 818// Multiclass for instructions which have a record overflow form as well 819// as a record form but no carry (i.e. mulld, mulldo, subf, subfo, etc.) 820multiclass XOForm_1rx<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 821 string asmbase, string asmstr, InstrItinClass itin, 822 list<dag> pattern> { 823 let BaseName = asmbase in { 824 def NAME : XOForm_1<opcode, xo, 0, OOL, IOL, 825 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 826 pattern>, RecFormRel; 827 let Defs = [CR0] in 828 def _rec : XOForm_1<opcode, xo, 0, OOL, IOL, 829 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 830 []>, isRecordForm, RecFormRel; 831 } 832 let BaseName = !strconcat(asmbase, "O") in { 833 let Defs = [XER] in 834 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 835 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 836 []>, RecFormRel; 837 let Defs = [XER, CR0] in 838 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 839 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 840 []>, isRecordForm, RecFormRel; 841 } 842} 843 844// Multiclass for instructions for which the non record form is not cracked 845// and the record form is cracked (i.e. divw, mullw, etc.) 846multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 847 string asmbase, string asmstr, InstrItinClass itin, 848 list<dag> pattern> { 849 let BaseName = asmbase in { 850 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 851 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 852 pattern>, RecFormRel; 853 let Defs = [CR0] in 854 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 855 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 856 []>, isRecordForm, RecFormRel, PPC970_DGroup_First, 857 PPC970_DGroup_Cracked; 858 } 859 let BaseName = !strconcat(asmbase, "O") in { 860 let Defs = [XER] in 861 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 862 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 863 []>, RecFormRel; 864 let Defs = [XER, CR0] in 865 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 866 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 867 []>, isRecordForm, RecFormRel; 868 } 869} 870 871multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 872 string asmbase, string asmstr, InstrItinClass itin, 873 list<dag> pattern> { 874 let BaseName = asmbase in { 875 let Defs = [CARRY] in 876 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 877 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 878 pattern>, RecFormRel; 879 let Defs = [CARRY, CR0] in 880 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 881 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 882 []>, isRecordForm, RecFormRel; 883 } 884 let BaseName = !strconcat(asmbase, "O") in { 885 let Defs = [CARRY, XER] in 886 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 887 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 888 []>, RecFormRel; 889 let Defs = [CARRY, XER, CR0] in 890 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 891 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 892 []>, isRecordForm, RecFormRel; 893 } 894} 895 896multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 897 string asmbase, string asmstr, InstrItinClass itin, 898 list<dag> pattern> { 899 let BaseName = asmbase in { 900 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 901 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 902 pattern>, RecFormRel; 903 let Defs = [CR0] in 904 def _rec : XOForm_3<opcode, xo, oe, OOL, IOL, 905 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 906 []>, isRecordForm, RecFormRel; 907 } 908 let BaseName = !strconcat(asmbase, "O") in { 909 let Defs = [XER] in 910 def O : XOForm_3<opcode, xo, 1, OOL, IOL, 911 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 912 []>, RecFormRel; 913 let Defs = [XER, CR0] in 914 def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL, 915 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 916 []>, isRecordForm, RecFormRel; 917 } 918} 919 920multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 921 string asmbase, string asmstr, InstrItinClass itin, 922 list<dag> pattern> { 923 let BaseName = asmbase in { 924 let Defs = [CARRY] in 925 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 926 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 927 pattern>, RecFormRel; 928 let Defs = [CARRY, CR0] in 929 def _rec : XOForm_3<opcode, xo, oe, OOL, IOL, 930 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 931 []>, isRecordForm, RecFormRel; 932 } 933 let BaseName = !strconcat(asmbase, "O") in { 934 let Defs = [CARRY, XER] in 935 def O : XOForm_3<opcode, xo, 1, OOL, IOL, 936 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 937 []>, RecFormRel; 938 let Defs = [CARRY, XER, CR0] in 939 def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL, 940 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 941 []>, isRecordForm, RecFormRel; 942 } 943} 944 945multiclass MForm_1r<bits<6> opcode, dag OOL, dag IOL, 946 string asmbase, string asmstr, InstrItinClass itin, 947 list<dag> pattern> { 948 let BaseName = asmbase in { 949 def NAME : MForm_1<opcode, OOL, IOL, 950 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 951 pattern>, RecFormRel; 952 let Defs = [CR0] in 953 def _rec : MForm_1<opcode, OOL, IOL, 954 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 955 []>, isRecordForm, RecFormRel; 956 } 957} 958 959multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL, 960 string asmbase, string asmstr, InstrItinClass itin, 961 list<dag> pattern> { 962 let BaseName = asmbase in { 963 def NAME : MForm_2<opcode, OOL, IOL, 964 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 965 pattern>, RecFormRel; 966 let Defs = [CR0] in 967 def _rec : MForm_2<opcode, OOL, IOL, 968 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 969 []>, isRecordForm, RecFormRel; 970 } 971} 972 973multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 974 string asmbase, string asmstr, InstrItinClass itin, 975 list<dag> pattern> { 976 let BaseName = asmbase in { 977 def NAME : MDForm_1<opcode, xo, OOL, IOL, 978 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 979 pattern>, RecFormRel; 980 let Defs = [CR0] in 981 def _rec : MDForm_1<opcode, xo, OOL, IOL, 982 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 983 []>, isRecordForm, RecFormRel; 984 } 985} 986 987multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 988 string asmbase, string asmstr, InstrItinClass itin, 989 list<dag> pattern> { 990 let BaseName = asmbase in { 991 def NAME : MDSForm_1<opcode, xo, OOL, IOL, 992 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 993 pattern>, RecFormRel; 994 let Defs = [CR0] in 995 def _rec : MDSForm_1<opcode, xo, OOL, IOL, 996 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 997 []>, isRecordForm, RecFormRel; 998 } 999} 1000 1001multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1002 string asmbase, string asmstr, InstrItinClass itin, 1003 list<dag> pattern> { 1004 let BaseName = asmbase in { 1005 let Defs = [CARRY] in 1006 def NAME : XSForm_1<opcode, xo, OOL, IOL, 1007 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1008 pattern>, RecFormRel; 1009 let Defs = [CARRY, CR0] in 1010 def _rec : XSForm_1<opcode, xo, OOL, IOL, 1011 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1012 []>, isRecordForm, RecFormRel; 1013 } 1014} 1015 1016multiclass XSForm_1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1017 string asmbase, string asmstr, InstrItinClass itin, 1018 list<dag> pattern> { 1019 let BaseName = asmbase in { 1020 def NAME : XSForm_1<opcode, xo, OOL, IOL, 1021 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1022 pattern>, RecFormRel; 1023 let Defs = [CR0] in 1024 def _rec : XSForm_1<opcode, xo, OOL, IOL, 1025 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1026 []>, isRecordForm, RecFormRel; 1027 } 1028} 1029 1030multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1031 string asmbase, string asmstr, InstrItinClass itin, 1032 list<dag> pattern> { 1033 let BaseName = asmbase in { 1034 def NAME : XForm_26<opcode, xo, OOL, IOL, 1035 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1036 pattern>, RecFormRel; 1037 let Defs = [CR1] in 1038 def _rec : XForm_26<opcode, xo, OOL, IOL, 1039 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1040 []>, isRecordForm, RecFormRel; 1041 } 1042} 1043 1044multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1045 string asmbase, string asmstr, InstrItinClass itin, 1046 list<dag> pattern> { 1047 let BaseName = asmbase in { 1048 def NAME : XForm_28<opcode, xo, OOL, IOL, 1049 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1050 pattern>, RecFormRel; 1051 let Defs = [CR1] in 1052 def _rec : XForm_28<opcode, xo, OOL, IOL, 1053 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1054 []>, isRecordForm, RecFormRel; 1055 } 1056} 1057 1058multiclass XForm_SP2_FRTB5r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1059 string asmbase, string asmstr, list<dag> pattern> { 1060 let BaseName = asmbase in { 1061 def NAME : XForm_SP2_FRTB5<opcode, xo, OOL, IOL, 1062 !strconcat(asmbase, !strconcat(" ", asmstr)), 1063 pattern, NoItinerary>, RecFormRel; 1064 let Defs = [CR1] in 1065 def _rec : XForm_SP2_FRTB5<opcode, xo, OOL, IOL, 1066 !strconcat(asmbase, !strconcat(". ", asmstr)), 1067 [], NoItinerary>, isRecordForm, RecFormRel; 1068 } 1069} 1070 1071multiclass XForm_S1_FRTB5r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1072 string asmbase, string asmstr, list<dag> pattern> { 1073 let BaseName = asmbase in { 1074 def NAME : XForm_S1_FRTB5<opcode, xo, OOL, IOL, 1075 !strconcat(asmbase, !strconcat(" ", asmstr)), 1076 pattern, NoItinerary>, RecFormRel; 1077 let Defs = [CR1] in 1078 def _rec : XForm_S1_FRTB5<opcode, xo, OOL, IOL, 1079 !strconcat(asmbase, !strconcat(". ", asmstr)), [], 1080 NoItinerary>, isRecordForm, RecFormRel; 1081 } 1082} 1083 1084multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1085 string asmbase, string asmstr, InstrItinClass itin, 1086 list<dag> pattern> { 1087 let BaseName = asmbase in { 1088 def NAME : AForm_1<opcode, xo, OOL, IOL, 1089 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1090 pattern>, RecFormRel; 1091 let Defs = [CR1] in 1092 def _rec : AForm_1<opcode, xo, OOL, IOL, 1093 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1094 []>, isRecordForm, RecFormRel; 1095 } 1096} 1097 1098multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1099 string asmbase, string asmstr, InstrItinClass itin, 1100 list<dag> pattern> { 1101 let BaseName = asmbase in { 1102 def NAME : AForm_2<opcode, xo, OOL, IOL, 1103 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1104 pattern>, RecFormRel; 1105 let Defs = [CR1] in 1106 def _rec : AForm_2<opcode, xo, OOL, IOL, 1107 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1108 []>, isRecordForm, RecFormRel; 1109 } 1110} 1111 1112multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1113 string asmbase, string asmstr, InstrItinClass itin, 1114 list<dag> pattern> { 1115 let BaseName = asmbase in { 1116 def NAME : AForm_3<opcode, xo, OOL, IOL, 1117 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1118 pattern>, RecFormRel; 1119 let Defs = [CR1] in 1120 def _rec : AForm_3<opcode, xo, OOL, IOL, 1121 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1122 []>, isRecordForm, RecFormRel; 1123 } 1124} 1125 1126multiclass 1127 Z23Form_TE5_FRTB5_RMC2r<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 1128 string asmbase, string asmstr, list<dag> pattern> { 1129 let BaseName = asmbase in { 1130 def NAME 1131 : Z23Form_TE5_FRTB5_RMC2<opcode, xo, OOL, IOL, 1132 !strconcat(asmbase, !strconcat(" ", asmstr)), 1133 pattern>, RecFormRel; 1134 let Defs = [CR0] in 1135 def _rec : Z23Form_TE5_FRTB5_RMC2<opcode, xo, OOL, IOL, 1136 !strconcat(asmbase, !strconcat(". ", asmstr)), 1137 []>, isRecordForm, RecFormRel; 1138 } 1139} 1140 1141multiclass 1142 Z23Form_FRTAB5_RMC2r<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 1143 string asmbase, string asmstr, list<dag> pattern> { 1144 let BaseName = asmbase in { 1145 def NAME : Z23Form_FRTAB5_RMC2<opcode, xo, OOL, IOL, 1146 !strconcat(asmbase, !strconcat(" ", asmstr)), 1147 pattern>, RecFormRel; 1148 let Defs = [CR1] in 1149 def _rec : Z23Form_FRTAB5_RMC2<opcode, xo, OOL, IOL, 1150 !strconcat(asmbase, !strconcat(". ", asmstr)), 1151 []>, isRecordForm, RecFormRel; 1152 } 1153} 1154 1155multiclass 1156 Z23Form_FRTB5_R1_RMC2r<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 1157 string asmbase, string asmstr, list<dag> pattern> { 1158 let BaseName = asmbase in { 1159 def NAME : Z23Form_FRTB5_R1_RMC2<opcode, xo, OOL, IOL, 1160 !strconcat(asmbase, !strconcat(" ", asmstr)), 1161 pattern>, RecFormRel; 1162 let Defs = [CR1] in 1163 def _rec : Z23Form_FRTB5_R1_RMC2<opcode, xo, OOL, IOL, 1164 !strconcat(asmbase, !strconcat(". ", asmstr)), 1165 []>, isRecordForm, RecFormRel; 1166 } 1167} 1168 1169multiclass Z22Form_FRTA5_SH6r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1170 string asmbase, string asmstr, list<dag> pattern> { 1171 let BaseName = asmbase in { 1172 def NAME : Z22Form_FRTA5_SH6<opcode, xo, OOL, IOL, 1173 !strconcat(asmbase, !strconcat(" ", asmstr)), 1174 pattern, NoItinerary>, RecFormRel; 1175 let Defs = [CR1] in 1176 def _rec : Z22Form_FRTA5_SH6<opcode, xo, OOL, IOL, 1177 !strconcat(asmbase, !strconcat(". ", asmstr)), 1178 [], NoItinerary>, isRecordForm, RecFormRel; 1179 } 1180} 1181 1182//===----------------------------------------------------------------------===// 1183// END OF MULTICLASS DEFINITIONS 1184//===----------------------------------------------------------------------===// 1185 1186//===----------------------------------------------------------------------===// 1187// PowerPC Instruction Definitions. 1188 1189// Pseudo instructions: 1190 1191let hasCtrlDep = 1 in { 1192let Defs = [R1], Uses = [R1] in { 1193def ADJCALLSTACKDOWN : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), 1194 "#ADJCALLSTACKDOWN $amt1 $amt2", 1195 [(callseq_start timm:$amt1, timm:$amt2)]>; 1196def ADJCALLSTACKUP : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), 1197 "#ADJCALLSTACKUP $amt1 $amt2", 1198 [(callseq_end timm:$amt1, timm:$amt2)]>; 1199} 1200} // hasCtrlDep 1201 1202let Defs = [R1], Uses = [R1] in 1203def DYNALLOC : PPCEmitTimePseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC", 1204 [(set i32:$result, 1205 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>; 1206def DYNAREAOFFSET : PPCEmitTimePseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET", 1207 [(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 1208// Probed alloca to support stack clash protection. 1209let Defs = [R1], Uses = [R1], hasNoSchedulingInfo = 1 in { 1210def PROBED_ALLOCA_32 : PPCCustomInserterPseudo<(outs gprc:$result), 1211 (ins gprc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_32", 1212 [(set i32:$result, 1213 (PPCprobedalloca i32:$negsize, iaddr:$fpsi))]>; 1214def PREPARE_PROBED_ALLOCA_32 : PPCEmitTimePseudo<(outs 1215 gprc:$fp, gprc:$actual_negsize), 1216 (ins gprc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_32", []>; 1217def PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 : PPCEmitTimePseudo<(outs 1218 gprc:$fp, gprc:$actual_negsize), 1219 (ins gprc:$negsize, memri:$fpsi), 1220 "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32", []>, 1221 RegConstraint<"$actual_negsize = $negsize">; 1222def PROBED_STACKALLOC_32 : PPCEmitTimePseudo<(outs gprc:$scratch, gprc:$temp), 1223 (ins i64imm:$stacksize), 1224 "#PROBED_STACKALLOC_32", []>; 1225} 1226 1227// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 1228// instruction selection into a branch sequence. 1229let PPC970_Single = 1 in { 1230 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes 1231 // because either operand might become the first operand in an isel, and 1232 // that operand cannot be r0. 1233 def SELECT_CC_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crrc:$cond, 1234 gprc_nor0:$T, gprc_nor0:$F, 1235 i32imm:$BROPC), "#SELECT_CC_I4", 1236 []>; 1237 def SELECT_CC_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crrc:$cond, 1238 g8rc_nox0:$T, g8rc_nox0:$F, 1239 i32imm:$BROPC), "#SELECT_CC_I8", 1240 []>; 1241 def SELECT_CC_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F, 1242 i32imm:$BROPC), "#SELECT_CC_F4", 1243 []>; 1244 def SELECT_CC_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F, 1245 i32imm:$BROPC), "#SELECT_CC_F8", 1246 []>; 1247 def SELECT_CC_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 1248 i32imm:$BROPC), "#SELECT_CC_F16", 1249 []>; 1250 def SELECT_CC_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 1251 i32imm:$BROPC), "#SELECT_CC_VRRC", 1252 []>; 1253 1254 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition 1255 // register bit directly. 1256 def SELECT_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crbitrc:$cond, 1257 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4", 1258 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>; 1259 def SELECT_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crbitrc:$cond, 1260 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8", 1261 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>; 1262let Predicates = [HasFPU] in { 1263 def SELECT_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crbitrc:$cond, 1264 f4rc:$T, f4rc:$F), "#SELECT_F4", 1265 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>; 1266 def SELECT_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crbitrc:$cond, 1267 f8rc:$T, f8rc:$F), "#SELECT_F8", 1268 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>; 1269 def SELECT_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond, 1270 vrrc:$T, vrrc:$F), "#SELECT_F16", 1271 [(set f128:$dst, (select i1:$cond, f128:$T, f128:$F))]>; 1272} 1273 def SELECT_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond, 1274 vrrc:$T, vrrc:$F), "#SELECT_VRRC", 1275 [(set v4i32:$dst, 1276 (select i1:$cond, v4i32:$T, v4i32:$F))]>; 1277} 1278 1279// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to 1280// scavenge a register for it. 1281let mayStore = 1 in { 1282def SPILL_CR : PPCEmitTimePseudo<(outs), (ins crrc:$cond, memri:$F), 1283 "#SPILL_CR", []>; 1284def SPILL_CRBIT : PPCEmitTimePseudo<(outs), (ins crbitrc:$cond, memri:$F), 1285 "#SPILL_CRBIT", []>; 1286} 1287 1288// RESTORE_CR - Indicate that we're restoring the CR register (previously 1289// spilled), so we'll need to scavenge a register for it. 1290let mayLoad = 1 in { 1291def RESTORE_CR : PPCEmitTimePseudo<(outs crrc:$cond), (ins memri:$F), 1292 "#RESTORE_CR", []>; 1293def RESTORE_CRBIT : PPCEmitTimePseudo<(outs crbitrc:$cond), (ins memri:$F), 1294 "#RESTORE_CRBIT", []>; 1295} 1296 1297let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in { 1298 let isPredicable = 1, isReturn = 1, Uses = [LR, RM] in 1299 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 1300 [(retglue)]>, Requires<[In32BitMode]>; 1301 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in { 1302 let isPredicable = 1 in 1303 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1304 []>; 1305 1306 let isCodeGenOnly = 1 in { 1307 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins (pred $BIBO, $CR):$cond), 1308 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 1309 []>; 1310 1311 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$BI), 1312 "bcctr 12, $BI, 0", IIC_BrB, []>; 1313 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$BI), 1314 "bcctr 4, $BI, 0", IIC_BrB, []>; 1315 } 1316 } 1317} 1318 1319// Set the float rounding mode. 1320let Uses = [RM], Defs = [RM] in { 1321def SETRNDi : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins u2imm:$RND), 1322 "#SETRNDi", [(set f64:$FRT, (int_ppc_setrnd (i32 imm:$RND)))]>; 1323 1324def SETRND : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins gprc:$in), 1325 "#SETRND", [(set f64:$FRT, (int_ppc_setrnd gprc :$in))]>; 1326 1327def SETFLM : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FLM), 1328 "#SETFLM", [(set f64:$FRT, (int_ppc_setflm f8rc:$FLM))]>; 1329} 1330 1331let Defs = [LR] in 1332 def MovePCtoLR : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR", []>, 1333 PPC970_Unit_BRU; 1334let Defs = [LR] in 1335 def MoveGOTtoLR : PPCEmitTimePseudo<(outs), (ins), "#MoveGOTtoLR", []>, 1336 PPC970_Unit_BRU; 1337 1338let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1339 hasSideEffects = 0 in { 1340 let isBarrier = 1 in { 1341 let isPredicable = 1 in 1342 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$LI), 1343 "b $LI", IIC_BrB, 1344 [(br bb:$LI)]>; 1345 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$LI), 1346 "ba $LI", IIC_BrB, []>; 1347 } 1348 1349 // BCC represents an arbitrary conditional branch on a predicate. 1350 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 1351 // a two-value operand where a dag node expects two operands. :( 1352 let isCodeGenOnly = 1 in { 1353 class BCC_class : BForm<16, 0, 0, (outs), (ins (pred $BIBO, $CR):$cond, condbrtarget:$BD), 1354 "b${cond:cc}${cond:pm} ${cond:reg}, $BD" 1355 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$BD)]*/>; 1356 def BCC : BCC_class; 1357 1358 // The same as BCC, except that it's not a terminator. Used for introducing 1359 // control flow dependency without creating new blocks. 1360 let isTerminator = 0 in def CTRL_DEP : BCC_class; 1361 1362 def BCCA : BForm<16, 1, 0, (outs), (ins (pred $BIBO, $CR):$cond, abscondbrtarget:$BD), 1363 "b${cond:cc}a${cond:pm} ${cond:reg}, $BD">; 1364 1365 let isReturn = 1, Uses = [LR, RM] in 1366 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins (pred $BIBO, $CR):$cond), 1367 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>; 1368 } 1369 1370 let isCodeGenOnly = 1 in { 1371 let Pattern = [(brcond i1:$BI, bb:$BD)] in 1372 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$BI, condbrtarget:$BD), 1373 "bc 12, $BI, $BD">; 1374 1375 let Pattern = [(brcond (not i1:$BI), bb:$BD)] in 1376 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$BI, condbrtarget:$BD), 1377 "bc 4, $BI, $BD">; 1378 1379 let isReturn = 1, Uses = [LR, RM] in { 1380 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$BI), 1381 "bclr 12, $BI, 0", IIC_BrB, []>; 1382 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$BI), 1383 "bclr 4, $BI, 0", IIC_BrB, []>; 1384 } 1385 } 1386 1387 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in { 1388 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 1389 "bdzlr", IIC_BrB, []>; 1390 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 1391 "bdnzlr", IIC_BrB, []>; 1392 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins), 1393 "bdzlr+", IIC_BrB, []>; 1394 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins), 1395 "bdnzlr+", IIC_BrB, []>; 1396 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins), 1397 "bdzlr-", IIC_BrB, []>; 1398 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins), 1399 "bdnzlr-", IIC_BrB, []>; 1400 } 1401 1402 let Defs = [CTR], Uses = [CTR] in { 1403 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$BD), 1404 "bdz $BD">; 1405 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$BD), 1406 "bdnz $BD">; 1407 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$BD), 1408 "bdza $BD">; 1409 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$BD), 1410 "bdnza $BD">; 1411 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$BD), 1412 "bdz+ $BD">; 1413 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$BD), 1414 "bdnz+ $BD">; 1415 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$BD), 1416 "bdza+ $BD">; 1417 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$BD), 1418 "bdnza+ $BD">; 1419 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$BD), 1420 "bdz- $BD">; 1421 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$BD), 1422 "bdnz- $BD">; 1423 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$BD), 1424 "bdza- $BD">; 1425 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$BD), 1426 "bdnza- $BD">; 1427 } 1428} 1429 1430// The unconditional BCL used by the SjLj setjmp code. 1431let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7, 1432 hasSideEffects = 0 in { 1433 let Defs = [LR], Uses = [RM] in { 1434 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$BD), 1435 "bcl 20, 31, $BD">; 1436 } 1437} 1438 1439let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { 1440 // Convenient aliases for call instructions 1441 let Uses = [RM] in { 1442 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$LI), 1443 "bl $LI", IIC_BrB, []>; // See Pat patterns below. 1444 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$LI), 1445 "bla $LI", IIC_BrB, [(PPCcall (i32 imm:$LI))]>; 1446 1447 let isCodeGenOnly = 1 in { 1448 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$LI), 1449 "bl $LI", IIC_BrB, []>; 1450 def BCCL : BForm<16, 0, 1, (outs), (ins (pred $BIBO, $CR):$cond, condbrtarget:$BD), 1451 "b${cond:cc}l${cond:pm} ${cond:reg}, $BD">; 1452 def BCCLA : BForm<16, 1, 1, (outs), (ins (pred $BIBO, $CR):$cond, abscondbrtarget:$BD), 1453 "b${cond:cc}la${cond:pm} ${cond:reg}, $BD">; 1454 1455 def BCL : BForm_4<16, 12, 0, 1, (outs), 1456 (ins crbitrc:$BI, condbrtarget:$BD), 1457 "bcl 12, $BI, $BD">; 1458 def BCLn : BForm_4<16, 4, 0, 1, (outs), 1459 (ins crbitrc:$BI, condbrtarget:$BD), 1460 "bcl 4, $BI, $BD">; 1461 def BL_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 1462 (outs), (ins calltarget:$LI), 1463 "bl $LI\n\tnop", IIC_BrB, []>; 1464 } 1465 } 1466 let Uses = [CTR, RM] in { 1467 let isPredicable = 1 in 1468 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 1469 "bctrl", IIC_BrB, [(PPCbctrl)]>, 1470 Requires<[In32BitMode]>; 1471 1472 let isCodeGenOnly = 1 in { 1473 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins (pred $BIBO, $CR):$cond), 1474 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 1475 []>; 1476 1477 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$BI), 1478 "bcctrl 12, $BI, 0", IIC_BrB, []>; 1479 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$BI), 1480 "bcctrl 4, $BI, 0", IIC_BrB, []>; 1481 } 1482 } 1483 let Uses = [LR, RM] in { 1484 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins), 1485 "blrl", IIC_BrB, []>; 1486 1487 let isCodeGenOnly = 1 in { 1488 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins (pred $BIBO, $CR):$cond), 1489 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB, 1490 []>; 1491 1492 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$BI), 1493 "bclrl 12, $BI, 0", IIC_BrB, []>; 1494 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$BI), 1495 "bclrl 4, $BI, 0", IIC_BrB, []>; 1496 } 1497 } 1498 let Defs = [CTR], Uses = [CTR, RM] in { 1499 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$BD), 1500 "bdzl $BD">; 1501 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$BD), 1502 "bdnzl $BD">; 1503 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$BD), 1504 "bdzla $BD">; 1505 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$BD), 1506 "bdnzla $BD">; 1507 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$BD), 1508 "bdzl+ $BD">; 1509 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$BD), 1510 "bdnzl+ $BD">; 1511 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$BD), 1512 "bdzla+ $BD">; 1513 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$BD), 1514 "bdnzla+ $BD">; 1515 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$BD), 1516 "bdzl- $BD">; 1517 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$BD), 1518 "bdnzl- $BD">; 1519 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$BD), 1520 "bdzla- $BD">; 1521 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$BD), 1522 "bdnzla- $BD">; 1523 } 1524 let Defs = [CTR], Uses = [CTR, LR, RM] in { 1525 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins), 1526 "bdzlrl", IIC_BrB, []>; 1527 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins), 1528 "bdnzlrl", IIC_BrB, []>; 1529 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins), 1530 "bdzlrl+", IIC_BrB, []>; 1531 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins), 1532 "bdnzlrl+", IIC_BrB, []>; 1533 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins), 1534 "bdzlrl-", IIC_BrB, []>; 1535 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins), 1536 "bdnzlrl-", IIC_BrB, []>; 1537 } 1538} 1539 1540let isCall = 1, PPC970_Unit = 7, Defs = [LR, RM], isCodeGenOnly = 1 in { 1541 // Convenient aliases for call instructions 1542 let Uses = [RM] in { 1543 def BL_RM : IForm<18, 0, 1, (outs), (ins calltarget:$LI), 1544 "bl $LI", IIC_BrB, []>; // See Pat patterns below. 1545 def BLA_RM : IForm<18, 1, 1, (outs), (ins abscalltarget:$LI), 1546 "bla $LI", IIC_BrB, [(PPCcall_rm (i32 imm:$LI))]>; 1547 1548 def BL_NOP_RM : IForm_and_DForm_4_zero<18, 0, 1, 24, 1549 (outs), (ins calltarget:$LI), 1550 "bl $LI\n\tnop", IIC_BrB, []>; 1551 } 1552 let Uses = [CTR, RM] in { 1553 let isPredicable = 1 in 1554 def BCTRL_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 1555 "bctrl", IIC_BrB, [(PPCbctrl_rm)]>, 1556 Requires<[In32BitMode]>; 1557 } 1558} 1559 1560let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1561def TCRETURNdi :PPCEmitTimePseudo< (outs), 1562 (ins calltarget:$dst, i32imm:$offset), 1563 "#TC_RETURNd $dst $offset", 1564 []>; 1565 1566 1567let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1568def TCRETURNai :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 1569 "#TC_RETURNa $func $offset", 1570 [(PPCtc_return (i32 imm:$func), imm:$offset)]>; 1571 1572let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1573def TCRETURNri : PPCEmitTimePseudo<(outs), (ins CTRRC:$dst, i32imm:$offset), 1574 "#TC_RETURNr $dst $offset", 1575 []>; 1576 1577let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 1578 Defs = [LR, R2], Uses = [CTR, RM], RST = 2 in { 1579 def BCTRL_LWZinto_toc: 1580 XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs), 1581 (ins (memri $D, $RA):$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB, 1582 [(PPCbctrl_load_toc iaddr:$addr)]>, Requires<[In32BitMode]>; 1583 1584} 1585 1586let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 1587 Defs = [LR, R2, RM], Uses = [CTR, RM], RST = 2 in { 1588 def BCTRL_LWZinto_toc_RM: 1589 XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs), 1590 (ins (memri $D, $RA):$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB, 1591 [(PPCbctrl_load_toc_rm iaddr:$addr)]>, Requires<[In32BitMode]>; 1592 1593} 1594 1595let isCodeGenOnly = 1, hasSideEffects = 0 in { 1596 1597let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 1598 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 1599def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1600 []>, Requires<[In32BitMode]>; 1601 1602let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1603 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1604def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$LI), 1605 "b $LI", IIC_BrB, 1606 []>; 1607 1608let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1609 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1610def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$LI), 1611 "ba $LI", IIC_BrB, 1612 []>; 1613 1614} 1615 1616// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 1617// is not. 1618let hasSideEffects = 1 in { 1619 let Defs = [CTR] in 1620 def EH_SjLj_SetJmp32 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 1621 "#EH_SJLJ_SETJMP32", 1622 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 1623 Requires<[In32BitMode]>; 1624} 1625 1626let hasSideEffects = 1, isBarrier = 1 in { 1627 let isTerminator = 1 in 1628 def EH_SjLj_LongJmp32 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 1629 "#EH_SJLJ_LONGJMP32", 1630 [(PPCeh_sjlj_longjmp addr:$buf)]>, 1631 Requires<[In32BitMode]>; 1632} 1633 1634// This pseudo is never removed from the function, as it serves as 1635// a terminator. Size is set to 0 to prevent the builtin assembler 1636// from emitting it. 1637let isBranch = 1, isTerminator = 1, Size = 0 in { 1638 def EH_SjLj_Setup : PPCEmitTimePseudo<(outs), (ins directbrtarget:$dst), 1639 "#EH_SjLj_Setup\t$dst", []>; 1640} 1641 1642// System call. 1643let PPC970_Unit = 7 in { 1644 def SC : SCForm<17, 1, 0, (outs), (ins i32imm:$LEV), 1645 "sc $LEV", IIC_BrB, [(PPCsc (i32 imm:$LEV))]>; 1646} 1647 1648// We mark SCV as having no scheduling model since it is only meant to be used 1649// as inline assembly. If we implement a builtin pattern for it we will need to 1650// add it to the P9 and P10 scheduling models. 1651let Predicates = [IsISA3_0], hasNoSchedulingInfo = 1 in { 1652 def SCV : SCForm<17, 0, 1, (outs), (ins i32imm:$LEV), 1653 "scv $LEV", IIC_BrB, []>; 1654} 1655 1656// Branch history rolling buffer. 1657def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB, 1658 [(PPCclrbhrb)]>, 1659 PPC970_DGroup_Single; 1660// The $dmy argument used for MFBHRBE is not needed; however, including 1661// it avoids automatic generation of PPCFastISel::fastEmit_i(), which 1662// interferes with necessary special handling (see PPCFastISel.cpp). 1663def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$RT), 1664 (ins u10imm:$imm, u10imm:$dmy), 1665 "mfbhrbe $RT, $imm", IIC_BrB, 1666 [(set i32:$RT, 1667 (PPCmfbhrbe imm:$imm, imm:$dmy))]>, 1668 PPC970_DGroup_First; 1669 1670def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$S), "rfebb $S", 1671 IIC_BrB, [(PPCrfebb (i32 imm:$S))]>, 1672 PPC970_DGroup_Single; 1673 1674def : InstAlias<"rfebb", (RFEBB 1)>; 1675 1676// DCB* instructions. 1677def DCBA : DCB_Form<758, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcba $addr", 1678 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$addr)]>, 1679 PPC970_DGroup_Single; 1680def DCBI : DCB_Form<470, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbi $addr", 1681 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$addr)]>, 1682 PPC970_DGroup_Single; 1683def DCBST : DCB_Form<54, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbst $addr", 1684 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$addr)]>, 1685 PPC970_DGroup_Single; 1686def DCBZ : DCB_Form<1014, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbz $addr", 1687 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$addr)]>, 1688 PPC970_DGroup_Single; 1689def DCBZL : DCB_Form<1014, 1, (outs), (ins (memrr $RA, $RB):$addr), "dcbzl $addr", 1690 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$addr)]>, 1691 PPC970_DGroup_Single; 1692 1693def DCBF : DCB_Form_hint<86, (outs), (ins u3imm:$TH, (memrr $RA, $RB):$addr), 1694 "dcbf $addr, $TH", IIC_LdStDCBF, []>, 1695 PPC970_DGroup_Single; 1696 1697let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in { 1698def DCBT : DCB_Form_hint<278, (outs), (ins u5imm:$TH, (memrr $RA, $RB):$addr), 1699 "dcbt $addr, $TH", IIC_LdStDCBF, []>, 1700 PPC970_DGroup_Single; 1701def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, (memrr $RA, $RB):$addr), 1702 "dcbtst $addr, $TH", IIC_LdStDCBF, []>, 1703 PPC970_DGroup_Single; 1704} // hasSideEffects = 0 1705 1706def ICBLC : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr), 1707 "icblc $CT, $addr", IIC_LdStStore>, Requires<[HasICBT]>; 1708def ICBLQ : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr), 1709 "icblq. $CT, $addr", IIC_LdStLoad>, Requires<[HasICBT]>; 1710def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr), 1711 "icbt $CT, $addr", IIC_LdStLoad>, Requires<[HasICBT]>; 1712def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr), 1713 "icbtls $CT, $addr", IIC_LdStLoad>, Requires<[HasICBT]>; 1714 1715def : Pat<(int_ppc_dcbt xoaddr:$dst), 1716 (DCBT 0, xoaddr:$dst)>; 1717def : Pat<(int_ppc_dcbtst xoaddr:$dst), 1718 (DCBTST 0, xoaddr:$dst)>; 1719def : Pat<(int_ppc_dcbf xoaddr:$dst), 1720 (DCBF 0, xoaddr:$dst)>; 1721def : Pat<(int_ppc_icbt xoaddr:$dst), 1722 (ICBT 0, xoaddr:$dst)>; 1723 1724def : Pat<(prefetch xoaddr:$dst, (i32 0), timm, (i32 1)), 1725 (DCBT 0, xoaddr:$dst)>; // data prefetch for loads 1726def : Pat<(prefetch xoaddr:$dst, (i32 1), timm, (i32 1)), 1727 (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores 1728def : Pat<(prefetch xoaddr:$dst, (i32 0), timm, (i32 0)), 1729 (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read) 1730 1731def : Pat<(int_ppc_dcbt_with_hint xoaddr:$dst, i32:$TH), 1732 (DCBT i32:$TH, xoaddr:$dst)>; 1733def : Pat<(int_ppc_dcbtst_with_hint xoaddr:$dst, i32:$TH), 1734 (DCBTST i32:$TH, xoaddr:$dst)>; 1735 1736// Atomic operations 1737// FIXME: some of these might be used with constant operands. This will result 1738// in constant materialization instructions that may be redundant. We currently 1739// clean this up in PPCMIPeephole with calls to 1740// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 1741// in the first place. 1742let Defs = [CR0] in { 1743 def ATOMIC_LOAD_ADD_I8 : PPCCustomInserterPseudo< 1744 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8", 1745 [(set i32:$dst, (atomic_load_add_8 ForceXForm:$ptr, i32:$incr))]>; 1746 def ATOMIC_LOAD_SUB_I8 : PPCCustomInserterPseudo< 1747 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8", 1748 [(set i32:$dst, (atomic_load_sub_8 ForceXForm:$ptr, i32:$incr))]>; 1749 def ATOMIC_LOAD_AND_I8 : PPCCustomInserterPseudo< 1750 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8", 1751 [(set i32:$dst, (atomic_load_and_8 ForceXForm:$ptr, i32:$incr))]>; 1752 def ATOMIC_LOAD_OR_I8 : PPCCustomInserterPseudo< 1753 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8", 1754 [(set i32:$dst, (atomic_load_or_8 ForceXForm:$ptr, i32:$incr))]>; 1755 def ATOMIC_LOAD_XOR_I8 : PPCCustomInserterPseudo< 1756 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8", 1757 [(set i32:$dst, (atomic_load_xor_8 ForceXForm:$ptr, i32:$incr))]>; 1758 def ATOMIC_LOAD_NAND_I8 : PPCCustomInserterPseudo< 1759 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8", 1760 [(set i32:$dst, (atomic_load_nand_8 ForceXForm:$ptr, i32:$incr))]>; 1761 def ATOMIC_LOAD_MIN_I8 : PPCCustomInserterPseudo< 1762 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I8", 1763 [(set i32:$dst, (atomic_load_min_8 ForceXForm:$ptr, i32:$incr))]>; 1764 def ATOMIC_LOAD_MAX_I8 : PPCCustomInserterPseudo< 1765 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I8", 1766 [(set i32:$dst, (atomic_load_max_8 ForceXForm:$ptr, i32:$incr))]>; 1767 def ATOMIC_LOAD_UMIN_I8 : PPCCustomInserterPseudo< 1768 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I8", 1769 [(set i32:$dst, (atomic_load_umin_8 ForceXForm:$ptr, i32:$incr))]>; 1770 def ATOMIC_LOAD_UMAX_I8 : PPCCustomInserterPseudo< 1771 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I8", 1772 [(set i32:$dst, (atomic_load_umax_8 ForceXForm:$ptr, i32:$incr))]>; 1773 def ATOMIC_LOAD_ADD_I16 : PPCCustomInserterPseudo< 1774 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16", 1775 [(set i32:$dst, (atomic_load_add_16 ForceXForm:$ptr, i32:$incr))]>; 1776 def ATOMIC_LOAD_SUB_I16 : PPCCustomInserterPseudo< 1777 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16", 1778 [(set i32:$dst, (atomic_load_sub_16 ForceXForm:$ptr, i32:$incr))]>; 1779 def ATOMIC_LOAD_AND_I16 : PPCCustomInserterPseudo< 1780 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16", 1781 [(set i32:$dst, (atomic_load_and_16 ForceXForm:$ptr, i32:$incr))]>; 1782 def ATOMIC_LOAD_OR_I16 : PPCCustomInserterPseudo< 1783 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16", 1784 [(set i32:$dst, (atomic_load_or_16 ForceXForm:$ptr, i32:$incr))]>; 1785 def ATOMIC_LOAD_XOR_I16 : PPCCustomInserterPseudo< 1786 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16", 1787 [(set i32:$dst, (atomic_load_xor_16 ForceXForm:$ptr, i32:$incr))]>; 1788 def ATOMIC_LOAD_NAND_I16 : PPCCustomInserterPseudo< 1789 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16", 1790 [(set i32:$dst, (atomic_load_nand_16 ForceXForm:$ptr, i32:$incr))]>; 1791 def ATOMIC_LOAD_MIN_I16 : PPCCustomInserterPseudo< 1792 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I16", 1793 [(set i32:$dst, (atomic_load_min_16 ForceXForm:$ptr, i32:$incr))]>; 1794 def ATOMIC_LOAD_MAX_I16 : PPCCustomInserterPseudo< 1795 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I16", 1796 [(set i32:$dst, (atomic_load_max_16 ForceXForm:$ptr, i32:$incr))]>; 1797 def ATOMIC_LOAD_UMIN_I16 : PPCCustomInserterPseudo< 1798 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I16", 1799 [(set i32:$dst, (atomic_load_umin_16 ForceXForm:$ptr, i32:$incr))]>; 1800 def ATOMIC_LOAD_UMAX_I16 : PPCCustomInserterPseudo< 1801 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I16", 1802 [(set i32:$dst, (atomic_load_umax_16 ForceXForm:$ptr, i32:$incr))]>; 1803 def ATOMIC_LOAD_ADD_I32 : PPCCustomInserterPseudo< 1804 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32", 1805 [(set i32:$dst, (atomic_load_add_32 ForceXForm:$ptr, i32:$incr))]>; 1806 def ATOMIC_LOAD_SUB_I32 : PPCCustomInserterPseudo< 1807 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32", 1808 [(set i32:$dst, (atomic_load_sub_32 ForceXForm:$ptr, i32:$incr))]>; 1809 def ATOMIC_LOAD_AND_I32 : PPCCustomInserterPseudo< 1810 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32", 1811 [(set i32:$dst, (atomic_load_and_32 ForceXForm:$ptr, i32:$incr))]>; 1812 def ATOMIC_LOAD_OR_I32 : PPCCustomInserterPseudo< 1813 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32", 1814 [(set i32:$dst, (atomic_load_or_32 ForceXForm:$ptr, i32:$incr))]>; 1815 def ATOMIC_LOAD_XOR_I32 : PPCCustomInserterPseudo< 1816 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32", 1817 [(set i32:$dst, (atomic_load_xor_32 ForceXForm:$ptr, i32:$incr))]>; 1818 def ATOMIC_LOAD_NAND_I32 : PPCCustomInserterPseudo< 1819 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32", 1820 [(set i32:$dst, (atomic_load_nand_32 ForceXForm:$ptr, i32:$incr))]>; 1821 def ATOMIC_LOAD_MIN_I32 : PPCCustomInserterPseudo< 1822 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I32", 1823 [(set i32:$dst, (atomic_load_min_32 ForceXForm:$ptr, i32:$incr))]>; 1824 def ATOMIC_LOAD_MAX_I32 : PPCCustomInserterPseudo< 1825 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I32", 1826 [(set i32:$dst, (atomic_load_max_32 ForceXForm:$ptr, i32:$incr))]>; 1827 def ATOMIC_LOAD_UMIN_I32 : PPCCustomInserterPseudo< 1828 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I32", 1829 [(set i32:$dst, (atomic_load_umin_32 ForceXForm:$ptr, i32:$incr))]>; 1830 def ATOMIC_LOAD_UMAX_I32 : PPCCustomInserterPseudo< 1831 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I32", 1832 [(set i32:$dst, (atomic_load_umax_32 ForceXForm:$ptr, i32:$incr))]>; 1833 1834 def ATOMIC_CMP_SWAP_I8 : PPCCustomInserterPseudo< 1835 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8", 1836 [(set i32:$dst, (atomic_cmp_swap_8 ForceXForm:$ptr, i32:$old, i32:$new))]>; 1837 def ATOMIC_CMP_SWAP_I16 : PPCCustomInserterPseudo< 1838 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new", 1839 [(set i32:$dst, (atomic_cmp_swap_16 ForceXForm:$ptr, i32:$old, i32:$new))]>; 1840 def ATOMIC_CMP_SWAP_I32 : PPCCustomInserterPseudo< 1841 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new", 1842 [(set i32:$dst, (atomic_cmp_swap_32 ForceXForm:$ptr, i32:$old, i32:$new))]>; 1843 1844 def ATOMIC_SWAP_I8 : PPCCustomInserterPseudo< 1845 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8", 1846 [(set i32:$dst, (atomic_swap_8 ForceXForm:$ptr, i32:$new))]>; 1847 def ATOMIC_SWAP_I16 : PPCCustomInserterPseudo< 1848 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16", 1849 [(set i32:$dst, (atomic_swap_16 ForceXForm:$ptr, i32:$new))]>; 1850 def ATOMIC_SWAP_I32 : PPCCustomInserterPseudo< 1851 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32", 1852 [(set i32:$dst, (atomic_swap_32 ForceXForm:$ptr, i32:$new))]>; 1853} 1854 1855def : Pat<(PPCatomicCmpSwap_8 ForceXForm:$ptr, i32:$old, i32:$new), 1856 (ATOMIC_CMP_SWAP_I8 ForceXForm:$ptr, i32:$old, i32:$new)>; 1857def : Pat<(PPCatomicCmpSwap_16 ForceXForm:$ptr, i32:$old, i32:$new), 1858 (ATOMIC_CMP_SWAP_I16 ForceXForm:$ptr, i32:$old, i32:$new)>; 1859 1860// Instructions to support atomic operations 1861let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { 1862def LBARX : XForm_1_memOp<31, 52, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1863 "lbarx $RST, $addr", IIC_LdStLWARX, []>, 1864 Requires<[HasPartwordAtomics]>; 1865 1866def LHARX : XForm_1_memOp<31, 116, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1867 "lharx $RST, $addr", IIC_LdStLWARX, []>, 1868 Requires<[HasPartwordAtomics]>; 1869 1870def LWARX : XForm_1_memOp<31, 20, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1871 "lwarx $RST, $addr", IIC_LdStLWARX, []>; 1872 1873// Instructions to support lock versions of atomics 1874// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 1875def LBARXL : XForm_1_memOp<31, 52, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1876 "lbarx $RST, $addr, 1", IIC_LdStLWARX, []>, isRecordForm, 1877 Requires<[HasPartwordAtomics]>; 1878 1879def LHARXL : XForm_1_memOp<31, 116, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1880 "lharx $RST, $addr, 1", IIC_LdStLWARX, []>, isRecordForm, 1881 Requires<[HasPartwordAtomics]>; 1882 1883def LWARXL : XForm_1_memOp<31, 20, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1884 "lwarx $RST, $addr, 1", IIC_LdStLWARX, []>, isRecordForm; 1885 1886// The atomic instructions use the destination register as well as the next one 1887// or two registers in order (modulo 31). 1888let hasExtraSrcRegAllocReq = 1 in 1889def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$RST), (ins gprc:$RA, u5imm:$RB), 1890 "lwat $RST, $RA, $RB", IIC_LdStLoad>, 1891 Requires<[IsISA3_0]>; 1892} 1893 1894let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in { 1895def STBCX : XForm_1_memOp<31, 694, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 1896 "stbcx. $RST, $addr", IIC_LdStSTWCX, []>, 1897 isRecordForm, Requires<[HasPartwordAtomics]>; 1898 1899def STHCX : XForm_1_memOp<31, 726, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 1900 "sthcx. $RST, $addr", IIC_LdStSTWCX, []>, 1901 isRecordForm, Requires<[HasPartwordAtomics]>; 1902 1903def STWCX : XForm_1_memOp<31, 150, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 1904 "stwcx. $RST, $addr", IIC_LdStSTWCX, []>, isRecordForm; 1905} 1906 1907let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 1908def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$RST, gprc:$RA, u5imm:$RB), 1909 "stwat $RST, $RA, $RB", IIC_LdStStore>, 1910 Requires<[IsISA3_0]>; 1911 1912let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 1913def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>; 1914 1915def TWI : DForm_base<3, (outs), (ins u5imm:$RST, gprc:$RA, s16imm:$D, variable_ops), 1916 "twi $RST, $RA, $D", IIC_IntTrapW, []>; 1917def TW : XForm_1<31, 4, (outs), (ins u5imm:$RST, gprc:$RA, gprc:$RB, variable_ops), 1918 "tw $RST, $RA, $RB", IIC_IntTrapW, []>; 1919def TDI : DForm_base<2, (outs), (ins u5imm:$RST, g8rc:$RA, s16imm:$D, variable_ops), 1920 "tdi $RST, $RA, $D", IIC_IntTrapD, []>; 1921def TD : XForm_1<31, 68, (outs), (ins u5imm:$RST, g8rc:$RA, g8rc:$RB, variable_ops), 1922 "td $RST, $RA, $RB", IIC_IntTrapD, []>; 1923 1924def POPCNTB : XForm_11<31, 122, (outs gprc:$RA), (ins gprc:$RST), 1925 "popcntb $RA, $RST", IIC_IntGeneral, 1926 [(set i32:$RA, (int_ppc_popcntb i32:$RST))]>; 1927 1928def CDTBCD : XForm_11<31, 282, (outs gprc:$RA), (ins gprc:$RST), 1929 "cdtbcd $RA, $RST", IIC_IntGeneral, []>; 1930def CBCDTD : XForm_11<31, 314, (outs gprc:$RA), (ins gprc:$RST), 1931 "cbcdtd $RA, $RST", IIC_IntGeneral, []>; 1932 1933def ADDG6S : XOForm_1<31, 74, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 1934 "addg6s $RT, $RA, $RB", IIC_IntGeneral, []>; 1935 1936//===----------------------------------------------------------------------===// 1937// PPC32 Load Instructions. 1938// 1939 1940// Unindexed (r+i) Loads. 1941let PPC970_Unit = 2 in { 1942def LBZ : DForm_1<34, (outs gprc:$RST), (ins (memri $D, $RA):$addr), 1943 "lbz $RST, $addr", IIC_LdStLoad, 1944 [(set i32:$RST, (zextloadi8 DForm:$addr))]>, ZExt32To64, 1945 SExt32To64; 1946def LHA : DForm_1<42, (outs gprc:$RST), (ins (memri $D, $RA):$addr), 1947 "lha $RST, $addr", IIC_LdStLHA, 1948 [(set i32:$RST, (sextloadi16 DForm:$addr))]>, 1949 PPC970_DGroup_Cracked, SExt32To64; 1950def LHZ : DForm_1<40, (outs gprc:$RST), (ins (memri $D, $RA):$addr), 1951 "lhz $RST, $addr", IIC_LdStLoad, 1952 [(set i32:$RST, (zextloadi16 DForm:$addr))]>, ZExt32To64, 1953 SExt32To64; 1954def LWZ : DForm_1<32, (outs gprc:$RST), (ins (memri $D, $RA):$addr), 1955 "lwz $RST, $addr", IIC_LdStLoad, 1956 [(set i32:$RST, (load DForm:$addr))]>, ZExt32To64; 1957 1958let Predicates = [HasFPU] in { 1959def LFS : DForm_1<48, (outs f4rc:$RST), (ins (memri $D, $RA):$addr), 1960 "lfs $RST, $addr", IIC_LdStLFD, 1961 [(set f32:$RST, (load DForm:$addr))]>; 1962def LFD : DForm_1<50, (outs f8rc:$RST), (ins (memri $D, $RA):$addr), 1963 "lfd $RST, $addr", IIC_LdStLFD, 1964 [(set f64:$RST, (load DForm:$addr))]>; 1965} 1966 1967 1968// Unindexed (r+i) Loads with Update (preinc). 1969let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { 1970def LBZU : DForm_1<35, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 1971 "lbzu $RST, $addr", IIC_LdStLoadUpd, 1972 []>, RegConstraint<"$RA = $ea_result">; 1973 1974def LHAU : DForm_1<43, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 1975 "lhau $RST, $addr", IIC_LdStLHAU, 1976 []>, RegConstraint<"$addr.reg = $ea_result">, 1977 NoEncode<"$ea_result">; 1978 1979def LHZU : DForm_1<41, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 1980 "lhzu $RST, $addr", IIC_LdStLoadUpd, 1981 []>, RegConstraint<"$addr.reg = $ea_result">, 1982 NoEncode<"$ea_result">; 1983 1984def LWZU : DForm_1<33, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 1985 "lwzu $RST, $addr", IIC_LdStLoadUpd, 1986 []>, RegConstraint<"$addr.reg = $ea_result">, 1987 NoEncode<"$ea_result">; 1988 1989let Predicates = [HasFPU] in { 1990def LFSU : DForm_1<49, (outs f4rc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 1991 "lfsu $RST, $addr", IIC_LdStLFDU, 1992 []>, RegConstraint<"$addr.reg = $ea_result">, 1993 NoEncode<"$ea_result">; 1994 1995def LFDU : DForm_1<51, (outs f8rc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 1996 "lfdu $RST, $addr", IIC_LdStLFDU, 1997 []>, RegConstraint<"$addr.reg = $ea_result">, 1998 NoEncode<"$ea_result">; 1999} 2000 2001 2002// Indexed (r+r) Loads with Update (preinc). 2003def LBZUX : XForm_1_memOp<31, 119, (outs gprc:$RST, ptr_rc_nor0:$ea_result), 2004 (ins (memrr $RA, $RB):$addr), 2005 "lbzux $RST, $addr", IIC_LdStLoadUpdX, 2006 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2007 NoEncode<"$ea_result">; 2008 2009def LHAUX : XForm_1_memOp<31, 375, (outs gprc:$RST, ptr_rc_nor0:$ea_result), 2010 (ins (memrr $RA, $RB):$addr), 2011 "lhaux $RST, $addr", IIC_LdStLHAUX, 2012 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2013 NoEncode<"$ea_result">; 2014 2015def LHZUX : XForm_1_memOp<31, 311, (outs gprc:$RST, ptr_rc_nor0:$ea_result), 2016 (ins (memrr $RA, $RB):$addr), 2017 "lhzux $RST, $addr", IIC_LdStLoadUpdX, 2018 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2019 NoEncode<"$ea_result">; 2020 2021def LWZUX : XForm_1_memOp<31, 55, (outs gprc:$RST, ptr_rc_nor0:$ea_result), 2022 (ins (memrr $RA, $RB):$addr), 2023 "lwzux $RST, $addr", IIC_LdStLoadUpdX, 2024 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2025 NoEncode<"$ea_result">; 2026 2027let Predicates = [HasFPU] in { 2028def LFSUX : XForm_1_memOp<31, 567, (outs f4rc:$RST, ptr_rc_nor0:$ea_result), 2029 (ins (memrr $RA, $RB):$addr), 2030 "lfsux $RST, $addr", IIC_LdStLFDUX, 2031 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2032 NoEncode<"$ea_result">; 2033 2034def LFDUX : XForm_1_memOp<31, 631, (outs f8rc:$RST, ptr_rc_nor0:$ea_result), 2035 (ins (memrr $RA, $RB):$addr), 2036 "lfdux $RST, $addr", IIC_LdStLFDUX, 2037 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2038 NoEncode<"$ea_result">; 2039} 2040} 2041} 2042 2043// Indexed (r+r) Loads. 2044// 2045let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { 2046def LBZX : XForm_1_memOp<31, 87, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2047 "lbzx $RST, $addr", IIC_LdStLoad, 2048 [(set i32:$RST, (zextloadi8 XForm:$addr))]>, ZExt32To64, 2049 SExt32To64; 2050def LHAX : XForm_1_memOp<31, 343, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2051 "lhax $RST, $addr", IIC_LdStLHA, 2052 [(set i32:$RST, (sextloadi16 XForm:$addr))]>, 2053 PPC970_DGroup_Cracked, SExt32To64; 2054def LHZX : XForm_1_memOp<31, 279, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2055 "lhzx $RST, $addr", IIC_LdStLoad, 2056 [(set i32:$RST, (zextloadi16 XForm:$addr))]>, ZExt32To64, 2057 SExt32To64; 2058def LWZX : XForm_1_memOp<31, 23, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2059 "lwzx $RST, $addr", IIC_LdStLoad, 2060 [(set i32:$RST, (load XForm:$addr))]>, ZExt32To64; 2061def LHBRX : XForm_1_memOp<31, 790, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2062 "lhbrx $RST, $addr", IIC_LdStLoad, 2063 [(set i32:$RST, (PPClbrx ForceXForm:$addr, i16))]>, ZExt32To64; 2064def LWBRX : XForm_1_memOp<31, 534, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2065 "lwbrx $RST, $addr", IIC_LdStLoad, 2066 [(set i32:$RST, (PPClbrx ForceXForm:$addr, i32))]>, ZExt32To64; 2067 2068let Predicates = [HasFPU] in { 2069def LFSX : XForm_25_memOp<31, 535, (outs f4rc:$RST), (ins (memrr $RA, $RB):$addr), 2070 "lfsx $RST, $addr", IIC_LdStLFD, 2071 [(set f32:$RST, (load XForm:$addr))]>; 2072def LFDX : XForm_25_memOp<31, 599, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr), 2073 "lfdx $RST, $addr", IIC_LdStLFD, 2074 [(set f64:$RST, (load XForm:$addr))]>; 2075 2076def LFIWAX : XForm_25_memOp<31, 855, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr), 2077 "lfiwax $RST, $addr", IIC_LdStLFD, 2078 [(set f64:$RST, (PPClfiwax ForceXForm:$addr))]>; 2079def LFIWZX : XForm_25_memOp<31, 887, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr), 2080 "lfiwzx $RST, $addr", IIC_LdStLFD, 2081 [(set f64:$RST, (PPClfiwzx ForceXForm:$addr))]>; 2082} 2083} 2084 2085// Load Multiple 2086let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in 2087def LMW : DForm_1<46, (outs gprc:$RST), (ins (memri $D, $RA):$src), 2088 "lmw $RST, $src", IIC_LdStLMW, []>; 2089 2090//===----------------------------------------------------------------------===// 2091// PPC32 Store Instructions. 2092// 2093 2094// Unindexed (r+i) Stores. 2095let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2096def STB : DForm_1<38, (outs), (ins gprc:$RST, (memri $D, $RA):$dst), 2097 "stb $RST, $dst", IIC_LdStStore, 2098 [(truncstorei8 i32:$RST, DForm:$dst)]>; 2099def STH : DForm_1<44, (outs), (ins gprc:$RST, (memri $D, $RA):$dst), 2100 "sth $RST, $dst", IIC_LdStStore, 2101 [(truncstorei16 i32:$RST, DForm:$dst)]>; 2102def STW : DForm_1<36, (outs), (ins gprc:$RST, (memri $D, $RA):$dst), 2103 "stw $RST, $dst", IIC_LdStStore, 2104 [(store i32:$RST, DForm:$dst)]>; 2105let Predicates = [HasFPU] in { 2106def STFS : DForm_1<52, (outs), (ins f4rc:$RST, (memri $D, $RA):$dst), 2107 "stfs $RST, $dst", IIC_LdStSTFD, 2108 [(store f32:$RST, DForm:$dst)]>; 2109def STFD : DForm_1<54, (outs), (ins f8rc:$RST, (memri $D, $RA):$dst), 2110 "stfd $RST, $dst", IIC_LdStSTFD, 2111 [(store f64:$RST, DForm:$dst)]>; 2112} 2113} 2114 2115// Unindexed (r+i) Stores with Update (preinc). 2116let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2117def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst), 2118 "stbu $RST, $dst", IIC_LdStSTU, []>, 2119 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2120def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst), 2121 "sthu $RST, $dst", IIC_LdStSTU, []>, 2122 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2123def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst), 2124 "stwu $RST, $dst", IIC_LdStSTU, []>, 2125 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2126let Predicates = [HasFPU] in { 2127def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$RST, (memri $D, $RA):$dst), 2128 "stfsu $RST, $dst", IIC_LdStSTFDU, []>, 2129 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2130def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$RST, (memri $D, $RA):$dst), 2131 "stfdu $RST, $dst", IIC_LdStSTFDU, []>, 2132 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2133} 2134} 2135 2136// Patterns to match the pre-inc stores. We can't put the patterns on 2137// the instruction definitions directly as ISel wants the address base 2138// and offset to be separate operands, not a single complex operand. 2139def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2140 (STBU $rS, iaddroff:$ptroff, $ptrreg)>; 2141def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2142 (STHU $rS, iaddroff:$ptroff, $ptrreg)>; 2143def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2144 (STWU $rS, iaddroff:$ptroff, $ptrreg)>; 2145def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2146 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>; 2147def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2148 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>; 2149 2150// Indexed (r+r) Stores. 2151let PPC970_Unit = 2 in { 2152def STBX : XForm_8_memOp<31, 215, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 2153 "stbx $RST, $addr", IIC_LdStStore, 2154 [(truncstorei8 i32:$RST, XForm:$addr)]>, 2155 PPC970_DGroup_Cracked; 2156def STHX : XForm_8_memOp<31, 407, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 2157 "sthx $RST, $addr", IIC_LdStStore, 2158 [(truncstorei16 i32:$RST, XForm:$addr)]>, 2159 PPC970_DGroup_Cracked; 2160def STWX : XForm_8_memOp<31, 151, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 2161 "stwx $RST, $addr", IIC_LdStStore, 2162 [(store i32:$RST, XForm:$addr)]>, 2163 PPC970_DGroup_Cracked; 2164 2165def STHBRX: XForm_8_memOp<31, 918, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 2166 "sthbrx $RST, $addr", IIC_LdStStore, 2167 [(PPCstbrx i32:$RST, ForceXForm:$addr, i16)]>, 2168 PPC970_DGroup_Cracked; 2169def STWBRX: XForm_8_memOp<31, 662, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 2170 "stwbrx $RST, $addr", IIC_LdStStore, 2171 [(PPCstbrx i32:$RST, ForceXForm:$addr, i32)]>, 2172 PPC970_DGroup_Cracked; 2173 2174let Predicates = [HasFPU] in { 2175def STFIWX: XForm_28_memOp<31, 983, (outs), (ins f8rc:$RST, (memrr $RA, $RB):$addr), 2176 "stfiwx $RST, $addr", IIC_LdStSTFD, 2177 [(PPCstfiwx f64:$RST, ForceXForm:$addr)]>; 2178 2179def STFSX : XForm_28_memOp<31, 663, (outs), (ins f4rc:$RST, (memrr $RA, $RB):$addr), 2180 "stfsx $RST, $addr", IIC_LdStSTFD, 2181 [(store f32:$RST, XForm:$addr)]>; 2182def STFDX : XForm_28_memOp<31, 727, (outs), (ins f8rc:$RST, (memrr $RA, $RB):$addr), 2183 "stfdx $RST, $addr", IIC_LdStSTFD, 2184 [(store f64:$RST, XForm:$addr)]>; 2185} 2186} 2187 2188// Indexed (r+r) Stores with Update (preinc). 2189let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2190def STBUX : XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 2191 (ins gprc:$RST, (memrr $RA, $RB):$addr), 2192 "stbux $RST, $addr", IIC_LdStSTUX, []>, 2193 RegConstraint<"$addr.ptrreg = $ea_res">, 2194 NoEncode<"$ea_res">, 2195 PPC970_DGroup_Cracked; 2196def STHUX : XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 2197 (ins gprc:$RST, (memrr $RA, $RB):$addr), 2198 "sthux $RST, $addr", IIC_LdStSTUX, []>, 2199 RegConstraint<"$addr.ptrreg = $ea_res">, 2200 NoEncode<"$ea_res">, 2201 PPC970_DGroup_Cracked; 2202def STWUX : XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 2203 (ins gprc:$RST, (memrr $RA, $RB):$addr), 2204 "stwux $RST, $addr", IIC_LdStSTUX, []>, 2205 RegConstraint<"$addr.ptrreg = $ea_res">, 2206 NoEncode<"$ea_res">, 2207 PPC970_DGroup_Cracked; 2208let Predicates = [HasFPU] in { 2209def STFSUX: XForm_8_memOp<31, 695, (outs ptr_rc_nor0:$ea_res), 2210 (ins f4rc:$RST, (memrr $RA, $RB):$addr), 2211 "stfsux $RST, $addr", IIC_LdStSTFDU, []>, 2212 RegConstraint<"$addr.ptrreg = $ea_res">, 2213 NoEncode<"$ea_res">, 2214 PPC970_DGroup_Cracked; 2215def STFDUX: XForm_8_memOp<31, 759, (outs ptr_rc_nor0:$ea_res), 2216 (ins f8rc:$RST, (memrr $RA, $RB):$addr), 2217 "stfdux $RST, $addr", IIC_LdStSTFDU, []>, 2218 RegConstraint<"$addr.ptrreg = $ea_res">, 2219 NoEncode<"$ea_res">, 2220 PPC970_DGroup_Cracked; 2221} 2222} 2223 2224// Patterns to match the pre-inc stores. We can't put the patterns on 2225// the instruction definitions directly as ISel wants the address base 2226// and offset to be separate operands, not a single complex operand. 2227def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2228 (STBUX $rS, $ptrreg, $ptroff)>; 2229def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2230 (STHUX $rS, $ptrreg, $ptroff)>; 2231def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2232 (STWUX $rS, $ptrreg, $ptroff)>; 2233let Predicates = [HasFPU] in { 2234def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2235 (STFSUX $rS, $ptrreg, $ptroff)>; 2236def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2237 (STFDUX $rS, $ptrreg, $ptroff)>; 2238} 2239 2240// Store Multiple 2241let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 2242def STMW : DForm_1<47, (outs), (ins gprc:$RST, (memri $D, $RA):$dst), 2243 "stmw $RST, $dst", IIC_LdStLMW, []>; 2244 2245def SYNC : XForm_24_sync<31, 598, (outs), (ins u2imm:$L), 2246 "sync $L", IIC_LdStSync, []>; 2247 2248let isCodeGenOnly = 1 in { 2249 def MSYNC : XForm_24_sync<31, 598, (outs), (ins), 2250 "msync", IIC_LdStSync, []> { 2251 let L = 0; 2252 } 2253} 2254 2255// We used to have EIEIO as value but E[0-9A-Z] is a reserved name 2256def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins), 2257 "eieio", IIC_LdStLoad, []>; 2258 2259def PseudoEIEIO : PPCEmitTimePseudo<(outs), (ins), "#PPCEIEIO", 2260 [(int_ppc_eieio)]>; 2261 2262def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>; 2263def : Pat<(int_ppc_iospace_sync), (SYNC 0)>, Requires<[HasSYNC]>; 2264def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>; 2265def : Pat<(int_ppc_iospace_lwsync), (SYNC 1)>, Requires<[HasSYNC]>; 2266def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2267def : Pat<(int_ppc_iospace_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2268def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2269def : Pat<(int_ppc_iospace_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2270def : Pat<(int_ppc_eieio), (PseudoEIEIO)>; 2271def : Pat<(int_ppc_iospace_eieio), (PseudoEIEIO)>; 2272 2273//===----------------------------------------------------------------------===// 2274// PPC32 Arithmetic Instructions. 2275// 2276 2277let PPC970_Unit = 1 in { // FXU Operations. 2278def ADDI : DForm_2<14, (outs gprc:$RST), (ins gprc_nor0:$RA, s16imm:$D), 2279 "addi $RST, $RA, $D", IIC_IntSimple, 2280 [(set i32:$RST, (add i32:$RA, imm32SExt16:$D))]>; 2281let BaseName = "addic" in { 2282let Defs = [CARRY] in 2283def ADDIC : DForm_2<12, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D), 2284 "addic $RST, $RA, $D", IIC_IntGeneral, 2285 [(set i32:$RST, (addc i32:$RA, imm32SExt16:$D))]>, 2286 RecFormRel, PPC970_DGroup_Cracked; 2287let Defs = [CARRY, CR0] in 2288def ADDIC_rec : DForm_2<13, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D), 2289 "addic. $RST, $RA, $D", IIC_IntGeneral, 2290 []>, isRecordForm, RecFormRel; 2291} 2292def ADDIS : DForm_2<15, (outs gprc:$RST), (ins gprc_nor0:$RA, s17imm:$D), 2293 "addis $RST, $RA, $D", IIC_IntSimple, 2294 [(set i32:$RST, (add i32:$RA, imm16ShiftedSExt:$D))]>; 2295let isCodeGenOnly = 1 in 2296def LA : DForm_2<14, (outs gprc:$RST), (ins gprc_nor0:$RA, s16imm:$D), 2297 "la $RST, $D($RA)", IIC_IntGeneral, 2298 [(set i32:$RST, (add i32:$RA, 2299 (PPClo tglobaladdr:$D, 0)))]>; 2300def MULLI : DForm_2< 7, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D), 2301 "mulli $RST, $RA, $D", IIC_IntMulLI, 2302 [(set i32:$RST, (mul i32:$RA, imm32SExt16:$D))]>; 2303let Defs = [CARRY] in 2304def SUBFIC : DForm_2< 8, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D), 2305 "subfic $RST, $RA, $D", IIC_IntGeneral, 2306 [(set i32:$RST, (subc imm32SExt16:$D, i32:$RA))]>; 2307 2308let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 2309 def LI : DForm_2_r0<14, (outs gprc:$RST), (ins s16imm:$D), 2310 "li $RST, $D", IIC_IntSimple, 2311 [(set i32:$RST, imm32SExt16:$D)]>, SExt32To64; 2312 def LIS : DForm_2_r0<15, (outs gprc:$RST), (ins s17imm:$D), 2313 "lis $RST, $D", IIC_IntSimple, 2314 [(set i32:$RST, imm16ShiftedSExt:$D)]>, SExt32To64; 2315} 2316} 2317 2318def : InstAlias<"li $rD, $imm", (ADDI gprc:$rD, ZERO, s16imm:$imm)>; 2319def : InstAlias<"lis $rD, $imm", (ADDIS gprc:$rD, ZERO, s17imm:$imm)>; 2320 2321let PPC970_Unit = 1 in { // FXU Operations. 2322let Defs = [CR0] in { 2323def ANDI_rec : DForm_4<28, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2324 "andi. $RA, $RST, $D", IIC_IntGeneral, 2325 [(set i32:$RA, (and i32:$RST, immZExt16:$D))]>, 2326 isRecordForm, ZExt32To64, SExt32To64; 2327def ANDIS_rec : DForm_4<29, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2328 "andis. $RA, $RST, $D", IIC_IntGeneral, 2329 [(set i32:$RA, (and i32:$RST, imm16ShiftedZExt:$D))]>, 2330 isRecordForm, ZExt32To64; 2331} 2332def ORI : DForm_4<24, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2333 "ori $RA, $RST, $D", IIC_IntSimple, 2334 [(set i32:$RA, (or i32:$RST, immZExt16:$D))]>; 2335def ORIS : DForm_4<25, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2336 "oris $RA, $RST, $D", IIC_IntSimple, 2337 [(set i32:$RA, (or i32:$RST, imm16ShiftedZExt:$D))]>; 2338def XORI : DForm_4<26, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2339 "xori $RA, $RST, $D", IIC_IntSimple, 2340 [(set i32:$RA, (xor i32:$RST, immZExt16:$D))]>; 2341def XORIS : DForm_4<27, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2342 "xoris $RA, $RST, $D", IIC_IntSimple, 2343 [(set i32:$RA, (xor i32:$RST, imm16ShiftedZExt:$D))]>; 2344 2345def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple, 2346 []>; 2347let isCodeGenOnly = 1 in { 2348// The POWER6 and POWER7 have special group-terminating nops. 2349def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins), 2350 "ori 1, 1, 0", IIC_IntSimple, []>; 2351def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins), 2352 "ori 2, 2, 0", IIC_IntSimple, []>; 2353} 2354 2355let isCompare = 1, hasSideEffects = 0 in { 2356 def CMPWI : DForm_5_ext<11, (outs crrc:$BF), (ins gprc:$RA, s16imm:$D), 2357 "cmpwi $BF, $RA, $D", IIC_IntCompare>; 2358 def CMPLWI : DForm_6_ext<10, (outs crrc:$BF), (ins gprc:$RA, u16imm:$D), 2359 "cmplwi $BF, $RA, $D", IIC_IntCompare>; 2360 def CMPRB : X_BF3_L1_RS5_RS5<31, 192, (outs crrc:$BF), 2361 (ins u1imm:$L, gprc:$RA, gprc:$RB), 2362 "cmprb $BF, $L, $RA, $RB", IIC_IntCompare, []>, 2363 Requires<[IsISA3_0]>; 2364} 2365} 2366 2367let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. 2368let isCommutable = 1 in { 2369defm NAND : XForm_6r<31, 476, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2370 "nand", "$RA, $RST, $RB", IIC_IntSimple, 2371 [(set i32:$RA, (not (and i32:$RST, i32:$RB)))]>; 2372defm AND : XForm_6r<31, 28, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2373 "and", "$RA, $RST, $RB", IIC_IntSimple, 2374 [(set i32:$RA, (and i32:$RST, i32:$RB))]>; 2375} // isCommutable 2376defm ANDC : XForm_6r<31, 60, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2377 "andc", "$RA, $RST, $RB", IIC_IntSimple, 2378 [(set i32:$RA, (and i32:$RST, (not i32:$RB)))]>; 2379let isCommutable = 1 in { 2380defm OR : XForm_6r<31, 444, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2381 "or", "$RA, $RST, $RB", IIC_IntSimple, 2382 [(set i32:$RA, (or i32:$RST, i32:$RB))]>; 2383defm NOR : XForm_6r<31, 124, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2384 "nor", "$RA, $RST, $RB", IIC_IntSimple, 2385 [(set i32:$RA, (not (or i32:$RST, i32:$RB)))]>; 2386} // isCommutable 2387defm ORC : XForm_6r<31, 412, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2388 "orc", "$RA, $RST, $RB", IIC_IntSimple, 2389 [(set i32:$RA, (or i32:$RST, (not i32:$RB)))]>; 2390let isCommutable = 1 in { 2391defm EQV : XForm_6r<31, 284, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2392 "eqv", "$RA, $RST, $RB", IIC_IntSimple, 2393 [(set i32:$RA, (not (xor i32:$RST, i32:$RB)))]>; 2394defm XOR : XForm_6r<31, 316, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2395 "xor", "$RA, $RST, $RB", IIC_IntSimple, 2396 [(set i32:$RA, (xor i32:$RST, i32:$RB))]>; 2397} // isCommutable 2398defm SLW : XForm_6r<31, 24, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2399 "slw", "$RA, $RST, $RB", IIC_IntGeneral, 2400 [(set i32:$RA, (PPCshl i32:$RST, i32:$RB))]>, ZExt32To64; 2401defm SRW : XForm_6r<31, 536, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2402 "srw", "$RA, $RST, $RB", IIC_IntGeneral, 2403 [(set i32:$RA, (PPCsrl i32:$RST, i32:$RB))]>, ZExt32To64; 2404defm SRAW : XForm_6rc<31, 792, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2405 "sraw", "$RA, $RST, $RB", IIC_IntShift, 2406 [(set i32:$RA, (PPCsra i32:$RST, i32:$RB))]>, SExt32To64; 2407} 2408 2409def : InstAlias<"mr $rA, $rB", (OR gprc:$rA, gprc:$rB, gprc:$rB)>; 2410def : InstAlias<"mr. $rA, $rB", (OR_rec gprc:$rA, gprc:$rB, gprc:$rB)>; 2411 2412def : InstAlias<"not $rA, $rS", (NOR gprc:$rA, gprc:$rS, gprc:$rS)>; 2413def : InstAlias<"not. $rA, $rS", (NOR_rec gprc:$rA, gprc:$rS, gprc:$rS)>; 2414 2415def : InstAlias<"nop", (ORI R0, R0, 0)>; 2416 2417let PPC970_Unit = 1 in { // FXU Operations. 2418let hasSideEffects = 0 in { 2419defm SRAWI : XForm_10rc<31, 824, (outs gprc:$RA), (ins gprc:$RST, u5imm:$RB), 2420 "srawi", "$RA, $RST, $RB", IIC_IntShift, 2421 [(set i32:$RA, (sra i32:$RST, (i32 imm:$RB)))]>, 2422 SExt32To64; 2423defm CNTLZW : XForm_11r<31, 26, (outs gprc:$RA), (ins gprc:$RST), 2424 "cntlzw", "$RA, $RST", IIC_IntGeneral, 2425 [(set i32:$RA, (ctlz i32:$RST))]>, ZExt32To64; 2426defm CNTTZW : XForm_11r<31, 538, (outs gprc:$RA), (ins gprc:$RST), 2427 "cnttzw", "$RA, $RST", IIC_IntGeneral, 2428 [(set i32:$RA, (cttz i32:$RST))]>, Requires<[IsISA3_0]>, 2429 ZExt32To64; 2430defm EXTSB : XForm_11r<31, 954, (outs gprc:$RA), (ins gprc:$RST), 2431 "extsb", "$RA, $RST", IIC_IntSimple, 2432 [(set i32:$RA, (sext_inreg i32:$RST, i8))]>, SExt32To64; 2433defm EXTSH : XForm_11r<31, 922, (outs gprc:$RA), (ins gprc:$RST), 2434 "extsh", "$RA, $RST", IIC_IntSimple, 2435 [(set i32:$RA, (sext_inreg i32:$RST, i16))]>, SExt32To64; 2436 2437let isCommutable = 1 in 2438def CMPB : XForm_6<31, 508, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2439 "cmpb $RA, $RST, $RB", IIC_IntGeneral, 2440 [(set i32:$RA, (PPCcmpb i32:$RST, i32:$RB))]>; 2441} 2442let isCompare = 1, hasSideEffects = 0 in { 2443 def CMPW : XForm_16_ext<31, 0, (outs crrc:$BF), (ins gprc:$RA, gprc:$RB), 2444 "cmpw $BF, $RA, $RB", IIC_IntCompare>; 2445 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$BF), (ins gprc:$RA, gprc:$RB), 2446 "cmplw $BF, $RA, $RB", IIC_IntCompare>; 2447} 2448} 2449let PPC970_Unit = 3, Predicates = [HasFPU] in { // FPU Operations. 2450let isCompare = 1, mayRaiseFPException = 1, hasSideEffects = 0 in { 2451 def FCMPUS : XForm_17<63, 0, (outs crrc:$BF), (ins f4rc:$RA, f4rc:$RB), 2452 "fcmpu $BF, $RA, $RB", IIC_FPCompare>; 2453 def FCMPOS : XForm_17<63, 32, (outs crrc:$BF), (ins f4rc:$RA, f4rc:$RB), 2454 "fcmpo $BF, $RA, $RB", IIC_FPCompare>; 2455 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 2456 def FCMPUD : XForm_17<63, 0, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB), 2457 "fcmpu $BF, $RA, $RB", IIC_FPCompare>; 2458 def FCMPOD : XForm_17<63, 32, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB), 2459 "fcmpo $BF, $RA, $RB", IIC_FPCompare>; 2460 } 2461} 2462 2463def FTDIV: XForm_17<63, 128, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB), 2464 "ftdiv $BF, $RA, $RB", IIC_FPCompare>; 2465def FTSQRT: XForm_17a<63, 160, (outs crrc:$BF), (ins f8rc:$RB), 2466 "ftsqrt $BF, $RB", IIC_FPCompare, 2467 [(set i32:$BF, (PPCftsqrt f64:$RB))]>; 2468 2469let mayRaiseFPException = 1, hasSideEffects = 0 in { 2470 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2471 defm FRIND : XForm_26r<63, 392, (outs f8rc:$RST), (ins f8rc:$RB), 2472 "frin", "$RST, $RB", IIC_FPGeneral, 2473 [(set f64:$RST, (any_fround f64:$RB))]>; 2474 defm FRINS : XForm_26r<63, 392, (outs f4rc:$RST), (ins f4rc:$RB), 2475 "frin", "$RST, $RB", IIC_FPGeneral, 2476 [(set f32:$RST, (any_fround f32:$RB))]>; 2477 2478 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2479 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$RST), (ins f8rc:$RB), 2480 "frip", "$RST, $RB", IIC_FPGeneral, 2481 [(set f64:$RST, (any_fceil f64:$RB))]>; 2482 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$RST), (ins f4rc:$RB), 2483 "frip", "$RST, $RB", IIC_FPGeneral, 2484 [(set f32:$RST, (any_fceil f32:$RB))]>; 2485 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2486 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$RST), (ins f8rc:$RB), 2487 "friz", "$RST, $RB", IIC_FPGeneral, 2488 [(set f64:$RST, (any_ftrunc f64:$RB))]>; 2489 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$RST), (ins f4rc:$RB), 2490 "friz", "$RST, $RB", IIC_FPGeneral, 2491 [(set f32:$RST, (any_ftrunc f32:$RB))]>; 2492 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2493 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$RST), (ins f8rc:$RB), 2494 "frim", "$RST, $RB", IIC_FPGeneral, 2495 [(set f64:$RST, (any_ffloor f64:$RB))]>; 2496 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$RST), (ins f4rc:$RB), 2497 "frim", "$RST, $RB", IIC_FPGeneral, 2498 [(set f32:$RST, (any_ffloor f32:$RB))]>; 2499} 2500 2501let Uses = [RM], mayRaiseFPException = 1, hasSideEffects = 0 in { 2502 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$RST), (ins f8rc:$RB), 2503 "fctiw", "$RST, $RB", IIC_FPGeneral, 2504 []>; 2505 defm FCTIWU : XForm_26r<63, 142, (outs f8rc:$RST), (ins f8rc:$RB), 2506 "fctiwu", "$RST, $RB", IIC_FPGeneral, 2507 []>; 2508 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$RST), (ins f8rc:$RB), 2509 "fctiwz", "$RST, $RB", IIC_FPGeneral, 2510 [(set f64:$RST, (PPCany_fctiwz f64:$RB))]>; 2511 2512 defm FRSP : XForm_26r<63, 12, (outs f4rc:$RST), (ins f8rc:$RB), 2513 "frsp", "$RST, $RB", IIC_FPGeneral, 2514 [(set f32:$RST, (any_fpround f64:$RB))]>; 2515 2516 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$RST), (ins f8rc:$RB), 2517 "fsqrt", "$RST, $RB", IIC_FPSqrtD, 2518 [(set f64:$RST, (any_fsqrt f64:$RB))]>; 2519 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$RST), (ins f4rc:$RB), 2520 "fsqrts", "$RST, $RB", IIC_FPSqrtS, 2521 [(set f32:$RST, (any_fsqrt f32:$RB))]>; 2522} 2523} 2524 2525def : Pat<(PPCfsqrt f64:$frA), (FSQRT $frA)>; 2526 2527/// Note that FMR is defined as pseudo-ops on the PPC970 because they are 2528/// often coalesced away and we don't want the dispatch group builder to think 2529/// that they will fill slots (which could cause the load of a LSU reject to 2530/// sneak into a d-group with a store). 2531let hasSideEffects = 0, Predicates = [HasFPU] in 2532defm FMR : XForm_26r<63, 72, (outs f4rc:$RST), (ins f4rc:$RB), 2533 "fmr", "$RST, $RB", IIC_FPGeneral, 2534 []>, // (set f32:$RST, f32:$RB) 2535 PPC970_Unit_Pseudo; 2536 2537let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations. 2538// These are artificially split into two different forms, for 4/8 byte FP. 2539defm FABSS : XForm_26r<63, 264, (outs f4rc:$RST), (ins f4rc:$RB), 2540 "fabs", "$RST, $RB", IIC_FPGeneral, 2541 [(set f32:$RST, (fabs f32:$RB))]>; 2542let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2543defm FABSD : XForm_26r<63, 264, (outs f8rc:$RST), (ins f8rc:$RB), 2544 "fabs", "$RST, $RB", IIC_FPGeneral, 2545 [(set f64:$RST, (fabs f64:$RB))]>; 2546defm FNABSS : XForm_26r<63, 136, (outs f4rc:$RST), (ins f4rc:$RB), 2547 "fnabs", "$RST, $RB", IIC_FPGeneral, 2548 [(set f32:$RST, (fneg (fabs f32:$RB)))]>; 2549let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2550defm FNABSD : XForm_26r<63, 136, (outs f8rc:$RST), (ins f8rc:$RB), 2551 "fnabs", "$RST, $RB", IIC_FPGeneral, 2552 [(set f64:$RST, (fneg (fabs f64:$RB)))]>; 2553defm FNEGS : XForm_26r<63, 40, (outs f4rc:$RST), (ins f4rc:$RB), 2554 "fneg", "$RST, $RB", IIC_FPGeneral, 2555 [(set f32:$RST, (fneg f32:$RB))]>; 2556let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2557defm FNEGD : XForm_26r<63, 40, (outs f8rc:$RST), (ins f8rc:$RB), 2558 "fneg", "$RST, $RB", IIC_FPGeneral, 2559 [(set f64:$RST, (fneg f64:$RB))]>; 2560 2561defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$RST), (ins f4rc:$RA, f4rc:$RB), 2562 "fcpsgn", "$RST, $RA, $RB", IIC_FPGeneral, 2563 [(set f32:$RST, (fcopysign f32:$RB, f32:$RA))]>; 2564let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2565defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB), 2566 "fcpsgn", "$RST, $RA, $RB", IIC_FPGeneral, 2567 [(set f64:$RST, (fcopysign f64:$RB, f64:$RA))]>; 2568 2569// Reciprocal estimates. 2570let mayRaiseFPException = 1 in { 2571defm FRE : XForm_26r<63, 24, (outs f8rc:$RST), (ins f8rc:$RB), 2572 "fre", "$RST, $RB", IIC_FPGeneral, 2573 [(set f64:$RST, (PPCfre f64:$RB))]>; 2574defm FRES : XForm_26r<59, 24, (outs f4rc:$RST), (ins f4rc:$RB), 2575 "fres", "$RST, $RB", IIC_FPGeneral, 2576 [(set f32:$RST, (PPCfre f32:$RB))]>; 2577defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$RST), (ins f8rc:$RB), 2578 "frsqrte", "$RST, $RB", IIC_FPGeneral, 2579 [(set f64:$RST, (PPCfrsqrte f64:$RB))]>; 2580defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$RST), (ins f4rc:$RB), 2581 "frsqrtes", "$RST, $RB", IIC_FPGeneral, 2582 [(set f32:$RST, (PPCfrsqrte f32:$RB))]>; 2583} 2584} 2585 2586// XL-Form instructions. condition register logical ops. 2587// 2588let hasSideEffects = 0 in 2589def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA), 2590 "mcrf $BF, $BFA", IIC_BrMCR>, 2591 PPC970_DGroup_First, PPC970_Unit_CRU; 2592 2593// FIXME: According to the ISA (section 2.5.1 of version 2.06), the 2594// condition-register logical instructions have preferred forms. Specifically, 2595// it is preferred that the bit specified by the BT field be in the same 2596// condition register as that specified by the bit BB. We might want to account 2597// for this via hinting the register allocator and anti-dep breakers, or we 2598// could constrain the register class to force this constraint and then loosen 2599// it during register allocation via convertToThreeAddress or some similar 2600// mechanism. 2601 2602let isCommutable = 1 in { 2603def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD), 2604 (ins crbitrc:$CRA, crbitrc:$CRB), 2605 "crand $CRD, $CRA, $CRB", IIC_BrCR, 2606 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>; 2607 2608def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD), 2609 (ins crbitrc:$CRA, crbitrc:$CRB), 2610 "crnand $CRD, $CRA, $CRB", IIC_BrCR, 2611 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>; 2612 2613def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD), 2614 (ins crbitrc:$CRA, crbitrc:$CRB), 2615 "cror $CRD, $CRA, $CRB", IIC_BrCR, 2616 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>; 2617 2618def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD), 2619 (ins crbitrc:$CRA, crbitrc:$CRB), 2620 "crxor $CRD, $CRA, $CRB", IIC_BrCR, 2621 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>; 2622 2623def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD), 2624 (ins crbitrc:$CRA, crbitrc:$CRB), 2625 "crnor $CRD, $CRA, $CRB", IIC_BrCR, 2626 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>; 2627def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD), 2628 (ins crbitrc:$CRA, crbitrc:$CRB), 2629 "creqv $CRD, $CRA, $CRB", IIC_BrCR, 2630 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>; 2631} // isCommutable 2632 2633let isCodeGenOnly = 1 in 2634def CRNOT : XLForm_1s<19, 33, (outs crbitrc:$CRD), (ins crbitrc:$CRA), 2635 "crnot $CRD, $CRA", IIC_BrCR, 2636 [(set i1:$CRD, (not i1:$CRA))]>; 2637 2638def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD), 2639 (ins crbitrc:$CRA, crbitrc:$CRB), 2640 "crandc $CRD, $CRA, $CRB", IIC_BrCR, 2641 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>; 2642 2643def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD), 2644 (ins crbitrc:$CRA, crbitrc:$CRB), 2645 "crorc $CRD, $CRA, $CRB", IIC_BrCR, 2646 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>; 2647 2648let isCodeGenOnly = 1 in { 2649let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 2650def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$CRD), (ins), 2651 "creqv $CRD, $CRD, $CRD", IIC_BrCR, 2652 [(set i1:$CRD, 1)]>; 2653 2654def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$CRD), (ins), 2655 "crxor $CRD, $CRD, $CRD", IIC_BrCR, 2656 [(set i1:$CRD, 0)]>; 2657} 2658 2659let Defs = [CR1EQ], CRD = 6 in { 2660def CR6SET : XLForm_1_ext<19, 289, (outs), (ins), 2661 "creqv 6, 6, 6", IIC_BrCR, 2662 [(PPCcr6set)]>; 2663 2664def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins), 2665 "crxor 6, 6, 6", IIC_BrCR, 2666 [(PPCcr6unset)]>; 2667} 2668} 2669 2670// XFX-Form instructions. Instructions that deal with SPRs. 2671// 2672 2673def MFSPR : XFXForm_1<31, 339, (outs gprc:$RST), (ins i32imm:$SPR), 2674 "mfspr $RST, $SPR", IIC_SprMFSPR>; 2675def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RST), 2676 "mtspr $SPR, $RST", IIC_SprMTSPR>; 2677 2678def MFTB : XFXForm_1<31, 371, (outs gprc:$RST), (ins i32imm:$SPR), 2679 "mftb $RST, $SPR", IIC_SprMFTB>; 2680 2681def MFPMR : XFXForm_1<31, 334, (outs gprc:$RST), (ins i32imm:$SPR), 2682 "mfpmr $RST, $SPR", IIC_SprMFPMR>; 2683 2684def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RST), 2685 "mtpmr $SPR, $RST", IIC_SprMTPMR>; 2686 2687 2688// A pseudo-instruction used to implement the read of the 64-bit cycle counter 2689// on a 32-bit target. 2690let hasSideEffects = 1 in 2691def ReadTB : PPCCustomInserterPseudo<(outs gprc:$lo, gprc:$hi), (ins), 2692 "#ReadTB", []>; 2693 2694let Uses = [CTR] in { 2695def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$RST), (ins), 2696 "mfctr $RST", IIC_SprMFSPR>, 2697 PPC970_DGroup_First, PPC970_Unit_FXU; 2698} 2699let Defs = [CTR], Pattern = [(PPCmtctr i32:$RST)] in { 2700def MTCTR : XFXForm_1_ext<31, 467, 9, (outs), (ins gprc:$RST), 2701 "mtctr $RST", IIC_SprMTSPR>, 2702 PPC970_DGroup_First, PPC970_Unit_FXU; 2703} 2704let hasSideEffects = 1, isCodeGenOnly = 1, isNotDuplicable = 1, Defs = [CTR] in { 2705let Pattern = [(int_set_loop_iterations i32:$RST)] in 2706def MTCTRloop : XFXForm_1_ext<31, 467, 9, (outs), (ins gprc:$RST), 2707 "mtctr $RST", IIC_SprMTSPR>, 2708 PPC970_DGroup_First, PPC970_Unit_FXU; 2709} 2710 2711let hasSideEffects = 1, hasNoSchedulingInfo = 1, isNotDuplicable = 1, Uses = [CTR], Defs = [CTR] in 2712def DecreaseCTRloop : PPCEmitTimePseudo<(outs crbitrc:$rT), (ins i32imm:$stride), 2713 "#DecreaseCTRloop", [(set i1:$rT, (int_loop_decrement (i32 imm:$stride)))]>; 2714 2715let hasSideEffects = 0 in { 2716let Defs = [LR] in { 2717def MTLR : XFXForm_1_ext<31, 467, 8, (outs), (ins gprc:$RST), 2718 "mtlr $RST", IIC_SprMTSPR>, 2719 PPC970_DGroup_First, PPC970_Unit_FXU; 2720} 2721let Uses = [LR] in { 2722def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$RST), (ins), 2723 "mflr $RST", IIC_SprMFSPR>, 2724 PPC970_DGroup_First, PPC970_Unit_FXU; 2725} 2726} 2727 2728let hasSideEffects = 1 in { 2729 def MTUDSCR : XFXForm_1_ext<31, 467, 3, (outs), (ins gprc:$RST), 2730 "mtspr 3, $RST", IIC_SprMTSPR>, 2731 PPC970_DGroup_Single, PPC970_Unit_FXU; 2732 def MFUDSCR : XFXForm_1_ext<31, 339, 3, (outs gprc:$RST), (ins), 2733 "mfspr $RST, 3", IIC_SprMFSPR>, 2734 PPC970_DGroup_First, PPC970_Unit_FXU; 2735} 2736 2737// Disable these alias on AIX since they are not supported. 2738let Predicates = [ModernAs] in { 2739// Aliases for moving to/from dscr to mtspr/mfspr 2740def : InstAlias<"mtudscr $Rx", (MTUDSCR gprc:$Rx)>; 2741def : InstAlias<"mfudscr $Rx", (MFUDSCR gprc:$Rx)>; 2742} 2743 2744let isCodeGenOnly = 1 in { 2745 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed 2746 // like a GPR on the PPC970. As such, copies in and out have the same 2747 // performance characteristics as an OR instruction. 2748 def MTVRSAVE : XFXForm_1_ext<31, 467, 256, (outs), (ins gprc:$RST), 2749 "mtspr 256, $RST", IIC_IntGeneral>, 2750 PPC970_DGroup_Single, PPC970_Unit_FXU; 2751 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$RST), (ins), 2752 "mfspr $RST, 256", IIC_IntGeneral>, 2753 PPC970_DGroup_First, PPC970_Unit_FXU; 2754 2755 def MTVRSAVEv : XFXForm_1_ext<31, 467, 256, 2756 (outs VRSAVERC:$SPR), (ins gprc:$RST), 2757 "mtspr 256, $RST", IIC_IntGeneral>, 2758 PPC970_DGroup_Single, PPC970_Unit_FXU; 2759 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$RST), 2760 (ins VRSAVERC:$SPR), 2761 "mfspr $RST, 256", IIC_IntGeneral>, 2762 PPC970_DGroup_First, PPC970_Unit_FXU; 2763} 2764 2765// Aliases for mtvrsave/mfvrsave to mfspr/mtspr. 2766def : InstAlias<"mtvrsave $rS", (MTVRSAVE gprc:$rS)>; 2767def : InstAlias<"mfvrsave $rS", (MFVRSAVE gprc:$rS)>; 2768 2769let hasSideEffects = 0 in { 2770// mtocrf's input needs to be prepared by shifting by an amount dependent 2771// on the cr register selected. Thus, post-ra anti-dep breaking must not 2772// later change that register assignment. 2773let hasExtraDefRegAllocReq = 1 in { 2774def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$RST), 2775 "mtocrf $FXM, $RST", IIC_BrMCRX>, 2776 PPC970_DGroup_First, PPC970_Unit_CRU; 2777 2778// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 2779// is dependent on the cr fields being set. 2780def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$RST), 2781 "mtcrf $FXM, $RST", IIC_BrMCRX>, 2782 PPC970_MicroCode, PPC970_Unit_CRU; 2783} // hasExtraDefRegAllocReq = 1 2784 2785// mfocrf's input needs to be prepared by shifting by an amount dependent 2786// on the cr register selected. Thus, post-ra anti-dep breaking must not 2787// later change that register assignment. 2788let hasExtraSrcRegAllocReq = 1 in { 2789def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$RST), (ins crbitm:$FXM), 2790 "mfocrf $RST, $FXM", IIC_SprMFCRF>, 2791 PPC970_DGroup_First, PPC970_Unit_CRU; 2792 2793// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 2794// is dependent on the cr fields being copied. 2795def MFCR : XFXForm_3<31, 19, (outs gprc:$RT), (ins), 2796 "mfcr $RT", IIC_SprMFCR>, 2797 PPC970_MicroCode, PPC970_Unit_CRU; 2798} // hasExtraSrcRegAllocReq = 1 2799 2800def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins), 2801 "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>; 2802} // hasSideEffects = 0 2803 2804def : InstAlias<"mtcr $rA", (MTCRF 255, gprc:$rA)>; 2805 2806let Predicates = [HasFPU] in { 2807// Custom inserter instruction to perform FADD in round-to-zero mode. 2808let Uses = [RM], mayRaiseFPException = 1 in { 2809 def FADDrtz: PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "", 2810 [(set f64:$FRT, (PPCany_faddrtz f64:$FRA, f64:$FRB))]>; 2811} 2812 2813// The above pseudo gets expanded to make use of the following instructions 2814// to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level. 2815 2816// When FM is 30/31, we are setting the 62/63 bit of FPSCR, the implicit-def 2817// RM should be set. 2818let hasSideEffects = 1, Defs = [RM] in { 2819def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), 2820 "mtfsb0 $FM", IIC_IntMTFSB0, 2821 [(int_ppc_mtfsb0 timm:$FM)]>, 2822 PPC970_DGroup_Single, PPC970_Unit_FPU; 2823def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), 2824 "mtfsb1 $FM", IIC_IntMTFSB0, 2825 [(int_ppc_mtfsb1 timm:$FM)]>, 2826 PPC970_DGroup_Single, PPC970_Unit_FPU; 2827} 2828 2829let Defs = [RM], hasSideEffects = 1 in { 2830 let isCodeGenOnly = 1 in 2831 def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$RT), 2832 "mtfsf $FM, $RT", IIC_IntMTFSB0, 2833 [(int_ppc_mtfsf timm:$FM, f64:$RT)]>, 2834 PPC970_DGroup_Single, PPC970_Unit_FPU; 2835} 2836let Uses = [RM], hasSideEffects = 1 in { 2837 def MFFS : XForm_42<63, 583, (outs f8rc:$RST), (ins), 2838 "mffs $RST", IIC_IntMFFS, 2839 [(set f64:$RST, (PPCmffs))]>, 2840 PPC970_DGroup_Single, PPC970_Unit_FPU; 2841 2842 let Defs = [CR1] in 2843 def MFFS_rec : XForm_42<63, 583, (outs f8rc:$RST), (ins), 2844 "mffs. $RST", IIC_IntMFFS, []>, isRecordForm; 2845 2846 def MFFSCE : X_FRT5_XO2_XO3_XO10<63, 0, 1, 583, (outs f8rc:$RST), (ins), 2847 "mffsce $RST", IIC_IntMFFS, []>, 2848 PPC970_DGroup_Single, PPC970_Unit_FPU; 2849 2850 def MFFSCDRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 4, 583, (outs f8rc:$RST), 2851 (ins f8rc:$FRB), "mffscdrn $RST, $FRB", 2852 IIC_IntMFFS, []>, 2853 PPC970_DGroup_Single, PPC970_Unit_FPU; 2854 2855 def MFFSCDRNI : X_FRT5_XO2_XO3_DRM3_XO10<63, 2, 5, 583, (outs f8rc:$RST), 2856 (ins u3imm:$DRM), 2857 "mffscdrni $RST, $DRM", 2858 IIC_IntMFFS, []>, 2859 PPC970_DGroup_Single, PPC970_Unit_FPU; 2860 2861 def MFFSCRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 6, 583, (outs f8rc:$RST), 2862 (ins f8rc:$FRB), "mffscrn $RST, $FRB", 2863 IIC_IntMFFS, []>, 2864 PPC970_DGroup_Single, PPC970_Unit_FPU; 2865 2866 def MFFSCRNI : X_FRT5_XO2_XO3_RM2_X10<63, 2, 7, 583, (outs f8rc:$RST), 2867 (ins u2imm:$RM), "mffscrni $RST, $RM", 2868 IIC_IntMFFS, []>, 2869 PPC970_DGroup_Single, PPC970_Unit_FPU; 2870 2871 def MFFSL : X_FRT5_XO2_XO3_XO10<63, 3, 0, 583, (outs f8rc:$RST), (ins), 2872 "mffsl $RST", IIC_IntMFFS, []>, 2873 PPC970_DGroup_Single, PPC970_Unit_FPU; 2874} 2875} 2876 2877let Predicates = [IsISA3_0] in { 2878def MODSW : XForm_8<31, 779, (outs gprc:$RST), (ins gprc:$RA, gprc:$RB), 2879 "modsw $RST, $RA, $RB", IIC_IntDivW, 2880 [(set i32:$RST, (srem i32:$RA, i32:$RB))]>; 2881def MODUW : XForm_8<31, 267, (outs gprc:$RST), (ins gprc:$RA, gprc:$RB), 2882 "moduw $RST, $RA, $RB", IIC_IntDivW, 2883 [(set i32:$RST, (urem i32:$RA, i32:$RB))]>; 2884let hasSideEffects = 1 in 2885def ADDEX : Z23Form_RTAB5_CY2<31, 170, (outs gprc:$RT), 2886 (ins gprc:$RA, gprc:$RB, u2imm:$CY), 2887 "addex $RT, $RA, $RB, $CY", IIC_IntGeneral, []>; 2888} 2889 2890let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. 2891// XO-Form instructions. Arithmetic instructions that can set overflow bit 2892let isCommutable = 1 in 2893defm ADD4 : XOForm_1rx<31, 266, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2894 "add", "$RT, $RA, $RB", IIC_IntSimple, 2895 [(set i32:$RT, (add i32:$RA, i32:$RB))]>; 2896let isCodeGenOnly = 1 in 2897def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$RT), (ins gprc:$RA, tlsreg32:$RB), 2898 "add $RT, $RA, $RB", IIC_IntSimple, 2899 [(set i32:$RT, (add i32:$RA, tglobaltlsaddr:$RB))]>; 2900let isCommutable = 1 in 2901defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2902 "addc", "$RT, $RA, $RB", IIC_IntGeneral, 2903 [(set i32:$RT, (addc i32:$RA, i32:$RB))]>, 2904 PPC970_DGroup_Cracked; 2905 2906defm DIVW : XOForm_1rcr<31, 491, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2907 "divw", "$RT, $RA, $RB", IIC_IntDivW, 2908 [(set i32:$RT, (sdiv i32:$RA, i32:$RB))]>; 2909defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2910 "divwu", "$RT, $RA, $RB", IIC_IntDivW, 2911 [(set i32:$RT, (udiv i32:$RA, i32:$RB))]>; 2912defm DIVWE : XOForm_1rcr<31, 427, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2913 "divwe", "$RT, $RA, $RB", IIC_IntDivW, 2914 [(set i32:$RT, (int_ppc_divwe gprc:$RA, gprc:$RB))]>, 2915 Requires<[HasExtDiv]>; 2916defm DIVWEU : XOForm_1rcr<31, 395, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2917 "divweu", "$RT, $RA, $RB", IIC_IntDivW, 2918 [(set i32:$RT, (int_ppc_divweu gprc:$RA, gprc:$RB))]>, 2919 Requires<[HasExtDiv]>; 2920let isCommutable = 1 in { 2921defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2922 "mulhw", "$RT, $RA, $RB", IIC_IntMulHW, 2923 [(set i32:$RT, (mulhs i32:$RA, i32:$RB))]>; 2924defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2925 "mulhwu", "$RT, $RA, $RB", IIC_IntMulHWU, 2926 [(set i32:$RT, (mulhu i32:$RA, i32:$RB))]>; 2927defm MULLW : XOForm_1rx<31, 235, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2928 "mullw", "$RT, $RA, $RB", IIC_IntMulHW, 2929 [(set i32:$RT, (mul i32:$RA, i32:$RB))]>; 2930} // isCommutable 2931defm SUBF : XOForm_1rx<31, 40, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2932 "subf", "$RT, $RA, $RB", IIC_IntGeneral, 2933 [(set i32:$RT, (sub i32:$RB, i32:$RA))]>; 2934defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2935 "subfc", "$RT, $RA, $RB", IIC_IntGeneral, 2936 [(set i32:$RT, (subc i32:$RB, i32:$RA))]>, 2937 PPC970_DGroup_Cracked; 2938defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$RT), (ins gprc:$RA), 2939 "neg", "$RT, $RA", IIC_IntSimple, 2940 [(set i32:$RT, (ineg i32:$RA))]>; 2941let Uses = [CARRY] in { 2942let isCommutable = 1 in 2943defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2944 "adde", "$RT, $RA, $RB", IIC_IntGeneral, 2945 [(set i32:$RT, (adde i32:$RA, i32:$RB))]>; 2946defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$RT), (ins gprc:$RA), 2947 "addme", "$RT, $RA", IIC_IntGeneral, 2948 [(set i32:$RT, (adde i32:$RA, -1))]>; 2949defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$RT), (ins gprc:$RA), 2950 "addze", "$RT, $RA", IIC_IntGeneral, 2951 [(set i32:$RT, (adde i32:$RA, 0))]>; 2952defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2953 "subfe", "$RT, $RA, $RB", IIC_IntGeneral, 2954 [(set i32:$RT, (sube i32:$RB, i32:$RA))]>; 2955defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$RT), (ins gprc:$RA), 2956 "subfme", "$RT, $RA", IIC_IntGeneral, 2957 [(set i32:$RT, (sube -1, i32:$RA))]>; 2958defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$RT), (ins gprc:$RA), 2959 "subfze", "$RT, $RA", IIC_IntGeneral, 2960 [(set i32:$RT, (sube 0, i32:$RA))]>; 2961} 2962} 2963 2964def : InstAlias<"sub $rA, $rB, $rC", (SUBF gprc:$rA, gprc:$rC, gprc:$rB)>; 2965def : InstAlias<"sub. $rA, $rB, $rC", (SUBF_rec gprc:$rA, gprc:$rC, gprc:$rB)>; 2966def : InstAlias<"subc $rA, $rB, $rC", (SUBFC gprc:$rA, gprc:$rC, gprc:$rB)>; 2967def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC_rec gprc:$rA, gprc:$rC, gprc:$rB)>; 2968 2969// A-Form instructions. Most of the instructions executed in the FPU are of 2970// this type. 2971// 2972let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations. 2973let mayRaiseFPException = 1, Uses = [RM] in { 2974let isCommutable = 1 in { 2975 defm FMADD : AForm_1r<63, 29, 2976 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2977 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2978 [(set f64:$FRT, (any_fma f64:$FRA, f64:$FRC, f64:$FRB))]>; 2979 defm FMADDS : AForm_1r<59, 29, 2980 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2981 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2982 [(set f32:$FRT, (any_fma f32:$FRA, f32:$FRC, f32:$FRB))]>; 2983 defm FMSUB : AForm_1r<63, 28, 2984 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2985 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2986 [(set f64:$FRT, 2987 (any_fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>; 2988 defm FMSUBS : AForm_1r<59, 28, 2989 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2990 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2991 [(set f32:$FRT, 2992 (any_fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>; 2993 defm FNMADD : AForm_1r<63, 31, 2994 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2995 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2996 [(set f64:$FRT, 2997 (fneg (any_fma f64:$FRA, f64:$FRC, f64:$FRB)))]>; 2998 defm FNMADDS : AForm_1r<59, 31, 2999 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3000 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3001 [(set f32:$FRT, 3002 (fneg (any_fma f32:$FRA, f32:$FRC, f32:$FRB)))]>; 3003 defm FNMSUB : AForm_1r<63, 30, 3004 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3005 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 3006 [(set f64:$FRT, (fneg (any_fma f64:$FRA, f64:$FRC, 3007 (fneg f64:$FRB))))]>; 3008 defm FNMSUBS : AForm_1r<59, 30, 3009 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3010 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3011 [(set f32:$FRT, (fneg (any_fma f32:$FRA, f32:$FRC, 3012 (fneg f32:$FRB))))]>; 3013} // isCommutable 3014} 3015// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 3016// having 4 of these, force the comparison to always be an 8-byte double (code 3017// should use an FMRSD if the input comparison value really wants to be a float) 3018// and 4/8 byte forms for the result and operand type.. 3019let Interpretation64Bit = 1, isCodeGenOnly = 1 in 3020defm FSELD : AForm_1r<63, 23, 3021 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3022 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3023 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>; 3024defm FSELS : AForm_1r<63, 23, 3025 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3026 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3027 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>; 3028let Uses = [RM], mayRaiseFPException = 1 in { 3029 let isCommutable = 1 in { 3030 defm FADD : AForm_2r<63, 21, 3031 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3032 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub, 3033 [(set f64:$FRT, (any_fadd f64:$FRA, f64:$FRB))]>; 3034 defm FADDS : AForm_2r<59, 21, 3035 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3036 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral, 3037 [(set f32:$FRT, (any_fadd f32:$FRA, f32:$FRB))]>; 3038 } // isCommutable 3039 defm FDIV : AForm_2r<63, 18, 3040 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3041 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD, 3042 [(set f64:$FRT, (any_fdiv f64:$FRA, f64:$FRB))]>; 3043 defm FDIVS : AForm_2r<59, 18, 3044 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3045 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS, 3046 [(set f32:$FRT, (any_fdiv f32:$FRA, f32:$FRB))]>; 3047 let isCommutable = 1 in { 3048 defm FMUL : AForm_3r<63, 25, 3049 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC), 3050 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused, 3051 [(set f64:$FRT, (any_fmul f64:$FRA, f64:$FRC))]>; 3052 defm FMULS : AForm_3r<59, 25, 3053 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC), 3054 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral, 3055 [(set f32:$FRT, (any_fmul f32:$FRA, f32:$FRC))]>; 3056 } // isCommutable 3057 defm FSUB : AForm_2r<63, 20, 3058 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3059 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub, 3060 [(set f64:$FRT, (any_fsub f64:$FRA, f64:$FRB))]>; 3061 defm FSUBS : AForm_2r<59, 20, 3062 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3063 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral, 3064 [(set f32:$FRT, (any_fsub f32:$FRA, f32:$FRB))]>; 3065 } 3066} 3067 3068let hasSideEffects = 0 in { 3069let PPC970_Unit = 1 in { // FXU Operations. 3070 let isSelect = 1 in 3071 def ISEL : AForm_4<31, 15, 3072 (outs gprc:$RT), (ins gprc_nor0:$RA, gprc:$RB, crbitrc:$COND), 3073 "isel $RT, $RA, $RB, $COND", IIC_IntISEL, 3074 []>; 3075} 3076 3077let PPC970_Unit = 1 in { // FXU Operations. 3078// M-Form instructions. rotate and mask instructions. 3079// 3080let isCommutable = 1 in { 3081// RLWIMI can be commuted if the rotate amount is zero. 3082defm RLWIMI : MForm_2r<20, (outs gprc:$RA), 3083 (ins gprc:$RAi, gprc:$RS, u5imm:$SH, u5imm:$MB, 3084 u5imm:$ME), "rlwimi", "$RA, $RS, $SH, $MB, $ME", 3085 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 3086 RegConstraint<"$RAi = $RA">, NoEncode<"$RAi">; 3087} 3088let BaseName = "rlwinm" in { 3089def RLWINM : MForm_2<21, 3090 (outs gprc:$RA), (ins gprc:$RS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 3091 "rlwinm $RA, $RS, $SH, $MB, $ME", IIC_IntGeneral, 3092 []>, RecFormRel; 3093let Defs = [CR0] in 3094def RLWINM_rec : MForm_2<21, 3095 (outs gprc:$RA), (ins gprc:$RS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 3096 "rlwinm. $RA, $RS, $SH, $MB, $ME", IIC_IntGeneral, 3097 []>, isRecordForm, RecFormRel, PPC970_DGroup_Cracked; 3098} 3099defm RLWNM : MForm_1r<23, (outs gprc:$RA), 3100 (ins gprc:$RS, gprc:$RB, u5imm:$MB, u5imm:$ME), 3101 "rlwnm", "$RA, $RS, $RB, $MB, $ME", IIC_IntGeneral, 3102 []>; 3103} 3104} // hasSideEffects = 0 3105 3106//===----------------------------------------------------------------------===// 3107// PowerPC Instruction Patterns 3108// 3109 3110// Arbitrary immediate support. Implement in terms of LIS/ORI. 3111def : Pat<(i32 imm:$imm), 3112 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 3113 3114// Implement the 'not' operation with the NOR instruction. 3115def i32not : OutPatFrag<(ops node:$in), 3116 (NOR $in, $in)>; 3117def : Pat<(not i32:$in), 3118 (i32not $in)>; 3119 3120// ADD an arbitrary immediate. 3121def : Pat<(add i32:$in, imm:$imm), 3122 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 3123// OR an arbitrary immediate. 3124def : Pat<(or i32:$in, imm:$imm), 3125 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 3126// XOR an arbitrary immediate. 3127def : Pat<(xor i32:$in, imm:$imm), 3128 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 3129// SUBFIC 3130def : Pat<(sub imm32SExt16:$imm, i32:$in), 3131 (SUBFIC $in, imm:$imm)>; 3132 3133// SHL/SRL 3134def : Pat<(shl i32:$in, (i32 imm:$imm)), 3135 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>; 3136def : Pat<(srl i32:$in, (i32 imm:$imm)), 3137 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>; 3138 3139// ROTL 3140def : Pat<(rotl i32:$in, i32:$sh), 3141 (RLWNM $in, $sh, 0, 31)>; 3142def : Pat<(rotl i32:$in, (i32 imm:$imm)), 3143 (RLWINM $in, imm:$imm, 0, 31)>; 3144 3145// RLWNM 3146def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm), 3147 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 3148 3149// Calls 3150def : Pat<(PPCcall (i32 tglobaladdr:$dst)), 3151 (BL tglobaladdr:$dst)>; 3152 3153def : Pat<(PPCcall (i32 texternalsym:$dst)), 3154 (BL texternalsym:$dst)>; 3155 3156def : Pat<(PPCcall_rm (i32 tglobaladdr:$dst)), 3157 (BL_RM tglobaladdr:$dst)>; 3158 3159def : Pat<(PPCcall_rm (i32 texternalsym:$dst)), 3160 (BL_RM texternalsym:$dst)>; 3161 3162// Calls for AIX only 3163def : Pat<(PPCcall (i32 mcsym:$dst)), 3164 (BL mcsym:$dst)>; 3165 3166def : Pat<(PPCcall_nop (i32 mcsym:$dst)), 3167 (BL_NOP mcsym:$dst)>; 3168 3169def : Pat<(PPCcall_nop (i32 texternalsym:$dst)), 3170 (BL_NOP texternalsym:$dst)>; 3171 3172def : Pat<(PPCcall_rm (i32 mcsym:$dst)), 3173 (BL_RM mcsym:$dst)>; 3174 3175def : Pat<(PPCcall_nop_rm (i32 mcsym:$dst)), 3176 (BL_NOP_RM mcsym:$dst)>; 3177 3178def : Pat<(PPCcall_nop_rm (i32 texternalsym:$dst)), 3179 (BL_NOP_RM texternalsym:$dst)>; 3180 3181def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm), 3182 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>; 3183 3184def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm), 3185 (TCRETURNdi texternalsym:$dst, imm:$imm)>; 3186 3187def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm), 3188 (TCRETURNri CTRRC:$dst, imm:$imm)>; 3189 3190def : Pat<(int_ppc_readflm), (MFFS)>; 3191def : Pat<(int_ppc_mffsl), (MFFSL)>; 3192 3193// Hi and Lo for Darwin Global Addresses. 3194def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 3195def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 3196def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 3197def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 3198def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 3199def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 3200def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>; 3201def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>; 3202def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in), 3203 (ADDIS $in, tglobaltlsaddr:$g)>; 3204def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in), 3205 (ADDI $in, tglobaltlsaddr:$g)>; 3206def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)), 3207 (ADDIS $in, tglobaladdr:$g)>; 3208def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)), 3209 (ADDIS $in, tconstpool:$g)>; 3210def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)), 3211 (ADDIS $in, tjumptable:$g)>; 3212def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)), 3213 (ADDIS $in, tblockaddress:$g)>; 3214 3215// Support for thread-local storage. 3216def PPC32GOT: PPCEmitTimePseudo<(outs gprc:$rD), (ins), "#PPC32GOT", 3217 [(set i32:$rD, (PPCppc32GOT))]>; 3218 3219// Get the _GLOBAL_OFFSET_TABLE_ in PIC mode. 3220// This uses two output registers, the first as the real output, the second as a 3221// temporary register, used internally in code generation. 3222def PPC32PICGOT: PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT", 3223 []>, NoEncode<"$rT">; 3224 3225def LDgotTprelL32: PPCEmitTimePseudo<(outs gprc_nor0:$rD), (ins s16imm:$disp, gprc_nor0:$reg), 3226 "#LDgotTprelL32", 3227 [(set i32:$rD, 3228 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>; 3229def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g), 3230 (ADD4TLS $in, tglobaltlsaddr:$g)>; 3231 3232def ADDItlsgdL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3233 "#ADDItlsgdL32", 3234 [(set i32:$rD, 3235 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>; 3236// LR is a true define, while the rest of the Defs are clobbers. R3 is 3237// explicitly defined when this op is created, so not mentioned here. 3238let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3239 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3240def GETtlsADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), 3241 "GETtlsADDR32", 3242 [(set i32:$rD, 3243 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>; 3244// R3 is explicitly defined when this op is created, so not mentioned here. 3245// The rest of the Defs are the exact set of registers that will be clobbered by 3246// the call. 3247let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3248 Defs = [R0,R4,R5,R11,LR,CR0] in 3249def GETtlsADDR32AIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$offset, gprc:$handle), 3250 "GETtlsADDR32AIX", 3251 [(set i32:$rD, 3252 (PPCgetTlsAddr i32:$offset, i32:$handle))]>; 3253 3254// For local-exec accesses on 32-bit AIX, a call to .__get_tpointer is 3255// generated to retrieve the thread pointer. GETtlsTpointer32AIX clobbers both 3256// R3 and the LR (link register). 3257let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3258 Defs = [R3,LR] in 3259def GETtlsTpointer32AIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins), 3260 "GETtlsTpointer32AIX", 3261 [(set i32:$rD, (PPCgetTpointer))]>; 3262 3263// The following pattern matches local- and initial-exec TLS accesses on 32-bit AIX. 3264// PPCaddTls is used in local- and initial-exec accesses in order to: 3265// - Get the address of a variable (add the variable offset to the thread 3266// pointer, retrieved by calling .__get_tpointer). 3267// - Create an opportunity to optimize the user of the loaded address. 3268def : Pat<(PPCaddTls i32:$in, i32:$addr), 3269 (ADD4TLS $in, $addr)>; 3270 3271// Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded. R3 and LR 3272// are true defines while the rest of the Defs are clobbers. 3273let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3274 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3275def ADDItlsgdLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), 3276 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), 3277 "#ADDItlsgdLADDR32", 3278 [(set i32:$rD, 3279 (PPCaddiTlsgdLAddr i32:$reg, 3280 tglobaltlsaddr:$disp, 3281 tglobaltlsaddr:$sym))]>; 3282def ADDItlsldL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3283 "#ADDItlsldL32", 3284 [(set i32:$rD, 3285 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>; 3286// This pseudo is expanded to two copies to put the variable offset in R4 and 3287// the region handle in R3 and GETtlsADDR32AIX. 3288def TLSGDAIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$offset, gprc:$handle), 3289 "#TLSGDAIX", 3290 [(set i32:$rD, 3291 (PPCTlsgdAIX i32:$offset, i32:$handle))]>; 3292// LR is a true define, while the rest of the Defs are clobbers. R3 is 3293// explicitly defined when this op is created, so not mentioned here. 3294let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3295 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3296def GETtlsldADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), 3297 "GETtlsldADDR32", 3298 [(set i32:$rD, 3299 (PPCgetTlsldAddr i32:$reg, 3300 tglobaltlsaddr:$sym))]>; 3301// Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded. R3 and LR 3302// are true defines while the rest of the Defs are clobbers. 3303let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3304 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3305def ADDItlsldLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), 3306 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), 3307 "#ADDItlsldLADDR32", 3308 [(set i32:$rD, 3309 (PPCaddiTlsldLAddr i32:$reg, 3310 tglobaltlsaddr:$disp, 3311 tglobaltlsaddr:$sym))]>; 3312def ADDIdtprelL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3313 "#ADDIdtprelL32", 3314 [(set i32:$rD, 3315 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>; 3316def ADDISdtprelHA32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3317 "#ADDISdtprelHA32", 3318 [(set i32:$rD, 3319 (PPCaddisDtprelHA i32:$reg, 3320 tglobaltlsaddr:$disp))]>; 3321 3322// Support for Position-independent code 3323def LWZtoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg), 3324 "#LWZtoc", 3325 [(set i32:$rD, 3326 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3327def LWZtocL : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc_nor0:$reg), 3328 "#LWZtocL", 3329 [(set i32:$rD, 3330 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3331def ADDIStocHA : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, tocentry32:$disp), 3332 "#ADDIStocHA", 3333 [(set i32:$rD, 3334 (PPCtoc_entry i32:$reg, tglobaladdr:$disp))]>; 3335// Local Data Transform 3336def ADDItoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg), 3337 "#ADDItoc", 3338 [(set i32:$rD, 3339 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3340 3341// Get Global (GOT) Base Register offset, from the word immediately preceding 3342// the function label. 3343def UpdateGBR : PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>; 3344 3345// Pseudo-instruction marked for deletion. When deleting the instruction would 3346// cause iterator invalidation in MIR transformation passes, this pseudo can be 3347// used instead. It will be removed unconditionally at pre-emit time (prior to 3348// branch selection). 3349def UNENCODED_NOP: PPCEmitTimePseudo<(outs), (ins), "#UNENCODED_NOP", []>; 3350 3351// Standard shifts. These are represented separately from the real shifts above 3352// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 3353// amounts. 3354def : Pat<(sra i32:$rS, i32:$rB), 3355 (SRAW $rS, $rB)>; 3356def : Pat<(srl i32:$rS, i32:$rB), 3357 (SRW $rS, $rB)>; 3358def : Pat<(shl i32:$rS, i32:$rB), 3359 (SLW $rS, $rB)>; 3360 3361def : Pat<(i32 (zextloadi1 DForm:$src)), 3362 (LBZ DForm:$src)>; 3363def : Pat<(i32 (zextloadi1 XForm:$src)), 3364 (LBZX XForm:$src)>; 3365def : Pat<(i32 (extloadi1 DForm:$src)), 3366 (LBZ DForm:$src)>; 3367def : Pat<(i32 (extloadi1 XForm:$src)), 3368 (LBZX XForm:$src)>; 3369def : Pat<(i32 (extloadi8 DForm:$src)), 3370 (LBZ DForm:$src)>; 3371def : Pat<(i32 (extloadi8 XForm:$src)), 3372 (LBZX XForm:$src)>; 3373def : Pat<(i32 (extloadi16 DForm:$src)), 3374 (LHZ DForm:$src)>; 3375def : Pat<(i32 (extloadi16 XForm:$src)), 3376 (LHZX XForm:$src)>; 3377let Predicates = [HasFPU] in { 3378def : Pat<(f64 (extloadf32 DForm:$src)), 3379 (COPY_TO_REGCLASS (LFS DForm:$src), F8RC)>; 3380def : Pat<(f64 (extloadf32 XForm:$src)), 3381 (COPY_TO_REGCLASS (LFSX XForm:$src), F8RC)>; 3382 3383def : Pat<(f64 (any_fpextend f32:$src)), 3384 (COPY_TO_REGCLASS $src, F8RC)>; 3385} 3386 3387// Only seq_cst fences require the heavyweight sync (SYNC 0). 3388// All others can use the lightweight sync (SYNC 1). 3389// source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html 3390// The rule for seq_cst is duplicated to work with both 64 bits and 32 bits 3391// versions of Power. 3392def : Pat<(atomic_fence (i64 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>; 3393def : Pat<(atomic_fence (i32 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>; 3394def : Pat<(atomic_fence (timm), (timm)), (SYNC 1)>, Requires<[HasSYNC]>; 3395def : Pat<(atomic_fence (timm), (timm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 3396 3397let Predicates = [HasFPU] in { 3398// Additional fnmsub patterns for custom node 3399def : Pat<(PPCfnmsub f64:$A, f64:$B, f64:$C), 3400 (FNMSUB $A, $B, $C)>; 3401def : Pat<(PPCfnmsub f32:$A, f32:$B, f32:$C), 3402 (FNMSUBS $A, $B, $C)>; 3403def : Pat<(fneg (PPCfnmsub f64:$A, f64:$B, f64:$C)), 3404 (FMSUB $A, $B, $C)>; 3405def : Pat<(fneg (PPCfnmsub f32:$A, f32:$B, f32:$C)), 3406 (FMSUBS $A, $B, $C)>; 3407def : Pat<(PPCfnmsub f64:$A, f64:$B, (fneg f64:$C)), 3408 (FNMADD $A, $B, $C)>; 3409def : Pat<(PPCfnmsub f32:$A, f32:$B, (fneg f32:$C)), 3410 (FNMADDS $A, $B, $C)>; 3411 3412// FCOPYSIGN's operand types need not agree. 3413def : Pat<(fcopysign f64:$frB, f32:$frA), 3414 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>; 3415def : Pat<(fcopysign f32:$frB, f64:$frA), 3416 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>; 3417} 3418 3419// XL Compat intrinsics. 3420def : Pat<(int_ppc_fmsub f64:$A, f64:$B, f64:$C), (FMSUB $A, $B, $C)>; 3421def : Pat<(int_ppc_fmsubs f32:$A, f32:$B, f32:$C), (FMSUBS $A, $B, $C)>; 3422def : Pat<(int_ppc_fnmadd f64:$A, f64:$B, f64:$C), (FNMADD $A, $B, $C)>; 3423def : Pat<(int_ppc_fnmadds f32:$A, f32:$B, f32:$C), (FNMADDS $A, $B, $C)>; 3424def : Pat<(int_ppc_fre f64:$A), (FRE $A)>; 3425def : Pat<(int_ppc_fres f32:$A), (FRES $A)>; 3426def : Pat<(int_ppc_fnabs f64:$A), (FNABSD $A)>; 3427def : Pat<(int_ppc_fnabss f32:$A), (FNABSS $A)>; 3428 3429include "PPCInstrAltivec.td" 3430include "PPCInstrSPE.td" 3431include "PPCInstr64Bit.td" 3432include "PPCInstrVSX.td" 3433include "PPCInstrHTM.td" 3434 3435def crnot : OutPatFrag<(ops node:$in), 3436 (CRNOT $in)>; 3437def : Pat<(not i1:$in), 3438 (crnot $in)>; 3439 3440// Pseudo-instructions for alternate assembly syntax (never used by codegen). 3441// These are aliases that require C++ handling to convert to the target 3442// instruction, while InstAliases can be handled directly by tblgen. 3443class PPCAsmPseudo<string asm, dag iops> 3444 : Instruction { 3445 let Namespace = "PPC"; 3446 bit PPC64 = 0; // Default value, override with isPPC64 3447 3448 let OutOperandList = (outs); 3449 let InOperandList = iops; 3450 let Pattern = []; 3451 let AsmString = asm; 3452 let isAsmParserOnly = 1; 3453 let isPseudo = 1; 3454 let hasNoSchedulingInfo = 1; 3455} 3456 3457// Prefixed instructions may require access to the above defs at a later 3458// time so we include this after the def. 3459include "PPCInstrP10.td" 3460include "PPCInstrFutureMMA.td" 3461include "PPCInstrFuture.td" 3462include "PPCInstrMMA.td" 3463include "PPCInstrDFP.td" 3464 3465// Patterns for arithmetic i1 operations. 3466def : Pat<(add i1:$a, i1:$b), 3467 (CRXOR $a, $b)>; 3468def : Pat<(sub i1:$a, i1:$b), 3469 (CRXOR $a, $b)>; 3470def : Pat<(mul i1:$a, i1:$b), 3471 (CRAND $a, $b)>; 3472 3473// We're sometimes asked to materialize i1 -1, which is just 1 in this case 3474// (-1 is used to mean all bits set). 3475def : Pat<(i1 -1), (CRSET)>; 3476 3477// i1 extensions, implemented in terms of isel. 3478def : Pat<(i32 (zext i1:$in)), 3479 (SELECT_I4 $in, (LI 1), (LI 0))>; 3480def : Pat<(i32 (sext i1:$in)), 3481 (SELECT_I4 $in, (LI -1), (LI 0))>; 3482 3483def : Pat<(i64 (zext i1:$in)), 3484 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 3485def : Pat<(i64 (sext i1:$in)), 3486 (SELECT_I8 $in, (LI8 -1), (LI8 0))>; 3487 3488// FIXME: We should choose either a zext or a sext based on other constants 3489// already around. 3490def : Pat<(i32 (anyext i1:$in)), 3491 (SELECT_I4 $in, (LI 1), (LI 0))>; 3492def : Pat<(i64 (anyext i1:$in)), 3493 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 3494 3495// match setcc on i1 variables. 3496// CRANDC is: 3497// 1 1 : F 3498// 1 0 : T 3499// 0 1 : F 3500// 0 0 : F 3501// 3502// LT is: 3503// -1 -1 : F 3504// -1 0 : T 3505// 0 -1 : F 3506// 0 0 : F 3507// 3508// ULT is: 3509// 1 1 : F 3510// 1 0 : F 3511// 0 1 : T 3512// 0 0 : F 3513def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)), 3514 (CRANDC $s1, $s2)>; 3515def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)), 3516 (CRANDC $s2, $s1)>; 3517// CRORC is: 3518// 1 1 : T 3519// 1 0 : T 3520// 0 1 : F 3521// 0 0 : T 3522// 3523// LE is: 3524// -1 -1 : T 3525// -1 0 : T 3526// 0 -1 : F 3527// 0 0 : T 3528// 3529// ULE is: 3530// 1 1 : T 3531// 1 0 : F 3532// 0 1 : T 3533// 0 0 : T 3534def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)), 3535 (CRORC $s1, $s2)>; 3536def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)), 3537 (CRORC $s2, $s1)>; 3538 3539def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)), 3540 (CREQV $s1, $s2)>; 3541 3542// GE is: 3543// -1 -1 : T 3544// -1 0 : F 3545// 0 -1 : T 3546// 0 0 : T 3547// 3548// UGE is: 3549// 1 1 : T 3550// 1 0 : T 3551// 0 1 : F 3552// 0 0 : T 3553def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)), 3554 (CRORC $s2, $s1)>; 3555def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)), 3556 (CRORC $s1, $s2)>; 3557 3558// GT is: 3559// -1 -1 : F 3560// -1 0 : F 3561// 0 -1 : T 3562// 0 0 : F 3563// 3564// UGT is: 3565// 1 1 : F 3566// 1 0 : T 3567// 0 1 : F 3568// 0 0 : F 3569def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)), 3570 (CRANDC $s2, $s1)>; 3571def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)), 3572 (CRANDC $s1, $s2)>; 3573 3574def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)), 3575 (CRXOR $s1, $s2)>; 3576 3577// match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE, 3578// SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for 3579// floating-point types. 3580 3581multiclass CRNotPat<dag pattern, dag result> { 3582 def : Pat<pattern, (crnot result)>; 3583 def : Pat<(not pattern), result>; 3584 3585 // We can also fold the crnot into an extension: 3586 def : Pat<(i32 (zext pattern)), 3587 (SELECT_I4 result, (LI 0), (LI 1))>; 3588 def : Pat<(i32 (sext pattern)), 3589 (SELECT_I4 result, (LI 0), (LI -1))>; 3590 3591 // We can also fold the crnot into an extension: 3592 def : Pat<(i64 (zext pattern)), 3593 (SELECT_I8 result, (LI8 0), (LI8 1))>; 3594 def : Pat<(i64 (sext pattern)), 3595 (SELECT_I8 result, (LI8 0), (LI8 -1))>; 3596 3597 // FIXME: We should choose either a zext or a sext based on other constants 3598 // already around. 3599 def : Pat<(i32 (anyext pattern)), 3600 (SELECT_I4 result, (LI 0), (LI 1))>; 3601 3602 def : Pat<(i64 (anyext pattern)), 3603 (SELECT_I8 result, (LI8 0), (LI8 1))>; 3604} 3605 3606// FIXME: Because of what seems like a bug in TableGen's type-inference code, 3607// we need to write imm:$imm in the output patterns below, not just $imm, or 3608// else the resulting matcher will not correctly add the immediate operand 3609// (making it a register operand instead). 3610 3611// extended SETCC. 3612multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag, 3613 OutPatFrag rfrag, OutPatFrag rfrag8> { 3614 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))), 3615 (rfrag $s1)>; 3616 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))), 3617 (rfrag8 $s1)>; 3618 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))), 3619 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 3620 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))), 3621 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 3622 3623 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))), 3624 (rfrag $s1)>; 3625 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))), 3626 (rfrag8 $s1)>; 3627 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))), 3628 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 3629 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))), 3630 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 3631} 3632 3633// Note that we do all inversions below with i(32|64)not, instead of using 3634// (xori x, 1) because on the A2 nor has single-cycle latency while xori 3635// has 2-cycle latency. 3636 3637defm : ExtSetCCPat<SETEQ, 3638 PatFrag<(ops node:$in, node:$cc), 3639 (setcc $in, 0, $cc)>, 3640 OutPatFrag<(ops node:$in), 3641 (RLWINM (CNTLZW $in), 27, 31, 31)>, 3642 OutPatFrag<(ops node:$in), 3643 (RLDICL (CNTLZD $in), 58, 63)> >; 3644 3645defm : ExtSetCCPat<SETNE, 3646 PatFrag<(ops node:$in, node:$cc), 3647 (setcc $in, 0, $cc)>, 3648 OutPatFrag<(ops node:$in), 3649 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>, 3650 OutPatFrag<(ops node:$in), 3651 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >; 3652 3653defm : ExtSetCCPat<SETLT, 3654 PatFrag<(ops node:$in, node:$cc), 3655 (setcc $in, 0, $cc)>, 3656 OutPatFrag<(ops node:$in), 3657 (RLWINM $in, 1, 31, 31)>, 3658 OutPatFrag<(ops node:$in), 3659 (RLDICL $in, 1, 63)> >; 3660 3661defm : ExtSetCCPat<SETGE, 3662 PatFrag<(ops node:$in, node:$cc), 3663 (setcc $in, 0, $cc)>, 3664 OutPatFrag<(ops node:$in), 3665 (RLWINM (i32not $in), 1, 31, 31)>, 3666 OutPatFrag<(ops node:$in), 3667 (RLDICL (i64not $in), 1, 63)> >; 3668 3669defm : ExtSetCCPat<SETGT, 3670 PatFrag<(ops node:$in, node:$cc), 3671 (setcc $in, 0, $cc)>, 3672 OutPatFrag<(ops node:$in), 3673 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>, 3674 OutPatFrag<(ops node:$in), 3675 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >; 3676 3677defm : ExtSetCCPat<SETLE, 3678 PatFrag<(ops node:$in, node:$cc), 3679 (setcc $in, 0, $cc)>, 3680 OutPatFrag<(ops node:$in), 3681 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>, 3682 OutPatFrag<(ops node:$in), 3683 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >; 3684 3685defm : ExtSetCCPat<SETLT, 3686 PatFrag<(ops node:$in, node:$cc), 3687 (setcc $in, -1, $cc)>, 3688 OutPatFrag<(ops node:$in), 3689 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>, 3690 OutPatFrag<(ops node:$in), 3691 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 3692 3693defm : ExtSetCCPat<SETGE, 3694 PatFrag<(ops node:$in, node:$cc), 3695 (setcc $in, -1, $cc)>, 3696 OutPatFrag<(ops node:$in), 3697 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>, 3698 OutPatFrag<(ops node:$in), 3699 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 3700 3701defm : ExtSetCCPat<SETGT, 3702 PatFrag<(ops node:$in, node:$cc), 3703 (setcc $in, -1, $cc)>, 3704 OutPatFrag<(ops node:$in), 3705 (RLWINM (i32not $in), 1, 31, 31)>, 3706 OutPatFrag<(ops node:$in), 3707 (RLDICL (i64not $in), 1, 63)> >; 3708 3709defm : ExtSetCCPat<SETLE, 3710 PatFrag<(ops node:$in, node:$cc), 3711 (setcc $in, -1, $cc)>, 3712 OutPatFrag<(ops node:$in), 3713 (RLWINM $in, 1, 31, 31)>, 3714 OutPatFrag<(ops node:$in), 3715 (RLDICL $in, 1, 63)> >; 3716 3717// An extended SETCC with shift amount. 3718multiclass ExtSetCCShiftPat<CondCode cc, PatFrag pfrag, 3719 OutPatFrag rfrag, OutPatFrag rfrag8> { 3720 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3721 (rfrag $s1, $sa)>; 3722 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3723 (rfrag8 $s1, $sa)>; 3724 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3725 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>; 3726 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3727 (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>; 3728 3729 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3730 (rfrag $s1, $sa)>; 3731 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3732 (rfrag8 $s1, $sa)>; 3733 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3734 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>; 3735 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3736 (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>; 3737} 3738 3739defm : ExtSetCCShiftPat<SETNE, 3740 PatFrag<(ops node:$in, node:$sa, node:$cc), 3741 (setcc (and $in, (shl 1, $sa)), 0, $cc)>, 3742 OutPatFrag<(ops node:$in, node:$sa), 3743 (RLWNM $in, (SUBFIC $sa, 32), 31, 31)>, 3744 OutPatFrag<(ops node:$in, node:$sa), 3745 (RLDCL $in, (SUBFIC $sa, 64), 63)> >; 3746 3747defm : ExtSetCCShiftPat<SETEQ, 3748 PatFrag<(ops node:$in, node:$sa, node:$cc), 3749 (setcc (and $in, (shl 1, $sa)), 0, $cc)>, 3750 OutPatFrag<(ops node:$in, node:$sa), 3751 (RLWNM (i32not $in), 3752 (SUBFIC $sa, 32), 31, 31)>, 3753 OutPatFrag<(ops node:$in, node:$sa), 3754 (RLDCL (i64not $in), 3755 (SUBFIC $sa, 64), 63)> >; 3756 3757// SETCC for i32. 3758def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)), 3759 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 3760def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)), 3761 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 3762def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)), 3763 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 3764def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)), 3765 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 3766def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)), 3767 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 3768def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)), 3769 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 3770 3771// For non-equality comparisons, the default code would materialize the 3772// constant, then compare against it, like this: 3773// lis r2, 4660 3774// ori r2, r2, 22136 3775// cmpw cr0, r3, r2 3776// beq cr0,L6 3777// Since we are just comparing for equality, we can emit this instead: 3778// xoris r0,r3,0x1234 3779// cmplwi cr0,r0,0x5678 3780// beq cr0,L6 3781 3782def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)), 3783 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 3784 (LO16 imm:$imm)), sub_eq)>; 3785 3786def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)), 3787 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 3788def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)), 3789 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 3790def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)), 3791 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 3792def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)), 3793 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 3794def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)), 3795 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 3796 3797// SETCC for i64. 3798def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)), 3799 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 3800def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)), 3801 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 3802def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)), 3803 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 3804def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)), 3805 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 3806def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)), 3807 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 3808def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)), 3809 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 3810 3811// For non-equality comparisons, the default code would materialize the 3812// constant, then compare against it, like this: 3813// lis r2, 4660 3814// ori r2, r2, 22136 3815// cmpd cr0, r3, r2 3816// beq cr0,L6 3817// Since we are just comparing for equality, we can emit this instead: 3818// xoris r0,r3,0x1234 3819// cmpldi cr0,r0,0x5678 3820// beq cr0,L6 3821 3822def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)), 3823 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 3824 (LO16 imm:$imm)), sub_eq)>; 3825 3826def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)), 3827 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 3828def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)), 3829 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 3830def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)), 3831 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 3832def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)), 3833 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 3834def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)), 3835 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 3836 3837let Predicates = [IsNotISA3_1] in { 3838// Instantiations of CRNotPat for i32. 3839defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)), 3840 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 3841defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)), 3842 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 3843defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)), 3844 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 3845defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)), 3846 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 3847defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)), 3848 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 3849defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)), 3850 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 3851 3852defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)), 3853 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 3854 (LO16 imm:$imm)), sub_eq)>; 3855 3856defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)), 3857 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 3858defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)), 3859 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 3860defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)), 3861 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 3862defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)), 3863 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 3864defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)), 3865 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 3866 3867// Instantiations of CRNotPat for i64. 3868defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)), 3869 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 3870defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)), 3871 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 3872defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)), 3873 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 3874defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)), 3875 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 3876defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)), 3877 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 3878defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)), 3879 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 3880 3881defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)), 3882 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 3883 (LO16 imm:$imm)), sub_eq)>; 3884 3885defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)), 3886 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 3887defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)), 3888 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 3889defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)), 3890 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 3891defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)), 3892 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 3893defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)), 3894 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 3895} 3896 3897multiclass FSetCCPat<SDPatternOperator SetCC, ValueType Ty, I FCmp> { 3898 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)), 3899 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 3900 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)), 3901 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 3902 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)), 3903 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 3904 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)), 3905 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 3906 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)), 3907 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 3908 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)), 3909 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 3910 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)), 3911 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>; 3912 3913 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOLT)), 3914 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 3915 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLT)), 3916 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 3917 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOGT)), 3918 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 3919 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGT)), 3920 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 3921 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOEQ)), 3922 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 3923 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETEQ)), 3924 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 3925 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUO)), 3926 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>; 3927} 3928 3929let Predicates = [HasFPU] in { 3930// FCMPU: If either of the operands is a Signaling NaN, then VXSNAN is set. 3931// SETCC for f32. 3932defm : FSetCCPat<any_fsetcc, f32, FCMPUS>; 3933 3934// SETCC for f64. 3935defm : FSetCCPat<any_fsetcc, f64, FCMPUD>; 3936 3937// SETCC for f128. 3938defm : FSetCCPat<any_fsetcc, f128, XSCMPUQP>; 3939 3940// FCMPO: If either of the operands is a Signaling NaN, then VXSNAN is set and, 3941// if neither operand is a Signaling NaN but at least one operand is a Quiet NaN, 3942// then VXVC is set. 3943// SETCCS for f32. 3944defm : FSetCCPat<strict_fsetccs, f32, FCMPOS>; 3945 3946// SETCCS for f64. 3947defm : FSetCCPat<strict_fsetccs, f64, FCMPOD>; 3948 3949// SETCCS for f128. 3950defm : FSetCCPat<strict_fsetccs, f128, XSCMPOQP>; 3951} 3952 3953// This must be in this file because it relies on patterns defined in this file 3954// after the inclusion of the instruction sets. 3955let Predicates = [HasSPE] in { 3956// SETCC for f32. 3957def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOLT)), 3958 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3959def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETLT)), 3960 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3961def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOGT)), 3962 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3963def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETGT)), 3964 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3965def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOEQ)), 3966 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3967def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETEQ)), 3968 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3969 3970defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETUGE)), 3971 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3972defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETGE)), 3973 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3974defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETULE)), 3975 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3976defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETLE)), 3977 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3978defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETUNE)), 3979 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3980defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETNE)), 3981 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3982 3983// SETCC for f64. 3984def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOLT)), 3985 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 3986def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETLT)), 3987 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 3988def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOGT)), 3989 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 3990def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETGT)), 3991 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 3992def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOEQ)), 3993 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 3994def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETEQ)), 3995 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 3996 3997defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETUGE)), 3998 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 3999defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETGE)), 4000 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 4001defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETULE)), 4002 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 4003defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETLE)), 4004 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 4005defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETUNE)), 4006 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4007defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETNE)), 4008 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4009} 4010// match select on i1 variables: 4011def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)), 4012 (CROR (CRAND $cond , $tval), 4013 (CRAND (crnot $cond), $fval))>; 4014 4015// match selectcc on i1 variables: 4016// select (lhs == rhs), tval, fval is: 4017// ((lhs == rhs) & tval) | (!(lhs == rhs) & fval) 4018def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)), 4019 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 4020 (CRAND (CRORC $rhs, $lhs), $fval))>; 4021def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)), 4022 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 4023 (CRAND (CRORC $lhs, $rhs), $fval))>; 4024def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)), 4025 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 4026 (CRAND (CRANDC $rhs, $lhs), $fval))>; 4027def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)), 4028 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 4029 (CRAND (CRANDC $lhs, $rhs), $fval))>; 4030def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)), 4031 (CROR (CRAND (CREQV $lhs, $rhs), $tval), 4032 (CRAND (CRXOR $lhs, $rhs), $fval))>; 4033def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)), 4034 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 4035 (CRAND (CRANDC $lhs, $rhs), $fval))>; 4036def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)), 4037 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 4038 (CRAND (CRANDC $rhs, $lhs), $fval))>; 4039def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)), 4040 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 4041 (CRAND (CRORC $lhs, $rhs), $fval))>; 4042def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)), 4043 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 4044 (CRAND (CRORC $rhs, $lhs), $fval))>; 4045def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)), 4046 (CROR (CRAND (CREQV $lhs, $rhs), $fval), 4047 (CRAND (CRXOR $lhs, $rhs), $tval))>; 4048 4049// match selectcc on i1 variables with non-i1 output. 4050def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)), 4051 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4052def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)), 4053 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4054def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)), 4055 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 4056def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)), 4057 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 4058def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)), 4059 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>; 4060def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)), 4061 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 4062def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)), 4063 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 4064def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)), 4065 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4066def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)), 4067 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4068def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)), 4069 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>; 4070 4071def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)), 4072 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4073def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)), 4074 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4075def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)), 4076 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 4077def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULE)), 4078 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 4079def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)), 4080 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>; 4081def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)), 4082 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 4083def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)), 4084 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 4085def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)), 4086 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4087def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)), 4088 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4089def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)), 4090 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>; 4091 4092let Predicates = [HasFPU] in { 4093def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)), 4094 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4095def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)), 4096 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4097def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)), 4098 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 4099def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)), 4100 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 4101def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)), 4102 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>; 4103def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)), 4104 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 4105def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)), 4106 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 4107def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)), 4108 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4109def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)), 4110 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4111def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)), 4112 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>; 4113 4114def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)), 4115 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4116def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)), 4117 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4118def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)), 4119 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 4120def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)), 4121 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 4122def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)), 4123 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>; 4124def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)), 4125 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 4126def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)), 4127 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 4128def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)), 4129 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4130def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)), 4131 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4132def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)), 4133 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>; 4134} 4135 4136def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLT)), 4137 (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>; 4138def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULT)), 4139 (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>; 4140def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLE)), 4141 (SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>; 4142def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULE)), 4143 (SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>; 4144def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETEQ)), 4145 (SELECT_F16 (CREQV $lhs, $rhs), $tval, $fval)>; 4146def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGE)), 4147 (SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>; 4148def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGE)), 4149 (SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>; 4150def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGT)), 4151 (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>; 4152def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGT)), 4153 (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>; 4154def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETNE)), 4155 (SELECT_F16 (CRXOR $lhs, $rhs), $tval, $fval)>; 4156 4157def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)), 4158 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 4159def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULT)), 4160 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 4161def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)), 4162 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 4163def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULE)), 4164 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 4165def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)), 4166 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>; 4167def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)), 4168 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 4169def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGE)), 4170 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 4171def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)), 4172 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 4173def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGT)), 4174 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 4175def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)), 4176 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>; 4177 4178def ANDI_rec_1_EQ_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in), 4179 "#ANDI_rec_1_EQ_BIT", 4180 [(set i1:$dst, (trunc (not i32:$in)))]>; 4181def ANDI_rec_1_GT_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in), 4182 "#ANDI_rec_1_GT_BIT", 4183 [(set i1:$dst, (trunc i32:$in))]>; 4184 4185def ANDI_rec_1_EQ_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in), 4186 "#ANDI_rec_1_EQ_BIT8", 4187 [(set i1:$dst, (trunc (not i64:$in)))]>; 4188def ANDI_rec_1_GT_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in), 4189 "#ANDI_rec_1_GT_BIT8", 4190 [(set i1:$dst, (trunc i64:$in))]>; 4191 4192def : Pat<(i1 (not (trunc i32:$in))), 4193 (ANDI_rec_1_EQ_BIT $in)>; 4194def : Pat<(i1 (not (trunc i64:$in))), 4195 (ANDI_rec_1_EQ_BIT8 $in)>; 4196 4197def : Pat<(int_ppc_fsel f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), (FSELD $FRA, $FRC, $FRB)>; 4198def : Pat<(int_ppc_frsqrte f8rc:$frB), (FRSQRTE $frB)>; 4199def : Pat<(int_ppc_frsqrtes f4rc:$frB), (FRSQRTES $frB)>; 4200 4201//===----------------------------------------------------------------------===// 4202// PowerPC Instructions used for assembler/disassembler only 4203// 4204 4205// FIXME: For B=0 or B > 8, the registers following RT are used. 4206// WARNING: Do not add patterns for this instruction without fixing this. 4207def LSWI : XForm_base_r3xo_memOp<31, 597, (outs gprc:$RST), 4208 (ins gprc:$RA, u5imm:$RB), 4209 "lswi $RST, $RA, $RB", IIC_LdStLoad, []>; 4210 4211// FIXME: For B=0 or B > 8, the registers following RT are used. 4212// WARNING: Do not add patterns for this instruction without fixing this. 4213def STSWI : XForm_base_r3xo_memOp<31, 725, (outs), 4214 (ins gprc:$RST, gprc:$RA, u5imm:$RB), 4215 "stswi $RST, $RA, $RB", IIC_LdStLoad, []>; 4216 4217def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins), 4218 "isync", IIC_SprISYNC, []>; 4219 4220def ICBI : XForm_1a<31, 982, (outs), (ins (memrr $RA, $RB):$addr), 4221 "icbi $addr", IIC_LdStICBI, []>; 4222 4223def WAIT : XForm_24_sync<31, 30, (outs), (ins u2imm:$L), 4224 "wait $L", IIC_LdStLoad, []>; 4225 4226def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO), 4227 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>; 4228 4229def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR), 4230 "mtsr $SR, $RS", IIC_SprMTSR>; 4231 4232def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR), 4233 "mfsr $RS, $SR", IIC_SprMFSR>; 4234 4235def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB), 4236 "mtsrin $RS, $RB", IIC_SprMTSR>; 4237 4238def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB), 4239 "mfsrin $RS, $RB", IIC_SprMFSR>; 4240 4241def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, u1imm:$L), 4242 "mtmsr $RS, $L", IIC_SprMTMSR>; 4243 4244def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS), 4245 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> { 4246 let L = 0; 4247} 4248 4249def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>, 4250 Requires<[IsBookE]> { 4251 bits<1> E; 4252 4253 let Inst{16} = E; 4254 let Inst{21-30} = 163; 4255} 4256 4257def DCCCI : XForm_tlb<454, (outs), (ins gprc:$RA, gprc:$RB), 4258 "dccci $RA, $RB", IIC_LdStLoad>, Requires<[IsPPC4xx]>; 4259def ICCCI : XForm_tlb<966, (outs), (ins gprc:$RA, gprc:$RB), 4260 "iccci $RA, $RB", IIC_LdStLoad>, Requires<[IsPPC4xx]>; 4261 4262def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; 4263def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; 4264def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; 4265def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; 4266 4267def MFMSR : XForm_rs<31, 83, (outs gprc:$RST), (ins), 4268 "mfmsr $RST", IIC_SprMFMSR, []>; 4269 4270def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, u1imm:$L), 4271 "mtmsrd $RS, $L", IIC_SprMTMSRD>; 4272 4273def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA), 4274 "mcrfs $BF, $BFA", IIC_BrMCR>; 4275 4276// All MTFSF variants may change the rounding mode so conservatively set it 4277// as an implicit def for all of them. 4278let Predicates = [HasFPU] in { 4279let Defs = [RM], hasSideEffects = 1 in { 4280let isCodeGenOnly = 1, 4281 Pattern = [(int_ppc_mtfsfi timm:$BF, timm:$U)], W = 0 in 4282def MTFSFIb : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U), 4283 "mtfsfi $BF, $U", IIC_IntMFFS>; 4284def MTFSFI : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U, i32imm:$W), 4285 "mtfsfi $BF, $U, $W", IIC_IntMFFS>; 4286let Defs = [CR1] in 4287def MTFSFI_rec : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U, u1imm:$W), 4288 "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isRecordForm; 4289 4290def MTFSF : XFLForm_1<63, 711, (outs), 4291 (ins i32imm:$FLM, f8rc:$FRB, u1imm:$L, i32imm:$W), 4292 "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>; 4293let Defs = [CR1] in 4294def MTFSF_rec : XFLForm_1<63, 711, (outs), 4295 (ins i32imm:$FLM, f8rc:$FRB, u1imm:$L, i32imm:$W), 4296 "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isRecordForm; 4297} 4298 4299def : InstAlias<"mtfsfi $BF, $U", (MTFSFI u3imm:$BF, u4imm:$U, 0)>; 4300def : InstAlias<"mtfsfi. $BF, $U", (MTFSFI_rec u3imm:$BF, u4imm:$U, 0)>; 4301def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>; 4302def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSF_rec i32imm:$FLM, f8rc:$FRB, 0, 0)>; 4303} 4304 4305def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB), 4306 "slbie $RB", IIC_SprSLBIE, []>; 4307 4308def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RST, gprc:$RB), 4309 "slbmte $RST, $RB", IIC_SprSLBMTE, []>; 4310 4311def SLBMFEE : XForm_26<31, 915, (outs gprc:$RST), (ins gprc:$RB), 4312 "slbmfee $RST, $RB", IIC_SprSLBMFEE, []>; 4313 4314def SLBMFEV : XLForm_1_gen<31, 851, (outs gprc:$RT), (ins gprc:$RB), 4315 "slbmfev $RT, $RB", IIC_SprSLBMFEV, []>; 4316 4317def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>; 4318 4319let Defs = [CR0] in 4320def SLBFEE_rec : XForm_26<31, 979, (outs gprc:$RST), (ins gprc:$RB), 4321 "slbfee. $RST, $RB", IIC_SprSLBFEE, []>, isRecordForm; 4322 4323def TLBIA : XForm_0<31, 370, (outs), (ins), 4324 "tlbia", IIC_SprTLBIA, []>; 4325 4326def TLBSYNC : XForm_0<31, 566, (outs), (ins), 4327 "tlbsync", IIC_SprTLBSYNC, []>; 4328 4329def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB), 4330 "tlbiel $RB", IIC_SprTLBIEL, []>; 4331 4332def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB), 4333 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; 4334def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB), 4335 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; 4336 4337def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RST, gprc:$RB), 4338 "tlbie $RB,$RST", IIC_SprTLBIE, []>; 4339 4340def TLBSX : XForm_tlb<914, (outs), (ins gprc:$RA, gprc:$RB), "tlbsx $RA, $RB", 4341 IIC_LdStLoad>, Requires<[IsBookE]>; 4342 4343def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$RA, gprc:$RB), "tlbivax $RA, $RB", 4344 IIC_LdStLoad>, Requires<[IsBookE]>; 4345 4346def TLBILX : XForm_tlbilx<18, (outs), (ins u2imm:$T, gprc:$RA, gprc:$RB), 4347 "tlbilx $T, $RA, $RB", IIC_LdStLoad>, Requires<[IsBookE]>; 4348 4349def TLBRE : XForm_24_eieio<31, 946, (outs), (ins), 4350 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>; 4351 4352def TLBWE : XForm_24_eieio<31, 978, (outs), (ins), 4353 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>; 4354 4355def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RST), (ins gprc:$RA, i1imm:$WS), 4356 "tlbre $RST, $RA, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; 4357 4358def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RST, gprc:$RA, i1imm:$WS), 4359 "tlbwe $RST, $RA, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; 4360 4361def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$RA, gprc:$RB), 4362 "tlbsx $RST, $RA, $RB", IIC_LdStLoad, []>, 4363 Requires<[IsPPC4xx]>; 4364def TLBSX2D : XForm_base_r3xo<31, 914, (outs), 4365 (ins gprc:$RST, gprc:$RA, gprc:$RB), 4366 "tlbsx. $RST, $RA, $RB", IIC_LdStLoad, []>, 4367 Requires<[IsPPC4xx]>, isRecordForm; 4368 4369def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>; 4370 4371def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>, 4372 Requires<[IsBookE]>; 4373def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>, 4374 Requires<[IsBookE]>; 4375 4376def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>, 4377 Requires<[IsE500]>; 4378def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>, 4379 Requires<[IsE500]>; 4380 4381def MFDCR : XFXForm_1<31, 323, (outs gprc:$RST), (ins i32imm:$SPR), 4382 "mfdcr $RST, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>; 4383def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RST, i32imm:$SPR), 4384 "mtdcr $SPR, $RST", IIC_SprMTSPR>, Requires<[IsPPC4xx]>; 4385 4386def HRFID : XLForm_1_np<19, 274, (outs), (ins), "hrfid", IIC_BrB, []>; 4387def NAP : XLForm_1_np<19, 434, (outs), (ins), "nap", IIC_BrB, []>; 4388 4389def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>; 4390 4391def LBZCIX : XForm_base_r3xo_memOp<31, 853, (outs gprc:$RST), 4392 (ins gprc:$RA, gprc:$RB), 4393 "lbzcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4394def LHZCIX : XForm_base_r3xo_memOp<31, 821, (outs gprc:$RST), 4395 (ins gprc:$RA, gprc:$RB), 4396 "lhzcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4397def LWZCIX : XForm_base_r3xo_memOp<31, 789, (outs gprc:$RST), 4398 (ins gprc:$RA, gprc:$RB), 4399 "lwzcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4400def LDCIX : XForm_base_r3xo_memOp<31, 885, (outs gprc:$RST), 4401 (ins gprc:$RA, gprc:$RB), 4402 "ldcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4403 4404def STBCIX : XForm_base_r3xo_memOp<31, 981, (outs), 4405 (ins gprc:$RST, gprc:$RA, gprc:$RB), 4406 "stbcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4407def STHCIX : XForm_base_r3xo_memOp<31, 949, (outs), 4408 (ins gprc:$RST, gprc:$RA, gprc:$RB), 4409 "sthcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4410def STWCIX : XForm_base_r3xo_memOp<31, 917, (outs), 4411 (ins gprc:$RST, gprc:$RA, gprc:$RB), 4412 "stwcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4413def STDCIX : XForm_base_r3xo_memOp<31, 1013, (outs), 4414 (ins gprc:$RST, gprc:$RA, gprc:$RB), 4415 "stdcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4416 4417// External PID Load Store Instructions 4418 4419def LBEPX : XForm_1<31, 95, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 4420 "lbepx $RST, $addr", IIC_LdStLoad, []>, 4421 Requires<[IsE500]>; 4422 4423def LFDEPX : XForm_25<31, 607, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr), 4424 "lfdepx $RST, $addr", IIC_LdStLFD, []>, 4425 Requires<[IsE500]>; 4426 4427def LHEPX : XForm_1<31, 287, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 4428 "lhepx $RST, $addr", IIC_LdStLoad, []>, 4429 Requires<[IsE500]>; 4430 4431def LWEPX : XForm_1<31, 31, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 4432 "lwepx $RST, $addr", IIC_LdStLoad, []>, 4433 Requires<[IsE500]>; 4434 4435def STBEPX : XForm_8<31, 223, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 4436 "stbepx $RST, $addr", IIC_LdStStore, []>, 4437 Requires<[IsE500]>; 4438 4439def STFDEPX : XForm_28_memOp<31, 735, (outs), (ins f8rc:$RST, (memrr $RA, $RB):$addr), 4440 "stfdepx $RST, $addr", IIC_LdStSTFD, []>, 4441 Requires<[IsE500]>; 4442 4443def STHEPX : XForm_8<31, 415, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 4444 "sthepx $RST, $addr", IIC_LdStStore, []>, 4445 Requires<[IsE500]>; 4446 4447def STWEPX : XForm_8<31, 159, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 4448 "stwepx $RST, $addr", IIC_LdStStore, []>, 4449 Requires<[IsE500]>; 4450 4451def DCBFEP : DCB_Form<127, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbfep $addr", 4452 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4453 4454def DCBSTEP : DCB_Form<63, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbstep $addr", 4455 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4456 4457def DCBTEP : DCB_Form_hint<319, (outs), (ins (memrr $RA, $RB):$addr, u5imm:$TH), 4458 "dcbtep $TH, $addr", IIC_LdStDCBF, []>, 4459 Requires<[IsE500]>; 4460 4461def DCBTSTEP : DCB_Form_hint<255, (outs), (ins (memrr $RA, $RB):$addr, u5imm:$TH), 4462 "dcbtstep $TH, $addr", IIC_LdStDCBF, []>, 4463 Requires<[IsE500]>; 4464 4465def DCBZEP : DCB_Form<1023, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbzep $addr", 4466 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4467 4468def DCBZLEP : DCB_Form<1023, 1, (outs), (ins (memrr $RA, $RB):$addr), "dcbzlep $addr", 4469 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4470 4471def ICBIEP : XForm_1a<31, 991, (outs), (ins (memrr $RA, $RB):$addr), "icbiep $addr", 4472 IIC_LdStICBI, []>, Requires<[IsE500]>; 4473 4474//===----------------------------------------------------------------------===// 4475// PowerPC Assembler Instruction Aliases 4476// 4477 4478def : InstAlias<"sc", (SC 0)>; 4479 4480def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>; 4481def : InstAlias<"hwsync", (SYNC 0), 0>, Requires<[HasSYNC]>; 4482def : InstAlias<"msync", (SYNC 0), 0>, Requires<[HasSYNC]>; 4483def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>; 4484def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>; 4485 4486def : InstAlias<"wait", (WAIT 0)>; 4487def : InstAlias<"waitrsv", (WAIT 1)>; 4488def : InstAlias<"waitimpl", (WAIT 2)>; 4489 4490def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>; 4491 4492def DCBTx : PPCAsmPseudo<"dcbt $dst", (ins memrr:$dst)>; 4493def DCBTSTx : PPCAsmPseudo<"dcbtst $dst", (ins memrr:$dst)>; 4494 4495def DCBTCT : PPCAsmPseudo<"dcbtct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4496def DCBTDS : PPCAsmPseudo<"dcbtds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4497def DCBTT : PPCAsmPseudo<"dcbtt $dst", (ins memrr:$dst)>; 4498 4499def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4500def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4501def DCBTSTT : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>; 4502 4503def DCBFx : PPCAsmPseudo<"dcbf $dst", (ins memrr:$dst)>; 4504def DCBFL : PPCAsmPseudo<"dcbfl $dst", (ins memrr:$dst)>; 4505def DCBFLP : PPCAsmPseudo<"dcbflp $dst", (ins memrr:$dst)>; 4506 4507def : Pat<(int_ppc_isync), (ISYNC)>; 4508def : Pat<(int_ppc_dcbfl xoaddr:$dst), 4509 (DCBF 1, xoaddr:$dst)>; 4510def : Pat<(int_ppc_dcbflp xoaddr:$dst), 4511 (DCBF 3, xoaddr:$dst)>; 4512 4513let Predicates = [IsISA3_1] in { 4514 def DCBFPS : PPCAsmPseudo<"dcbfps $dst", (ins memrr:$dst)>; 4515 def DCBSTPS : PPCAsmPseudo<"dcbstps $dst", (ins memrr:$dst)>; 4516 4517 def : Pat<(int_ppc_dcbfps xoaddr:$dst), 4518 (DCBF 4, xoaddr:$dst)>; 4519 def : Pat<(int_ppc_dcbstps xoaddr:$dst), 4520 (DCBF 6, xoaddr:$dst)>; 4521} 4522 4523def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 4524def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 4525def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 4526def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 4527 4528def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>; 4529def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>; 4530def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>; 4531 4532def : InstAlias<"xnop", (XORI R0, R0, 0)>; 4533 4534def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>; 4535def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>; 4536 4537//Disable this alias on AIX for now because as does not support them. 4538let Predicates = [ModernAs] in { 4539 4540foreach BR = 0-7 in { 4541 def : InstAlias<"mfbr"#BR#" $Rx", 4542 (MFDCR gprc:$Rx, !add(BR, 0x80))>, 4543 Requires<[IsPPC4xx]>; 4544 def : InstAlias<"mtbr"#BR#" $Rx", 4545 (MTDCR gprc:$Rx, !add(BR, 0x80))>, 4546 Requires<[IsPPC4xx]>; 4547} 4548 4549def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>; 4550def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>; 4551def : InstAlias<"mtudscr $Rx", (MTSPR 3, gprc:$Rx)>; 4552def : InstAlias<"mfudscr $Rx", (MFSPR gprc:$Rx, 3)>; 4553 4554def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>; 4555def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>; 4556 4557def : InstAlias<"mtlr $Rx", (MTSPR 8, gprc:$Rx)>; 4558def : InstAlias<"mflr $Rx", (MFSPR gprc:$Rx, 8)>; 4559 4560def : InstAlias<"mtctr $Rx", (MTSPR 9, gprc:$Rx)>; 4561def : InstAlias<"mfctr $Rx", (MFSPR gprc:$Rx, 9)>; 4562 4563def : InstAlias<"mtuamr $Rx", (MTSPR 13, gprc:$Rx)>; 4564def : InstAlias<"mfuamr $Rx", (MFSPR gprc:$Rx, 13)>; 4565 4566def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>; 4567def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>; 4568 4569def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>; 4570def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>; 4571 4572def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>; 4573def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>; 4574 4575def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>; 4576def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>; 4577 4578def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>; 4579def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>; 4580 4581def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>; 4582def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>; 4583 4584def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>; 4585def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>; 4586 4587def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>; 4588def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>; 4589 4590def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>; 4591def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>; 4592 4593def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>; 4594def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>; 4595 4596foreach SPRG = 4-7 in { 4597 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>, 4598 Requires<[IsBookE]>; 4599 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>, 4600 Requires<[IsBookE]>; 4601 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>, 4602 Requires<[IsBookE]>; 4603 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>, 4604 Requires<[IsBookE]>; 4605} 4606 4607foreach SPRG = 0-3 in { 4608 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>; 4609 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>; 4610 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>; 4611 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>; 4612} 4613 4614def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>; 4615def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>; 4616 4617def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>; 4618def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>; 4619 4620def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>; 4621 4622def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>; 4623def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>; 4624 4625foreach BATR = 0-3 in { 4626 def : InstAlias<"mtdbatu "#BATR#", $Rx", 4627 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>, 4628 Requires<[IsPPC6xx]>; 4629 def : InstAlias<"mfdbatu $Rx, "#BATR, 4630 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>, 4631 Requires<[IsPPC6xx]>; 4632 def : InstAlias<"mtdbatl "#BATR#", $Rx", 4633 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>, 4634 Requires<[IsPPC6xx]>; 4635 def : InstAlias<"mfdbatl $Rx, "#BATR, 4636 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>, 4637 Requires<[IsPPC6xx]>; 4638 def : InstAlias<"mtibatu "#BATR#", $Rx", 4639 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>, 4640 Requires<[IsPPC6xx]>; 4641 def : InstAlias<"mfibatu $Rx, "#BATR, 4642 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>, 4643 Requires<[IsPPC6xx]>; 4644 def : InstAlias<"mtibatl "#BATR#", $Rx", 4645 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>, 4646 Requires<[IsPPC6xx]>; 4647 def : InstAlias<"mfibatl $Rx, "#BATR, 4648 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>, 4649 Requires<[IsPPC6xx]>; 4650} 4651 4652def : InstAlias<"mtppr $RT", (MTSPR 896, gprc:$RT)>; 4653def : InstAlias<"mfppr $RT", (MFSPR gprc:$RT, 896)>; 4654 4655def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4656def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>; 4657 4658def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4659def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>; 4660 4661def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4662def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>; 4663 4664def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>; 4665def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4666 4667def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>; 4668def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4669 4670def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4671def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>; 4672 4673def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4674def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>; 4675 4676def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4677def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>; 4678 4679def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4680def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>; 4681 4682} 4683 4684def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>; 4685 4686def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>, 4687 Requires<[IsPPC4xx]>; 4688def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>, 4689 Requires<[IsPPC4xx]>; 4690def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>, 4691 Requires<[IsPPC4xx]>; 4692def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>, 4693 Requires<[IsPPC4xx]>; 4694 4695def : InstAlias<"tlbilxlpid", (TLBILX 0, R0, R0)>, Requires<[IsBookE]>; 4696def : InstAlias<"tlbilxpid", (TLBILX 1, R0, R0)>, Requires<[IsBookE]>; 4697def : InstAlias<"tlbilxva $RA, $RB", (TLBILX 3, gprc:$RA, gprc:$RB)>, 4698 Requires<[IsBookE]>; 4699def : InstAlias<"tlbilxva $RB", (TLBILX 3, R0, gprc:$RB)>, Requires<[IsBookE]>; 4700 4701def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>; 4702 4703def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm", 4704 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4705def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm", 4706 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4707def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm", 4708 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4709def SUBIC_rec : PPCAsmPseudo<"subic. $rA, $rB, $imm", 4710 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4711 4712def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b", 4713 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>, 4714 ZExt32To64; 4715def EXTLWI_rec : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b", 4716 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>, 4717 ZExt32To64; 4718def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b", 4719 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4720def EXTRWI_rec : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b", 4721 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4722def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b", 4723 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4724def INSLWI_rec : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b", 4725 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4726def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b", 4727 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4728def INSRWI_rec : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b", 4729 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4730def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n", 4731 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4732def ROTRWI_rec : PPCAsmPseudo<"rotrwi. $rA, $rS, $n", 4733 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4734def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n", 4735 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4736def SLWI_rec : PPCAsmPseudo<"slwi. $rA, $rS, $n", 4737 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4738def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n", 4739 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4740def SRWI_rec : PPCAsmPseudo<"srwi. $rA, $rS, $n", 4741 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4742def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n", 4743 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4744def CLRRWI_rec : PPCAsmPseudo<"clrrwi. $rA, $rS, $n", 4745 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4746def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n", 4747 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 4748def CLRLSLWI_rec : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n", 4749 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 4750 4751def : InstAlias<"isellt $rT, $rA, $rB", 4752 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0LT)>; 4753def : InstAlias<"iselgt $rT, $rA, $rB", 4754 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0GT)>; 4755def : InstAlias<"iseleq $rT, $rA, $rB", 4756 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0EQ)>; 4757 4758def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 4759def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 4760def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 4761def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM_rec gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 4762def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 4763def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 4764 4765def : InstAlias<"cntlzw $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>; 4766def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW_rec gprc:$rA, gprc:$rS)>; 4767// The POWER variant 4768def : MnemonicAlias<"cntlz", "cntlzw">; 4769def : MnemonicAlias<"cntlz.", "cntlzw.">; 4770 4771def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b", 4772 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4773def EXTLDI_rec : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b", 4774 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4775def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b", 4776 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4777def EXTRDI_rec : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b", 4778 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4779def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b", 4780 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4781def INSRDI_rec : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b", 4782 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4783def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n", 4784 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4785def ROTRDI_rec : PPCAsmPseudo<"rotrdi. $rA, $rS, $n", 4786 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4787def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n", 4788 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4789def SLDI_rec : PPCAsmPseudo<"sldi. $rA, $rS, $n", 4790 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4791def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n", 4792 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4793def SRDI_rec : PPCAsmPseudo<"srdi. $rA, $rS, $n", 4794 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4795def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n", 4796 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4797def CLRRDI_rec : PPCAsmPseudo<"clrrdi. $rA, $rS, $n", 4798 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4799def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n", 4800 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 4801def CLRLSLDI_rec : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n", 4802 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 4803def SUBPCIS : PPCAsmPseudo<"subpcis $RT, $D", (ins g8rc:$RT, s16imm:$D)>; 4804 4805def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 4806def : InstAlias<"rotldi $rA, $rS, $n", 4807 (RLDICL_32_64 g8rc:$rA, gprc:$rS, u6imm:$n, 0)>; 4808def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 4809def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 4810def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCL_rec g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 4811def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 4812def : InstAlias<"clrldi $rA, $rS, $n", 4813 (RLDICL_32_64 g8rc:$rA, gprc:$rS, 0, u6imm:$n)>; 4814def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 4815def : InstAlias<"lnia $RT", (ADDPCIS g8rc:$RT, 0)>; 4816 4817def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b", 4818 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4819def RLWINMbm_rec : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b", 4820 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4821def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b", 4822 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4823def RLWIMIbm_rec : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b", 4824 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4825def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b", 4826 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4827def RLWNMbm_rec : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b", 4828 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4829 4830// These generic branch instruction forms are used for the assembler parser only. 4831// Defs and Uses are conservative, since we don't know the BO value. 4832let PPC970_Unit = 7, isBranch = 1, hasSideEffects = 0 in { 4833 let Defs = [CTR], Uses = [CTR, RM] in { 4834 def gBC : BForm_3<16, 0, 0, (outs), 4835 (ins u5imm:$BO, crbitrc:$BI, condbrtarget:$BD), 4836 "bc $BO, $BI, $BD">; 4837 def gBCA : BForm_3<16, 1, 0, (outs), 4838 (ins u5imm:$BO, crbitrc:$BI, abscondbrtarget:$BD), 4839 "bca $BO, $BI, $BD">; 4840 let isAsmParserOnly = 1 in { 4841 def gBCat : BForm_3_at<16, 0, 0, (outs), 4842 (ins u5imm:$BO, atimm:$at, crbitrc:$BI, 4843 condbrtarget:$BD), 4844 "bc$at $BO, $BI, $BD">; 4845 def gBCAat : BForm_3_at<16, 1, 0, (outs), 4846 (ins u5imm:$BO, atimm:$at, crbitrc:$BI, 4847 abscondbrtarget:$BD), 4848 "bca$at $BO, $BI, $BD">; 4849 } // isAsmParserOnly = 1 4850 } 4851 let Defs = [LR, CTR], Uses = [CTR, RM] in { 4852 def gBCL : BForm_3<16, 0, 1, (outs), 4853 (ins u5imm:$BO, crbitrc:$BI, condbrtarget:$BD), 4854 "bcl $BO, $BI, $BD">; 4855 def gBCLA : BForm_3<16, 1, 1, (outs), 4856 (ins u5imm:$BO, crbitrc:$BI, abscondbrtarget:$BD), 4857 "bcla $BO, $BI, $BD">; 4858 let isAsmParserOnly = 1 in { 4859 def gBCLat : BForm_3_at<16, 0, 1, (outs), 4860 (ins u5imm:$BO, atimm:$at, crbitrc:$BI, 4861 condbrtarget:$BD), 4862 "bcl$at $BO, $BI, $BD">; 4863 def gBCLAat : BForm_3_at<16, 1, 1, (outs), 4864 (ins u5imm:$BO, atimm:$at, crbitrc:$BI, 4865 abscondbrtarget:$BD), 4866 "bcla$at $BO, $BI, $BD">; 4867 } // // isAsmParserOnly = 1 4868 } 4869 let Defs = [CTR], Uses = [CTR, LR, RM] in 4870 def gBCLR : XLForm_2<19, 16, 0, (outs), 4871 (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH), 4872 "bclr $BO, $BI, $BH", IIC_BrB, []>; 4873 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 4874 def gBCLRL : XLForm_2<19, 16, 1, (outs), 4875 (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH), 4876 "bclrl $BO, $BI, $BH", IIC_BrB, []>; 4877 let Defs = [CTR], Uses = [CTR, LR, RM] in 4878 def gBCCTR : XLForm_2<19, 528, 0, (outs), 4879 (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH), 4880 "bcctr $BO, $BI, $BH", IIC_BrB, []>; 4881 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 4882 def gBCCTRL : XLForm_2<19, 528, 1, (outs), 4883 (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH), 4884 "bcctrl $BO, $BI, $BH", IIC_BrB, []>; 4885} 4886 4887multiclass BranchSimpleMnemonicAT<string pm, int at> { 4888 def : InstAlias<"bc"#pm#" $bo, $bi, $dst", (gBCat u5imm:$bo, at, crbitrc:$bi, 4889 condbrtarget:$dst)>; 4890 def : InstAlias<"bca"#pm#" $bo, $bi, $dst", (gBCAat u5imm:$bo, at, crbitrc:$bi, 4891 condbrtarget:$dst)>; 4892 def : InstAlias<"bcl"#pm#" $bo, $bi, $dst", (gBCLat u5imm:$bo, at, crbitrc:$bi, 4893 condbrtarget:$dst)>; 4894 def : InstAlias<"bcla"#pm#" $bo, $bi, $dst", (gBCLAat u5imm:$bo, at, crbitrc:$bi, 4895 condbrtarget:$dst)>; 4896} 4897defm : BranchSimpleMnemonicAT<"+", 3>; 4898defm : BranchSimpleMnemonicAT<"-", 2>; 4899 4900def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>; 4901def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>; 4902def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>; 4903def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>; 4904 4905multiclass BranchSimpleMnemonic1<string name, string pm, int bo> { 4906 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>; 4907 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 4908 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>; 4909 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>; 4910 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 4911 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>; 4912} 4913multiclass BranchSimpleMnemonic2<string name, string pm, int bo> 4914 : BranchSimpleMnemonic1<name, pm, bo> { 4915 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>; 4916 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>; 4917} 4918defm : BranchSimpleMnemonic2<"t", "", 12>; 4919defm : BranchSimpleMnemonic2<"f", "", 4>; 4920defm : BranchSimpleMnemonic2<"t", "-", 14>; 4921defm : BranchSimpleMnemonic2<"f", "-", 6>; 4922defm : BranchSimpleMnemonic2<"t", "+", 15>; 4923defm : BranchSimpleMnemonic2<"f", "+", 7>; 4924defm : BranchSimpleMnemonic1<"dnzt", "", 8>; 4925defm : BranchSimpleMnemonic1<"dnzf", "", 0>; 4926defm : BranchSimpleMnemonic1<"dzt", "", 10>; 4927defm : BranchSimpleMnemonic1<"dzf", "", 2>; 4928 4929multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> { 4930 def : InstAlias<"b"#name#pm#" $cc, $dst", 4931 (BCC bibo, crrc:$cc, condbrtarget:$dst)>; 4932 def : InstAlias<"b"#name#pm#" $dst", 4933 (BCC bibo, CR0, condbrtarget:$dst)>; 4934 4935 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst", 4936 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>; 4937 def : InstAlias<"b"#name#"a"#pm#" $dst", 4938 (BCCA bibo, CR0, abscondbrtarget:$dst)>; 4939 4940 def : InstAlias<"b"#name#"lr"#pm#" $cc", 4941 (BCCLR bibo, crrc:$cc)>; 4942 def : InstAlias<"b"#name#"lr"#pm, 4943 (BCCLR bibo, CR0)>; 4944 4945 def : InstAlias<"b"#name#"ctr"#pm#" $cc", 4946 (BCCCTR bibo, crrc:$cc)>; 4947 def : InstAlias<"b"#name#"ctr"#pm, 4948 (BCCCTR bibo, CR0)>; 4949 4950 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst", 4951 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>; 4952 def : InstAlias<"b"#name#"l"#pm#" $dst", 4953 (BCCL bibo, CR0, condbrtarget:$dst)>; 4954 4955 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst", 4956 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>; 4957 def : InstAlias<"b"#name#"la"#pm#" $dst", 4958 (BCCLA bibo, CR0, abscondbrtarget:$dst)>; 4959 4960 def : InstAlias<"b"#name#"lrl"#pm#" $cc", 4961 (BCCLRL bibo, crrc:$cc)>; 4962 def : InstAlias<"b"#name#"lrl"#pm, 4963 (BCCLRL bibo, CR0)>; 4964 4965 def : InstAlias<"b"#name#"ctrl"#pm#" $cc", 4966 (BCCCTRL bibo, crrc:$cc)>; 4967 def : InstAlias<"b"#name#"ctrl"#pm, 4968 (BCCCTRL bibo, CR0)>; 4969} 4970multiclass BranchExtendedMnemonic<string name, int bibo> { 4971 defm : BranchExtendedMnemonicPM<name, "", bibo>; 4972 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>; 4973 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>; 4974} 4975defm : BranchExtendedMnemonic<"lt", 12>; 4976defm : BranchExtendedMnemonic<"gt", 44>; 4977defm : BranchExtendedMnemonic<"eq", 76>; 4978defm : BranchExtendedMnemonic<"un", 108>; 4979defm : BranchExtendedMnemonic<"so", 108>; 4980defm : BranchExtendedMnemonic<"ge", 4>; 4981defm : BranchExtendedMnemonic<"nl", 4>; 4982defm : BranchExtendedMnemonic<"le", 36>; 4983defm : BranchExtendedMnemonic<"ng", 36>; 4984defm : BranchExtendedMnemonic<"ne", 68>; 4985defm : BranchExtendedMnemonic<"nu", 100>; 4986defm : BranchExtendedMnemonic<"ns", 100>; 4987 4988def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; 4989def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; 4990def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; 4991def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; 4992def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>; 4993def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; 4994def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>; 4995def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; 4996 4997def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>; 4998def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>; 4999def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>; 5000def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>; 5001def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>; 5002def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 5003def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>; 5004def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 5005 5006def : InstAlias<"trap", (TW 31, R0, R0)>; 5007 5008multiclass TrapExtendedMnemonic<string name, int to> { 5009 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>; 5010 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>; 5011 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>; 5012 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>; 5013} 5014defm : TrapExtendedMnemonic<"lt", 16>; 5015defm : TrapExtendedMnemonic<"le", 20>; 5016defm : TrapExtendedMnemonic<"eq", 4>; 5017defm : TrapExtendedMnemonic<"ge", 12>; 5018defm : TrapExtendedMnemonic<"gt", 8>; 5019defm : TrapExtendedMnemonic<"nl", 12>; 5020defm : TrapExtendedMnemonic<"ne", 24>; 5021defm : TrapExtendedMnemonic<"ng", 20>; 5022defm : TrapExtendedMnemonic<"llt", 2>; 5023defm : TrapExtendedMnemonic<"lle", 6>; 5024defm : TrapExtendedMnemonic<"lge", 5>; 5025defm : TrapExtendedMnemonic<"lgt", 1>; 5026defm : TrapExtendedMnemonic<"lnl", 5>; 5027defm : TrapExtendedMnemonic<"lng", 6>; 5028defm : TrapExtendedMnemonic<"u", 31>; 5029 5030// Atomic loads 5031def : Pat<(atomic_load_8 DForm:$src), (LBZ memri:$src)>; 5032def : Pat<(atomic_load_16 DForm:$src), (LHZ memri:$src)>; 5033def : Pat<(atomic_load_32 DForm:$src), (LWZ memri:$src)>; 5034def : Pat<(atomic_load_8 XForm:$src), (LBZX memrr:$src)>; 5035def : Pat<(atomic_load_16 XForm:$src), (LHZX memrr:$src)>; 5036def : Pat<(atomic_load_32 XForm:$src), (LWZX memrr:$src)>; 5037 5038// Atomic stores 5039def : Pat<(atomic_store_8 i32:$val, DForm:$ptr), (STB gprc:$val, memri:$ptr)>; 5040def : Pat<(atomic_store_16 i32:$val, DForm:$ptr), (STH gprc:$val, memri:$ptr)>; 5041def : Pat<(atomic_store_32 i32:$val, DForm:$ptr), (STW gprc:$val, memri:$ptr)>; 5042def : Pat<(atomic_store_8 i32:$val, XForm:$ptr), (STBX gprc:$val, memrr:$ptr)>; 5043def : Pat<(atomic_store_16 i32:$val, XForm:$ptr), (STHX gprc:$val, memrr:$ptr)>; 5044def : Pat<(atomic_store_32 i32:$val, XForm:$ptr), (STWX gprc:$val, memrr:$ptr)>; 5045 5046let Predicates = [IsISA3_0] in { 5047 5048// Copy-Paste Facility 5049// We prefix 'CP' to COPY due to name conflict in Target.td. We also prefix to 5050// PASTE for naming consistency. 5051let mayLoad = 1 in 5052def CP_COPY : X_RA5_RB5<31, 774, "copy" , gprc, IIC_LdStCOPY, []>; 5053 5054let mayStore = 1, Defs = [CR0] in 5055def CP_PASTE_rec : X_L1_RA5_RB5<31, 902, "paste.", gprc, IIC_LdStPASTE, []>, isRecordForm; 5056 5057def : InstAlias<"paste. $RA, $RB", (CP_PASTE_rec gprc:$RA, gprc:$RB, 1)>; 5058def CP_ABORT : XForm_0<31, 838, (outs), (ins), "cpabort", IIC_SprABORT, []>; 5059 5060// Message Synchronize 5061def MSGSYNC : XForm_0<31, 886, (outs), (ins), "msgsync", IIC_SprMSGSYNC, []>; 5062 5063// Power-Saving Mode Instruction: 5064def STOP : XForm_0<19, 370, (outs), (ins), "stop", IIC_SprSTOP, []>; 5065 5066def SETB : XForm_44<31, 128, (outs gprc:$RT), (ins crrc:$BFA), 5067 "setb $RT, $BFA", IIC_IntGeneral>, SExt32To64; 5068} // IsISA3_0 5069 5070let Predicates = [IsISA3_0] in { 5071def : Pat<(i32 (int_ppc_cmprb i32:$a, gprc:$b, gprc:$c)), 5072 (i32 (SETB (CMPRB u1imm:$a, $b, $c)))>; 5073} 5074def : Pat<(i32 (int_ppc_mulhw gprc:$a, gprc:$b)), 5075 (i32 (MULHW $a, $b))>; 5076def : Pat<(i32 (int_ppc_mulhwu gprc:$a, gprc:$b)), 5077 (i32 (MULHWU $a, $b))>; 5078def : Pat<(i32 (int_ppc_cmpb gprc:$a, gprc:$b)), 5079 (i32 (CMPB $a, $b))>; 5080 5081def : Pat<(int_ppc_load2r ForceXForm:$ptr), 5082 (LHBRX ForceXForm:$ptr)>; 5083def : Pat<(int_ppc_load4r ForceXForm:$ptr), 5084 (LWBRX ForceXForm:$ptr)>; 5085def : Pat<(int_ppc_store2r gprc:$a, ForceXForm:$ptr), 5086 (STHBRX gprc:$a, ForceXForm:$ptr)>; 5087def : Pat<(int_ppc_store4r gprc:$a, ForceXForm:$ptr), 5088 (STWBRX gprc:$a, ForceXForm:$ptr)>; 5089 5090 5091// Fast 32-bit reverse bits algorithm: 5092// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit): 5093// n = ((n >> 1) & 0x55555555) | ((n << 1) & 0xAAAAAAAA); 5094// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit): 5095// n = ((n >> 2) & 0x33333333) | ((n << 2) & 0xCCCCCCCC); 5096// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit): 5097// n = ((n >> 4) & 0x0F0F0F0F) | ((n << 4) & 0xF0F0F0F0); 5098// Step 4: byte reverse (Suppose n = [B1,B2,B3,B4]): 5099// Step 4.1: Put B4,B2 in the right position (rotate left 3 bytes): 5100// n' = (n rotl 24); After which n' = [B4, B1, B2, B3] 5101// Step 4.2: Insert B3 to the right position: 5102// n' = rlwimi n', n, 8, 8, 15; After which n' = [B4, B3, B2, B3] 5103// Step 4.3: Insert B1 to the right position: 5104// n' = rlwimi n', n, 8, 24, 31; After which n' = [B4, B3, B2, B1] 5105def MaskValues { 5106 dag Lo1 = (ORI (LIS 0x5555), 0x5555); 5107 dag Hi1 = (ORI (LIS 0xAAAA), 0xAAAA); 5108 dag Lo2 = (ORI (LIS 0x3333), 0x3333); 5109 dag Hi2 = (ORI (LIS 0xCCCC), 0xCCCC); 5110 dag Lo4 = (ORI (LIS 0x0F0F), 0x0F0F); 5111 dag Hi4 = (ORI (LIS 0xF0F0), 0xF0F0); 5112} 5113 5114def Shift1 { 5115 dag Right = (RLWINM $A, 31, 1, 31); 5116 dag Left = (RLWINM $A, 1, 0, 30); 5117} 5118 5119def Swap1 { 5120 dag Bit = (OR (AND Shift1.Right, MaskValues.Lo1), 5121 (AND Shift1.Left, MaskValues.Hi1)); 5122} 5123 5124def Shift2 { 5125 dag Right = (RLWINM Swap1.Bit, 30, 2, 31); 5126 dag Left = (RLWINM Swap1.Bit, 2, 0, 29); 5127} 5128 5129def Swap2 { 5130 dag Bits = (OR (AND Shift2.Right, MaskValues.Lo2), 5131 (AND Shift2.Left, MaskValues.Hi2)); 5132} 5133 5134def Shift4 { 5135 dag Right = (RLWINM Swap2.Bits, 28, 4, 31); 5136 dag Left = (RLWINM Swap2.Bits, 4, 0, 27); 5137} 5138 5139def Swap4 { 5140 dag Bits = (OR (AND Shift4.Right, MaskValues.Lo4), 5141 (AND Shift4.Left, MaskValues.Hi4)); 5142} 5143 5144def Rotate { 5145 dag Left3Bytes = (RLWINM Swap4.Bits, 24, 0, 31); 5146} 5147 5148def RotateInsertByte3 { 5149 dag Left = (RLWIMI Rotate.Left3Bytes, Swap4.Bits, 8, 8, 15); 5150} 5151 5152def RotateInsertByte1 { 5153 dag Left = (RLWIMI RotateInsertByte3.Left, Swap4.Bits, 8, 24, 31); 5154} 5155 5156// Clear the upper half of the register when in 64-bit mode 5157let Predicates = [In64BitMode] in 5158def : Pat<(i32 (bitreverse i32:$A)), (RLDICL_32 RotateInsertByte1.Left, 0, 32)>; 5159let Predicates = [In32BitMode] in 5160def : Pat<(i32 (bitreverse i32:$A)), RotateInsertByte1.Left>; 5161 5162// Fast 64-bit reverse bits algorithm: 5163// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit): 5164// n = ((n >> 1) & 0x5555555555555555) | ((n << 1) & 0xAAAAAAAAAAAAAAAA); 5165// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit): 5166// n = ((n >> 2) & 0x3333333333333333) | ((n << 2) & 0xCCCCCCCCCCCCCCCC); 5167// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit): 5168// n = ((n >> 4) & 0x0F0F0F0F0F0F0F0F) | ((n << 4) & 0xF0F0F0F0F0F0F0F0); 5169// Step 4: byte reverse (Suppose n = [B0,B1,B2,B3,B4,B5,B6,B7]): 5170// Apply the same byte reverse algorithm mentioned above for the fast 32-bit 5171// reverse to both the high 32 bit and low 32 bit of the 64 bit value. And 5172// then OR them together to get the final result. 5173def MaskValues64 { 5174 dag Lo1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo1, sub_32)); 5175 dag Hi1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi1, sub_32)); 5176 dag Lo2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo2, sub_32)); 5177 dag Hi2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi2, sub_32)); 5178 dag Lo4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo4, sub_32)); 5179 dag Hi4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi4, sub_32)); 5180} 5181 5182def DWMaskValues { 5183 dag Lo1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo1, 32, 31), 0x5555), 0x5555); 5184 dag Hi1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi1, 32, 31), 0xAAAA), 0xAAAA); 5185 dag Lo2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo2, 32, 31), 0x3333), 0x3333); 5186 dag Hi2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi2, 32, 31), 0xCCCC), 0xCCCC); 5187 dag Lo4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo4, 32, 31), 0x0F0F), 0x0F0F); 5188 dag Hi4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi4, 32, 31), 0xF0F0), 0xF0F0); 5189} 5190 5191def DWSwapInByte { 5192 dag Swap1 = (OR8 (AND8 (RLDICL $A, 63, 1), DWMaskValues.Lo1), 5193 (AND8 (RLDICR $A, 1, 62), DWMaskValues.Hi1)); 5194 dag Swap2 = (OR8 (AND8 (RLDICL Swap1, 62, 2), DWMaskValues.Lo2), 5195 (AND8 (RLDICR Swap1, 2, 61), DWMaskValues.Hi2)); 5196 dag Swap4 = (OR8 (AND8 (RLDICL Swap2, 60, 4), DWMaskValues.Lo4), 5197 (AND8 (RLDICR Swap2, 4, 59), DWMaskValues.Hi4)); 5198} 5199 5200// Intra-byte swap is done, now start inter-byte swap. 5201def DWBytes4567 { 5202 dag Word = (i32 (EXTRACT_SUBREG DWSwapInByte.Swap4, sub_32)); 5203} 5204 5205def DWBytes7456 { 5206 dag Word = (RLWINM DWBytes4567.Word, 24, 0, 31); 5207} 5208 5209def DWBytes7656 { 5210 dag Word = (RLWIMI DWBytes7456.Word, DWBytes4567.Word, 8, 8, 15); 5211} 5212 5213// B7 B6 B5 B4 in the right order 5214def DWBytes7654 { 5215 dag Word = (RLWIMI DWBytes7656.Word, DWBytes4567.Word, 8, 24, 31); 5216 dag DWord = 5217 (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32)); 5218} 5219 5220def DWBytes0123 { 5221 dag Word = (i32 (EXTRACT_SUBREG (RLDICL DWSwapInByte.Swap4, 32, 32), sub_32)); 5222} 5223 5224def DWBytes3012 { 5225 dag Word = (RLWINM DWBytes0123.Word, 24, 0, 31); 5226} 5227 5228def DWBytes3212 { 5229 dag Word = (RLWIMI DWBytes3012.Word, DWBytes0123.Word, 8, 8, 15); 5230} 5231 5232// B3 B2 B1 B0 in the right order 5233def DWBytes3210 { 5234 dag Word = (RLWIMI DWBytes3212.Word, DWBytes0123.Word, 8, 24, 31); 5235 dag DWord = 5236 (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32)); 5237} 5238 5239// These instructions store a hash computed from the value of the link register 5240// and the value of the stack pointer. 5241let mayStore = 1 in { 5242def HASHST : XForm_XD6_RA5_RB5<31, 722, (outs), 5243 (ins gprc:$RB, (memrihash $D, $RA):$addr), 5244 "hashst $RB, $addr", IIC_IntGeneral, []>; 5245def HASHSTP : XForm_XD6_RA5_RB5<31, 658, (outs), 5246 (ins gprc:$RB, (memrihash $D, $RA):$addr), 5247 "hashstp $RB, $addr", IIC_IntGeneral, []>; 5248} 5249 5250// These instructions check a hash computed from the value of the link register 5251// and the value of the stack pointer. The hasSideEffects flag is needed as the 5252// instruction may TRAP if the hash does not match the hash stored at the 5253// specified address. 5254let mayLoad = 1, hasSideEffects = 1 in { 5255def HASHCHK : XForm_XD6_RA5_RB5<31, 754, (outs), 5256 (ins gprc:$RB, (memrihash $D, $RA):$addr), 5257 "hashchk $RB, $addr", IIC_IntGeneral, []>; 5258def HASHCHKP : XForm_XD6_RA5_RB5<31, 690, (outs), 5259 (ins gprc:$RB, (memrihash $D, $RA):$addr), 5260 "hashchkp $RB, $addr", IIC_IntGeneral, []>; 5261} 5262 5263let Defs = [CR7], Itinerary = IIC_LdStSync in 5264def CFENCE : PPCPostRAExpPseudo<(outs), (ins gprc:$cr), "#CFENCE", []>; 5265 5266// Now both high word and low word are reversed, next 5267// swap the high word and low word. 5268def : Pat<(i64 (bitreverse i64:$A)), 5269 (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>; 5270 5271def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A), 5272 (STWCX gprc:$A, ForceXForm:$dst)>; 5273def : Pat<(PPCStoreCond ForceXForm:$dst, gprc:$A, 4), 5274 (STWCX gprc:$A, ForceXForm:$dst)>; 5275def : Pat<(int_ppc_stbcx ForceXForm:$dst, gprc:$A), 5276 (STBCX gprc:$A, ForceXForm:$dst)>; 5277def : Pat<(PPCStoreCond ForceXForm:$dst, gprc:$A, 1), 5278 (STBCX gprc:$A, ForceXForm:$dst)>; 5279 5280def : Pat<(int_ppc_fcfid f64:$A), 5281 (XSCVSXDDP $A)>; 5282def : Pat<(int_ppc_fcfud f64:$A), 5283 (XSCVUXDDP $A)>; 5284def : Pat<(int_ppc_fctid f64:$A), 5285 (FCTID $A)>; 5286def : Pat<(int_ppc_fctidz f64:$A), 5287 (XSCVDPSXDS $A)>; 5288def : Pat<(int_ppc_fctiw f64:$A), 5289 (FCTIW $A)>; 5290def : Pat<(int_ppc_fctiwz f64:$A), 5291 (XSCVDPSXWS $A)>; 5292def : Pat<(int_ppc_fctudz f64:$A), 5293 (XSCVDPUXDS $A)>; 5294def : Pat<(int_ppc_fctuwz f64:$A), 5295 (XSCVDPUXWS $A)>; 5296 5297def : Pat<(int_ppc_mfmsr), (MFMSR)>; 5298def : Pat<(int_ppc_mftbu), (MFTB 269)>; 5299def : Pat<(i32 (int_ppc_mfspr timm:$SPR)), 5300 (MFSPR $SPR)>; 5301def : Pat<(int_ppc_mtspr timm:$SPR, gprc:$RT), 5302 (MTSPR $SPR, $RT)>; 5303def : Pat<(int_ppc_mtmsr gprc:$RS), 5304 (MTMSR $RS, 0)>; 5305 5306let Predicates = [IsISA2_07] in { 5307 def : Pat<(int_ppc_sthcx ForceXForm:$dst, gprc:$A), 5308 (STHCX gprc:$A, ForceXForm:$dst)>; 5309 def : Pat<(PPCStoreCond ForceXForm:$dst, gprc:$A, 2), 5310 (STHCX gprc:$A, ForceXForm:$dst)>; 5311} 5312def : Pat<(int_ppc_dcbtstt ForceXForm:$dst), 5313 (DCBTST 16, ForceXForm:$dst)>; 5314def : Pat<(int_ppc_dcbtt ForceXForm:$dst), 5315 (DCBT 16, ForceXForm:$dst)>; 5316 5317def : Pat<(int_ppc_stfiw ForceXForm:$dst, f64:$XT), 5318 (STFIWX f64:$XT, ForceXForm:$dst)>; 5319