1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that PPC uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H 15 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H 16 17 #include "PPCInstrInfo.h" 18 #include "llvm/CodeGen/CallingConvLower.h" 19 #include "llvm/CodeGen/MachineFunction.h" 20 #include "llvm/CodeGen/MachineMemOperand.h" 21 #include "llvm/CodeGen/SelectionDAG.h" 22 #include "llvm/CodeGen/SelectionDAGNodes.h" 23 #include "llvm/CodeGen/TargetLowering.h" 24 #include "llvm/CodeGen/ValueTypes.h" 25 #include "llvm/IR/Attributes.h" 26 #include "llvm/IR/CallingConv.h" 27 #include "llvm/IR/Function.h" 28 #include "llvm/IR/InlineAsm.h" 29 #include "llvm/IR/Metadata.h" 30 #include "llvm/IR/Type.h" 31 #include "llvm/Support/MachineValueType.h" 32 #include <utility> 33 34 namespace llvm { 35 36 namespace PPCISD { 37 38 // When adding a NEW PPCISD node please add it to the correct position in 39 // the enum. The order of elements in this enum matters! 40 // Values that are added after this entry: 41 // STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE 42 // are considered memory opcodes and are treated differently than entries 43 // that come before it. For example, ADD or MUL should be placed before 44 // the ISD::FIRST_TARGET_MEMORY_OPCODE while a LOAD or STORE should come 45 // after it. 46 enum NodeType : unsigned { 47 // Start the numbering where the builtin ops and target ops leave off. 48 FIRST_NUMBER = ISD::BUILTIN_OP_END, 49 50 /// FSEL - Traditional three-operand fsel node. 51 /// 52 FSEL, 53 54 /// XSMAXCDP, XSMINCDP - C-type min/max instructions. 55 XSMAXCDP, 56 XSMINCDP, 57 58 /// FCFID - The FCFID instruction, taking an f64 operand and producing 59 /// and f64 value containing the FP representation of the integer that 60 /// was temporarily in the f64 operand. 61 FCFID, 62 63 /// Newer FCFID[US] integer-to-floating-point conversion instructions for 64 /// unsigned integers and single-precision outputs. 65 FCFIDU, 66 FCFIDS, 67 FCFIDUS, 68 69 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 70 /// operand, producing an f64 value containing the integer representation 71 /// of that FP value. 72 FCTIDZ, 73 FCTIWZ, 74 75 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for 76 /// unsigned integers with round toward zero. 77 FCTIDUZ, 78 FCTIWUZ, 79 80 /// Floating-point-to-interger conversion instructions 81 FP_TO_UINT_IN_VSR, 82 FP_TO_SINT_IN_VSR, 83 84 /// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in 85 /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer. 86 VEXTS, 87 88 /// Reciprocal estimate instructions (unary FP ops). 89 FRE, 90 FRSQRTE, 91 92 /// Test instruction for software square root. 93 FTSQRT, 94 95 /// Square root instruction. 96 FSQRT, 97 98 /// VPERM - The PPC VPERM Instruction. 99 /// 100 VPERM, 101 102 /// XXSPLT - The PPC VSX splat instructions 103 /// 104 XXSPLT, 105 106 /// XXSPLTI_SP_TO_DP - The PPC VSX splat instructions for immediates for 107 /// converting immediate single precision numbers to double precision 108 /// vector or scalar. 109 XXSPLTI_SP_TO_DP, 110 111 /// XXSPLTI32DX - The PPC XXSPLTI32DX instruction. 112 /// 113 XXSPLTI32DX, 114 115 /// VECINSERT - The PPC vector insert instruction 116 /// 117 VECINSERT, 118 119 /// VECSHL - The PPC vector shift left instruction 120 /// 121 VECSHL, 122 123 /// XXPERMDI - The PPC XXPERMDI instruction 124 /// 125 XXPERMDI, 126 127 /// The CMPB instruction (takes two operands of i32 or i64). 128 CMPB, 129 130 /// Hi/Lo - These represent the high and low 16-bit parts of a global 131 /// address respectively. These nodes have two operands, the first of 132 /// which must be a TargetGlobalAddress, and the second of which must be a 133 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', 134 /// though these are usually folded into other nodes. 135 Hi, 136 Lo, 137 138 /// The following two target-specific nodes are used for calls through 139 /// function pointers in the 64-bit SVR4 ABI. 140 141 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) 142 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 143 /// compute an allocation on the stack. 144 DYNALLOC, 145 146 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 147 /// compute an offset from native SP to the address of the most recent 148 /// dynamic alloca. 149 DYNAREAOFFSET, 150 151 /// To avoid stack clash, allocation is performed by block and each block is 152 /// probed. 153 PROBED_ALLOCA, 154 155 /// The result of the mflr at function entry, used for PIC code. 156 GlobalBaseReg, 157 158 /// These nodes represent PPC shifts. 159 /// 160 /// For scalar types, only the last `n + 1` bits of the shift amounts 161 /// are used, where n is log2(sizeof(element) * 8). See sld/slw, etc. 162 /// for exact behaviors. 163 /// 164 /// For vector types, only the last n bits are used. See vsld. 165 SRL, 166 SRA, 167 SHL, 168 169 /// FNMSUB - Negated multiply-subtract instruction. 170 FNMSUB, 171 172 /// EXTSWSLI = The PPC extswsli instruction, which does an extend-sign 173 /// word and shift left immediate. 174 EXTSWSLI, 175 176 /// The combination of sra[wd]i and addze used to implemented signed 177 /// integer division by a power of 2. The first operand is the dividend, 178 /// and the second is the constant shift amount (representing the 179 /// divisor). 180 SRA_ADDZE, 181 182 /// CALL - A direct function call. 183 /// CALL_NOP is a call with the special NOP which follows 64-bit 184 /// CALL_NOTOC the caller does not use the TOC. 185 /// SVR4 calls and 32-bit/64-bit AIX calls. 186 CALL, 187 CALL_NOP, 188 CALL_NOTOC, 189 190 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a 191 /// MTCTR instruction. 192 MTCTR, 193 194 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a 195 /// BCTRL instruction. 196 BCTRL, 197 198 /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl 199 /// instruction and the TOC reload required on 64-bit ELF, 32-bit AIX 200 /// and 64-bit AIX. 201 BCTRL_LOAD_TOC, 202 203 /// Return with a flag operand, matched by 'blr' 204 RET_FLAG, 205 206 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction. 207 /// This copies the bits corresponding to the specified CRREG into the 208 /// resultant GPR. Bits corresponding to other CR regs are undefined. 209 MFOCRF, 210 211 /// Direct move from a VSX register to a GPR 212 MFVSR, 213 214 /// Direct move from a GPR to a VSX register (algebraic) 215 MTVSRA, 216 217 /// Direct move from a GPR to a VSX register (zero) 218 MTVSRZ, 219 220 /// Direct move of 2 consecutive GPR to a VSX register. 221 BUILD_FP128, 222 223 /// BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and 224 /// EXTRACT_ELEMENT but take f64 arguments instead of i64, as i64 is 225 /// unsupported for this target. 226 /// Merge 2 GPRs to a single SPE register. 227 BUILD_SPE64, 228 229 /// Extract SPE register component, second argument is high or low. 230 EXTRACT_SPE, 231 232 /// Extract a subvector from signed integer vector and convert to FP. 233 /// It is primarily used to convert a (widened) illegal integer vector 234 /// type to a legal floating point vector type. 235 /// For example v2i32 -> widened to v4i32 -> v2f64 236 SINT_VEC_TO_FP, 237 238 /// Extract a subvector from unsigned integer vector and convert to FP. 239 /// As with SINT_VEC_TO_FP, used for converting illegal types. 240 UINT_VEC_TO_FP, 241 242 /// PowerPC instructions that have SCALAR_TO_VECTOR semantics tend to 243 /// place the value into the least significant element of the most 244 /// significant doubleword in the vector. This is not element zero for 245 /// anything smaller than a doubleword on either endianness. This node has 246 /// the same semantics as SCALAR_TO_VECTOR except that the value remains in 247 /// the aforementioned location in the vector register. 248 SCALAR_TO_VECTOR_PERMUTED, 249 250 // FIXME: Remove these once the ANDI glue bug is fixed: 251 /// i1 = ANDI_rec_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the 252 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to 253 /// implement truncation of i32 or i64 to i1. 254 ANDI_rec_1_EQ_BIT, 255 ANDI_rec_1_GT_BIT, 256 257 // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit 258 // target (returns (Lo, Hi)). It takes a chain operand. 259 READ_TIME_BASE, 260 261 // EH_SJLJ_SETJMP - SjLj exception handling setjmp. 262 EH_SJLJ_SETJMP, 263 264 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp. 265 EH_SJLJ_LONGJMP, 266 267 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* 268 /// instructions. For lack of better number, we use the opcode number 269 /// encoding for the OPC field to identify the compare. For example, 838 270 /// is VCMPGTSH. 271 VCMP, 272 273 /// RESVEC, OUTFLAG = VCMP_rec(LHS, RHS, OPC) - Represents one of the 274 /// altivec VCMP*_rec instructions. For lack of better number, we use the 275 /// opcode number encoding for the OPC field to identify the compare. For 276 /// example, 838 is VCMPGTSH. 277 VCMP_rec, 278 279 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This 280 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the 281 /// condition register to branch on, OPC is the branch opcode to use (e.g. 282 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is 283 /// an optional input flag argument. 284 COND_BRANCH, 285 286 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based 287 /// loops. 288 BDNZ, 289 BDZ, 290 291 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding 292 /// towards zero. Used only as part of the long double-to-int 293 /// conversion sequence. 294 FADDRTZ, 295 296 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register. 297 MFFS, 298 299 /// TC_RETURN - A tail call return. 300 /// operand #0 chain 301 /// operand #1 callee (register or absolute) 302 /// operand #2 stack adjustment 303 /// operand #3 optional in flag 304 TC_RETURN, 305 306 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls 307 CR6SET, 308 CR6UNSET, 309 310 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS 311 /// for non-position independent code on PPC32. 312 PPC32_GOT, 313 314 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and 315 /// local dynamic TLS and position indendepent code on PPC32. 316 PPC32_PICGOT, 317 318 /// G8RC = ADDIS_GOT_TPREL_HA %x2, Symbol - Used by the initial-exec 319 /// TLS model, produces an ADDIS8 instruction that adds the GOT 320 /// base to sym\@got\@tprel\@ha. 321 ADDIS_GOT_TPREL_HA, 322 323 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec 324 /// TLS model, produces a LD instruction with base register G8RReg 325 /// and offset sym\@got\@tprel\@l. This completes the addition that 326 /// finds the offset of "sym" relative to the thread pointer. 327 LD_GOT_TPREL_L, 328 329 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS 330 /// model, produces an ADD instruction that adds the contents of 331 /// G8RReg to the thread pointer. Symbol contains a relocation 332 /// sym\@tls which is to be replaced by the thread pointer and 333 /// identifies to the linker that the instruction is part of a 334 /// TLS sequence. 335 ADD_TLS, 336 337 /// G8RC = ADDIS_TLSGD_HA %x2, Symbol - For the general-dynamic TLS 338 /// model, produces an ADDIS8 instruction that adds the GOT base 339 /// register to sym\@got\@tlsgd\@ha. 340 ADDIS_TLSGD_HA, 341 342 /// %x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS 343 /// model, produces an ADDI8 instruction that adds G8RReg to 344 /// sym\@got\@tlsgd\@l and stores the result in X3. Hidden by 345 /// ADDIS_TLSGD_L_ADDR until after register assignment. 346 ADDI_TLSGD_L, 347 348 /// %x3 = GET_TLS_ADDR %x3, Symbol - For the general-dynamic TLS 349 /// model, produces a call to __tls_get_addr(sym\@tlsgd). Hidden by 350 /// ADDIS_TLSGD_L_ADDR until after register assignment. 351 GET_TLS_ADDR, 352 353 /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that 354 /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following 355 /// register assignment. 356 ADDI_TLSGD_L_ADDR, 357 358 /// G8RC = ADDIS_TLSLD_HA %x2, Symbol - For the local-dynamic TLS 359 /// model, produces an ADDIS8 instruction that adds the GOT base 360 /// register to sym\@got\@tlsld\@ha. 361 ADDIS_TLSLD_HA, 362 363 /// %x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS 364 /// model, produces an ADDI8 instruction that adds G8RReg to 365 /// sym\@got\@tlsld\@l and stores the result in X3. Hidden by 366 /// ADDIS_TLSLD_L_ADDR until after register assignment. 367 ADDI_TLSLD_L, 368 369 /// %x3 = GET_TLSLD_ADDR %x3, Symbol - For the local-dynamic TLS 370 /// model, produces a call to __tls_get_addr(sym\@tlsld). Hidden by 371 /// ADDIS_TLSLD_L_ADDR until after register assignment. 372 GET_TLSLD_ADDR, 373 374 /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that 375 /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion 376 /// following register assignment. 377 ADDI_TLSLD_L_ADDR, 378 379 /// G8RC = ADDIS_DTPREL_HA %x3, Symbol - For the local-dynamic TLS 380 /// model, produces an ADDIS8 instruction that adds X3 to 381 /// sym\@dtprel\@ha. 382 ADDIS_DTPREL_HA, 383 384 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS 385 /// model, produces an ADDI8 instruction that adds G8RReg to 386 /// sym\@got\@dtprel\@l. 387 ADDI_DTPREL_L, 388 389 /// G8RC = PADDI_DTPREL %x3, Symbol - For the pc-rel based local-dynamic TLS 390 /// model, produces a PADDI8 instruction that adds X3 to sym\@dtprel. 391 PADDI_DTPREL, 392 393 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded 394 /// during instruction selection to optimize a BUILD_VECTOR into 395 /// operations on splats. This is necessary to avoid losing these 396 /// optimizations due to constant folding. 397 VADD_SPLAT, 398 399 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned 400 /// operand identifies the operating system entry point. 401 SC, 402 403 /// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer. 404 CLRBHRB, 405 406 /// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch 407 /// history rolling buffer entry. 408 MFBHRBE, 409 410 /// CHAIN = RFEBB CHAIN, State - Return from event-based branch. 411 RFEBB, 412 413 /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little 414 /// endian. Maps to an xxswapd instruction that corrects an lxvd2x 415 /// or stxvd2x instruction. The chain is necessary because the 416 /// sequence replaces a load and needs to provide the same number 417 /// of outputs. 418 XXSWAPD, 419 420 /// An SDNode for swaps that are not associated with any loads/stores 421 /// and thereby have no chain. 422 SWAP_NO_CHAIN, 423 424 /// An SDNode for Power9 vector absolute value difference. 425 /// operand #0 vector 426 /// operand #1 vector 427 /// operand #2 constant i32 0 or 1, to indicate whether needs to patch 428 /// the most significant bit for signed i32 429 /// 430 /// Power9 VABSD* instructions are designed to support unsigned integer 431 /// vectors (byte/halfword/word), if we want to make use of them for signed 432 /// integer vectors, we have to flip their sign bits first. To flip sign bit 433 /// for byte/halfword integer vector would become inefficient, but for word 434 /// integer vector, we can leverage XVNEGSP to make it efficiently. eg: 435 /// abs(sub(a,b)) => VABSDUW(a+0x80000000, b+0x80000000) 436 /// => VABSDUW((XVNEGSP a), (XVNEGSP b)) 437 VABSD, 438 439 /// FP_EXTEND_HALF(VECTOR, IDX) - Custom extend upper (IDX=0) half or 440 /// lower (IDX=1) half of v4f32 to v2f64. 441 FP_EXTEND_HALF, 442 443 /// MAT_PCREL_ADDR = Materialize a PC Relative address. This can be done 444 /// either through an add like PADDI or through a PC Relative load like 445 /// PLD. 446 MAT_PCREL_ADDR, 447 448 /// TLS_DYNAMIC_MAT_PCREL_ADDR = Materialize a PC Relative address for 449 /// TLS global address when using dynamic access models. This can be done 450 /// through an add like PADDI. 451 TLS_DYNAMIC_MAT_PCREL_ADDR, 452 453 /// TLS_LOCAL_EXEC_MAT_ADDR = Materialize an address for TLS global address 454 /// when using local exec access models, and when prefixed instructions are 455 /// available. This is used with ADD_TLS to produce an add like PADDI. 456 TLS_LOCAL_EXEC_MAT_ADDR, 457 458 /// ACC_BUILD = Build an accumulator register from 4 VSX registers. 459 ACC_BUILD, 460 461 /// PAIR_BUILD = Build a vector pair register from 2 VSX registers. 462 PAIR_BUILD, 463 464 /// EXTRACT_VSX_REG = Extract one of the underlying vsx registers of 465 /// an accumulator or pair register. This node is needed because 466 /// EXTRACT_SUBVECTOR expects the input and output vectors to have the same 467 /// element type. 468 EXTRACT_VSX_REG, 469 470 /// XXMFACC = This corresponds to the xxmfacc instruction. 471 XXMFACC, 472 473 // Constrained conversion from floating point to int 474 STRICT_FCTIDZ = ISD::FIRST_TARGET_STRICTFP_OPCODE, 475 STRICT_FCTIWZ, 476 STRICT_FCTIDUZ, 477 STRICT_FCTIWUZ, 478 479 /// Constrained integer-to-floating-point conversion instructions. 480 STRICT_FCFID, 481 STRICT_FCFIDU, 482 STRICT_FCFIDS, 483 STRICT_FCFIDUS, 484 485 /// Constrained floating point add in round-to-zero mode. 486 STRICT_FADDRTZ, 487 488 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a 489 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of 490 /// the GPRC input, then stores it through Ptr. Type can be either i16 or 491 /// i32. 492 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE, 493 494 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a 495 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, 496 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 497 /// or i32. 498 LBRX, 499 500 /// STFIWX - The STFIWX instruction. The first operand is an input token 501 /// chain, then an f64 value to store, then an address to store it to. 502 STFIWX, 503 504 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point 505 /// load which sign-extends from a 32-bit integer value into the 506 /// destination 64-bit register. 507 LFIWAX, 508 509 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point 510 /// load which zero-extends from a 32-bit integer value into the 511 /// destination 64-bit register. 512 LFIWZX, 513 514 /// GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an 515 /// integer smaller than 64 bits into a VSR. The integer is zero-extended. 516 /// This can be used for converting loaded integers to floating point. 517 LXSIZX, 518 519 /// STXSIX - The STXSI[bh]X instruction. The first operand is an input 520 /// chain, then an f64 value to store, then an address to store it to, 521 /// followed by a byte-width for the store. 522 STXSIX, 523 524 /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian. 525 /// Maps directly to an lxvd2x instruction that will be followed by 526 /// an xxswapd. 527 LXVD2X, 528 529 /// LXVRZX - Load VSX Vector Rightmost and Zero Extend 530 /// This node represents v1i128 BUILD_VECTOR of a zero extending load 531 /// instruction from <byte, halfword, word, or doubleword> to i128. 532 /// Allows utilization of the Load VSX Vector Rightmost Instructions. 533 LXVRZX, 534 535 /// VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian. 536 /// Maps directly to one of lxvd2x/lxvw4x/lxvh8x/lxvb16x depending on 537 /// the vector type to load vector in big-endian element order. 538 LOAD_VEC_BE, 539 540 /// VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a 541 /// v2f32 value into the lower half of a VSR register. 542 LD_VSX_LH, 543 544 /// VSRC, CHAIN = LD_SPLAT, CHAIN, Ptr - a splatting load memory 545 /// instructions such as LXVDSX, LXVWSX. 546 LD_SPLAT, 547 548 /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian. 549 /// Maps directly to an stxvd2x instruction that will be preceded by 550 /// an xxswapd. 551 STXVD2X, 552 553 /// CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian. 554 /// Maps directly to one of stxvd2x/stxvw4x/stxvh8x/stxvb16x depending on 555 /// the vector type to store vector in big-endian element order. 556 STORE_VEC_BE, 557 558 /// Store scalar integers from VSR. 559 ST_VSR_SCAL_INT, 560 561 /// ATOMIC_CMP_SWAP - the exact same as the target-independent nodes 562 /// except they ensure that the compare input is zero-extended for 563 /// sub-word versions because the atomic loads zero-extend. 564 ATOMIC_CMP_SWAP_8, 565 ATOMIC_CMP_SWAP_16, 566 567 /// GPRC = TOC_ENTRY GA, TOC 568 /// Loads the entry for GA from the TOC, where the TOC base is given by 569 /// the last operand. 570 TOC_ENTRY 571 }; 572 573 } // end namespace PPCISD 574 575 /// Define some predicates that are used for node matching. 576 namespace PPC { 577 578 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 579 /// VPKUHUM instruction. 580 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 581 SelectionDAG &DAG); 582 583 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 584 /// VPKUWUM instruction. 585 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 586 SelectionDAG &DAG); 587 588 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a 589 /// VPKUDUM instruction. 590 bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 591 SelectionDAG &DAG); 592 593 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 594 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 595 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 596 unsigned ShuffleKind, SelectionDAG &DAG); 597 598 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 599 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 600 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 601 unsigned ShuffleKind, SelectionDAG &DAG); 602 603 /// isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for 604 /// a VMRGEW or VMRGOW instruction 605 bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven, 606 unsigned ShuffleKind, SelectionDAG &DAG); 607 /// isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable 608 /// for a XXSLDWI instruction. 609 bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, 610 bool &Swap, bool IsLE); 611 612 /// isXXBRHShuffleMask - Return true if this is a shuffle mask suitable 613 /// for a XXBRH instruction. 614 bool isXXBRHShuffleMask(ShuffleVectorSDNode *N); 615 616 /// isXXBRWShuffleMask - Return true if this is a shuffle mask suitable 617 /// for a XXBRW instruction. 618 bool isXXBRWShuffleMask(ShuffleVectorSDNode *N); 619 620 /// isXXBRDShuffleMask - Return true if this is a shuffle mask suitable 621 /// for a XXBRD instruction. 622 bool isXXBRDShuffleMask(ShuffleVectorSDNode *N); 623 624 /// isXXBRQShuffleMask - Return true if this is a shuffle mask suitable 625 /// for a XXBRQ instruction. 626 bool isXXBRQShuffleMask(ShuffleVectorSDNode *N); 627 628 /// isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable 629 /// for a XXPERMDI instruction. 630 bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, 631 bool &Swap, bool IsLE); 632 633 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the 634 /// shift amount, otherwise return -1. 635 int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, 636 SelectionDAG &DAG); 637 638 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 639 /// specifies a splat of a single element that is suitable for input to 640 /// VSPLTB/VSPLTH/VSPLTW. 641 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize); 642 643 /// isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by 644 /// the XXINSERTW instruction introduced in ISA 3.0. This is essentially any 645 /// shuffle of v4f32/v4i32 vectors that just inserts one element from one 646 /// vector into the other. This function will also set a couple of 647 /// output parameters for how much the source vector needs to be shifted and 648 /// what byte number needs to be specified for the instruction to put the 649 /// element in the desired location of the target vector. 650 bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, 651 unsigned &InsertAtByte, bool &Swap, bool IsLE); 652 653 /// getSplatIdxForPPCMnemonics - Return the splat index as a value that is 654 /// appropriate for PPC mnemonics (which have a big endian bias - namely 655 /// elements are counted from the left of the vector register). 656 unsigned getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize, 657 SelectionDAG &DAG); 658 659 /// get_VSPLTI_elt - If this is a build_vector of constants which can be 660 /// formed by using a vspltis[bhw] instruction of the specified element 661 /// size, return the constant being splatted. The ByteSize field indicates 662 /// the number of bytes of each element [124] -> [bhw]. 663 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 664 665 } // end namespace PPC 666 667 class PPCTargetLowering : public TargetLowering { 668 const PPCSubtarget &Subtarget; 669 670 public: 671 explicit PPCTargetLowering(const PPCTargetMachine &TM, 672 const PPCSubtarget &STI); 673 674 /// getTargetNodeName() - This method returns the name of a target specific 675 /// DAG node. 676 const char *getTargetNodeName(unsigned Opcode) const override; 677 678 bool isSelectSupported(SelectSupportKind Kind) const override { 679 // PowerPC does not support scalar condition selects on vectors. 680 return (Kind != SelectSupportKind::ScalarCondVectorVal); 681 } 682 683 /// getPreferredVectorAction - The code we generate when vector types are 684 /// legalized by promoting the integer element type is often much worse 685 /// than code we generate if we widen the type for applicable vector types. 686 /// The issue with promoting is that the vector is scalaraized, individual 687 /// elements promoted and then the vector is rebuilt. So say we load a pair 688 /// of v4i8's and shuffle them. This will turn into a mess of 8 extending 689 /// loads, moves back into VSR's (or memory ops if we don't have moves) and 690 /// then the VPERM for the shuffle. All in all a very slow sequence. 691 TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) 692 const override { 693 if (VT.getVectorNumElements() != 1 && VT.getScalarSizeInBits() % 8 == 0) 694 return TypeWidenVector; 695 return TargetLoweringBase::getPreferredVectorAction(VT); 696 } 697 698 bool useSoftFloat() const override; 699 700 bool hasSPE() const; 701 702 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 703 return MVT::i32; 704 } 705 706 bool isCheapToSpeculateCttz() const override { 707 return true; 708 } 709 710 bool isCheapToSpeculateCtlz() const override { 711 return true; 712 } 713 714 bool isCtlzFast() const override { 715 return true; 716 } 717 718 bool isEqualityCmpFoldedWithSignedCmp() const override { 719 return false; 720 } 721 722 bool hasAndNotCompare(SDValue) const override { 723 return true; 724 } 725 726 bool preferIncOfAddToSubOfNot(EVT VT) const override; 727 728 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { 729 return VT.isScalarInteger(); 730 } 731 732 SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, 733 bool OptForSize, NegatibleCost &Cost, 734 unsigned Depth = 0) const override; 735 736 /// getSetCCResultType - Return the ISD::SETCC ValueType 737 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 738 EVT VT) const override; 739 740 /// Return true if target always beneficiates from combining into FMA for a 741 /// given value type. This must typically return false on targets where FMA 742 /// takes more cycles to execute than FADD. 743 bool enableAggressiveFMAFusion(EVT VT) const override; 744 745 /// getPreIndexedAddressParts - returns true by value, base pointer and 746 /// offset pointer and addressing mode by reference if the node's address 747 /// can be legally represented as pre-indexed load / store address. 748 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 749 SDValue &Offset, 750 ISD::MemIndexedMode &AM, 751 SelectionDAG &DAG) const override; 752 753 /// SelectAddressEVXRegReg - Given the specified addressed, check to see if 754 /// it can be more efficiently represented as [r+imm]. 755 bool SelectAddressEVXRegReg(SDValue N, SDValue &Base, SDValue &Index, 756 SelectionDAG &DAG) const; 757 758 /// SelectAddressRegReg - Given the specified addressed, check to see if it 759 /// can be more efficiently represented as [r+imm]. If \p EncodingAlignment 760 /// is non-zero, only accept displacement which is not suitable for [r+imm]. 761 /// Returns false if it can be represented by [r+imm], which are preferred. 762 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, 763 SelectionDAG &DAG, 764 MaybeAlign EncodingAlignment = None) const; 765 766 /// SelectAddressRegImm - Returns true if the address N can be represented 767 /// by a base register plus a signed 16-bit displacement [r+imm], and if it 768 /// is not better represented as reg+reg. If \p EncodingAlignment is 769 /// non-zero, only accept displacements suitable for instruction encoding 770 /// requirement, i.e. multiples of 4 for DS form. 771 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, 772 SelectionDAG &DAG, 773 MaybeAlign EncodingAlignment) const; 774 bool SelectAddressRegImm34(SDValue N, SDValue &Disp, SDValue &Base, 775 SelectionDAG &DAG) const; 776 777 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be 778 /// represented as an indexed [r+r] operation. 779 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, 780 SelectionDAG &DAG) const; 781 782 /// SelectAddressPCRel - Represent the specified address as pc relative to 783 /// be represented as [pc+imm] 784 bool SelectAddressPCRel(SDValue N, SDValue &Base) const; 785 786 Sched::Preference getSchedulingPreference(SDNode *N) const override; 787 788 /// LowerOperation - Provide custom lowering hooks for some operations. 789 /// 790 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 791 792 /// ReplaceNodeResults - Replace the results of node with an illegal result 793 /// type with new values built out of custom code. 794 /// 795 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 796 SelectionDAG &DAG) const override; 797 798 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const; 799 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const; 800 801 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 802 803 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 804 SmallVectorImpl<SDNode *> &Created) const override; 805 806 Register getRegisterByName(const char* RegName, LLT VT, 807 const MachineFunction &MF) const override; 808 809 void computeKnownBitsForTargetNode(const SDValue Op, 810 KnownBits &Known, 811 const APInt &DemandedElts, 812 const SelectionDAG &DAG, 813 unsigned Depth = 0) const override; 814 815 Align getPrefLoopAlignment(MachineLoop *ML) const override; 816 817 bool shouldInsertFencesForAtomic(const Instruction *I) const override { 818 return true; 819 } 820 821 Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, 822 AtomicOrdering Ord) const override; 823 Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, 824 AtomicOrdering Ord) const override; 825 826 MachineBasicBlock * 827 EmitInstrWithCustomInserter(MachineInstr &MI, 828 MachineBasicBlock *MBB) const override; 829 MachineBasicBlock *EmitAtomicBinary(MachineInstr &MI, 830 MachineBasicBlock *MBB, 831 unsigned AtomicSize, 832 unsigned BinOpcode, 833 unsigned CmpOpcode = 0, 834 unsigned CmpPred = 0) const; 835 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr &MI, 836 MachineBasicBlock *MBB, 837 bool is8bit, 838 unsigned Opcode, 839 unsigned CmpOpcode = 0, 840 unsigned CmpPred = 0) const; 841 842 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI, 843 MachineBasicBlock *MBB) const; 844 845 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI, 846 MachineBasicBlock *MBB) const; 847 848 MachineBasicBlock *emitProbedAlloca(MachineInstr &MI, 849 MachineBasicBlock *MBB) const; 850 851 bool hasInlineStackProbe(MachineFunction &MF) const override; 852 853 unsigned getStackProbeSize(MachineFunction &MF) const; 854 855 ConstraintType getConstraintType(StringRef Constraint) const override; 856 857 /// Examine constraint string and operand type and determine a weight value. 858 /// The operand object must already have been set up with the operand type. 859 ConstraintWeight getSingleConstraintMatchWeight( 860 AsmOperandInfo &info, const char *constraint) const override; 861 862 std::pair<unsigned, const TargetRegisterClass *> 863 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 864 StringRef Constraint, MVT VT) const override; 865 866 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 867 /// function arguments in the caller parameter area. This is the actual 868 /// alignment, not its logarithm. 869 unsigned getByValTypeAlignment(Type *Ty, 870 const DataLayout &DL) const override; 871 872 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 873 /// vector. If it is invalid, don't add anything to Ops. 874 void LowerAsmOperandForConstraint(SDValue Op, 875 std::string &Constraint, 876 std::vector<SDValue> &Ops, 877 SelectionDAG &DAG) const override; 878 879 unsigned 880 getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 881 if (ConstraintCode == "es") 882 return InlineAsm::Constraint_es; 883 else if (ConstraintCode == "o") 884 return InlineAsm::Constraint_o; 885 else if (ConstraintCode == "Q") 886 return InlineAsm::Constraint_Q; 887 else if (ConstraintCode == "Z") 888 return InlineAsm::Constraint_Z; 889 else if (ConstraintCode == "Zy") 890 return InlineAsm::Constraint_Zy; 891 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 892 } 893 894 /// isLegalAddressingMode - Return true if the addressing mode represented 895 /// by AM is legal for this target, for a load/store of the specified type. 896 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 897 Type *Ty, unsigned AS, 898 Instruction *I = nullptr) const override; 899 900 /// isLegalICmpImmediate - Return true if the specified immediate is legal 901 /// icmp immediate, that is the target has icmp instructions which can 902 /// compare a register against the immediate without having to materialize 903 /// the immediate into a register. 904 bool isLegalICmpImmediate(int64_t Imm) const override; 905 906 /// isLegalAddImmediate - Return true if the specified immediate is legal 907 /// add immediate, that is the target has add instructions which can 908 /// add a register and the immediate without having to materialize 909 /// the immediate into a register. 910 bool isLegalAddImmediate(int64_t Imm) const override; 911 912 /// isTruncateFree - Return true if it's free to truncate a value of 913 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in 914 /// register X1 to i32 by referencing its sub-register R1. 915 bool isTruncateFree(Type *Ty1, Type *Ty2) const override; 916 bool isTruncateFree(EVT VT1, EVT VT2) const override; 917 918 bool isZExtFree(SDValue Val, EVT VT2) const override; 919 920 bool isFPExtFree(EVT DestVT, EVT SrcVT) const override; 921 922 /// Returns true if it is beneficial to convert a load of a constant 923 /// to just the constant itself. 924 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 925 Type *Ty) const override; 926 927 bool convertSelectOfConstantsToMath(EVT VT) const override { 928 return true; 929 } 930 931 bool decomposeMulByConstant(LLVMContext &Context, EVT VT, 932 SDValue C) const override; 933 934 bool isDesirableToTransformToIntegerOp(unsigned Opc, 935 EVT VT) const override { 936 // Only handle float load/store pair because float(fpr) load/store 937 // instruction has more cycles than integer(gpr) load/store in PPC. 938 if (Opc != ISD::LOAD && Opc != ISD::STORE) 939 return false; 940 if (VT != MVT::f32 && VT != MVT::f64) 941 return false; 942 943 return true; 944 } 945 946 // Returns true if the address of the global is stored in TOC entry. 947 bool isAccessedAsGotIndirect(SDValue N) const; 948 949 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 950 951 bool getTgtMemIntrinsic(IntrinsicInfo &Info, 952 const CallInst &I, 953 MachineFunction &MF, 954 unsigned Intrinsic) const override; 955 956 /// It returns EVT::Other if the type should be determined using generic 957 /// target-independent logic. 958 EVT getOptimalMemOpType(const MemOp &Op, 959 const AttributeList &FuncAttributes) const override; 960 961 /// Is unaligned memory access allowed for the given type, and is it fast 962 /// relative to software emulation. 963 bool allowsMisalignedMemoryAccesses( 964 EVT VT, unsigned AddrSpace, unsigned Align = 1, 965 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 966 bool *Fast = nullptr) const override; 967 968 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster 969 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be 970 /// expanded to FMAs when this method returns true, otherwise fmuladd is 971 /// expanded to fmul + fadd. 972 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 973 EVT VT) const override; 974 975 bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override; 976 977 /// isProfitableToHoist - Check if it is profitable to hoist instruction 978 /// \p I to its dominator block. 979 /// For example, it is not profitable if \p I and it's only user can form a 980 /// FMA instruction, because Powerpc prefers FMADD. 981 bool isProfitableToHoist(Instruction *I) const override; 982 983 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override; 984 985 // Should we expand the build vector with shuffles? 986 bool 987 shouldExpandBuildVectorWithShuffles(EVT VT, 988 unsigned DefinedValues) const override; 989 990 // Keep the zero-extensions for arguments to libcalls. 991 bool shouldKeepZExtForFP16Conv() const override { return true; } 992 993 /// createFastISel - This method returns a target-specific FastISel object, 994 /// or null if the target does not support "fast" instruction selection. 995 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 996 const TargetLibraryInfo *LibInfo) const override; 997 998 /// Returns true if an argument of type Ty needs to be passed in a 999 /// contiguous block of registers in calling convention CallConv. 1000 bool functionArgumentNeedsConsecutiveRegisters( 1001 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override { 1002 // We support any array type as "consecutive" block in the parameter 1003 // save area. The element type defines the alignment requirement and 1004 // whether the argument should go in GPRs, FPRs, or VRs if available. 1005 // 1006 // Note that clang uses this capability both to implement the ELFv2 1007 // homogeneous float/vector aggregate ABI, and to avoid having to use 1008 // "byval" when passing aggregates that might fully fit in registers. 1009 return Ty->isArrayTy(); 1010 } 1011 1012 /// If a physical register, this returns the register that receives the 1013 /// exception address on entry to an EH pad. 1014 Register 1015 getExceptionPointerRegister(const Constant *PersonalityFn) const override; 1016 1017 /// If a physical register, this returns the register that receives the 1018 /// exception typeid on entry to a landing pad. 1019 Register 1020 getExceptionSelectorRegister(const Constant *PersonalityFn) const override; 1021 1022 /// Override to support customized stack guard loading. 1023 bool useLoadStackGuardNode() const override; 1024 void insertSSPDeclarations(Module &M) const override; 1025 1026 bool isFPImmLegal(const APFloat &Imm, EVT VT, 1027 bool ForCodeSize) const override; 1028 1029 unsigned getJumpTableEncoding() const override; 1030 bool isJumpTableRelative() const override; 1031 SDValue getPICJumpTableRelocBase(SDValue Table, 1032 SelectionDAG &DAG) const override; 1033 const MCExpr *getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 1034 unsigned JTI, 1035 MCContext &Ctx) const override; 1036 1037 /// Structure that collects some common arguments that get passed around 1038 /// between the functions for call lowering. 1039 struct CallFlags { 1040 const CallingConv::ID CallConv; 1041 const bool IsTailCall : 1; 1042 const bool IsVarArg : 1; 1043 const bool IsPatchPoint : 1; 1044 const bool IsIndirect : 1; 1045 const bool HasNest : 1; 1046 const bool NoMerge : 1; 1047 1048 CallFlags(CallingConv::ID CC, bool IsTailCall, bool IsVarArg, 1049 bool IsPatchPoint, bool IsIndirect, bool HasNest, bool NoMerge) 1050 : CallConv(CC), IsTailCall(IsTailCall), IsVarArg(IsVarArg), 1051 IsPatchPoint(IsPatchPoint), IsIndirect(IsIndirect), 1052 HasNest(HasNest), NoMerge(NoMerge) {} 1053 }; 1054 1055 private: 1056 struct ReuseLoadInfo { 1057 SDValue Ptr; 1058 SDValue Chain; 1059 SDValue ResChain; 1060 MachinePointerInfo MPI; 1061 bool IsDereferenceable = false; 1062 bool IsInvariant = false; 1063 Align Alignment; 1064 AAMDNodes AAInfo; 1065 const MDNode *Ranges = nullptr; 1066 1067 ReuseLoadInfo() = default; 1068 1069 MachineMemOperand::Flags MMOFlags() const { 1070 MachineMemOperand::Flags F = MachineMemOperand::MONone; 1071 if (IsDereferenceable) 1072 F |= MachineMemOperand::MODereferenceable; 1073 if (IsInvariant) 1074 F |= MachineMemOperand::MOInvariant; 1075 return F; 1076 } 1077 }; 1078 1079 bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI, 1080 SelectionDAG &DAG, 1081 ISD::LoadExtType ET = ISD::NON_EXTLOAD) const; 1082 void spliceIntoChain(SDValue ResChain, SDValue NewResChain, 1083 SelectionDAG &DAG) const; 1084 1085 void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI, 1086 SelectionDAG &DAG, const SDLoc &dl) const; 1087 SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG, 1088 const SDLoc &dl) const; 1089 1090 bool directMoveIsProfitable(const SDValue &Op) const; 1091 SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG, 1092 const SDLoc &dl) const; 1093 1094 SDValue LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG, 1095 const SDLoc &dl) const; 1096 1097 SDValue LowerTRUNCATEVector(SDValue Op, SelectionDAG &DAG) const; 1098 1099 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const; 1100 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const; 1101 1102 bool 1103 IsEligibleForTailCallOptimization(SDValue Callee, 1104 CallingConv::ID CalleeCC, 1105 bool isVarArg, 1106 const SmallVectorImpl<ISD::InputArg> &Ins, 1107 SelectionDAG& DAG) const; 1108 1109 bool IsEligibleForTailCallOptimization_64SVR4( 1110 SDValue Callee, CallingConv::ID CalleeCC, const CallBase *CB, 1111 bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, 1112 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const; 1113 1114 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG, int SPDiff, 1115 SDValue Chain, SDValue &LROpOut, 1116 SDValue &FPOpOut, 1117 const SDLoc &dl) const; 1118 1119 SDValue getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, SDValue GA) const; 1120 1121 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 1122 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 1123 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 1124 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 1125 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 1126 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 1127 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 1128 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 1129 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 1130 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 1131 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const; 1132 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 1133 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; 1134 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 1135 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const; 1136 SDValue LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const; 1137 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 1138 SDValue LowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const; 1139 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 1140 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 1141 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const; 1142 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 1143 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, 1144 const SDLoc &dl) const; 1145 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 1146 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 1147 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const; 1148 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const; 1149 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const; 1150 SDValue LowerFunnelShift(SDValue Op, SelectionDAG &DAG) const; 1151 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 1152 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 1153 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 1154 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 1155 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 1156 SDValue LowerBSWAP(SDValue Op, SelectionDAG &DAG) const; 1157 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 1158 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 1159 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; 1160 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; 1161 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 1162 SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const; 1163 1164 SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const; 1165 SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const; 1166 1167 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 1168 CallingConv::ID CallConv, bool isVarArg, 1169 const SmallVectorImpl<ISD::InputArg> &Ins, 1170 const SDLoc &dl, SelectionDAG &DAG, 1171 SmallVectorImpl<SDValue> &InVals) const; 1172 1173 SDValue FinishCall(CallFlags CFlags, const SDLoc &dl, SelectionDAG &DAG, 1174 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, 1175 SDValue InFlag, SDValue Chain, SDValue CallSeqStart, 1176 SDValue &Callee, int SPDiff, unsigned NumBytes, 1177 const SmallVectorImpl<ISD::InputArg> &Ins, 1178 SmallVectorImpl<SDValue> &InVals, 1179 const CallBase *CB) const; 1180 1181 SDValue 1182 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1183 const SmallVectorImpl<ISD::InputArg> &Ins, 1184 const SDLoc &dl, SelectionDAG &DAG, 1185 SmallVectorImpl<SDValue> &InVals) const override; 1186 1187 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 1188 SmallVectorImpl<SDValue> &InVals) const override; 1189 1190 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 1191 bool isVarArg, 1192 const SmallVectorImpl<ISD::OutputArg> &Outs, 1193 LLVMContext &Context) const override; 1194 1195 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1196 const SmallVectorImpl<ISD::OutputArg> &Outs, 1197 const SmallVectorImpl<SDValue> &OutVals, 1198 const SDLoc &dl, SelectionDAG &DAG) const override; 1199 1200 SDValue extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, 1201 SelectionDAG &DAG, SDValue ArgVal, 1202 const SDLoc &dl) const; 1203 1204 SDValue LowerFormalArguments_AIX( 1205 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1206 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1207 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 1208 SDValue LowerFormalArguments_64SVR4( 1209 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1210 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1211 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 1212 SDValue LowerFormalArguments_32SVR4( 1213 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1214 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1215 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; 1216 1217 SDValue createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff, 1218 SDValue CallSeqStart, 1219 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1220 const SDLoc &dl) const; 1221 1222 SDValue LowerCall_64SVR4(SDValue Chain, SDValue Callee, CallFlags CFlags, 1223 const SmallVectorImpl<ISD::OutputArg> &Outs, 1224 const SmallVectorImpl<SDValue> &OutVals, 1225 const SmallVectorImpl<ISD::InputArg> &Ins, 1226 const SDLoc &dl, SelectionDAG &DAG, 1227 SmallVectorImpl<SDValue> &InVals, 1228 const CallBase *CB) const; 1229 SDValue LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallFlags CFlags, 1230 const SmallVectorImpl<ISD::OutputArg> &Outs, 1231 const SmallVectorImpl<SDValue> &OutVals, 1232 const SmallVectorImpl<ISD::InputArg> &Ins, 1233 const SDLoc &dl, SelectionDAG &DAG, 1234 SmallVectorImpl<SDValue> &InVals, 1235 const CallBase *CB) const; 1236 SDValue LowerCall_AIX(SDValue Chain, SDValue Callee, CallFlags CFlags, 1237 const SmallVectorImpl<ISD::OutputArg> &Outs, 1238 const SmallVectorImpl<SDValue> &OutVals, 1239 const SmallVectorImpl<ISD::InputArg> &Ins, 1240 const SDLoc &dl, SelectionDAG &DAG, 1241 SmallVectorImpl<SDValue> &InVals, 1242 const CallBase *CB) const; 1243 1244 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 1245 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 1246 SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const; 1247 1248 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const; 1249 SDValue DAGCombineBuildVector(SDNode *N, DAGCombinerInfo &DCI) const; 1250 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const; 1251 SDValue combineStoreFPToInt(SDNode *N, DAGCombinerInfo &DCI) const; 1252 SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const; 1253 SDValue combineSHL(SDNode *N, DAGCombinerInfo &DCI) const; 1254 SDValue combineSRA(SDNode *N, DAGCombinerInfo &DCI) const; 1255 SDValue combineSRL(SDNode *N, DAGCombinerInfo &DCI) const; 1256 SDValue combineMUL(SDNode *N, DAGCombinerInfo &DCI) const; 1257 SDValue combineADD(SDNode *N, DAGCombinerInfo &DCI) const; 1258 SDValue combineFMALike(SDNode *N, DAGCombinerInfo &DCI) const; 1259 SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const; 1260 SDValue combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const; 1261 SDValue combineABS(SDNode *N, DAGCombinerInfo &DCI) const; 1262 SDValue combineVSelect(SDNode *N, DAGCombinerInfo &DCI) const; 1263 SDValue combineVectorShuffle(ShuffleVectorSDNode *SVN, 1264 SelectionDAG &DAG) const; 1265 SDValue combineVReverseMemOP(ShuffleVectorSDNode *SVN, LSBaseSDNode *LSBase, 1266 DAGCombinerInfo &DCI) const; 1267 1268 /// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces 1269 /// SETCC with integer subtraction when (1) there is a legal way of doing it 1270 /// (2) keeping the result of comparison in GPR has performance benefit. 1271 SDValue ConvertSETCCToSubtract(SDNode *N, DAGCombinerInfo &DCI) const; 1272 1273 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 1274 int &RefinementSteps, bool &UseOneConstNR, 1275 bool Reciprocal) const override; 1276 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 1277 int &RefinementSteps) const override; 1278 SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG, 1279 const DenormalMode &Mode) const override; 1280 SDValue getSqrtResultForDenormInput(SDValue Operand, 1281 SelectionDAG &DAG) const override; 1282 unsigned combineRepeatedFPDivisors() const override; 1283 1284 SDValue 1285 combineElementTruncationToVectorTruncation(SDNode *N, 1286 DAGCombinerInfo &DCI) const; 1287 1288 /// lowerToVINSERTH - Return the SDValue if this VECTOR_SHUFFLE can be 1289 /// handled by the VINSERTH instruction introduced in ISA 3.0. This is 1290 /// essentially any shuffle of v8i16 vectors that just inserts one element 1291 /// from one vector into the other. 1292 SDValue lowerToVINSERTH(ShuffleVectorSDNode *N, SelectionDAG &DAG) const; 1293 1294 /// lowerToVINSERTB - Return the SDValue if this VECTOR_SHUFFLE can be 1295 /// handled by the VINSERTB instruction introduced in ISA 3.0. This is 1296 /// essentially v16i8 vector version of VINSERTH. 1297 SDValue lowerToVINSERTB(ShuffleVectorSDNode *N, SelectionDAG &DAG) const; 1298 1299 /// lowerToXXSPLTI32DX - Return the SDValue if this VECTOR_SHUFFLE can be 1300 /// handled by the XXSPLTI32DX instruction introduced in ISA 3.1. 1301 SDValue lowerToXXSPLTI32DX(ShuffleVectorSDNode *N, SelectionDAG &DAG) const; 1302 1303 // Return whether the call instruction can potentially be optimized to a 1304 // tail call. This will cause the optimizers to attempt to move, or 1305 // duplicate return instructions to help enable tail call optimizations. 1306 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 1307 bool hasBitPreservingFPLogic(EVT VT) const override; 1308 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override; 1309 }; // end class PPCTargetLowering 1310 1311 namespace PPC { 1312 1313 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 1314 const TargetLibraryInfo *LibInfo); 1315 1316 } // end namespace PPC 1317 1318 bool isIntS16Immediate(SDNode *N, int16_t &Imm); 1319 bool isIntS16Immediate(SDValue Op, int16_t &Imm); 1320 bool isIntS34Immediate(SDNode *N, int64_t &Imm); 1321 bool isIntS34Immediate(SDValue Op, int64_t &Imm); 1322 1323 bool convertToNonDenormSingle(APInt &ArgAPInt); 1324 bool convertToNonDenormSingle(APFloat &ArgAPFloat); 1325 1326 } // end namespace llvm 1327 1328 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 1329