xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp (revision 6580f5c38dd5b01aeeaed16b370f1a12423437f0) 
1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about Hexagon target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "HexagonTargetMachine.h"
14 #include "Hexagon.h"
15 #include "HexagonISelLowering.h"
16 #include "HexagonLoopIdiomRecognition.h"
17 #include "HexagonMachineFunctionInfo.h"
18 #include "HexagonMachineScheduler.h"
19 #include "HexagonTargetObjectFile.h"
20 #include "HexagonTargetTransformInfo.h"
21 #include "HexagonVectorLoopCarriedReuse.h"
22 #include "TargetInfo/HexagonTargetInfo.h"
23 #include "llvm/CodeGen/Passes.h"
24 #include "llvm/CodeGen/TargetPassConfig.h"
25 #include "llvm/CodeGen/VLIWMachineScheduler.h"
26 #include "llvm/IR/Module.h"
27 #include "llvm/MC/TargetRegistry.h"
28 #include "llvm/Passes/PassBuilder.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Transforms/Scalar.h"
31 #include <optional>
32 
33 using namespace llvm;
34 
35 static cl::opt<bool>
36     EnableCExtOpt("hexagon-cext", cl::Hidden, cl::init(true),
37                   cl::desc("Enable Hexagon constant-extender optimization"));
38 
39 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::init(true),
40                                   cl::desc("Enable RDF-based optimizations"));
41 
42 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
43   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
44 
45 static cl::opt<bool>
46     DisableAModeOpt("disable-hexagon-amodeopt", cl::Hidden,
47                     cl::desc("Disable Hexagon Addressing Mode Optimization"));
48 
49 static cl::opt<bool>
50     DisableHexagonCFGOpt("disable-hexagon-cfgopt", cl::Hidden,
51                          cl::desc("Disable Hexagon CFG Optimization"));
52 
53 static cl::opt<bool>
54     DisableHCP("disable-hcp", cl::Hidden,
55                cl::desc("Disable Hexagon constant propagation"));
56 
57 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
58   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
59 
60 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
61                                           cl::init(true), cl::Hidden,
62                                           cl::desc("Early expansion of MUX"));
63 
64 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
65                                    cl::desc("Enable early if-conversion"));
66 
67 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
68   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
69 
70 static cl::opt<bool>
71     EnableCommGEP("hexagon-commgep", cl::init(true), cl::Hidden,
72                   cl::desc("Enable commoning of GEP instructions"));
73 
74 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
75   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
76 
77 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
78   cl::desc("Enable converting conditional transfers into MUX instructions"));
79 
80 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
81   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
82   "predicate instructions"));
83 
84 static cl::opt<bool>
85     EnableLoopPrefetch("hexagon-loop-prefetch", cl::Hidden,
86                        cl::desc("Enable loop data prefetch on Hexagon"));
87 
88 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
89   cl::desc("Disable splitting double registers"));
90 
91 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
92   cl::Hidden, cl::desc("Bit simplification"));
93 
94 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
95   cl::Hidden, cl::desc("Loop rescheduling"));
96 
97 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
98   cl::Hidden, cl::desc("Disable backend optimizations"));
99 
100 static cl::opt<bool>
101     EnableVectorPrint("enable-hexagon-vector-print", cl::Hidden,
102                       cl::desc("Enable Hexagon Vector print instr pass"));
103 
104 static cl::opt<bool>
105     EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden, cl::init(true),
106                       cl::desc("Enable vextract optimization"));
107 
108 static cl::opt<bool>
109     EnableVectorCombine("hexagon-vector-combine", cl::Hidden, cl::init(true),
110                         cl::desc("Enable HVX vector combining"));
111 
112 static cl::opt<bool> EnableInitialCFGCleanup(
113     "hexagon-initial-cfg-cleanup", cl::Hidden, cl::init(true),
114     cl::desc("Simplify the CFG after atomic expansion pass"));
115 
116 static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden,
117                                         cl::init(true),
118                                         cl::desc("Enable instsimplify"));
119 
120 /// HexagonTargetMachineModule - Note that this is used on hosts that
121 /// cannot link in a library unless there are references into the
122 /// library.  In particular, it seems that it is not possible to get
123 /// things to work on Win32 without this.  Though it is unused, do not
124 /// remove it.
125 extern "C" int HexagonTargetMachineModule;
126 int HexagonTargetMachineModule = 0;
127 
128 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
129   ScheduleDAGMILive *DAG = new VLIWMachineScheduler(
130       C, std::make_unique<HexagonConvergingVLIWScheduler>());
131   DAG->addMutation(std::make_unique<HexagonSubtarget::UsrOverflowMutation>());
132   DAG->addMutation(std::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
133   DAG->addMutation(std::make_unique<HexagonSubtarget::CallMutation>());
134   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
135   return DAG;
136 }
137 
138 static MachineSchedRegistry
139 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
140                     createVLIWMachineSched);
141 
142 namespace llvm {
143   extern char &HexagonExpandCondsetsID;
144   void initializeHexagonBitSimplifyPass(PassRegistry&);
145   void initializeHexagonConstExtendersPass(PassRegistry&);
146   void initializeHexagonConstPropagationPass(PassRegistry&);
147   void initializeHexagonCopyToCombinePass(PassRegistry&);
148   void initializeHexagonEarlyIfConversionPass(PassRegistry&);
149   void initializeHexagonExpandCondsetsPass(PassRegistry&);
150   void initializeHexagonGenMuxPass(PassRegistry&);
151   void initializeHexagonHardwareLoopsPass(PassRegistry&);
152   void initializeHexagonLoopIdiomRecognizeLegacyPassPass(PassRegistry &);
153   void initializeHexagonNewValueJumpPass(PassRegistry&);
154   void initializeHexagonOptAddrModePass(PassRegistry&);
155   void initializeHexagonPacketizerPass(PassRegistry&);
156   void initializeHexagonRDFOptPass(PassRegistry&);
157   void initializeHexagonSplitDoubleRegsPass(PassRegistry&);
158   void initializeHexagonVExtractPass(PassRegistry &);
159   void initializeHexagonVectorCombineLegacyPass(PassRegistry&);
160   void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &);
161   Pass *createHexagonLoopIdiomPass();
162   Pass *createHexagonVectorLoopCarriedReuseLegacyPass();
163 
164   FunctionPass *createHexagonBitSimplify();
165   FunctionPass *createHexagonBranchRelaxation();
166   FunctionPass *createHexagonCallFrameInformation();
167   FunctionPass *createHexagonCFGOptimizer();
168   FunctionPass *createHexagonCommonGEP();
169   FunctionPass *createHexagonConstExtenders();
170   FunctionPass *createHexagonConstPropagationPass();
171   FunctionPass *createHexagonCopyToCombine();
172   FunctionPass *createHexagonEarlyIfConversion();
173   FunctionPass *createHexagonFixupHwLoops();
174   FunctionPass *createHexagonGenExtract();
175   FunctionPass *createHexagonGenInsert();
176   FunctionPass *createHexagonGenMux();
177   FunctionPass *createHexagonGenPredicate();
178   FunctionPass *createHexagonHardwareLoops();
179   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
180                                      CodeGenOptLevel OptLevel);
181   FunctionPass *createHexagonLoopRescheduling();
182   FunctionPass *createHexagonNewValueJump();
183   FunctionPass *createHexagonOptAddrMode();
184   FunctionPass *createHexagonOptimizeSZextends();
185   FunctionPass *createHexagonPacketizer(bool Minimal);
186   FunctionPass *createHexagonPeephole();
187   FunctionPass *createHexagonRDFOpt();
188   FunctionPass *createHexagonSplitConst32AndConst64();
189   FunctionPass *createHexagonSplitDoubleRegs();
190   FunctionPass *createHexagonStoreWidening();
191   FunctionPass *createHexagonVectorCombineLegacyPass();
192   FunctionPass *createHexagonVectorPrint();
193   FunctionPass *createHexagonVExtract();
194 } // end namespace llvm;
195 
196 static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
197   return RM.value_or(Reloc::Static);
198 }
199 
200 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget() {
201   // Register the target.
202   RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
203 
204   PassRegistry &PR = *PassRegistry::getPassRegistry();
205   initializeHexagonBitSimplifyPass(PR);
206   initializeHexagonConstExtendersPass(PR);
207   initializeHexagonConstPropagationPass(PR);
208   initializeHexagonCopyToCombinePass(PR);
209   initializeHexagonEarlyIfConversionPass(PR);
210   initializeHexagonGenMuxPass(PR);
211   initializeHexagonHardwareLoopsPass(PR);
212   initializeHexagonLoopIdiomRecognizeLegacyPassPass(PR);
213   initializeHexagonNewValueJumpPass(PR);
214   initializeHexagonOptAddrModePass(PR);
215   initializeHexagonPacketizerPass(PR);
216   initializeHexagonRDFOptPass(PR);
217   initializeHexagonSplitDoubleRegsPass(PR);
218   initializeHexagonVectorCombineLegacyPass(PR);
219   initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PR);
220   initializeHexagonVExtractPass(PR);
221   initializeHexagonDAGToDAGISelPass(PR);
222 }
223 
224 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
225                                            StringRef CPU, StringRef FS,
226                                            const TargetOptions &Options,
227                                            std::optional<Reloc::Model> RM,
228                                            std::optional<CodeModel::Model> CM,
229                                            CodeGenOptLevel OL, bool JIT)
230     // Specify the vector alignment explicitly. For v512x1, the calculated
231     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
232     // the required minimum of 64 bytes.
233     : LLVMTargetMachine(
234           T,
235           "e-m:e-p:32:32:32-a:0-n16:32-"
236           "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
237           "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
238           TT, CPU, FS, Options, getEffectiveRelocModel(RM),
239           getEffectiveCodeModel(CM, CodeModel::Small),
240           (HexagonNoOpt ? CodeGenOptLevel::None : OL)),
241       TLOF(std::make_unique<HexagonTargetObjectFile>()) {
242   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
243   initAsmInfo();
244 }
245 
246 const HexagonSubtarget *
247 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
248   AttributeList FnAttrs = F.getAttributes();
249   Attribute CPUAttr =
250       FnAttrs.getFnAttr("target-cpu");
251   Attribute FSAttr =
252       FnAttrs.getFnAttr("target-features");
253 
254   std::string CPU =
255       CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
256   std::string FS =
257       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
258   // Append the preexisting target features last, so that +mattr overrides
259   // the "unsafe-fp-math" function attribute.
260   // Creating a separate target feature is not strictly necessary, it only
261   // exists to make "unsafe-fp-math" force creating a new subtarget.
262 
263   if (F.getFnAttribute("unsafe-fp-math").getValueAsBool())
264     FS = FS.empty() ? "+unsafe-fp" : "+unsafe-fp," + FS;
265 
266   auto &I = SubtargetMap[CPU + FS];
267   if (!I) {
268     // This needs to be done before we create a new subtarget since any
269     // creation will depend on the TM and the code generation flags on the
270     // function that reside in TargetOptions.
271     resetTargetOptions(F);
272     I = std::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
273   }
274   return I.get();
275 }
276 
277 void HexagonTargetMachine::registerPassBuilderCallbacks(
278     PassBuilder &PB, bool PopulateClassToPassNames) {
279   PB.registerLateLoopOptimizationsEPCallback(
280       [=](LoopPassManager &LPM, OptimizationLevel Level) {
281         LPM.addPass(HexagonLoopIdiomRecognitionPass());
282       });
283   PB.registerLoopOptimizerEndEPCallback(
284       [=](LoopPassManager &LPM, OptimizationLevel Level) {
285         LPM.addPass(HexagonVectorLoopCarriedReusePass());
286       });
287 }
288 
289 TargetTransformInfo
290 HexagonTargetMachine::getTargetTransformInfo(const Function &F) const {
291   return TargetTransformInfo(HexagonTTIImpl(this, F));
292 }
293 
294 MachineFunctionInfo *HexagonTargetMachine::createMachineFunctionInfo(
295     BumpPtrAllocator &Allocator, const Function &F,
296     const TargetSubtargetInfo *STI) const {
297   return HexagonMachineFunctionInfo::create<HexagonMachineFunctionInfo>(
298       Allocator, F, STI);
299 }
300 
301 HexagonTargetMachine::~HexagonTargetMachine() = default;
302 
303 namespace {
304 /// Hexagon Code Generator Pass Configuration Options.
305 class HexagonPassConfig : public TargetPassConfig {
306 public:
307   HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
308     : TargetPassConfig(TM, PM) {}
309 
310   HexagonTargetMachine &getHexagonTargetMachine() const {
311     return getTM<HexagonTargetMachine>();
312   }
313 
314   ScheduleDAGInstrs *
315   createMachineScheduler(MachineSchedContext *C) const override {
316     return createVLIWMachineSched(C);
317   }
318 
319   void addIRPasses() override;
320   bool addInstSelector() override;
321   void addPreRegAlloc() override;
322   void addPostRegAlloc() override;
323   void addPreSched2() override;
324   void addPreEmitPass() override;
325 };
326 } // namespace
327 
328 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
329   return new HexagonPassConfig(*this, PM);
330 }
331 
332 void HexagonPassConfig::addIRPasses() {
333   TargetPassConfig::addIRPasses();
334   bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
335 
336   if (!NoOpt) {
337     if (EnableInstSimplify)
338       addPass(createInstSimplifyLegacyPass());
339     addPass(createDeadCodeEliminationPass());
340   }
341 
342   addPass(createAtomicExpandPass());
343 
344   if (!NoOpt) {
345     if (EnableInitialCFGCleanup)
346       addPass(createCFGSimplificationPass(SimplifyCFGOptions()
347                                               .forwardSwitchCondToPhi(true)
348                                               .convertSwitchRangeToICmp(true)
349                                               .convertSwitchToLookupTable(true)
350                                               .needCanonicalLoops(false)
351                                               .hoistCommonInsts(true)
352                                               .sinkCommonInsts(true)));
353     if (EnableLoopPrefetch)
354       addPass(createLoopDataPrefetchPass());
355     if (EnableVectorCombine)
356       addPass(createHexagonVectorCombineLegacyPass());
357     if (EnableCommGEP)
358       addPass(createHexagonCommonGEP());
359     // Replace certain combinations of shifts and ands with extracts.
360     if (EnableGenExtract)
361       addPass(createHexagonGenExtract());
362   }
363 }
364 
365 bool HexagonPassConfig::addInstSelector() {
366   HexagonTargetMachine &TM = getHexagonTargetMachine();
367   bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
368 
369   if (!NoOpt)
370     addPass(createHexagonOptimizeSZextends());
371 
372   addPass(createHexagonISelDag(TM, getOptLevel()));
373 
374   if (!NoOpt) {
375     if (EnableVExtractOpt)
376       addPass(createHexagonVExtract());
377     // Create logical operations on predicate registers.
378     if (EnableGenPred)
379       addPass(createHexagonGenPredicate());
380     // Rotate loops to expose bit-simplification opportunities.
381     if (EnableLoopResched)
382       addPass(createHexagonLoopRescheduling());
383     // Split double registers.
384     if (!DisableHSDR)
385       addPass(createHexagonSplitDoubleRegs());
386     // Bit simplification.
387     if (EnableBitSimplify)
388       addPass(createHexagonBitSimplify());
389     addPass(createHexagonPeephole());
390     // Constant propagation.
391     if (!DisableHCP) {
392       addPass(createHexagonConstPropagationPass());
393       addPass(&UnreachableMachineBlockElimID);
394     }
395     if (EnableGenInsert)
396       addPass(createHexagonGenInsert());
397     if (EnableEarlyIf)
398       addPass(createHexagonEarlyIfConversion());
399   }
400 
401   return false;
402 }
403 
404 void HexagonPassConfig::addPreRegAlloc() {
405   if (getOptLevel() != CodeGenOptLevel::None) {
406     if (EnableCExtOpt)
407       addPass(createHexagonConstExtenders());
408     if (EnableExpandCondsets)
409       insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
410     if (!DisableStoreWidening)
411       addPass(createHexagonStoreWidening());
412     if (!DisableHardwareLoops)
413       addPass(createHexagonHardwareLoops());
414   }
415   if (TM->getOptLevel() >= CodeGenOptLevel::Default)
416     addPass(&MachinePipelinerID);
417 }
418 
419 void HexagonPassConfig::addPostRegAlloc() {
420   if (getOptLevel() != CodeGenOptLevel::None) {
421     if (EnableRDFOpt)
422       addPass(createHexagonRDFOpt());
423     if (!DisableHexagonCFGOpt)
424       addPass(createHexagonCFGOptimizer());
425     if (!DisableAModeOpt)
426       addPass(createHexagonOptAddrMode());
427   }
428 }
429 
430 void HexagonPassConfig::addPreSched2() {
431   addPass(createHexagonCopyToCombine());
432   if (getOptLevel() != CodeGenOptLevel::None)
433     addPass(&IfConverterID);
434   addPass(createHexagonSplitConst32AndConst64());
435 }
436 
437 void HexagonPassConfig::addPreEmitPass() {
438   bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
439 
440   if (!NoOpt)
441     addPass(createHexagonNewValueJump());
442 
443   addPass(createHexagonBranchRelaxation());
444 
445   if (!NoOpt) {
446     if (!DisableHardwareLoops)
447       addPass(createHexagonFixupHwLoops());
448     // Generate MUX from pairs of conditional transfers.
449     if (EnableGenMux)
450       addPass(createHexagonGenMux());
451   }
452 
453   // Packetization is mandatory: it handles gather/scatter at all opt levels.
454   addPass(createHexagonPacketizer(NoOpt));
455 
456   if (EnableVectorPrint)
457     addPass(createHexagonVectorPrint());
458 
459   // Add CFI instructions if necessary.
460   addPass(createHexagonCallFrameInformation());
461 }
462