1//===-- AVRInstrInfo.td - AVR Instruction defs -------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the AVR instructions in TableGen format. 10// 11//===----------------------------------------------------------------------===// 12 13include "AVRInstrFormats.td" 14 15//===----------------------------------------------------------------------===// 16// AVR Type Profiles 17//===----------------------------------------------------------------------===// 18 19def SDT_AVRCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>; 20def SDT_AVRCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>; 21def SDT_AVRCall : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; 22def SDT_AVRWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 23def SDT_AVRBrcond : SDTypeProfile<0, 2, 24 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>]>; 25def SDT_AVRCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 26def SDT_AVRTst : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 27def SDT_AVRSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 28 SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 29 30//===----------------------------------------------------------------------===// 31// AVR Specific Node Definitions 32//===----------------------------------------------------------------------===// 33 34def AVRretflag : SDNode<"AVRISD::RET_FLAG", SDTNone, 35 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 36def AVRretiflag : SDNode<"AVRISD::RETI_FLAG", SDTNone, 37 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 38 39def AVRcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AVRCallSeqStart, 40 [SDNPHasChain, SDNPOutGlue]>; 41def AVRcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AVRCallSeqEnd, 42 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 43 44def AVRcall : SDNode<"AVRISD::CALL", SDT_AVRCall, 45 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>; 46 47def AVRWrapper : SDNode<"AVRISD::WRAPPER", SDT_AVRWrapper>; 48 49def AVRbrcond : SDNode<"AVRISD::BRCOND", SDT_AVRBrcond, 50 [SDNPHasChain, SDNPInGlue]>; 51def AVRcmp : SDNode<"AVRISD::CMP", SDT_AVRCmp, [SDNPOutGlue]>; 52def AVRcmpc : SDNode<"AVRISD::CMPC", SDT_AVRCmp, [SDNPInGlue, SDNPOutGlue]>; 53def AVRtst : SDNode<"AVRISD::TST", SDT_AVRTst, [SDNPOutGlue]>; 54def AVRselectcc: SDNode<"AVRISD::SELECT_CC", SDT_AVRSelectCC, [SDNPInGlue]>; 55 56// Shift nodes. 57def AVRlsl : SDNode<"AVRISD::LSL", SDTIntUnaryOp>; 58def AVRlsr : SDNode<"AVRISD::LSR", SDTIntUnaryOp>; 59def AVRrol : SDNode<"AVRISD::ROL", SDTIntUnaryOp>; 60def AVRror : SDNode<"AVRISD::ROR", SDTIntUnaryOp>; 61def AVRasr : SDNode<"AVRISD::ASR", SDTIntUnaryOp>; 62def AVRlsl7 : SDNode<"AVRISD::LSL7", SDTIntUnaryOp>; 63def AVRlsr7 : SDNode<"AVRISD::LSR7", SDTIntUnaryOp>; 64def AVRasr7 : SDNode<"AVRISD::ASR7", SDTIntUnaryOp>; 65 66// Pseudo shift nodes for non-constant shift amounts. 67def AVRlslLoop : SDNode<"AVRISD::LSLLOOP", SDTIntShiftOp>; 68def AVRlsrLoop : SDNode<"AVRISD::LSRLOOP", SDTIntShiftOp>; 69def AVRrolLoop : SDNode<"AVRISD::ROLLOOP", SDTIntShiftOp>; 70def AVRrorLoop : SDNode<"AVRISD::RORLOOP", SDTIntShiftOp>; 71def AVRasrLoop : SDNode<"AVRISD::ASRLOOP", SDTIntShiftOp>; 72 73// SWAP node. 74def AVRSwap : SDNode<"AVRISD::SWAP", SDTIntUnaryOp>; 75 76//===----------------------------------------------------------------------===// 77// AVR Operands, Complex Patterns and Transformations Definitions. 78//===----------------------------------------------------------------------===// 79 80def imm8_neg_XFORM : SDNodeXForm<imm, 81[{ 82 return CurDAG->getTargetConstant(-N->getAPIntValue(), SDLoc(N), MVT::i8); 83}]>; 84 85def imm16_neg_XFORM : SDNodeXForm<imm, 86[{ 87 return CurDAG->getTargetConstant(-N->getAPIntValue(), SDLoc(N), MVT::i16); 88}]>; 89 90def imm0_63_neg : PatLeaf<(imm), 91[{ 92 int64_t val = -N->getSExtValue(); 93 return val >= 0 && val < 64; 94}], imm16_neg_XFORM>; 95 96def uimm6 : PatLeaf<(imm), [{ return isUInt<6>(N->getZExtValue()); }]>; 97 98// imm_com8_XFORM - Return the complement of a imm_com8 value 99def imm_com8_XFORM : SDNodeXForm<imm, [{ 100 return CurDAG->getTargetConstant(~((uint8_t)N->getZExtValue()), SDLoc(N), 101 MVT::i8); 102}]>; 103 104// imm_com8 - Match an immediate that is a complement 105// of a 8-bit immediate. 106// Note: this pattern doesn't require an encoder method and such, as it's 107// only used on aliases (Pat<> and InstAlias<>). The actual encoding 108// is handled by the destination instructions, which use imm_com8. 109def imm_com8_asmoperand : AsmOperandClass { let Name = "ImmCom8"; } 110def imm_com8 : Operand<i8> { 111 let ParserMatchClass = imm_com8_asmoperand; 112} 113 114def ioaddr_XFORM : SDNodeXForm<imm, 115[{ 116 uint8_t offset = Subtarget->getIORegisterOffset(); 117 return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()) - offset, 118 SDLoc(N), MVT::i8); 119}]>; 120 121def iobitpos8_XFORM : SDNodeXForm<imm, 122[{ 123 return CurDAG->getTargetConstant(Log2_32(uint8_t(N->getZExtValue())), 124 SDLoc(N), MVT::i8); 125}]>; 126 127def iobitposn8_XFORM : SDNodeXForm<imm, 128[{ 129 return CurDAG->getTargetConstant(Log2_32(uint8_t(~N->getZExtValue())), 130 SDLoc(N), MVT::i8); 131}]>; 132 133def ioaddr8 : PatLeaf<(imm), 134[{ 135 uint8_t offset = Subtarget->getIORegisterOffset(); 136 uint64_t val = N->getZExtValue() - offset; 137 return val < 0x40; 138}], ioaddr_XFORM>; 139 140def lowioaddr8 : PatLeaf<(imm), 141[{ 142 uint8_t offset = Subtarget->getIORegisterOffset(); 143 uint64_t val = N->getZExtValue() - offset; 144 return val < 0x20; 145}], ioaddr_XFORM>; 146 147def ioaddr16 : PatLeaf<(imm), 148[{ 149 uint8_t offset = Subtarget->getIORegisterOffset(); 150 uint64_t val = N->getZExtValue() - offset; 151 return val < 0x3f; 152}], ioaddr_XFORM>; 153 154def iobitpos8 : PatLeaf<(imm), 155[{ 156 return isPowerOf2_32(uint8_t(N->getZExtValue())); 157}], iobitpos8_XFORM>; 158 159def iobitposn8 : PatLeaf<(imm), 160[{ 161 return isPowerOf2_32(uint8_t(~N->getZExtValue())); 162}], iobitposn8_XFORM>; 163 164def MemriAsmOperand : AsmOperandClass { 165 let Name = "Memri"; 166 let ParserMethod = "parseMemriOperand"; 167} 168 169/// Address operand for `reg+imm` used by STD and LDD. 170def memri : Operand<iPTR> 171{ 172 let MIOperandInfo = (ops PTRDISPREGS, i16imm); 173 174 let PrintMethod = "printMemri"; 175 let EncoderMethod = "encodeMemri"; 176 177 let ParserMatchClass = MemriAsmOperand; 178} 179 180// Address operand for `SP+imm` used by STD{W}SPQRr 181def memspi : Operand<iPTR> 182{ 183 let MIOperandInfo = (ops GPRSP, i16imm); 184} 185 186def relbrtarget_7 : Operand<OtherVT> 187{ 188 let PrintMethod = "printPCRelImm"; 189 let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_7_pcrel>"; 190} 191 192def brtarget_13 : Operand<OtherVT> 193{ 194 let PrintMethod = "printPCRelImm"; 195 let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_13_pcrel>"; 196} 197 198// The target of a 22 or 16-bit call/jmp instruction. 199def call_target : Operand<iPTR> 200{ 201 let EncoderMethod = "encodeCallTarget"; 202 let DecoderMethod = "decodeCallTarget"; 203} 204 205// A 16-bit address (which can lead to an R_AVR_16 relocation). 206def imm16 : Operand<i16> 207{ 208 let EncoderMethod = "encodeImm<AVR::fixup_16, 2>"; 209} 210 211/// A 6-bit immediate used in the ADIW/SBIW instructions. 212def imm_arith6 : Operand<i16> 213{ 214 let EncoderMethod = "encodeImm<AVR::fixup_6_adiw, 0>"; 215} 216 217/// An 8-bit immediate inside an instruction with the same format 218/// as the `LDI` instruction (the `FRdK` format). 219def imm_ldi8 : Operand<i8> 220{ 221 let EncoderMethod = "encodeImm<AVR::fixup_ldi, 0>"; 222} 223 224/// A 5-bit port number used in SBIC and friends (the `FIOBIT` format). 225def imm_port5 : Operand<i8> 226{ 227 let EncoderMethod = "encodeImm<AVR::fixup_port5, 0>"; 228} 229 230/// A 6-bit port number used in the `IN` instruction and friends (the 231/// `FIORdA` format. 232def imm_port6 : Operand<i8> 233{ 234 let EncoderMethod = "encodeImm<AVR::fixup_port6, 0>"; 235} 236 237// Addressing mode pattern reg+imm6 238def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], [SDNPWantRoot]>; 239 240// AsmOperand class for a pointer register. 241// Used with the LD/ST family of instructions. 242// See FSTLD in AVRInstrFormats.td 243def PtrRegAsmOperand : AsmOperandClass 244{ 245 let Name = "Reg"; 246} 247 248// A special operand type for the LD/ST instructions. 249// It converts the pointer register number into a two-bit field used in the 250// instruction. 251def LDSTPtrReg : Operand<i16> 252{ 253 let MIOperandInfo = (ops PTRREGS); 254 let EncoderMethod = "encodeLDSTPtrReg"; 255 256 let ParserMatchClass = PtrRegAsmOperand; 257} 258 259// A special operand type for the LDD/STD instructions. 260// It behaves identically to the LD/ST version, except restricts 261// the pointer registers to Y and Z. 262def LDDSTDPtrReg : Operand<i16> 263{ 264 let MIOperandInfo = (ops PTRDISPREGS); 265 let EncoderMethod = "encodeLDSTPtrReg"; 266 267 let ParserMatchClass = PtrRegAsmOperand; 268} 269 270//===----------------------------------------------------------------------===// 271// AVR predicates for subtarget features 272//===----------------------------------------------------------------------===// 273 274def HasSRAM : Predicate<"Subtarget->hasSRAM()">, 275 AssemblerPredicate<(all_of FeatureSRAM)>; 276 277def HasJMPCALL : Predicate<"Subtarget->hasJMPCALL()">, 278 AssemblerPredicate<(all_of FeatureJMPCALL)>; 279 280def HasIJMPCALL : Predicate<"Subtarget->hasIJMPCALL()">, 281 AssemblerPredicate<(all_of FeatureIJMPCALL)>; 282 283def HasEIJMPCALL : Predicate<"Subtarget->hasEIJMPCALL()">, 284 AssemblerPredicate<(all_of FeatureEIJMPCALL)>; 285 286def HasADDSUBIW : Predicate<"Subtarget->hasADDSUBIW()">, 287 AssemblerPredicate<(all_of FeatureADDSUBIW)>; 288 289def HasSmallStack : Predicate<"Subtarget->HasSmallStack()">, 290 AssemblerPredicate<(all_of FeatureSmallStack)>; 291 292def HasMOVW : Predicate<"Subtarget->hasMOVW()">, 293 AssemblerPredicate<(all_of FeatureMOVW)>; 294 295def HasLPM : Predicate<"Subtarget->hasLPM()">, 296 AssemblerPredicate<(all_of FeatureLPM)>; 297 298def HasLPMX : Predicate<"Subtarget->hasLPMX()">, 299 AssemblerPredicate<(all_of FeatureLPMX)>; 300 301def HasELPM : Predicate<"Subtarget->hasELPM()">, 302 AssemblerPredicate<(all_of FeatureELPM)>; 303 304def HasELPMX : Predicate<"Subtarget->hasELPMX()">, 305 AssemblerPredicate<(all_of FeatureELPMX)>; 306 307def HasSPM : Predicate<"Subtarget->hasSPM()">, 308 AssemblerPredicate<(all_of FeatureSPM)>; 309 310def HasSPMX : Predicate<"Subtarget->hasSPMX()">, 311 AssemblerPredicate<(all_of FeatureSPMX)>; 312 313def HasDES : Predicate<"Subtarget->hasDES()">, 314 AssemblerPredicate<(all_of FeatureDES)>; 315 316def SupportsRMW : Predicate<"Subtarget->supportsRMW()">, 317 AssemblerPredicate<(all_of FeatureRMW)>; 318 319def SupportsMultiplication : Predicate<"Subtarget->supportsMultiplication()">, 320 AssemblerPredicate<(all_of FeatureMultiplication)>; 321 322def HasBREAK : Predicate<"Subtarget->hasBREAK()">, 323 AssemblerPredicate<(all_of FeatureBREAK)>; 324 325def HasTinyEncoding : Predicate<"Subtarget->hasTinyEncoding()">, 326 AssemblerPredicate<(all_of FeatureTinyEncoding)>; 327 328 329// AVR specific condition code. These correspond to AVR_*_COND in 330// AVRInstrInfo.td. They must be kept in synch. 331def AVR_COND_EQ : PatLeaf<(i8 0)>; 332def AVR_COND_NE : PatLeaf<(i8 1)>; 333def AVR_COND_GE : PatLeaf<(i8 2)>; 334def AVR_COND_LT : PatLeaf<(i8 3)>; 335def AVR_COND_SH : PatLeaf<(i8 4)>; 336def AVR_COND_LO : PatLeaf<(i8 5)>; 337def AVR_COND_MI : PatLeaf<(i8 6)>; 338def AVR_COND_PL : PatLeaf<(i8 7)>; 339 340 341//===----------------------------------------------------------------------===// 342//===----------------------------------------------------------------------===// 343// AVR Instruction list 344//===----------------------------------------------------------------------===// 345//===----------------------------------------------------------------------===// 346 347// ADJCALLSTACKDOWN/UP implicitly use/def SP because they may be expanded into 348// a stack adjustment and the codegen must know that they may modify the stack 349// pointer before prolog-epilog rewriting occurs. 350// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 351// sub / add which can clobber SREG. 352let Defs = [SP, SREG], 353Uses = [SP] in 354{ 355 def ADJCALLSTACKDOWN : Pseudo<(outs), 356 (ins i16imm:$amt, i16imm:$amt2), 357 "#ADJCALLSTACKDOWN", 358 [(AVRcallseq_start timm:$amt, timm:$amt2)]>; 359 360 // R31R30 is used to update SP, since it is a scratch reg and this instruction 361 // is placed after the function call then R31R30 should be always free. 362 //let Defs = [R31R30], 363 //Uses = [R31R30] in 364 //:TODO: if we enable this, the pseudo is killed because it looks dead 365 def ADJCALLSTACKUP : Pseudo<(outs), 366 (ins i16imm:$amt1, i16imm:$amt2), 367 "#ADJCALLSTACKUP", 368 [(AVRcallseq_end timm:$amt1, timm:$amt2)]>; 369} 370 371//===----------------------------------------------------------------------===// 372// Addition 373//===----------------------------------------------------------------------===// 374let isCommutable = 1, 375Constraints = "$src = $rd", 376Defs = [SREG] in 377{ 378 // ADD Rd, Rr 379 // Adds two 8-bit registers. 380 def ADDRdRr : FRdRr<0b0000, 381 0b11, 382 (outs GPR8:$rd), 383 (ins GPR8:$src, GPR8:$rr), 384 "add\t$rd, $rr", 385 [(set i8:$rd, (add i8:$src, i8:$rr)), 386 (implicit SREG)]>; 387 388 // ADDW Rd+1:Rd, Rr+1:Rr 389 // Pseudo instruction to add four 8-bit registers as two 16-bit values. 390 // 391 // Expands to: 392 // add Rd, Rr 393 // adc Rd+1, Rr+1 394 def ADDWRdRr : Pseudo<(outs DREGS:$rd), 395 (ins DREGS:$src, DREGS:$rr), 396 "addw\t$rd, $rr", 397 [(set i16:$rd, (add i16:$src, i16:$rr)), 398 (implicit SREG)]>; 399 400 // ADC Rd, Rr 401 // Adds two 8-bit registers with carry. 402 let Uses = [SREG] in 403 def ADCRdRr : FRdRr<0b0001, 404 0b11, 405 (outs GPR8:$rd), 406 (ins GPR8:$src, GPR8:$rr), 407 "adc\t$rd, $rr", 408 [(set i8:$rd, (adde i8:$src, i8:$rr)), 409 (implicit SREG)]>; 410 411 // ADCW Rd+1:Rd, Rr+1:Rr 412 // Pseudo instruction to add four 8-bit registers as two 16-bit values with 413 // carry. 414 // 415 // Expands to: 416 // adc Rd, Rr 417 // adc Rd+1, Rr+1 418 let Uses = [SREG] in 419 def ADCWRdRr : Pseudo<(outs DREGS:$rd), 420 (ins DREGS:$src, DREGS:$rr), 421 "adcw\t$rd, $rr", 422 [(set i16:$rd, (adde i16:$src, i16:$rr)), 423 (implicit SREG)]>; 424 425 // AIDW Rd, k 426 // Adds an immediate 6-bit value K to Rd, placing the result in Rd. 427 def ADIWRdK : FWRdK<0b0, 428 (outs IWREGS:$rd), 429 (ins IWREGS:$src, imm_arith6:$k), 430 "adiw\t$rd, $k", 431 [(set i16:$rd, (add i16:$src, uimm6:$k)), 432 (implicit SREG)]>, 433 Requires<[HasADDSUBIW]>; 434} 435 436//===----------------------------------------------------------------------===// 437// Subtraction 438//===----------------------------------------------------------------------===// 439let Constraints = "$src = $rd", 440Defs = [SREG] in 441{ 442 // SUB Rd, Rr 443 // Subtracts the 8-bit value of Rr from Rd and places the value in Rd. 444 def SUBRdRr : FRdRr<0b0001, 445 0b10, 446 (outs GPR8:$rd), 447 (ins GPR8:$src, GPR8:$rr), 448 "sub\t$rd, $rr", 449 [(set i8:$rd, (sub i8:$src, i8:$rr)), 450 (implicit SREG)]>; 451 452 // SUBW Rd+1:Rd, Rr+1:Rr 453 // Subtracts two 16-bit values and places the result into Rd. 454 // 455 // Expands to: 456 // sub Rd, Rr 457 // sbc Rd+1, Rr+1 458 def SUBWRdRr : Pseudo<(outs DREGS:$rd), 459 (ins DREGS:$src, DREGS:$rr), 460 "subw\t$rd, $rr", 461 [(set i16:$rd, (sub i16:$src, i16:$rr)), 462 (implicit SREG)]>; 463 464 def SUBIRdK : FRdK<0b0101, 465 (outs LD8:$rd), 466 (ins LD8:$src, imm_ldi8:$k), 467 "subi\t$rd, $k", 468 [(set i8:$rd, (sub i8:$src, imm:$k)), 469 (implicit SREG)]>; 470 471 // SUBIW Rd+1:Rd, K+1:K 472 // 473 // Expands to: 474 // subi Rd, K 475 // sbci Rd+1, K+1 476 def SUBIWRdK : Pseudo<(outs DLDREGS:$rd), 477 (ins DLDREGS:$src, i16imm:$rr), 478 "subiw\t$rd, $rr", 479 [(set i16:$rd, (sub i16:$src, imm:$rr)), 480 (implicit SREG)]>; 481 482 def SBIWRdK : FWRdK<0b1, 483 (outs IWREGS:$rd), 484 (ins IWREGS:$src, imm_arith6:$k), 485 "sbiw\t$rd, $k", 486 [(set i16:$rd, (sub i16:$src, uimm6:$k)), 487 (implicit SREG)]>, 488 Requires<[HasADDSUBIW]>; 489 490 // Subtract with carry operations which must read the carry flag in SREG. 491 let Uses = [SREG] in 492 { 493 def SBCRdRr : FRdRr<0b0000, 494 0b10, 495 (outs GPR8:$rd), 496 (ins GPR8:$src, GPR8:$rr), 497 "sbc\t$rd, $rr", 498 [(set i8:$rd, (sube i8:$src, i8:$rr)), 499 (implicit SREG)]>; 500 501 // SBCW Rd+1:Rd, Rr+1:Rr 502 // 503 // Expands to: 504 // sbc Rd, Rr 505 // sbc Rd+1, Rr+1 506 def SBCWRdRr : Pseudo<(outs DREGS:$rd), 507 (ins DREGS:$src, DREGS:$rr), 508 "sbcw\t$rd, $rr", 509 [(set i16:$rd, (sube i16:$src, i16:$rr)), 510 (implicit SREG)]>; 511 512 def SBCIRdK : FRdK<0b0100, 513 (outs LD8:$rd), 514 (ins LD8:$src, imm_ldi8:$k), 515 "sbci\t$rd, $k", 516 [(set i8:$rd, (sube i8:$src, imm:$k)), 517 (implicit SREG)]>; 518 519 // SBCIW Rd+1:Rd, K+1:K 520 // sbci Rd, K 521 // sbci Rd+1, K+1 522 def SBCIWRdK : Pseudo<(outs DLDREGS:$rd), 523 (ins DLDREGS:$src, i16imm:$rr), 524 "sbciw\t$rd, $rr", 525 [(set i16:$rd, (sube i16:$src, imm:$rr)), 526 (implicit SREG)]>; 527 } 528} 529 530//===----------------------------------------------------------------------===// 531// Increment and Decrement 532//===----------------------------------------------------------------------===// 533let Constraints = "$src = $rd", 534Defs = [SREG] in 535{ 536 def INCRd : FRd<0b1001, 537 0b0100011, 538 (outs GPR8:$rd), 539 (ins GPR8:$src), 540 "inc\t$rd", 541 [(set i8:$rd, (add i8:$src, 1)), (implicit SREG)]>; 542 543 def DECRd : FRd<0b1001, 544 0b0101010, 545 (outs GPR8:$rd), 546 (ins GPR8:$src), 547 "dec\t$rd", 548 [(set i8:$rd, (add i8:$src, -1)), (implicit SREG)]>; 549} 550 551//===----------------------------------------------------------------------===// 552// Multiplication 553//===----------------------------------------------------------------------===// 554 555let isCommutable = 1, 556Defs = [R1, R0, SREG] in 557{ 558 // MUL Rd, Rr 559 // Multiplies Rd by Rr and places the result into R1:R0. 560 let usesCustomInserter = 1 in { 561 def MULRdRr : FRdRr<0b1001, 0b11, 562 (outs), 563 (ins GPR8:$lhs, GPR8:$rhs), 564 "mul\t$lhs, $rhs", 565 [/*(set R1, R0, (smullohi i8:$lhs, i8:$rhs))*/]>, 566 Requires<[SupportsMultiplication]>; 567 568 def MULSRdRr : FMUL2RdRr<0, 569 (outs), 570 (ins LD8:$lhs, LD8:$rhs), 571 "muls\t$lhs, $rhs", 572 []>, 573 Requires<[SupportsMultiplication]>; 574 } 575 576 def MULSURdRr : FMUL2RdRr<1, 577 (outs), 578 (ins LD8lo:$lhs, LD8lo:$rhs), 579 "mulsu\t$lhs, $rhs", 580 []>, 581 Requires<[SupportsMultiplication]>; 582 583 def FMUL : FFMULRdRr<0b01, 584 (outs), 585 (ins LD8lo:$lhs, LD8lo:$rhs), 586 "fmul\t$lhs, $rhs", 587 []>, 588 Requires<[SupportsMultiplication]>; 589 590 def FMULS : FFMULRdRr<0b10, 591 (outs), 592 (ins LD8lo:$lhs, LD8lo:$rhs), 593 "fmuls\t$lhs, $rhs", 594 []>, 595 Requires<[SupportsMultiplication]>; 596 597 def FMULSU : FFMULRdRr<0b11, 598 (outs), 599 (ins LD8lo:$lhs, LD8lo:$rhs), 600 "fmulsu\t$lhs, $rhs", 601 []>, 602 Requires<[SupportsMultiplication]>; 603} 604 605let Defs = [R15, R14, R13, R12, R11, R10, R9, 606 R8, R7, R6, R5, R4, R3, R2, R1, R0] in 607def DESK : FDES<(outs), 608 (ins i8imm:$k), 609 "des\t$k", 610 []>, 611 Requires<[HasDES]>; 612 613//===----------------------------------------------------------------------===// 614// Logic 615//===----------------------------------------------------------------------===// 616let Constraints = "$src = $rd", 617Defs = [SREG] in 618{ 619 // Register-Register logic instructions (which have the 620 // property of commutativity). 621 let isCommutable = 1 in 622 { 623 def ANDRdRr : FRdRr<0b0010, 624 0b00, 625 (outs GPR8:$rd), 626 (ins GPR8:$src, GPR8:$rr), 627 "and\t$rd, $rr", 628 [(set i8:$rd, (and i8:$src, i8:$rr)), 629 (implicit SREG)]>; 630 631 // ANDW Rd+1:Rd, Rr+1:Rr 632 // 633 // Expands to: 634 // and Rd, Rr 635 // and Rd+1, Rr+1 636 def ANDWRdRr : Pseudo<(outs DREGS:$rd), 637 (ins DREGS:$src, DREGS:$rr), 638 "andw\t$rd, $rr", 639 [(set i16:$rd, (and i16:$src, i16:$rr)), 640 (implicit SREG)]>; 641 642 def ORRdRr : FRdRr<0b0010, 643 0b10, 644 (outs GPR8:$rd), 645 (ins GPR8:$src, GPR8:$rr), 646 "or\t$rd, $rr", 647 [(set i8:$rd, (or i8:$src, i8:$rr)), 648 (implicit SREG)]>; 649 650 // ORW Rd+1:Rd, Rr+1:Rr 651 // 652 // Expands to: 653 // or Rd, Rr 654 // or Rd+1, Rr+1 655 def ORWRdRr : Pseudo<(outs DREGS:$rd), 656 (ins DREGS:$src, DREGS:$rr), 657 "orw\t$rd, $rr", 658 [(set i16:$rd, (or i16:$src, i16:$rr)), 659 (implicit SREG)]>; 660 661 def EORRdRr : FRdRr<0b0010, 662 0b01, 663 (outs GPR8:$rd), 664 (ins GPR8:$src, GPR8:$rr), 665 "eor\t$rd, $rr", 666 [(set i8:$rd, (xor i8:$src, i8:$rr)), 667 (implicit SREG)]>; 668 669 // EORW Rd+1:Rd, Rr+1:Rr 670 // 671 // Expands to: 672 // eor Rd, Rr 673 // eor Rd+1, Rr+1 674 def EORWRdRr : Pseudo<(outs DREGS:$rd), 675 (ins DREGS:$src, DREGS:$rr), 676 "eorw\t$rd, $rr", 677 [(set i16:$rd, (xor i16:$src, i16:$rr)), 678 (implicit SREG)]>; 679 } 680 681 def ANDIRdK : FRdK<0b0111, 682 (outs LD8:$rd), 683 (ins LD8:$src, imm_ldi8:$k), 684 "andi\t$rd, $k", 685 [(set i8:$rd, (and i8:$src, imm:$k)), 686 (implicit SREG)]>; 687 688 // ANDI Rd+1:Rd, K+1:K 689 // 690 // Expands to: 691 // andi Rd, K 692 // andi Rd+1, K+1 693 def ANDIWRdK : Pseudo<(outs DLDREGS:$rd), 694 (ins DLDREGS:$src, i16imm:$k), 695 "andiw\t$rd, $k", 696 [(set i16:$rd, (and i16:$src, imm:$k)), 697 (implicit SREG)]>; 698 699 def ORIRdK : FRdK<0b0110, 700 (outs LD8:$rd), 701 (ins LD8:$src, imm_ldi8:$k), 702 "ori\t$rd, $k", 703 [(set i8:$rd, (or i8:$src, imm:$k)), 704 (implicit SREG)]>; 705 706 // ORIW Rd+1:Rd, K+1,K 707 // 708 // Expands to: 709 // ori Rd, K 710 // ori Rd+1, K+1 711 def ORIWRdK : Pseudo<(outs DLDREGS:$rd), 712 (ins DLDREGS:$src, i16imm:$rr), 713 "oriw\t$rd, $rr", 714 [(set i16:$rd, (or i16:$src, imm:$rr)), 715 (implicit SREG)]>; 716} 717 718//===----------------------------------------------------------------------===// 719// One's/Two's Complement 720//===----------------------------------------------------------------------===// 721let Constraints = "$src = $rd", 722Defs = [SREG] in 723{ 724 def COMRd : FRd<0b1001, 725 0b0100000, 726 (outs GPR8:$rd), 727 (ins GPR8:$src), 728 "com\t$rd", 729 [(set i8:$rd, (not i8:$src)), (implicit SREG)]>; 730 731 // COMW Rd+1:Rd 732 // 733 // Expands to: 734 // com Rd 735 // com Rd+1 736 def COMWRd : Pseudo<(outs DREGS:$rd), 737 (ins DREGS:$src), 738 "comw\t$rd", 739 [(set i16:$rd, (not i16:$src)), (implicit SREG)]>; 740 741 def NEGRd : FRd<0b1001, 742 0b0100001, 743 (outs GPR8:$rd), 744 (ins GPR8:$src), 745 "neg\t$rd", 746 [(set i8:$rd, (ineg i8:$src)), (implicit SREG)]>; 747 748 // NEGW Rd+1:Rd 749 // 750 // Expands to: 751 // neg Rd+1 752 // neg Rd 753 // sbci Rd+1, 0 754 def NEGWRd : Pseudo<(outs DREGS:$rd), 755 (ins DREGS:$src), 756 "negw\t$rd", 757 [(set i16:$rd, (ineg i16:$src)), (implicit SREG)]>; 758} 759 760// TST Rd 761// Test for zero of minus. 762// This operation is identical to a `Rd AND Rd`. 763def : InstAlias<"tst\t$rd", (ANDRdRr GPR8:$rd, GPR8:$rd)>; 764 765// SBR Rd, K 766// 767// Mnemonic alias to 'ORI Rd, K'. Same bit pattern, same operands, 768// same everything. 769def : InstAlias<"sbr\t$rd, $k", 770 (ORIRdK LD8:$rd, imm_ldi8:$k), 771 /* Disable display, so we don't override ORI */ 0>; 772 773//===----------------------------------------------------------------------===// 774// Jump instructions 775//===----------------------------------------------------------------------===// 776let isBarrier = 1, 777isBranch = 1, 778isTerminator = 1 in 779{ 780 def RJMPk : FBRk<0, 781 (outs), 782 (ins brtarget_13:$target), 783 "rjmp\t$target", 784 [(br bb:$target)]>; 785 786 let isIndirectBranch = 1, 787 Uses = [R31R30] in 788 def IJMP : F16<0b1001010000001001, 789 (outs), 790 (ins), 791 "ijmp", 792 []>, 793 Requires<[HasIJMPCALL]>; 794 795 let isIndirectBranch = 1, 796 Uses = [R31R30] in 797 def EIJMP : F16<0b1001010000011001, 798 (outs), 799 (ins), 800 "eijmp", 801 []>, 802 Requires<[HasEIJMPCALL]>; 803 804 def JMPk : F32BRk<0b110, 805 (outs), 806 (ins call_target:$k), 807 "jmp\t$k", 808 []>, 809 Requires<[HasJMPCALL]>; 810} 811 812//===----------------------------------------------------------------------===// 813// Call instructions 814//===----------------------------------------------------------------------===// 815let isCall = 1 in 816{ 817 // SP is marked as a use to prevent stack-pointer assignments that appear 818 // immediately before calls from potentially appearing dead. 819 let Uses = [SP] in 820 def RCALLk : FBRk<1, 821 (outs), 822 (ins brtarget_13:$target), 823 "rcall\t$target", 824 []>; 825 826 // SP is marked as a use to prevent stack-pointer assignments that appear 827 // immediately before calls from potentially appearing dead. 828 let Uses = [SP, R31R30] in 829 def ICALL : F16<0b1001010100001001, 830 (outs), 831 (ins variable_ops), 832 "icall", 833 []>, 834 Requires<[HasIJMPCALL]>; 835 836 // SP is marked as a use to prevent stack-pointer assignments that appear 837 // immediately before calls from potentially appearing dead. 838 let Uses = [SP, R31R30] in 839 def EICALL : F16<0b1001010100011001, 840 (outs), 841 (ins variable_ops), 842 "eicall", 843 []>, 844 Requires<[HasEIJMPCALL]>; 845 846 // SP is marked as a use to prevent stack-pointer assignments that appear 847 // immediately before calls from potentially appearing dead. 848 // 849 //:TODO: the imm field can be either 16 or 22 bits in devices with more 850 // than 64k of ROM, fix it once we support the largest devices. 851 let Uses = [SP] in 852 def CALLk : F32BRk<0b111, 853 (outs), 854 (ins call_target:$k), 855 "call\t$k", 856 [(AVRcall imm:$k)]>, 857 Requires<[HasJMPCALL]>; 858} 859 860//===----------------------------------------------------------------------===// 861// Return instructions. 862//===----------------------------------------------------------------------===// 863let isTerminator = 1, 864isReturn = 1, 865isBarrier = 1 in 866{ 867 def RET : F16<0b1001010100001000, 868 (outs), 869 (ins), 870 "ret", 871 [(AVRretflag)]>; 872 873 def RETI : F16<0b1001010100011000, 874 (outs), 875 (ins), 876 "reti", 877 [(AVRretiflag)]>; 878} 879 880//===----------------------------------------------------------------------===// 881// Compare operations. 882//===----------------------------------------------------------------------===// 883let Defs = [SREG] in 884{ 885 // CPSE Rd, Rr 886 // Compare Rd and Rr, skipping the next instruction if they are equal. 887 let isBarrier = 1, 888 isBranch = 1, 889 isTerminator = 1 in 890 def CPSE : FRdRr<0b0001, 891 0b00, 892 (outs), 893 (ins GPR8:$rd, GPR8:$rr), 894 "cpse\t$rd, $rr", 895 []>; 896 897 def CPRdRr : FRdRr<0b0001, 898 0b01, 899 (outs), 900 (ins GPR8:$rd, GPR8:$rr), 901 "cp\t$rd, $rr", 902 [(AVRcmp i8:$rd, i8:$rr), (implicit SREG)]>; 903 904 // CPW Rd+1:Rd, Rr+1:Rr 905 // 906 // Expands to: 907 // cp Rd, Rr 908 // cpc Rd+1, Rr+1 909 def CPWRdRr : Pseudo<(outs), 910 (ins DREGS:$src, DREGS:$src2), 911 "cpw\t$src, $src2", 912 [(AVRcmp i16:$src, i16:$src2), (implicit SREG)]>; 913 914 let Uses = [SREG] in 915 def CPCRdRr : FRdRr<0b0000, 916 0b01, 917 (outs), 918 (ins GPR8:$rd, GPR8:$rr), 919 "cpc\t$rd, $rr", 920 [(AVRcmpc i8:$rd, i8:$rr), (implicit SREG)]>; 921 922 // CPCW Rd+1:Rd. Rr+1:Rr 923 // 924 // Expands to: 925 // cpc Rd, Rr 926 // cpc Rd+1, Rr+1 927 let Uses = [SREG] in 928 def CPCWRdRr : Pseudo<(outs), 929 (ins DREGS:$src, DREGS:$src2), 930 "cpcw\t$src, $src2", 931 [(AVRcmpc i16:$src, i16:$src2), (implicit SREG)]>; 932 933 // CPI Rd, K 934 // Compares a register with an 8 bit immediate. 935 def CPIRdK : FRdK<0b0011, 936 (outs), 937 (ins LD8:$rd, imm_ldi8:$k), 938 "cpi\t$rd, $k", 939 [(AVRcmp i8:$rd, imm:$k), (implicit SREG)]>; 940} 941 942//===----------------------------------------------------------------------===// 943// Register conditional skipping/branching operations. 944//===----------------------------------------------------------------------===// 945let isBranch = 1, 946isTerminator = 1 in 947{ 948 // Conditional skipping on GPR register bits, and 949 // conditional skipping on IO register bits. 950 let isBarrier = 1 in 951 { 952 def SBRCRrB : FRdB<0b10, 953 (outs), 954 (ins GPR8:$rr, i8imm:$b), 955 "sbrc\t$rr, $b", 956 []>; 957 958 def SBRSRrB : FRdB<0b11, 959 (outs), 960 (ins GPR8:$rr, i8imm:$b), 961 "sbrs\t$rr, $b", 962 []>; 963 964 def SBICAb : FIOBIT<0b01, 965 (outs), 966 (ins imm_port5:$a, i8imm:$b), 967 "sbic\t$a, $b", 968 []>; 969 970 def SBISAb : FIOBIT<0b11, 971 (outs), 972 (ins imm_port5:$a, i8imm:$b), 973 "sbis\t$a, $b", 974 []>; 975 } 976 977 // Relative branches on status flag bits. 978 let Uses = [SREG] in 979 { 980 // BRBS s, k 981 // Branch if `s` flag in status register is set. 982 def BRBSsk : FSK<0, 983 (outs), 984 (ins i8imm:$s, relbrtarget_7:$k), 985 "brbs\t$s, $k", 986 []>; 987 988 // BRBC s, k 989 // Branch if `s` flag in status register is clear. 990 def BRBCsk : FSK<1, 991 (outs), 992 (ins i8imm:$s, relbrtarget_7:$k), 993 "brbc\t$s, $k", 994 []>; 995 } 996} 997 998 999// BRCS k 1000// Branch if carry flag is set 1001def : InstAlias<"brcs\t$k", (BRBSsk 0, relbrtarget_7:$k)>; 1002 1003// BRCC k 1004// Branch if carry flag is clear 1005def : InstAlias<"brcc\t$k", (BRBCsk 0, relbrtarget_7:$k)>; 1006 1007// BRHS k 1008// Branch if half carry flag is set 1009def : InstAlias<"brhs\t$k", (BRBSsk 5, relbrtarget_7:$k)>; 1010 1011// BRHC k 1012// Branch if half carry flag is clear 1013def : InstAlias<"brhc\t$k", (BRBCsk 5, relbrtarget_7:$k)>; 1014 1015// BRTS k 1016// Branch if the T flag is set 1017def : InstAlias<"brts\t$k", (BRBSsk 6, relbrtarget_7:$k)>; 1018 1019// BRTC k 1020// Branch if the T flag is clear 1021def : InstAlias<"brtc\t$k", (BRBCsk 6, relbrtarget_7:$k)>; 1022 1023// BRVS k 1024// Branch if the overflow flag is set 1025def : InstAlias<"brvs\t$k", (BRBSsk 3, relbrtarget_7:$k)>; 1026 1027// BRVC k 1028// Branch if the overflow flag is clear 1029def : InstAlias<"brvc\t$k", (BRBCsk 3, relbrtarget_7:$k)>; 1030 1031// BRIE k 1032// Branch if the global interrupt flag is enabled 1033def : InstAlias<"brie\t$k", (BRBSsk 7, relbrtarget_7:$k)>; 1034 1035// BRID k 1036// Branch if the global interrupt flag is disabled 1037def : InstAlias<"brid\t$k", (BRBCsk 7, relbrtarget_7:$k)>; 1038 1039//===----------------------------------------------------------------------===// 1040// PC-relative conditional branches 1041//===----------------------------------------------------------------------===// 1042// Based on status register. We cannot simplify these into instruction aliases 1043// because we also need to be able to specify a pattern to match for ISel. 1044let isBranch = 1, 1045isTerminator = 1, 1046Uses = [SREG] in 1047{ 1048 def BREQk : FBRsk<0, 1049 0b001, 1050 (outs), 1051 (ins relbrtarget_7:$target), 1052 "breq\t$target", 1053 [(AVRbrcond bb:$target, AVR_COND_EQ)]>; 1054 1055 def BRNEk : FBRsk<1, 1056 0b001, 1057 (outs), 1058 (ins relbrtarget_7:$target), 1059 "brne\t$target", 1060 [(AVRbrcond bb:$target, AVR_COND_NE)]>; 1061 1062 1063 def BRSHk : FBRsk<1, 1064 0b000, 1065 (outs), 1066 (ins relbrtarget_7:$target), 1067 "brsh\t$target", 1068 [(AVRbrcond bb:$target, AVR_COND_SH)]>; 1069 1070 def BRLOk : FBRsk<0, 1071 0b000, 1072 (outs), 1073 (ins relbrtarget_7:$target), 1074 "brlo\t$target", 1075 [(AVRbrcond bb:$target, AVR_COND_LO)]>; 1076 1077 def BRMIk : FBRsk<0, 1078 0b010, 1079 (outs), 1080 (ins relbrtarget_7:$target), 1081 "brmi\t$target", 1082 [(AVRbrcond bb:$target, AVR_COND_MI)]>; 1083 1084 def BRPLk : FBRsk<1, 1085 0b010, 1086 (outs), 1087 (ins relbrtarget_7:$target), 1088 "brpl\t$target", 1089 [(AVRbrcond bb:$target, AVR_COND_PL)]>; 1090 1091 def BRGEk : FBRsk<1, 1092 0b100, 1093 (outs), 1094 (ins relbrtarget_7:$target), 1095 "brge\t$target", 1096 [(AVRbrcond bb:$target, AVR_COND_GE)]>; 1097 1098 def BRLTk : FBRsk<0, 1099 0b100, 1100 (outs), 1101 (ins relbrtarget_7:$target), 1102 "brlt\t$target", 1103 [(AVRbrcond bb:$target, AVR_COND_LT)]>; 1104} 1105 1106//===----------------------------------------------------------------------===// 1107// Data transfer instructions 1108//===----------------------------------------------------------------------===// 1109// 8 and 16-bit register move instructions. 1110let hasSideEffects = 0 in 1111{ 1112 def MOVRdRr : FRdRr<0b0010, 1113 0b11, 1114 (outs GPR8:$rd), 1115 (ins GPR8:$rr), 1116 "mov\t$rd, $rr", 1117 []>; 1118 1119 def MOVWRdRr : FMOVWRdRr<(outs DREGS:$dst), 1120 (ins DREGS:$src), 1121 "movw\t$dst, $src", 1122 []>, 1123 Requires<[HasMOVW]>; 1124} 1125 1126// Load immediate values into registers. 1127let isReMaterializable = 1 in 1128{ 1129 def LDIRdK : FRdK<0b1110, 1130 (outs LD8:$rd), 1131 (ins imm_ldi8:$k), 1132 "ldi\t$rd, $k", 1133 [(set i8:$rd, imm:$k)]>; 1134 1135 // LDIW Rd+1:Rd, K+1:K 1136 // 1137 // Expands to: 1138 // ldi Rd, K 1139 // ldi Rd+1, K+1 1140 def LDIWRdK : Pseudo<(outs DLDREGS:$dst), 1141 (ins i16imm:$src), 1142 "ldiw\t$dst, $src", 1143 [(set i16:$dst, imm:$src)]>; 1144} 1145 1146// Load from data space into register. 1147let canFoldAsLoad = 1, 1148isReMaterializable = 1 in 1149{ 1150 def LDSRdK : F32DM<0b0, 1151 (outs GPR8:$rd), 1152 (ins imm16:$k), 1153 "lds\t$rd, $k", 1154 [(set i8:$rd, (load imm:$k))]>, 1155 Requires<[HasSRAM]>; 1156 1157 // LDSW Rd+1:Rd, K+1:K 1158 // 1159 // Expands to: 1160 // lds Rd, (K+1:K) 1161 // lds Rd+1 (K+1:K) + 1 1162 def LDSWRdK : Pseudo<(outs DREGS:$dst), 1163 (ins i16imm:$src), 1164 "ldsw\t$dst, $src", 1165 [(set i16:$dst, (load imm:$src))]>, 1166 Requires<[HasSRAM]>; 1167} 1168 1169// Indirect loads. 1170let canFoldAsLoad = 1, 1171isReMaterializable = 1 in 1172{ 1173 def LDRdPtr : FSTLD<0, 1174 0b00, 1175 (outs GPR8:$reg), 1176 (ins LDSTPtrReg:$ptrreg), 1177 "ld\t$reg, $ptrreg", 1178 [(set GPR8:$reg, (load i16:$ptrreg))]>, 1179 Requires<[HasSRAM]>; 1180 1181 // LDW Rd+1:Rd, P 1182 // 1183 // Expands to: 1184 // ld Rd, P 1185 // ldd Rd+1, P+1 1186 let Constraints = "@earlyclobber $reg" in 1187 def LDWRdPtr : Pseudo<(outs DREGS:$reg), 1188 (ins PTRDISPREGS:$ptrreg), 1189 "ldw\t$reg, $ptrreg", 1190 [(set i16:$reg, (load i16:$ptrreg))]>, 1191 Requires<[HasSRAM]>; 1192} 1193 1194// Indirect loads (with postincrement or predecrement). 1195let mayLoad = 1, 1196hasSideEffects = 0, 1197Constraints = "$ptrreg = $base_wb,@earlyclobber $reg" in 1198{ 1199 def LDRdPtrPi : FSTLD<0, 1200 0b01, 1201 (outs GPR8:$reg, PTRREGS:$base_wb), 1202 (ins LDSTPtrReg:$ptrreg), 1203 "ld\t$reg, $ptrreg+", 1204 []>, 1205 Requires<[HasSRAM]>; 1206 1207 // LDW Rd+1:Rd, P+ 1208 // Expands to: 1209 // ld Rd, P+ 1210 // ld Rd+1, P+ 1211 def LDWRdPtrPi : Pseudo<(outs DREGS:$reg, PTRREGS:$base_wb), 1212 (ins PTRREGS:$ptrreg), 1213 "ldw\t$reg, $ptrreg+", 1214 []>, 1215 Requires<[HasSRAM]>; 1216 1217 def LDRdPtrPd : FSTLD<0, 1218 0b10, 1219 (outs GPR8:$reg, PTRREGS:$base_wb), 1220 (ins LDSTPtrReg:$ptrreg), 1221 "ld\t$reg, -$ptrreg", 1222 []>, 1223 Requires<[HasSRAM]>; 1224 1225 // LDW Rd+1:Rd, -P 1226 // 1227 // Expands to: 1228 // ld Rd+1, -P 1229 // ld Rd, -P 1230 def LDWRdPtrPd : Pseudo<(outs DREGS:$reg, PTRREGS:$base_wb), 1231 (ins PTRREGS:$ptrreg), 1232 "ldw\t$reg, -$ptrreg", 1233 []>, 1234 Requires<[HasSRAM]>; 1235} 1236 1237// Load indirect with displacement operations. 1238let canFoldAsLoad = 1, 1239isReMaterializable = 1 in 1240{ 1241 let Constraints = "@earlyclobber $reg" in 1242 def LDDRdPtrQ : FSTDLDD<0, 1243 (outs GPR8:$reg), 1244 (ins memri:$memri), 1245 "ldd\t$reg, $memri", 1246 [(set i8:$reg, (load addr:$memri))]>, 1247 Requires<[HasSRAM]>; 1248 1249 // LDDW Rd+1:Rd, P+q 1250 // 1251 // Expands to: 1252 // ldd Rd, P+q 1253 // ldd Rd+1, P+q+1 1254 let Constraints = "@earlyclobber $dst" in 1255 def LDDWRdPtrQ : Pseudo<(outs DREGS_WITHOUT_YZ_WORKAROUND:$dst), 1256 (ins memri:$memri), 1257 "lddw\t$dst, $memri", 1258 [(set i16:$dst, (load addr:$memri))]>, 1259 Requires<[HasSRAM]>; 1260 1261 // An identical pseudo instruction to LDDWRdPtrQ, expect restricted to the Y 1262 // register and without the @earlyclobber flag. 1263 // 1264 // Used to work around a bug caused by the register allocator not 1265 // being able to handle the expansion of a COPY into an machine instruction 1266 // that has an earlyclobber flag. This is because the register allocator will 1267 // try expand a copy from a register slot into an earlyclobber instruction. 1268 // Instructions that are earlyclobber need to be in a dedicated earlyclobber slot. 1269 // 1270 // This pseudo instruction can be used pre-AVR pseudo expansion in order to 1271 // get a frame index load without directly using earlyclobber instructions. 1272 // 1273 // The pseudo expansion pass trivially expands this into LDDWRdPtrQ. 1274 // 1275 // This instruction may be removed once PR13375 is fixed. 1276 let mayLoad = 1, 1277 hasSideEffects = 0 in 1278 def LDDWRdYQ : Pseudo<(outs DREGS:$dst), 1279 (ins memri:$memri), 1280 "lddw\t$dst, $memri", 1281 []>, 1282 Requires<[HasSRAM]>; 1283} 1284 1285class AtomicLoad<PatFrag Op, RegisterClass DRC, 1286 RegisterClass PTRRC> : 1287 Pseudo<(outs DRC:$rd), (ins PTRRC:$rr), "atomic_op", 1288 [(set DRC:$rd, (Op i16:$rr))]>; 1289 1290class AtomicStore<PatFrag Op, RegisterClass DRC, 1291 RegisterClass PTRRC> : 1292 Pseudo<(outs), (ins PTRRC:$rd, DRC:$rr), "atomic_op", 1293 [(Op i16:$rd, DRC:$rr)]>; 1294 1295class AtomicLoadOp<PatFrag Op, RegisterClass DRC, 1296 RegisterClass PTRRC> : 1297 Pseudo<(outs DRC:$rd), (ins PTRRC:$rr, DRC:$operand), 1298 "atomic_op", 1299 [(set DRC:$rd, (Op i16:$rr, DRC:$operand))]>; 1300 1301// FIXME: I think 16-bit atomic binary ops need to mark 1302// r0 as clobbered. 1303 1304// Atomic instructions 1305// =================== 1306// 1307// These are all expanded by AVRExpandPseudoInsts 1308// 1309// 8-bit operations can use any pointer register because 1310// they are expanded directly into an LD/ST instruction. 1311// 1312// 16-bit operations use 16-bit load/store postincrement instructions, 1313// which require PTRDISPREGS. 1314 1315def AtomicLoad8 : AtomicLoad<atomic_load_8, GPR8, PTRREGS>; 1316def AtomicLoad16 : AtomicLoad<atomic_load_16, DREGS, PTRDISPREGS>; 1317 1318def AtomicStore8 : AtomicStore<atomic_store_8, GPR8, PTRREGS>; 1319def AtomicStore16 : AtomicStore<atomic_store_16, DREGS, PTRDISPREGS>; 1320 1321class AtomicLoadOp8<PatFrag Op> : AtomicLoadOp<Op, GPR8, PTRREGS>; 1322class AtomicLoadOp16<PatFrag Op> : AtomicLoadOp<Op, DREGS, PTRDISPREGS>; 1323 1324def AtomicLoadAdd8 : AtomicLoadOp8<atomic_load_add_8>; 1325def AtomicLoadAdd16 : AtomicLoadOp16<atomic_load_add_16>; 1326def AtomicLoadSub8 : AtomicLoadOp8<atomic_load_sub_8>; 1327def AtomicLoadSub16 : AtomicLoadOp16<atomic_load_sub_16>; 1328def AtomicLoadAnd8 : AtomicLoadOp8<atomic_load_and_8>; 1329def AtomicLoadAnd16 : AtomicLoadOp16<atomic_load_and_16>; 1330def AtomicLoadOr8 : AtomicLoadOp8<atomic_load_or_8>; 1331def AtomicLoadOr16 : AtomicLoadOp16<atomic_load_or_16>; 1332def AtomicLoadXor8 : AtomicLoadOp8<atomic_load_xor_8>; 1333def AtomicLoadXor16 : AtomicLoadOp16<atomic_load_xor_16>; 1334def AtomicFence : Pseudo<(outs), (ins), "atomic_fence", 1335 [(atomic_fence timm, timm)]>; 1336 1337// Indirect store from register to data space. 1338def STSKRr : F32DM<0b1, 1339 (outs), 1340 (ins imm16:$k, GPR8:$rd), 1341 "sts\t$k, $rd", 1342 [(store i8:$rd, imm:$k)]>, 1343 Requires<[HasSRAM]>; 1344 1345// STSW K+1:K, Rr+1:Rr 1346// 1347// Expands to: 1348// sts Rr+1, (K+1:K) + 1 1349// sts Rr, (K+1:K) 1350def STSWKRr : Pseudo<(outs), 1351 (ins i16imm:$dst, DREGS:$src), 1352 "stsw\t$dst, $src", 1353 [(store i16:$src, imm:$dst)]>, 1354 Requires<[HasSRAM]>; 1355 1356// Indirect stores. 1357// ST P, Rr 1358// Stores the value of Rr into the location addressed by pointer P. 1359def STPtrRr : FSTLD<1, 1360 0b00, 1361 (outs), 1362 (ins LDSTPtrReg:$ptrreg, GPR8:$reg), 1363 "st\t$ptrreg, $reg", 1364 [(store GPR8:$reg, i16:$ptrreg)]>, 1365 Requires<[HasSRAM]>; 1366 1367// STW P, Rr+1:Rr 1368// Stores the value of Rr into the location addressed by pointer P. 1369// 1370// Expands to: 1371// st P, Rr 1372// std P+1, Rr+1 1373def STWPtrRr : Pseudo<(outs), 1374 (ins PTRDISPREGS:$ptrreg, DREGS:$reg), 1375 "stw\t$ptrreg, $reg", 1376 [(store i16:$reg, i16:$ptrreg)]>, 1377 Requires<[HasSRAM]>; 1378 1379// Indirect stores (with postincrement or predecrement). 1380let Constraints = "$ptrreg = $base_wb,@earlyclobber $base_wb" in 1381{ 1382 1383 // ST P+, Rr 1384 // Stores the value of Rr into the location addressed by pointer P. 1385 // Post increments P. 1386 def STPtrPiRr : FSTLD<1, 1387 0b01, 1388 (outs LDSTPtrReg:$base_wb), 1389 (ins LDSTPtrReg:$ptrreg, GPR8:$reg, i8imm:$offs), 1390 "st\t$ptrreg+, $reg", 1391 [(set i16:$base_wb, 1392 (post_store GPR8:$reg, i16:$ptrreg, imm:$offs))]>, 1393 Requires<[HasSRAM]>; 1394 1395 // STW P+, Rr+1:Rr 1396 // Stores the value of Rr into the location addressed by pointer P. 1397 // Post increments P. 1398 // 1399 // Expands to: 1400 // st P+, Rr 1401 // st P+, Rr+1 1402 def STWPtrPiRr : Pseudo<(outs PTRREGS:$base_wb), 1403 (ins PTRREGS:$ptrreg, DREGS:$trh, i8imm:$offs), 1404 "stw\t$ptrreg+, $trh", 1405 [(set PTRREGS:$base_wb, 1406 (post_store DREGS:$trh, PTRREGS:$ptrreg, imm:$offs))]>, 1407 Requires<[HasSRAM]>; 1408 1409 // ST -P, Rr 1410 // Stores the value of Rr into the location addressed by pointer P. 1411 // Pre decrements P. 1412 def STPtrPdRr : FSTLD<1, 1413 0b10, 1414 (outs LDSTPtrReg:$base_wb), 1415 (ins LDSTPtrReg:$ptrreg, GPR8:$reg, i8imm:$offs), 1416 "st\t-$ptrreg, $reg", 1417 [(set i16:$base_wb, 1418 (pre_store GPR8:$reg, i16:$ptrreg, imm:$offs))]>, 1419 Requires<[HasSRAM]>; 1420 1421 // STW -P, Rr+1:Rr 1422 // Stores the value of Rr into the location addressed by pointer P. 1423 // Pre decrements P. 1424 // 1425 // Expands to: 1426 // st -P, Rr+1 1427 // st -P, Rr 1428 def STWPtrPdRr : Pseudo<(outs PTRREGS:$base_wb), 1429 (ins PTRREGS:$ptrreg, DREGS:$reg, i8imm:$offs), 1430 "stw\t-$ptrreg, $reg", 1431 [(set PTRREGS:$base_wb, 1432 (pre_store i16:$reg, i16:$ptrreg, imm:$offs))]>, 1433 Requires<[HasSRAM]>; 1434} 1435 1436// Store indirect with displacement operations. 1437// STD P+q, Rr 1438// Stores the value of Rr into the location addressed by pointer P with a 1439// displacement of q. Does not modify P. 1440def STDPtrQRr : FSTDLDD<1, 1441 (outs), 1442 (ins memri:$memri, GPR8:$reg), 1443 "std\t$memri, $reg", 1444 [(store i8:$reg, addr:$memri)]>, 1445 Requires<[HasSRAM]>; 1446 1447// STDW P+q, Rr+1:Rr 1448// Stores the value of Rr into the location addressed by pointer P with a 1449// displacement of q. Does not modify P. 1450// 1451// Expands to: 1452// std P+q, Rr 1453// std P+q+1, Rr+1 1454def STDWPtrQRr : Pseudo<(outs), 1455 (ins memri:$memri, DREGS:$src), 1456 "stdw\t$memri, $src", 1457 [(store i16:$src, addr:$memri)]>, 1458 Requires<[HasSRAM]>; 1459 1460 1461// Load program memory operations. 1462let canFoldAsLoad = 1, 1463isReMaterializable = 1, 1464mayLoad = 1, 1465hasSideEffects = 0 in 1466{ 1467 let Defs = [R0], 1468 Uses = [R31R30] in 1469 def LPM : F16<0b1001010111001000, 1470 (outs), 1471 (ins), 1472 "lpm", 1473 []>, 1474 Requires<[HasLPM]>; 1475 1476 def LPMRdZ : FLPMX<0, 1477 0, 1478 (outs GPR8:$dst), 1479 (ins ZREG:$z), 1480 "lpm\t$dst, $z", 1481 []>, 1482 Requires<[HasLPMX]>; 1483 1484 // Load program memory, while postincrementing the Z register. 1485 let Defs = [R31R30] in 1486 { 1487 def LPMRdZPi : FLPMX<0, 1488 1, 1489 (outs GPR8:$dst), 1490 (ins ZREG:$z), 1491 "lpm\t$dst, $z+", 1492 []>, 1493 Requires<[HasLPMX]>; 1494 1495 def LPMWRdZ : Pseudo<(outs DREGS:$dst), 1496 (ins ZREG:$z), 1497 "lpmw\t$dst, $z", 1498 []>, 1499 Requires<[HasLPMX]>; 1500 1501 def LPMWRdZPi : Pseudo<(outs DREGS:$dst), 1502 (ins ZREG:$z), 1503 "lpmw\t$dst, $z+", 1504 []>, 1505 Requires<[HasLPMX]>; 1506 } 1507} 1508 1509// Extended load program memory operations. 1510let mayLoad = 1, 1511hasSideEffects = 0 in 1512{ 1513 let Defs = [R0], 1514 Uses = [R31R30] in 1515 def ELPM : F16<0b1001010111011000, 1516 (outs), 1517 (ins), 1518 "elpm", 1519 []>, 1520 Requires<[HasELPM]>; 1521 1522 def ELPMRdZ : FLPMX<1, 1523 0, 1524 (outs GPR8:$dst), 1525 (ins ZREG:$z), 1526 "elpm\t$dst, $z", 1527 []>, 1528 Requires<[HasELPMX]>; 1529 1530 let Defs = [R31R30] in 1531 def ELPMRdZPi : FLPMX<1, 1532 1, 1533 (outs GPR8:$dst), 1534 (ins ZREG: $z), 1535 "elpm\t$dst, $z+", 1536 []>, 1537 Requires<[HasELPMX]>; 1538} 1539 1540// Store program memory operations. 1541let Uses = [R1, R0] in 1542{ 1543 let Uses = [R31R30, R1, R0] in 1544 def SPM : F16<0b1001010111101000, 1545 (outs), 1546 (ins), 1547 "spm", 1548 []>, 1549 Requires<[HasSPM]>; 1550 1551 let Defs = [R31R30] in 1552 def SPMZPi : F16<0b1001010111111000, 1553 (outs), 1554 (ins ZREG:$z), 1555 "spm $z+", 1556 []>, 1557 Requires<[HasSPMX]>; 1558} 1559 1560// Read data from IO location operations. 1561let canFoldAsLoad = 1, 1562isReMaterializable = 1 in 1563{ 1564 def INRdA : FIORdA<(outs GPR8:$dst), 1565 (ins imm_port6:$src), 1566 "in\t$dst, $src", 1567 [(set i8:$dst, (load ioaddr8:$src))]>; 1568 1569 def INWRdA : Pseudo<(outs DREGS:$dst), 1570 (ins imm_port6:$src), 1571 "inw\t$dst, $src", 1572 [(set i16:$dst, (load ioaddr16:$src))]>; 1573} 1574 1575// Write data to IO location operations. 1576def OUTARr : FIOARr<(outs), 1577 (ins imm_port6:$dst, GPR8:$src), 1578 "out\t$dst, $src", 1579 [(store i8:$src, ioaddr8:$dst)]>; 1580 1581def OUTWARr : Pseudo<(outs), 1582 (ins imm_port6:$dst, DREGS:$src), 1583 "outw\t$dst, $src", 1584 [(store i16:$src, ioaddr16:$dst)]>; 1585 1586// Stack push/pop operations. 1587let Defs = [SP], 1588Uses = [SP], 1589hasSideEffects = 0 in 1590{ 1591 // Stack push operations. 1592 let mayStore = 1 in 1593 { 1594 def PUSHRr : FRd<0b1001, 1595 0b0011111, 1596 (outs), 1597 (ins GPR8:$reg), 1598 "push\t$reg", 1599 []>, 1600 Requires<[HasSRAM]>; 1601 1602 def PUSHWRr : Pseudo<(outs), 1603 (ins DREGS:$reg), 1604 "pushw\t$reg", 1605 []>, 1606 Requires<[HasSRAM]>; 1607 } 1608 1609 // Stack pop operations. 1610 let mayLoad = 1 in 1611 { 1612 def POPRd : FRd<0b1001, 1613 0b0001111, 1614 (outs GPR8:$reg), 1615 (ins), 1616 "pop\t$reg", 1617 []>, 1618 Requires<[HasSRAM]>; 1619 1620 def POPWRd : Pseudo<(outs DREGS:$reg), 1621 (ins), 1622 "popw\t$reg", 1623 []>, 1624 Requires<[HasSRAM]>; 1625 } 1626} 1627 1628// Read-Write-Modify (RMW) instructions. 1629def XCHZRd : FZRd<0b100, 1630 (outs GPR8:$rd), 1631 (ins ZREG:$z), 1632 "xch\t$z, $rd", 1633 []>, 1634 Requires<[SupportsRMW]>; 1635 1636def LASZRd : FZRd<0b101, 1637 (outs GPR8:$rd), 1638 (ins ZREG:$z), 1639 "las\t$z, $rd", 1640 []>, 1641 Requires<[SupportsRMW]>; 1642 1643def LACZRd : FZRd<0b110, 1644 (outs GPR8:$rd), 1645 (ins ZREG:$z), 1646 "lac\t$z, $rd", 1647 []>, 1648 Requires<[SupportsRMW]>; 1649 1650def LATZRd : FZRd<0b111, 1651 (outs GPR8:$rd), 1652 (ins ZREG:$z), 1653 "lat\t$z, $rd", 1654 []>, 1655 Requires<[SupportsRMW]>; 1656 1657//===----------------------------------------------------------------------===// 1658// Bit and bit-test instructions 1659//===----------------------------------------------------------------------===// 1660 1661// Bit shift/rotate operations. 1662let Constraints = "$src = $rd", 1663Defs = [SREG] in 1664{ 1665 // 8-bit LSL is an alias of ADD Rd, Rd 1666 1667 def LSLWRd : Pseudo<(outs DREGS:$rd), 1668 (ins DREGS:$src), 1669 "lslw\t$rd", 1670 [(set i16:$rd, (AVRlsl i16:$src)), (implicit SREG)]>; 1671 1672 def LSLB7Rd : Pseudo<(outs GPR8:$rd), 1673 (ins GPR8:$src), 1674 "lslb7\t$rd", 1675 [(set i8:$rd, (AVRlsl7 i8:$src)), (implicit SREG)]>; 1676 1677 def LSRRd : FRd<0b1001, 1678 0b0100110, 1679 (outs GPR8:$rd), 1680 (ins GPR8:$src), 1681 "lsr\t$rd", 1682 [(set i8:$rd, (AVRlsr i8:$src)), (implicit SREG)]>; 1683 1684 def LSRB7Rd : Pseudo<(outs GPR8:$rd), 1685 (ins GPR8:$src), 1686 "lsrb7\t$rd", 1687 [(set i8:$rd, (AVRlsr7 i8:$src)), (implicit SREG)]>; 1688 1689 def LSRWRd : Pseudo<(outs DREGS:$rd), 1690 (ins DREGS:$src), 1691 "lsrw\t$rd", 1692 [(set i16:$rd, (AVRlsr i16:$src)), (implicit SREG)]>; 1693 1694 def ASRRd : FRd<0b1001, 1695 0b0100101, 1696 (outs GPR8:$rd), 1697 (ins GPR8:$src), 1698 "asr\t$rd", 1699 [(set i8:$rd, (AVRasr i8:$src)), (implicit SREG)]>; 1700 1701 def ASRB7Rd : Pseudo<(outs GPR8:$rd), 1702 (ins GPR8:$src), 1703 "asrb7\t$rd", 1704 [(set i8:$rd, (AVRasr7 i8:$src)), (implicit SREG)]>; 1705 1706 def ASRWRd : Pseudo<(outs DREGS:$rd), 1707 (ins DREGS:$src), 1708 "asrw\t$rd", 1709 [(set i16:$rd, (AVRasr i16:$src)), (implicit SREG)]>; 1710 1711 // Bit rotate operations. 1712 let Uses = [SREG] in 1713 { 1714 // 8-bit ROL is an alias of ADC Rd, Rd 1715 1716 def ROLBRd : Pseudo<(outs GPR8:$rd), 1717 (ins GPR8:$src), 1718 "rolb\t$rd", 1719 [(set i8:$rd, (AVRrol i8:$src)), (implicit SREG)]>; 1720 1721 def RORBRd : Pseudo<(outs GPR8:$rd), 1722 (ins GPR8:$src), 1723 "rorb\t$rd", 1724 [(set i8:$rd, (AVRror i8:$src)), (implicit SREG)]>; 1725 1726 def ROLWRd : Pseudo<(outs DREGS:$rd), 1727 (ins DREGS:$src), 1728 "rolw\t$rd", 1729 [(set i16:$rd, (AVRrol i16:$src)), (implicit SREG)]>; 1730 1731 def RORRd : FRd<0b1001, 1732 0b0100111, 1733 (outs GPR8:$rd), 1734 (ins GPR8:$src), 1735 "ror\t$rd", 1736 []>; 1737 1738 def RORWRd : Pseudo<(outs DREGS:$rd), 1739 (ins DREGS:$src), 1740 "rorw\t$rd", 1741 [(set i16:$rd, (AVRror i16:$src)), (implicit SREG)]>; 1742 } 1743} 1744 1745// SWAP Rd 1746// Swaps the high and low nibbles in a register. 1747let Constraints = "$src = $rd" in 1748def SWAPRd : FRd<0b1001, 1749 0b0100010, 1750 (outs GPR8:$rd), 1751 (ins GPR8:$src), 1752 "swap\t$rd", 1753 [(set i8:$rd, (AVRSwap i8:$src))]>; 1754 1755// IO register bit set/clear operations. 1756//:TODO: add patterns when popcount(imm)==2 to be expanded with 2 sbi/cbi 1757// instead of in+ori+out which requires one more instr. 1758def SBIAb : FIOBIT<0b10, 1759 (outs), 1760 (ins imm_port5:$addr, i8imm:$bit), 1761 "sbi\t$addr, $bit", 1762 [(store (or (i8 (load lowioaddr8:$addr)), iobitpos8:$bit), 1763 lowioaddr8:$addr)]>; 1764 1765def CBIAb : FIOBIT<0b00, 1766 (outs), 1767 (ins imm_port5:$addr, i8imm:$bit), 1768 "cbi\t$addr, $bit", 1769 [(store (and (i8 (load lowioaddr8:$addr)), iobitposn8:$bit), 1770 lowioaddr8:$addr)]>; 1771 1772// Status register bit load/store operations. 1773let Defs = [SREG] in 1774def BST : FRdB<0b01, 1775 (outs), 1776 (ins GPR8:$rd, i8imm:$b), 1777 "bst\t$rd, $b", 1778 []>; 1779 1780let Uses = [SREG] in 1781def BLD : FRdB<0b00, 1782 (outs), 1783 (ins GPR8:$rd, i8imm:$b), 1784 "bld\t$rd, $b", 1785 []>; 1786 1787def CBR : InstAlias<"cbr\t$rd, $k", (ANDIRdK LD8:$rd, imm_com8:$k), 0>; 1788 1789// CLR Rd 1790// Alias for EOR Rd, Rd 1791// ------------- 1792// Clears all bits in a register. 1793def CLR : InstAlias<"clr\t$rd", (EORRdRr GPR8:$rd, GPR8:$rd)>; 1794 1795// LSL Rd 1796// Alias for ADD Rd, Rd 1797// -------------- 1798// Logical shift left one bit. 1799def LSL : InstAlias<"lsl\t$rd", (ADDRdRr GPR8:$rd, GPR8:$rd)>; 1800 1801def ROL : InstAlias<"rol\t$rd", (ADCRdRr GPR8:$rd, GPR8:$rd)>; 1802 1803// SER Rd 1804// Alias for LDI Rd, 0xff 1805// --------- 1806// Sets all bits in a register. 1807def : InstAlias<"ser\t$rd", (LDIRdK LD8:$rd, 0xff), 0>; 1808 1809let Defs = [SREG] in 1810def BSETs : FS<0, 1811 (outs), 1812 (ins i8imm:$s), 1813 "bset\t$s", 1814 []>; 1815 1816let Defs = [SREG] in 1817def BCLRs : FS<1, 1818 (outs), 1819 (ins i8imm:$s), 1820 "bclr\t$s", 1821 []>; 1822 1823// Set/clear aliases for the carry (C) status flag (bit 0). 1824def : InstAlias<"sec", (BSETs 0)>; 1825def : InstAlias<"clc", (BCLRs 0)>; 1826 1827// Set/clear aliases for the zero (Z) status flag (bit 1). 1828def : InstAlias<"sez", (BSETs 1)>; 1829def : InstAlias<"clz", (BCLRs 1)>; 1830 1831// Set/clear aliases for the negative (N) status flag (bit 2). 1832def : InstAlias<"sen", (BSETs 2)>; 1833def : InstAlias<"cln", (BCLRs 2)>; 1834 1835// Set/clear aliases for the overflow (V) status flag (bit 3). 1836def : InstAlias<"sev", (BSETs 3)>; 1837def : InstAlias<"clv", (BCLRs 3)>; 1838 1839// Set/clear aliases for the signed (S) status flag (bit 4). 1840def : InstAlias<"ses", (BSETs 4)>; 1841def : InstAlias<"cls", (BCLRs 4)>; 1842 1843// Set/clear aliases for the half-carry (H) status flag (bit 5). 1844def : InstAlias<"seh", (BSETs 5)>; 1845def : InstAlias<"clh", (BCLRs 5)>; 1846 1847// Set/clear aliases for the T status flag (bit 6). 1848def : InstAlias<"set", (BSETs 6)>; 1849def : InstAlias<"clt", (BCLRs 6)>; 1850 1851// Set/clear aliases for the interrupt (I) status flag (bit 7). 1852def : InstAlias<"sei", (BSETs 7)>; 1853def : InstAlias<"cli", (BCLRs 7)>; 1854 1855//===----------------------------------------------------------------------===// 1856// Special/Control instructions 1857//===----------------------------------------------------------------------===// 1858 1859// BREAK 1860// Breakpoint instruction 1861// --------- 1862// <|1001|0101|1001|1000> 1863def BREAK : F16<0b1001010110011000, 1864 (outs), 1865 (ins), 1866 "break", 1867 []>, 1868 Requires<[HasBREAK]>; 1869 1870// NOP 1871// No-operation instruction 1872// --------- 1873// <|0000|0000|0000|0000> 1874def NOP : F16<0b0000000000000000, 1875 (outs), 1876 (ins), 1877 "nop", 1878 []>; 1879 1880// SLEEP 1881// Sleep instruction 1882// --------- 1883// <|1001|0101|1000|1000> 1884def SLEEP : F16<0b1001010110001000, 1885 (outs), 1886 (ins), 1887 "sleep", 1888 []>; 1889 1890// WDR 1891// Watchdog reset 1892// --------- 1893// <|1001|0101|1010|1000> 1894def WDR : F16<0b1001010110101000, 1895 (outs), 1896 (ins), 1897 "wdr", 1898 []>; 1899 1900//===----------------------------------------------------------------------===// 1901// Pseudo instructions for later expansion 1902//===----------------------------------------------------------------------===// 1903 1904//:TODO: Optimize this for wider types AND optimize the following code 1905// compile int foo(char a, char b, char c, char d) {return d+b;} 1906// looks like a missed sext_inreg opportunity. 1907def SEXT : ExtensionPseudo< 1908 (outs DREGS:$dst), 1909 (ins GPR8:$src), 1910 "sext\t$dst, $src", 1911 [(set i16:$dst, (sext i8:$src)), (implicit SREG)] 1912>; 1913 1914def ZEXT : ExtensionPseudo< 1915 (outs DREGS:$dst), 1916 (ins GPR8:$src), 1917 "zext\t$dst, $src", 1918 [(set i16:$dst, (zext i8:$src)), (implicit SREG)] 1919>; 1920 1921// This pseudo gets expanded into a movw+adiw thus it clobbers SREG. 1922let Defs = [SREG], 1923 hasSideEffects = 0 in 1924def FRMIDX : Pseudo<(outs DLDREGS:$dst), 1925 (ins DLDREGS:$src, i16imm:$src2), 1926 "frmidx\t$dst, $src, $src2", 1927 []>; 1928 1929// This pseudo is either converted to a regular store or a push which clobbers 1930// SP. 1931def STDSPQRr : StorePseudo< 1932 (outs), 1933 (ins memspi:$dst, GPR8:$src), 1934 "stdstk\t$dst, $src", 1935 [(store i8:$src, addr:$dst)] 1936>; 1937 1938// This pseudo is either converted to a regular store or a push which clobbers 1939// SP. 1940def STDWSPQRr : StorePseudo< 1941 (outs), 1942 (ins memspi:$dst, DREGS:$src), 1943 "stdwstk\t$dst, $src", 1944 [(store i16:$src, addr:$dst)] 1945>; 1946 1947// SP read/write pseudos. 1948let hasSideEffects = 0 in 1949{ 1950 let Uses = [SP] in 1951 def SPREAD : Pseudo< 1952 (outs DREGS:$dst), 1953 (ins GPRSP:$src), 1954 "spread\t$dst, $src", 1955 [] 1956 >; 1957 1958 let Defs = [SP] in 1959 def SPWRITE : Pseudo< 1960 (outs GPRSP:$dst), 1961 (ins DREGS:$src), 1962 "spwrite\t$dst, $src", 1963 []>; 1964} 1965 1966def Select8 : SelectPseudo< 1967 (outs GPR8:$dst), 1968 (ins GPR8:$src, GPR8:$src2, i8imm:$cc), 1969 "# Select8 PSEUDO", 1970 [(set i8:$dst, (AVRselectcc i8:$src, i8:$src2, imm:$cc))] 1971>; 1972 1973def Select16 : SelectPseudo< 1974 (outs DREGS:$dst), 1975 (ins DREGS:$src, DREGS:$src2, i8imm:$cc), 1976 "# Select16 PSEUDO", 1977 [(set i16:$dst, (AVRselectcc i16:$src, i16:$src2, imm:$cc))] 1978>; 1979 1980def Lsl8 : ShiftPseudo< 1981 (outs GPR8:$dst), 1982 (ins GPR8:$src, GPR8:$cnt), 1983 "# Lsl8 PSEUDO", 1984 [(set i8:$dst, (AVRlslLoop i8:$src, i8:$cnt))] 1985>; 1986 1987def Lsl16 : ShiftPseudo< 1988 (outs DREGS:$dst), 1989 (ins DREGS:$src, GPR8:$cnt), 1990 "# Lsl16 PSEUDO", 1991 [(set i16:$dst, (AVRlslLoop i16:$src, i8:$cnt))] 1992>; 1993 1994def Lsr8 : ShiftPseudo< 1995 (outs GPR8:$dst), 1996 (ins GPR8:$src, GPR8:$cnt), 1997 "# Lsr8 PSEUDO", 1998 [(set i8:$dst, (AVRlsrLoop i8:$src, i8:$cnt))] 1999>; 2000 2001def Lsr16 : ShiftPseudo< 2002 (outs DREGS:$dst), 2003 (ins DREGS:$src, GPR8:$cnt), 2004 "# Lsr16 PSEUDO", 2005 [(set i16:$dst, (AVRlsrLoop i16:$src, i8:$cnt))] 2006>; 2007 2008def Rol8 : ShiftPseudo< 2009 (outs GPR8:$dst), 2010 (ins GPR8:$src, GPR8:$cnt), 2011 "# Rol8 PSEUDO", 2012 [(set i8:$dst, (AVRrolLoop i8:$src, i8:$cnt))] 2013>; 2014 2015def Rol16 : ShiftPseudo< 2016 (outs DREGS:$dst), 2017 (ins DREGS:$src, GPR8:$cnt), 2018 "# Rol16 PSEUDO", 2019 [(set i16:$dst, (AVRrolLoop i16:$src, i8:$cnt))] 2020>; 2021 2022def Ror8 : ShiftPseudo< 2023 (outs GPR8:$dst), 2024 (ins GPR8:$src, GPR8:$cnt), 2025 "# Ror8 PSEUDO", 2026 [(set i8:$dst, (AVRrorLoop i8:$src, i8:$cnt))] 2027>; 2028 2029def Ror16 : ShiftPseudo< 2030 (outs DREGS:$dst), 2031 (ins DREGS:$src, GPR8:$cnt), 2032 "# Ror16 PSEUDO", 2033 [(set i16:$dst, (AVRrorLoop i16:$src, i8:$cnt))] 2034>; 2035 2036def Asr8 : ShiftPseudo< 2037 (outs GPR8:$dst), 2038 (ins GPR8:$src, GPR8:$cnt), 2039 "# Asr8 PSEUDO", 2040 [(set i8:$dst, (AVRasrLoop i8:$src, i8:$cnt))] 2041>; 2042 2043def Asr16 : ShiftPseudo< 2044 (outs DREGS:$dst), 2045 (ins DREGS:$src, GPR8:$cnt), 2046 "# Asr16 PSEUDO", 2047 [(set i16:$dst, (AVRasrLoop i16:$src, i8:$cnt))] 2048>; 2049 2050 2051//===----------------------------------------------------------------------===// 2052// Non-Instruction Patterns 2053//===----------------------------------------------------------------------===// 2054 2055//:TODO: look in x86InstrCompiler.td for odd encoding trick related to 2056// add x, 128 -> sub x, -128. Clang is emitting an eor for this (ldi+eor) 2057 2058// the add instruction always writes the carry flag 2059def : Pat<(addc i8:$src, i8:$src2), 2060 (ADDRdRr i8:$src, i8:$src2)>; 2061def : Pat<(addc DREGS:$src, DREGS:$src2), 2062 (ADDWRdRr DREGS:$src, DREGS:$src2)>; 2063 2064// all sub instruction variants always writes the carry flag 2065def : Pat<(subc i8:$src, i8:$src2), 2066 (SUBRdRr i8:$src, i8:$src2)>; 2067def : Pat<(subc i16:$src, i16:$src2), 2068 (SUBWRdRr i16:$src, i16:$src2)>; 2069def : Pat<(subc i8:$src, imm:$src2), 2070 (SUBIRdK i8:$src, imm:$src2)>; 2071def : Pat<(subc i16:$src, imm:$src2), 2072 (SUBIWRdK i16:$src, imm:$src2)>; 2073 2074// These patterns convert add (x, -imm) to sub (x, imm) since we dont have 2075// any add with imm instructions. Also take care of the adiw/sbiw instructions. 2076def : Pat<(add i16:$src1, imm0_63_neg:$src2), 2077 (SBIWRdK i16:$src1, (imm0_63_neg:$src2))>; 2078def : Pat<(add i16:$src1, imm:$src2), 2079 (SUBIWRdK i16:$src1, (imm16_neg_XFORM imm:$src2))>; 2080def : Pat<(addc i16:$src1, imm:$src2), 2081 (SUBIWRdK i16:$src1, (imm16_neg_XFORM imm:$src2))>; 2082 2083def : Pat<(add i8:$src1, imm:$src2), 2084 (SUBIRdK i8:$src1, (imm8_neg_XFORM imm:$src2))>; 2085def : Pat<(addc i8:$src1, imm:$src2), 2086 (SUBIRdK i8:$src1, (imm8_neg_XFORM imm:$src2))>; 2087def : Pat<(adde i8:$src1, imm:$src2), 2088 (SBCIRdK i8:$src1, (imm8_neg_XFORM imm:$src2))>; 2089 2090// Calls. 2091def : Pat<(AVRcall (i16 tglobaladdr:$dst)), 2092 (CALLk tglobaladdr:$dst)>; 2093def : Pat<(AVRcall (i16 texternalsym:$dst)), 2094 (CALLk texternalsym:$dst)>; 2095 2096// `anyext` 2097def : Pat<(i16 (anyext i8:$src)), 2098 (INSERT_SUBREG (i16 (IMPLICIT_DEF)), i8:$src, sub_lo)>; 2099 2100// `trunc` 2101def : Pat<(i8 (trunc i16:$src)), 2102 (EXTRACT_SUBREG i16:$src, sub_lo)>; 2103 2104// sext_inreg 2105def : Pat<(sext_inreg i16:$src, i8), 2106 (SEXT (i8 (EXTRACT_SUBREG i16:$src, sub_lo)))>; 2107 2108// GlobalAddress 2109def : Pat<(i16 (AVRWrapper tglobaladdr:$dst)), 2110 (LDIWRdK tglobaladdr:$dst)>; 2111def : Pat<(add i16:$src, (AVRWrapper tglobaladdr:$src2)), 2112 (SUBIWRdK i16:$src, tglobaladdr:$src2)>; 2113def : Pat<(i8 (load (AVRWrapper tglobaladdr:$dst))), 2114 (LDSRdK tglobaladdr:$dst)>; 2115def : Pat<(i16 (load (AVRWrapper tglobaladdr:$dst))), 2116 (LDSWRdK tglobaladdr:$dst)>; 2117def : Pat<(store i8:$src, (i16 (AVRWrapper tglobaladdr:$dst))), 2118 (STSKRr tglobaladdr:$dst, i8:$src)>; 2119def : Pat<(store i16:$src, (i16 (AVRWrapper tglobaladdr:$dst))), 2120 (STSWKRr tglobaladdr:$dst, i16:$src)>; 2121 2122// BlockAddress 2123def : Pat<(i16 (AVRWrapper tblockaddress:$dst)), 2124 (LDIWRdK tblockaddress:$dst)>; 2125 2126// hi-reg truncation : trunc(int16 >> 8) 2127//:FIXME: i think it's better to emit an extract subreg node in the DAG than 2128// all this mess once we get optimal shift code 2129// lol... I think so, too. [@agnat] 2130def : Pat<(i8 (trunc (AVRlsr (AVRlsr (AVRlsr (AVRlsr (AVRlsr (AVRlsr (AVRlsr 2131 (AVRlsr DREGS:$src)))))))))), 2132 (EXTRACT_SUBREG DREGS:$src, sub_hi)>; 2133 2134// :FIXME: DAGCombiner produces an shl node after legalization from these seq: 2135// BR_JT -> (mul x, 2) -> (shl x, 1) 2136def : Pat<(shl i16:$src1, (i8 1)), 2137 (LSLWRd i16:$src1)>; 2138 2139// Lowering of 'tst' node to 'TST' instruction. 2140// TST is an alias of AND Rd, Rd. 2141def : Pat<(AVRtst i8:$rd), 2142 (ANDRdRr GPR8:$rd, GPR8:$rd)>; 2143 2144// Lowering of 'lsl' node to 'LSL' instruction. 2145// LSL is an alias of 'ADD Rd, Rd' 2146def : Pat<(AVRlsl i8:$rd), 2147 (ADDRdRr GPR8:$rd, GPR8:$rd)>; 2148 2149