1 //===-- ARMBaseInfo.cpp - ARM Base encoding information------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides basic encoding and assembly information for ARM. 10 // 11 //===----------------------------------------------------------------------===// 12 #include "ARMBaseInfo.h" 13 #include "llvm/ADT/ArrayRef.h" 14 #include "llvm/ADT/SmallVector.h" 15 16 using namespace llvm; 17 namespace llvm { 18 ARM::PredBlockMask expandPredBlockMask(ARM::PredBlockMask BlockMask, 19 ARMVCC::VPTCodes Kind) { 20 using PredBlockMask = ARM::PredBlockMask; 21 assert(Kind != ARMVCC::None && "Cannot expand a mask with None!"); 22 assert(llvm::countr_zero((unsigned)BlockMask) != 0 && "Mask is already full"); 23 24 auto ChooseMask = [&](PredBlockMask AddedThen, PredBlockMask AddedElse) { 25 return Kind == ARMVCC::Then ? AddedThen : AddedElse; 26 }; 27 28 switch (BlockMask) { 29 case PredBlockMask::T: 30 return ChooseMask(PredBlockMask::TT, PredBlockMask::TE); 31 case PredBlockMask::TT: 32 return ChooseMask(PredBlockMask::TTT, PredBlockMask::TTE); 33 case PredBlockMask::TE: 34 return ChooseMask(PredBlockMask::TET, PredBlockMask::TEE); 35 case PredBlockMask::TTT: 36 return ChooseMask(PredBlockMask::TTTT, PredBlockMask::TTTE); 37 case PredBlockMask::TTE: 38 return ChooseMask(PredBlockMask::TTET, PredBlockMask::TTEE); 39 case PredBlockMask::TET: 40 return ChooseMask(PredBlockMask::TETT, PredBlockMask::TETE); 41 case PredBlockMask::TEE: 42 return ChooseMask(PredBlockMask::TEET, PredBlockMask::TEEE); 43 default: 44 llvm_unreachable("Unknown Mask"); 45 } 46 } 47 48 namespace ARMSysReg { 49 50 // lookup system register using 12-bit SYSm value. 51 // Note: the search is uniqued using M1 mask 52 const MClassSysReg *lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm) { 53 return lookupMClassSysRegByM1Encoding12(SYSm); 54 } 55 56 // returns APSR with _<bits> qualifier. 57 // Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier 58 const MClassSysReg *lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm) { 59 return lookupMClassSysRegByM2M3Encoding8((1<<9)|(SYSm & 0xFF)); 60 } 61 62 // lookup system registers using 8-bit SYSm value 63 const MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm) { 64 return ARMSysReg::lookupMClassSysRegByM2M3Encoding8((1<<8)|(SYSm & 0xFF)); 65 } 66 67 #define GET_MCLASSSYSREG_IMPL 68 #include "ARMGenSystemRegister.inc" 69 70 } // end namespace ARMSysReg 71 72 namespace ARMBankedReg { 73 #define GET_BANKEDREG_IMPL 74 #include "ARMGenSystemRegister.inc" 75 } // end namespce ARMSysReg 76 } // end namespace llvm 77