1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the ARMMCCodeEmitter class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MCTargetDesc/ARMAddressingModes.h" 14 #include "MCTargetDesc/ARMBaseInfo.h" 15 #include "MCTargetDesc/ARMFixupKinds.h" 16 #include "MCTargetDesc/ARMMCExpr.h" 17 #include "llvm/ADT/APFloat.h" 18 #include "llvm/ADT/APInt.h" 19 #include "llvm/ADT/SmallVector.h" 20 #include "llvm/ADT/Statistic.h" 21 #include "llvm/MC/MCCodeEmitter.h" 22 #include "llvm/MC/MCContext.h" 23 #include "llvm/MC/MCExpr.h" 24 #include "llvm/MC/MCFixup.h" 25 #include "llvm/MC/MCInst.h" 26 #include "llvm/MC/MCInstrDesc.h" 27 #include "llvm/MC/MCInstrInfo.h" 28 #include "llvm/MC/MCRegisterInfo.h" 29 #include "llvm/MC/MCSubtargetInfo.h" 30 #include "llvm/Support/Casting.h" 31 #include "llvm/Support/Compiler.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/MathExtras.h" 34 #include "llvm/Support/raw_ostream.h" 35 #include "llvm/TargetParser/Triple.h" 36 #include <algorithm> 37 #include <cassert> 38 #include <cstdint> 39 #include <cstdlib> 40 41 using namespace llvm; 42 43 #define DEBUG_TYPE "mccodeemitter" 44 45 STATISTIC(MCNumEmitted, "Number of MC instructions emitted."); 46 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created."); 47 48 namespace { 49 50 class ARMMCCodeEmitter : public MCCodeEmitter { 51 const MCInstrInfo &MCII; 52 MCContext &CTX; 53 bool IsLittleEndian; 54 55 public: 56 ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle) 57 : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) { 58 } 59 ARMMCCodeEmitter(const ARMMCCodeEmitter &) = delete; 60 ARMMCCodeEmitter &operator=(const ARMMCCodeEmitter &) = delete; 61 ~ARMMCCodeEmitter() override = default; 62 63 bool isThumb(const MCSubtargetInfo &STI) const { 64 return STI.hasFeature(ARM::ModeThumb); 65 } 66 67 bool isThumb2(const MCSubtargetInfo &STI) const { 68 return isThumb(STI) && STI.hasFeature(ARM::FeatureThumb2); 69 } 70 71 bool isTargetMachO(const MCSubtargetInfo &STI) const { 72 const Triple &TT = STI.getTargetTriple(); 73 return TT.isOSBinFormatMachO(); 74 } 75 76 unsigned getMachineSoImmOpValue(unsigned SoImm) const; 77 78 // getBinaryCodeForInstr - TableGen'erated function for getting the 79 // binary encoding for an instruction. 80 uint64_t getBinaryCodeForInstr(const MCInst &MI, 81 SmallVectorImpl<MCFixup> &Fixups, 82 const MCSubtargetInfo &STI) const; 83 84 /// getMachineOpValue - Return binary encoding of operand. If the machine 85 /// operand requires relocation, record the relocation and return zero. 86 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 87 SmallVectorImpl<MCFixup> &Fixups, 88 const MCSubtargetInfo &STI) const; 89 90 /// getHiLoImmOpValue - Return the encoding for either the hi / low 16-bit, or 91 /// high/middle-high/middle-low/low 8 bits of the specified operand. This is 92 /// used for operands with :lower16:, :upper16: :lower0_7:, :lower8_15:, 93 /// :higher0_7:, and :higher8_15: prefixes. 94 uint32_t getHiLoImmOpValue(const MCInst &MI, unsigned OpIdx, 95 SmallVectorImpl<MCFixup> &Fixups, 96 const MCSubtargetInfo &STI) const; 97 98 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, 99 unsigned &Reg, unsigned &Imm, 100 SmallVectorImpl<MCFixup> &Fixups, 101 const MCSubtargetInfo &STI) const; 102 103 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate 104 /// BL branch target. 105 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 106 SmallVectorImpl<MCFixup> &Fixups, 107 const MCSubtargetInfo &STI) const; 108 109 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate 110 /// BLX branch target. 111 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 112 SmallVectorImpl<MCFixup> &Fixups, 113 const MCSubtargetInfo &STI) const; 114 115 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. 116 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, 117 SmallVectorImpl<MCFixup> &Fixups, 118 const MCSubtargetInfo &STI) const; 119 120 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. 121 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, 122 SmallVectorImpl<MCFixup> &Fixups, 123 const MCSubtargetInfo &STI) const; 124 125 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. 126 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, 127 SmallVectorImpl<MCFixup> &Fixups, 128 const MCSubtargetInfo &STI) const; 129 130 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate 131 /// branch target. 132 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 133 SmallVectorImpl<MCFixup> &Fixups, 134 const MCSubtargetInfo &STI) const; 135 136 /// getThumbBranchTargetOpValue - Return encoding info for 24-bit 137 /// immediate Thumb2 direct branch target. 138 uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 139 SmallVectorImpl<MCFixup> &Fixups, 140 const MCSubtargetInfo &STI) const; 141 142 /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate 143 /// branch target. 144 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 145 SmallVectorImpl<MCFixup> &Fixups, 146 const MCSubtargetInfo &STI) const; 147 uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 148 SmallVectorImpl<MCFixup> &Fixups, 149 const MCSubtargetInfo &STI) const; 150 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 151 SmallVectorImpl<MCFixup> &Fixups, 152 const MCSubtargetInfo &STI) const; 153 154 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate 155 /// ADR label target. 156 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 157 SmallVectorImpl<MCFixup> &Fixups, 158 const MCSubtargetInfo &STI) const; 159 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 160 SmallVectorImpl<MCFixup> &Fixups, 161 const MCSubtargetInfo &STI) const; 162 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 163 SmallVectorImpl<MCFixup> &Fixups, 164 const MCSubtargetInfo &STI) const; 165 166 uint32_t getITMaskOpValue(const MCInst &MI, unsigned OpIdx, 167 SmallVectorImpl<MCFixup> &Fixups, 168 const MCSubtargetInfo &STI) const; 169 170 /// getMVEShiftImmOpValue - Return encoding info for the 'sz:imm5' 171 /// operand. 172 uint32_t getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx, 173 SmallVectorImpl<MCFixup> &Fixups, 174 const MCSubtargetInfo &STI) const; 175 176 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' 177 /// operand. 178 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, 179 SmallVectorImpl<MCFixup> &Fixups, 180 const MCSubtargetInfo &STI) const; 181 182 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand. 183 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, 184 SmallVectorImpl<MCFixup> &Fixups, 185 const MCSubtargetInfo &STI) const; 186 187 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2' 188 /// operand. 189 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, 190 SmallVectorImpl<MCFixup> &Fixups, 191 const MCSubtargetInfo &STI) const; 192 193 /// getT2AddrModeImm7s4OpValue - Return encoding info for 'reg +/- imm7<<2' 194 /// operand. 195 uint32_t getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx, 196 SmallVectorImpl<MCFixup> &Fixups, 197 const MCSubtargetInfo &STI) const; 198 199 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2' 200 /// operand. 201 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, 202 SmallVectorImpl<MCFixup> &Fixups, 203 const MCSubtargetInfo &STI) const; 204 205 /// getT2ScaledImmOpValue - Return encoding info for '+/- immX<<Y' 206 /// operand. 207 template<unsigned Bits, unsigned Shift> 208 uint32_t getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx, 209 SmallVectorImpl<MCFixup> &Fixups, 210 const MCSubtargetInfo &STI) const; 211 212 /// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg' 213 /// operand. 214 uint32_t getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx, 215 SmallVectorImpl<MCFixup> &Fixups, 216 const MCSubtargetInfo &STI) const; 217 218 /// getMveAddrModeQOpValue - Return encoding info for 'reg +/- imm7<<{shift}' 219 /// operand. 220 template<int shift> 221 uint32_t getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx, 222 SmallVectorImpl<MCFixup> &Fixups, 223 const MCSubtargetInfo &STI) const; 224 225 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm' 226 /// operand as needed by load/store instructions. 227 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, 228 SmallVectorImpl<MCFixup> &Fixups, 229 const MCSubtargetInfo &STI) const; 230 231 /// getLdStmModeOpValue - Return encoding for load/store multiple mode. 232 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, 233 SmallVectorImpl<MCFixup> &Fixups, 234 const MCSubtargetInfo &STI) const { 235 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); 236 switch (Mode) { 237 default: llvm_unreachable("Unknown addressing sub-mode!"); 238 case ARM_AM::da: return 0; 239 case ARM_AM::ia: return 1; 240 case ARM_AM::db: return 2; 241 case ARM_AM::ib: return 3; 242 } 243 } 244 245 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 246 /// 247 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { 248 switch (ShOpc) { 249 case ARM_AM::no_shift: 250 case ARM_AM::lsl: return 0; 251 case ARM_AM::lsr: return 1; 252 case ARM_AM::asr: return 2; 253 case ARM_AM::ror: 254 case ARM_AM::rrx: return 3; 255 default: 256 llvm_unreachable("Invalid ShiftOpc!"); 257 } 258 } 259 260 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands. 261 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, 262 SmallVectorImpl<MCFixup> &Fixups, 263 const MCSubtargetInfo &STI) const; 264 265 /// getPostIdxRegOpValue - Return encoding for postidx_reg operands. 266 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, 267 SmallVectorImpl<MCFixup> &Fixups, 268 const MCSubtargetInfo &STI) const; 269 270 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands. 271 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, 272 SmallVectorImpl<MCFixup> &Fixups, 273 const MCSubtargetInfo &STI) const; 274 275 /// getAddrMode3OpValue - Return encoding for addrmode3 operands. 276 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, 277 SmallVectorImpl<MCFixup> &Fixups, 278 const MCSubtargetInfo &STI) const; 279 280 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12' 281 /// operand. 282 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, 283 SmallVectorImpl<MCFixup> &Fixups, 284 const MCSubtargetInfo &STI) const; 285 286 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands. 287 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, 288 SmallVectorImpl<MCFixup> &Fixups, 289 const MCSubtargetInfo &STI) const; 290 291 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. 292 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, 293 SmallVectorImpl<MCFixup> &Fixups, 294 const MCSubtargetInfo &STI) const; 295 296 /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand. 297 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, 298 SmallVectorImpl<MCFixup> &Fixups, 299 const MCSubtargetInfo &STI) const; 300 301 /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand. 302 uint32_t getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx, 303 SmallVectorImpl<MCFixup> &Fixups, 304 const MCSubtargetInfo &STI) const; 305 306 /// getCCOutOpValue - Return encoding of the 's' bit. 307 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op, 308 SmallVectorImpl<MCFixup> &Fixups, 309 const MCSubtargetInfo &STI) const { 310 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or 311 // '1' respectively. 312 return MI.getOperand(Op).getReg() == ARM::CPSR; 313 } 314 315 unsigned getModImmOpValue(const MCInst &MI, unsigned Op, 316 SmallVectorImpl<MCFixup> &Fixups, 317 const MCSubtargetInfo &ST) const { 318 const MCOperand &MO = MI.getOperand(Op); 319 320 // Support for fixups (MCFixup) 321 if (MO.isExpr()) { 322 const MCExpr *Expr = MO.getExpr(); 323 // Fixups resolve to plain values that need to be encoded. 324 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_mod_imm); 325 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 326 return 0; 327 } 328 329 // Immediate is already in its encoded format 330 return MO.getImm(); 331 } 332 333 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value. 334 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op, 335 SmallVectorImpl<MCFixup> &Fixups, 336 const MCSubtargetInfo &STI) const { 337 const MCOperand &MO = MI.getOperand(Op); 338 339 // Support for fixups (MCFixup) 340 if (MO.isExpr()) { 341 const MCExpr *Expr = MO.getExpr(); 342 // Fixups resolve to plain values that need to be encoded. 343 MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_so_imm); 344 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 345 return 0; 346 } 347 unsigned SoImm = MO.getImm(); 348 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm); 349 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?"); 350 return Encoded; 351 } 352 353 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, 354 SmallVectorImpl<MCFixup> &Fixups, 355 const MCSubtargetInfo &STI) const; 356 template<unsigned Bits, unsigned Shift> 357 unsigned getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum, 358 SmallVectorImpl<MCFixup> &Fixups, 359 const MCSubtargetInfo &STI) const; 360 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, 361 SmallVectorImpl<MCFixup> &Fixups, 362 const MCSubtargetInfo &STI) const; 363 364 /// getSORegOpValue - Return an encoded so_reg shifted register value. 365 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op, 366 SmallVectorImpl<MCFixup> &Fixups, 367 const MCSubtargetInfo &STI) const; 368 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op, 369 SmallVectorImpl<MCFixup> &Fixups, 370 const MCSubtargetInfo &STI) const; 371 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op, 372 SmallVectorImpl<MCFixup> &Fixups, 373 const MCSubtargetInfo &STI) const; 374 375 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op, 376 SmallVectorImpl<MCFixup> &Fixups, 377 const MCSubtargetInfo &STI) const { 378 return 64 - MI.getOperand(Op).getImm(); 379 } 380 381 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, 382 SmallVectorImpl<MCFixup> &Fixups, 383 const MCSubtargetInfo &STI) const; 384 385 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op, 386 SmallVectorImpl<MCFixup> &Fixups, 387 const MCSubtargetInfo &STI) const; 388 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, 389 SmallVectorImpl<MCFixup> &Fixups, 390 const MCSubtargetInfo &STI) const; 391 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, 392 SmallVectorImpl<MCFixup> &Fixups, 393 const MCSubtargetInfo &STI) const; 394 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, 395 SmallVectorImpl<MCFixup> &Fixups, 396 const MCSubtargetInfo &STI) const; 397 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, 398 SmallVectorImpl<MCFixup> &Fixups, 399 const MCSubtargetInfo &STI) const; 400 401 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op, 402 SmallVectorImpl<MCFixup> &Fixups, 403 const MCSubtargetInfo &STI) const; 404 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op, 405 SmallVectorImpl<MCFixup> &Fixups, 406 const MCSubtargetInfo &STI) const; 407 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op, 408 SmallVectorImpl<MCFixup> &Fixups, 409 const MCSubtargetInfo &STI) const; 410 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op, 411 SmallVectorImpl<MCFixup> &Fixups, 412 const MCSubtargetInfo &STI) const; 413 414 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op, 415 SmallVectorImpl<MCFixup> &Fixups, 416 const MCSubtargetInfo &STI) const; 417 418 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI, 419 unsigned EncodedValue, 420 const MCSubtargetInfo &STI) const; 421 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI, 422 unsigned EncodedValue, 423 const MCSubtargetInfo &STI) const; 424 unsigned NEONThumb2DupPostEncoder(const MCInst &MI, 425 unsigned EncodedValue, 426 const MCSubtargetInfo &STI) const; 427 unsigned NEONThumb2V8PostEncoder(const MCInst &MI, 428 unsigned EncodedValue, 429 const MCSubtargetInfo &STI) const; 430 431 unsigned VFPThumb2PostEncoder(const MCInst &MI, 432 unsigned EncodedValue, 433 const MCSubtargetInfo &STI) const; 434 435 uint32_t getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx, 436 SmallVectorImpl<MCFixup> &Fixups, 437 const MCSubtargetInfo &STI) const; 438 439 void EmitByte(unsigned char C, raw_ostream &OS) const { 440 OS << (char)C; 441 } 442 443 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const { 444 // Output the constant in little endian byte order. 445 for (unsigned i = 0; i != Size; ++i) { 446 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8; 447 EmitByte((Val >> Shift) & 0xff, OS); 448 } 449 } 450 451 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 452 SmallVectorImpl<MCFixup> &Fixups, 453 const MCSubtargetInfo &STI) const override; 454 455 template <bool isNeg, ARM::Fixups fixup> 456 uint32_t getBFTargetOpValue(const MCInst &MI, unsigned OpIdx, 457 SmallVectorImpl<MCFixup> &Fixups, 458 const MCSubtargetInfo &STI) const; 459 460 uint32_t getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx, 461 SmallVectorImpl<MCFixup> &Fixups, 462 const MCSubtargetInfo &STI) const; 463 464 uint32_t getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx, 465 SmallVectorImpl<MCFixup> &Fixups, 466 const MCSubtargetInfo &STI) const; 467 uint32_t getRestrictedCondCodeOpValue(const MCInst &MI, unsigned OpIdx, 468 SmallVectorImpl<MCFixup> &Fixups, 469 const MCSubtargetInfo &STI) const; 470 template <unsigned size> 471 uint32_t getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx, 472 SmallVectorImpl<MCFixup> &Fixups, 473 const MCSubtargetInfo &STI) const; 474 }; 475 476 } // end anonymous namespace 477 478 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing 479 /// instructions, and rewrite them to their Thumb2 form if we are currently in 480 /// Thumb2 mode. 481 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI, 482 unsigned EncodedValue, 483 const MCSubtargetInfo &STI) const { 484 if (isThumb2(STI)) { 485 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved 486 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are 487 // set to 1111. 488 unsigned Bit24 = EncodedValue & 0x01000000; 489 unsigned Bit28 = Bit24 << 4; 490 EncodedValue &= 0xEFFFFFFF; 491 EncodedValue |= Bit28; 492 EncodedValue |= 0x0F000000; 493 } 494 495 return EncodedValue; 496 } 497 498 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store 499 /// instructions, and rewrite them to their Thumb2 form if we are currently in 500 /// Thumb2 mode. 501 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI, 502 unsigned EncodedValue, 503 const MCSubtargetInfo &STI) const { 504 if (isThumb2(STI)) { 505 EncodedValue &= 0xF0FFFFFF; 506 EncodedValue |= 0x09000000; 507 } 508 509 return EncodedValue; 510 } 511 512 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup 513 /// instructions, and rewrite them to their Thumb2 form if we are currently in 514 /// Thumb2 mode. 515 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI, 516 unsigned EncodedValue, 517 const MCSubtargetInfo &STI) const { 518 if (isThumb2(STI)) { 519 EncodedValue &= 0x00FFFFFF; 520 EncodedValue |= 0xEE000000; 521 } 522 523 return EncodedValue; 524 } 525 526 /// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form 527 /// if we are in Thumb2. 528 unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI, 529 unsigned EncodedValue, 530 const MCSubtargetInfo &STI) const { 531 if (isThumb2(STI)) { 532 EncodedValue |= 0xC000000; // Set bits 27-26 533 } 534 535 return EncodedValue; 536 } 537 538 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite 539 /// them to their Thumb2 form if we are currently in Thumb2 mode. 540 unsigned ARMMCCodeEmitter:: 541 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue, 542 const MCSubtargetInfo &STI) const { 543 if (isThumb2(STI)) { 544 EncodedValue &= 0x0FFFFFFF; 545 EncodedValue |= 0xE0000000; 546 } 547 return EncodedValue; 548 } 549 550 /// getMachineOpValue - Return binary encoding of operand. If the machine 551 /// operand requires relocation, record the relocation and return zero. 552 unsigned ARMMCCodeEmitter:: 553 getMachineOpValue(const MCInst &MI, const MCOperand &MO, 554 SmallVectorImpl<MCFixup> &Fixups, 555 const MCSubtargetInfo &STI) const { 556 if (MO.isReg()) { 557 unsigned Reg = MO.getReg(); 558 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg); 559 560 // In NEON, Q registers are encoded as 2x their register number, 561 // because they're using the same indices as the D registers they 562 // overlap. In MVE, there are no 64-bit vector instructions, so 563 // the encodings all refer to Q-registers by their literal 564 // register number. 565 566 if (STI.hasFeature(ARM::HasMVEIntegerOps)) 567 return RegNo; 568 569 switch (Reg) { 570 default: 571 return RegNo; 572 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3: 573 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7: 574 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11: 575 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15: 576 return 2 * RegNo; 577 } 578 } else if (MO.isImm()) { 579 return static_cast<unsigned>(MO.getImm()); 580 } else if (MO.isDFPImm()) { 581 return static_cast<unsigned>(APFloat(bit_cast<double>(MO.getDFPImm())) 582 .bitcastToAPInt() 583 .getHiBits(32) 584 .getLimitedValue()); 585 } 586 587 llvm_unreachable("Unable to encode MCOperand!"); 588 } 589 590 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand. 591 bool ARMMCCodeEmitter:: 592 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, 593 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups, 594 const MCSubtargetInfo &STI) const { 595 const MCOperand &MO = MI.getOperand(OpIdx); 596 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 597 598 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 599 600 int32_t SImm = MO1.getImm(); 601 bool isAdd = true; 602 603 // Special value for #-0 604 if (SImm == INT32_MIN) { 605 SImm = 0; 606 isAdd = false; 607 } 608 609 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 610 if (SImm < 0) { 611 SImm = -SImm; 612 isAdd = false; 613 } 614 615 Imm = SImm; 616 return isAdd; 617 } 618 619 /// getBranchTargetOpValue - Helper function to get the branch target operand, 620 /// which is either an immediate or requires a fixup. 621 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 622 unsigned FixupKind, 623 SmallVectorImpl<MCFixup> &Fixups, 624 const MCSubtargetInfo &STI) { 625 const MCOperand &MO = MI.getOperand(OpIdx); 626 627 // If the destination is an immediate, we have nothing to do. 628 if (MO.isImm()) return MO.getImm(); 629 assert(MO.isExpr() && "Unexpected branch target type!"); 630 const MCExpr *Expr = MO.getExpr(); 631 MCFixupKind Kind = MCFixupKind(FixupKind); 632 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 633 634 // All of the information is in the fixup. 635 return 0; 636 } 637 638 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are 639 // determined by negating them and XOR'ing them with bit 23. 640 static int32_t encodeThumbBLOffset(int32_t offset) { 641 offset >>= 1; 642 uint32_t S = (offset & 0x800000) >> 23; 643 uint32_t J1 = (offset & 0x400000) >> 22; 644 uint32_t J2 = (offset & 0x200000) >> 21; 645 J1 = (~J1 & 0x1); 646 J2 = (~J2 & 0x1); 647 J1 ^= S; 648 J2 ^= S; 649 650 offset &= ~0x600000; 651 offset |= J1 << 22; 652 offset |= J2 << 21; 653 654 return offset; 655 } 656 657 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target. 658 uint32_t ARMMCCodeEmitter:: 659 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 660 SmallVectorImpl<MCFixup> &Fixups, 661 const MCSubtargetInfo &STI) const { 662 const MCOperand MO = MI.getOperand(OpIdx); 663 if (MO.isExpr()) 664 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, 665 Fixups, STI); 666 return encodeThumbBLOffset(MO.getImm()); 667 } 668 669 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate 670 /// BLX branch target. 671 uint32_t ARMMCCodeEmitter:: 672 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 673 SmallVectorImpl<MCFixup> &Fixups, 674 const MCSubtargetInfo &STI) const { 675 const MCOperand MO = MI.getOperand(OpIdx); 676 if (MO.isExpr()) 677 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, 678 Fixups, STI); 679 return encodeThumbBLOffset(MO.getImm()); 680 } 681 682 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. 683 uint32_t ARMMCCodeEmitter:: 684 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, 685 SmallVectorImpl<MCFixup> &Fixups, 686 const MCSubtargetInfo &STI) const { 687 const MCOperand MO = MI.getOperand(OpIdx); 688 if (MO.isExpr()) 689 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, 690 Fixups, STI); 691 return (MO.getImm() >> 1); 692 } 693 694 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. 695 uint32_t ARMMCCodeEmitter:: 696 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, 697 SmallVectorImpl<MCFixup> &Fixups, 698 const MCSubtargetInfo &STI) const { 699 const MCOperand MO = MI.getOperand(OpIdx); 700 if (MO.isExpr()) 701 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, 702 Fixups, STI); 703 return (MO.getImm() >> 1); 704 } 705 706 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. 707 uint32_t ARMMCCodeEmitter:: 708 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, 709 SmallVectorImpl<MCFixup> &Fixups, 710 const MCSubtargetInfo &STI) const { 711 const MCOperand MO = MI.getOperand(OpIdx); 712 if (MO.isExpr()) 713 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups, STI); 714 return (MO.getImm() >> 1); 715 } 716 717 /// Return true if this branch has a non-always predication 718 static bool HasConditionalBranch(const MCInst &MI) { 719 int NumOp = MI.getNumOperands(); 720 if (NumOp >= 2) { 721 for (int i = 0; i < NumOp-1; ++i) { 722 const MCOperand &MCOp1 = MI.getOperand(i); 723 const MCOperand &MCOp2 = MI.getOperand(i + 1); 724 if (MCOp1.isImm() && MCOp2.isReg() && 725 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) { 726 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL) 727 return true; 728 } 729 } 730 } 731 return false; 732 } 733 734 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch 735 /// target. 736 uint32_t ARMMCCodeEmitter:: 737 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 738 SmallVectorImpl<MCFixup> &Fixups, 739 const MCSubtargetInfo &STI) const { 740 // FIXME: This really, really shouldn't use TargetMachine. We don't want 741 // coupling between MC and TM anywhere we can help it. 742 if (isThumb2(STI)) 743 return 744 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI); 745 return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI); 746 } 747 748 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch 749 /// target. 750 uint32_t ARMMCCodeEmitter:: 751 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 752 SmallVectorImpl<MCFixup> &Fixups, 753 const MCSubtargetInfo &STI) const { 754 const MCOperand MO = MI.getOperand(OpIdx); 755 if (MO.isExpr()) { 756 if (HasConditionalBranch(MI)) 757 return ::getBranchTargetOpValue(MI, OpIdx, 758 ARM::fixup_arm_condbranch, Fixups, STI); 759 return ::getBranchTargetOpValue(MI, OpIdx, 760 ARM::fixup_arm_uncondbranch, Fixups, STI); 761 } 762 763 return MO.getImm() >> 2; 764 } 765 766 uint32_t ARMMCCodeEmitter:: 767 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 768 SmallVectorImpl<MCFixup> &Fixups, 769 const MCSubtargetInfo &STI) const { 770 const MCOperand MO = MI.getOperand(OpIdx); 771 if (MO.isExpr()) { 772 if (HasConditionalBranch(MI)) 773 return ::getBranchTargetOpValue(MI, OpIdx, 774 ARM::fixup_arm_condbl, Fixups, STI); 775 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups, STI); 776 } 777 778 return MO.getImm() >> 2; 779 } 780 781 uint32_t ARMMCCodeEmitter:: 782 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 783 SmallVectorImpl<MCFixup> &Fixups, 784 const MCSubtargetInfo &STI) const { 785 const MCOperand MO = MI.getOperand(OpIdx); 786 if (MO.isExpr()) 787 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI); 788 789 return MO.getImm() >> 1; 790 } 791 792 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit 793 /// immediate branch target. 794 uint32_t ARMMCCodeEmitter::getThumbBranchTargetOpValue( 795 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, 796 const MCSubtargetInfo &STI) const { 797 unsigned Val = 0; 798 const MCOperand MO = MI.getOperand(OpIdx); 799 800 if(MO.isExpr()) 801 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups, STI); 802 else 803 Val = MO.getImm() >> 1; 804 805 bool I = (Val & 0x800000); 806 bool J1 = (Val & 0x400000); 807 bool J2 = (Val & 0x200000); 808 if (I ^ J1) 809 Val &= ~0x400000; 810 else 811 Val |= 0x400000; 812 813 if (I ^ J2) 814 Val &= ~0x200000; 815 else 816 Val |= 0x200000; 817 818 return Val; 819 } 820 821 /// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate 822 /// ADR label target. 823 uint32_t ARMMCCodeEmitter:: 824 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 825 SmallVectorImpl<MCFixup> &Fixups, 826 const MCSubtargetInfo &STI) const { 827 const MCOperand MO = MI.getOperand(OpIdx); 828 if (MO.isExpr()) 829 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12, 830 Fixups, STI); 831 int64_t offset = MO.getImm(); 832 uint32_t Val = 0x2000; 833 834 int SoImmVal; 835 if (offset == INT32_MIN) { 836 Val = 0x1000; 837 SoImmVal = 0; 838 } else if (offset < 0) { 839 Val = 0x1000; 840 offset *= -1; 841 SoImmVal = ARM_AM::getSOImmVal(offset); 842 if(SoImmVal == -1) { 843 Val = 0x2000; 844 offset *= -1; 845 SoImmVal = ARM_AM::getSOImmVal(offset); 846 } 847 } else { 848 SoImmVal = ARM_AM::getSOImmVal(offset); 849 if(SoImmVal == -1) { 850 Val = 0x1000; 851 offset *= -1; 852 SoImmVal = ARM_AM::getSOImmVal(offset); 853 } 854 } 855 856 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 857 858 Val |= SoImmVal; 859 return Val; 860 } 861 862 /// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label 863 /// target. 864 uint32_t ARMMCCodeEmitter:: 865 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 866 SmallVectorImpl<MCFixup> &Fixups, 867 const MCSubtargetInfo &STI) const { 868 const MCOperand MO = MI.getOperand(OpIdx); 869 if (MO.isExpr()) 870 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12, 871 Fixups, STI); 872 int32_t Val = MO.getImm(); 873 if (Val == INT32_MIN) 874 Val = 0x1000; 875 else if (Val < 0) { 876 Val *= -1; 877 Val |= 0x1000; 878 } 879 return Val; 880 } 881 882 /// getITMaskOpValue - Return the architectural encoding of an IT 883 /// predication mask, given the MCOperand format. 884 uint32_t ARMMCCodeEmitter:: 885 getITMaskOpValue(const MCInst &MI, unsigned OpIdx, 886 SmallVectorImpl<MCFixup> &Fixups, 887 const MCSubtargetInfo &STI) const { 888 const MCOperand MaskMO = MI.getOperand(OpIdx); 889 assert(MaskMO.isImm() && "Unexpected operand type!"); 890 891 unsigned Mask = MaskMO.getImm(); 892 893 // IT masks are encoded as a sequence of replacement low-order bits 894 // for the condition code. So if the low bit of the starting 895 // condition code is 1, then we have to flip all the bits above the 896 // terminating bit (which is the lowest 1 bit). 897 assert(OpIdx > 0 && "IT mask appears first!"); 898 const MCOperand CondMO = MI.getOperand(OpIdx-1); 899 assert(CondMO.isImm() && "Unexpected operand type!"); 900 if (CondMO.getImm() & 1) { 901 unsigned LowBit = Mask & -Mask; 902 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 903 Mask ^= BitsAboveLowBit; 904 } 905 906 return Mask; 907 } 908 909 /// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label 910 /// target. 911 uint32_t ARMMCCodeEmitter:: 912 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 913 SmallVectorImpl<MCFixup> &Fixups, 914 const MCSubtargetInfo &STI) const { 915 const MCOperand MO = MI.getOperand(OpIdx); 916 if (MO.isExpr()) 917 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10, 918 Fixups, STI); 919 return MO.getImm(); 920 } 921 922 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg' 923 /// operand. 924 uint32_t ARMMCCodeEmitter:: 925 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, 926 SmallVectorImpl<MCFixup> &, 927 const MCSubtargetInfo &STI) const { 928 // [Rn, Rm] 929 // {5-3} = Rm 930 // {2-0} = Rn 931 const MCOperand &MO1 = MI.getOperand(OpIdx); 932 const MCOperand &MO2 = MI.getOperand(OpIdx + 1); 933 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 934 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); 935 return (Rm << 3) | Rn; 936 } 937 938 /// getMVEShiftImmOpValue - Return encoding info for the 'sz:imm5' 939 /// operand. 940 uint32_t 941 ARMMCCodeEmitter::getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx, 942 SmallVectorImpl<MCFixup> &Fixups, 943 const MCSubtargetInfo &STI) const { 944 // {4-0} = szimm5 945 // The value we are trying to encode is an immediate between either the 946 // range of [1-7] or [1-15] depending on whether we are dealing with the 947 // u8/s8 or the u16/s16 variants respectively. 948 // This value is encoded as follows, if ShiftImm is the value within those 949 // ranges then the encoding szimm5 = ShiftImm + size, where size is either 8 950 // or 16. 951 952 unsigned Size, ShiftImm; 953 switch(MI.getOpcode()) { 954 case ARM::MVE_VSHLL_imms16bh: 955 case ARM::MVE_VSHLL_imms16th: 956 case ARM::MVE_VSHLL_immu16bh: 957 case ARM::MVE_VSHLL_immu16th: 958 Size = 16; 959 break; 960 case ARM::MVE_VSHLL_imms8bh: 961 case ARM::MVE_VSHLL_imms8th: 962 case ARM::MVE_VSHLL_immu8bh: 963 case ARM::MVE_VSHLL_immu8th: 964 Size = 8; 965 break; 966 default: 967 llvm_unreachable("Use of operand not supported by this instruction"); 968 } 969 ShiftImm = MI.getOperand(OpIdx).getImm(); 970 return Size + ShiftImm; 971 } 972 973 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand. 974 uint32_t ARMMCCodeEmitter:: 975 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, 976 SmallVectorImpl<MCFixup> &Fixups, 977 const MCSubtargetInfo &STI) const { 978 // {17-13} = reg 979 // {12} = (U)nsigned (add == '1', sub == '0') 980 // {11-0} = imm12 981 unsigned Reg = 0, Imm12 = 0; 982 bool isAdd = true; 983 // If The first operand isn't a register, we have a label reference. 984 const MCOperand &MO = MI.getOperand(OpIdx); 985 if (MO.isReg()) { 986 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 987 if (MO1.isImm()) { 988 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI); 989 } else if (MO1.isExpr()) { 990 assert(!isThumb(STI) && !isThumb2(STI) && 991 "Thumb mode requires different encoding"); 992 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 993 isAdd = false; // 'U' bit is set as part of the fixup. 994 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_ldst_abs_12); 995 Fixups.push_back(MCFixup::create(0, MO1.getExpr(), Kind, MI.getLoc())); 996 } 997 } else if (MO.isExpr()) { 998 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 999 isAdd = false; // 'U' bit is set as part of the fixup. 1000 MCFixupKind Kind; 1001 if (isThumb2(STI)) 1002 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12); 1003 else 1004 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12); 1005 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc())); 1006 1007 ++MCNumCPRelocations; 1008 } else { 1009 Reg = ARM::PC; 1010 int32_t Offset = MO.getImm(); 1011 if (Offset == INT32_MIN) { 1012 Offset = 0; 1013 isAdd = false; 1014 } else if (Offset < 0) { 1015 Offset *= -1; 1016 isAdd = false; 1017 } 1018 Imm12 = Offset; 1019 } 1020 uint32_t Binary = Imm12 & 0xfff; 1021 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 1022 if (isAdd) 1023 Binary |= (1 << 12); 1024 Binary |= (Reg << 13); 1025 return Binary; 1026 } 1027 1028 template<unsigned Bits, unsigned Shift> 1029 uint32_t ARMMCCodeEmitter:: 1030 getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx, 1031 SmallVectorImpl<MCFixup> &Fixups, 1032 const MCSubtargetInfo &STI) const { 1033 // FIXME: The immediate operand should have already been encoded like this 1034 // before ever getting here. The encoder method should just need to combine 1035 // the MI operands for the register and the offset into a single 1036 // representation for the complex operand in the .td file. This isn't just 1037 // style, unfortunately. As-is, we can't represent the distinct encoding 1038 // for #-0. 1039 1040 // {Bits} = (U)nsigned (add == '1', sub == '0') 1041 // {(Bits-1)-0} = immediate 1042 int32_t Imm = MI.getOperand(OpIdx).getImm(); 1043 bool isAdd = Imm >= 0; 1044 1045 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 1046 if (Imm < 0) 1047 Imm = -(uint32_t)Imm; 1048 1049 Imm >>= Shift; 1050 1051 uint32_t Binary = Imm & ((1U << Bits) - 1); 1052 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 1053 if (isAdd) 1054 Binary |= (1U << Bits); 1055 return Binary; 1056 } 1057 1058 /// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg' 1059 /// operand. 1060 uint32_t ARMMCCodeEmitter:: 1061 getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx, 1062 SmallVectorImpl<MCFixup> &Fixups, 1063 const MCSubtargetInfo &STI) const { 1064 // {6-3} Rn 1065 // {2-0} Qm 1066 const MCOperand &M0 = MI.getOperand(OpIdx); 1067 const MCOperand &M1 = MI.getOperand(OpIdx + 1); 1068 1069 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(M0.getReg()); 1070 unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M1.getReg()); 1071 1072 assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits"); 1073 1074 return (Rn << 3) | Qm; 1075 } 1076 1077 /// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg' 1078 /// operand. 1079 template<int shift> 1080 uint32_t ARMMCCodeEmitter:: 1081 getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx, 1082 SmallVectorImpl<MCFixup> &Fixups, 1083 const MCSubtargetInfo &STI) const { 1084 // {10-8} Qm 1085 // {7-0} Imm 1086 const MCOperand &M0 = MI.getOperand(OpIdx); 1087 const MCOperand &M1 = MI.getOperand(OpIdx + 1); 1088 1089 unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M0.getReg()); 1090 int32_t Imm = M1.getImm(); 1091 1092 bool isAdd = Imm >= 0; 1093 1094 Imm >>= shift; 1095 1096 if (!isAdd) 1097 Imm = -(uint32_t)Imm; 1098 1099 Imm &= 0x7f; 1100 1101 if (isAdd) 1102 Imm |= 0x80; 1103 1104 assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits"); 1105 1106 return (Qm << 8) | Imm; 1107 } 1108 1109 /// getT2AddrModeImm8s4OpValue - Return encoding info for 1110 /// 'reg +/- imm8<<2' operand. 1111 uint32_t ARMMCCodeEmitter:: 1112 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, 1113 SmallVectorImpl<MCFixup> &Fixups, 1114 const MCSubtargetInfo &STI) const { 1115 // {12-9} = reg 1116 // {8} = (U)nsigned (add == '1', sub == '0') 1117 // {7-0} = imm8 1118 unsigned Reg, Imm8; 1119 bool isAdd = true; 1120 // If The first operand isn't a register, we have a label reference. 1121 const MCOperand &MO = MI.getOperand(OpIdx); 1122 if (!MO.isReg()) { 1123 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 1124 Imm8 = 0; 1125 isAdd = false ; // 'U' bit is set as part of the fixup. 1126 1127 assert(MO.isExpr() && "Unexpected machine operand type!"); 1128 const MCExpr *Expr = MO.getExpr(); 1129 MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10); 1130 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 1131 1132 ++MCNumCPRelocations; 1133 } else 1134 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI); 1135 1136 // FIXME: The immediate operand should have already been encoded like this 1137 // before ever getting here. The encoder method should just need to combine 1138 // the MI operands for the register and the offset into a single 1139 // representation for the complex operand in the .td file. This isn't just 1140 // style, unfortunately. As-is, we can't represent the distinct encoding 1141 // for #-0. 1142 assert(((Imm8 & 0x3) == 0) && "Not a valid immediate!"); 1143 uint32_t Binary = (Imm8 >> 2) & 0xff; 1144 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 1145 if (isAdd) 1146 Binary |= (1 << 8); 1147 Binary |= (Reg << 9); 1148 return Binary; 1149 } 1150 1151 /// getT2AddrModeImm7s4OpValue - Return encoding info for 1152 /// 'reg +/- imm7<<2' operand. 1153 uint32_t 1154 ARMMCCodeEmitter::getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx, 1155 SmallVectorImpl<MCFixup> &Fixups, 1156 const MCSubtargetInfo &STI) const { 1157 // {11-8} = reg 1158 // {7} = (A)dd (add == '1', sub == '0') 1159 // {6-0} = imm7 1160 unsigned Reg, Imm7; 1161 // If The first operand isn't a register, we have a label reference. 1162 bool isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm7, Fixups, STI); 1163 1164 // FIXME: The immediate operand should have already been encoded like this 1165 // before ever getting here. The encoder method should just need to combine 1166 // the MI operands for the register and the offset into a single 1167 // representation for the complex operand in the .td file. This isn't just 1168 // style, unfortunately. As-is, we can't represent the distinct encoding 1169 // for #-0. 1170 uint32_t Binary = (Imm7 >> 2) & 0xff; 1171 // Immediate is always encoded as positive. The 'A' bit controls add vs sub. 1172 if (isAdd) 1173 Binary |= (1 << 7); 1174 Binary |= (Reg << 8); 1175 return Binary; 1176 } 1177 1178 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 1179 /// 'reg + imm8<<2' operand. 1180 uint32_t ARMMCCodeEmitter:: 1181 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, 1182 SmallVectorImpl<MCFixup> &Fixups, 1183 const MCSubtargetInfo &STI) const { 1184 // {11-8} = reg 1185 // {7-0} = imm8 1186 const MCOperand &MO = MI.getOperand(OpIdx); 1187 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1188 unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1189 unsigned Imm8 = MO1.getImm(); 1190 return (Reg << 8) | Imm8; 1191 } 1192 1193 uint32_t ARMMCCodeEmitter::getHiLoImmOpValue(const MCInst &MI, unsigned OpIdx, 1194 SmallVectorImpl<MCFixup> &Fixups, 1195 const MCSubtargetInfo &STI) const { 1196 // {20-16} = imm{15-12} 1197 // {11-0} = imm{11-0} 1198 const MCOperand &MO = MI.getOperand(OpIdx); 1199 if (MO.isImm()) 1200 // Hi / lo bits already extracted during earlier passes. 1201 return static_cast<unsigned>(MO.getImm()); 1202 1203 // Handle :upper16:, :lower16:, :upper8_15:, :upper0_7:, :lower8_15: 1204 // :lower0_7: assembly prefixes. 1205 const MCExpr *E = MO.getExpr(); 1206 MCFixupKind Kind; 1207 if (E->getKind() == MCExpr::Target) { 1208 const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E); 1209 E = ARM16Expr->getSubExpr(); 1210 1211 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(E)) { 1212 const int64_t Value = MCE->getValue(); 1213 if (Value > UINT32_MAX) 1214 report_fatal_error("constant value truncated (limited to 32-bit)"); 1215 1216 switch (ARM16Expr->getKind()) { 1217 case ARMMCExpr::VK_ARM_HI16: 1218 return (int32_t(Value) & 0xffff0000) >> 16; 1219 case ARMMCExpr::VK_ARM_LO16: 1220 return (int32_t(Value) & 0x0000ffff); 1221 1222 case ARMMCExpr::VK_ARM_HI_8_15: 1223 return (int32_t(Value) & 0xff000000) >> 24; 1224 case ARMMCExpr::VK_ARM_HI_0_7: 1225 return (int32_t(Value) & 0x00ff0000) >> 16; 1226 case ARMMCExpr::VK_ARM_LO_8_15: 1227 return (int32_t(Value) & 0x0000ff00) >> 8; 1228 case ARMMCExpr::VK_ARM_LO_0_7: 1229 return (int32_t(Value) & 0x000000ff); 1230 1231 default: llvm_unreachable("Unsupported ARMFixup"); 1232 } 1233 } 1234 1235 switch (ARM16Expr->getKind()) { 1236 default: llvm_unreachable("Unsupported ARMFixup"); 1237 case ARMMCExpr::VK_ARM_HI16: 1238 Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movt_hi16 1239 : ARM::fixup_arm_movt_hi16); 1240 break; 1241 case ARMMCExpr::VK_ARM_LO16: 1242 Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movw_lo16 1243 : ARM::fixup_arm_movw_lo16); 1244 break; 1245 case ARMMCExpr::VK_ARM_HI_8_15: 1246 if (!isThumb(STI)) 1247 llvm_unreachable(":upper_8_15: not supported in Arm state"); 1248 Kind = MCFixupKind(ARM::fixup_arm_thumb_upper_8_15); 1249 break; 1250 case ARMMCExpr::VK_ARM_HI_0_7: 1251 if (!isThumb(STI)) 1252 llvm_unreachable(":upper_0_7: not supported in Arm state"); 1253 Kind = MCFixupKind(ARM::fixup_arm_thumb_upper_0_7); 1254 break; 1255 case ARMMCExpr::VK_ARM_LO_8_15: 1256 if (!isThumb(STI)) 1257 llvm_unreachable(":lower_8_15: not supported in Arm state"); 1258 Kind = MCFixupKind(ARM::fixup_arm_thumb_lower_8_15); 1259 break; 1260 case ARMMCExpr::VK_ARM_LO_0_7: 1261 if (!isThumb(STI)) 1262 llvm_unreachable(":lower_0_7: not supported in Arm state"); 1263 Kind = MCFixupKind(ARM::fixup_arm_thumb_lower_0_7); 1264 break; 1265 } 1266 1267 Fixups.push_back(MCFixup::create(0, E, Kind, MI.getLoc())); 1268 return 0; 1269 } 1270 // If the expression doesn't have :upper16:, :lower16: on it, it's just a 1271 // plain immediate expression, previously those evaluated to the lower 16 bits 1272 // of the expression regardless of whether we have a movt or a movw, but that 1273 // led to misleadingly results. This is disallowed in the AsmParser in 1274 // validateInstruction() so this should never happen. The same holds for 1275 // thumb1 :upper8_15:, :upper0_7:, lower8_15: or :lower0_7: with movs or adds. 1276 llvm_unreachable("expression without :upper16:, :lower16:, :upper8_15:," 1277 ":upper0_7:, lower8_15: or :lower0_7:"); 1278 } 1279 1280 uint32_t ARMMCCodeEmitter:: 1281 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, 1282 SmallVectorImpl<MCFixup> &Fixups, 1283 const MCSubtargetInfo &STI) const { 1284 const MCOperand &MO = MI.getOperand(OpIdx); 1285 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1286 const MCOperand &MO2 = MI.getOperand(OpIdx+2); 1287 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1288 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 1289 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()); 1290 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; 1291 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); 1292 unsigned SBits = getShiftOp(ShOp); 1293 1294 // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift 1295 // amount. However, it would be an easy mistake to make so check here. 1296 assert((ShImm & ~0x1f) == 0 && "Out of range shift amount"); 1297 1298 // {16-13} = Rn 1299 // {12} = isAdd 1300 // {11-0} = shifter 1301 // {3-0} = Rm 1302 // {4} = 0 1303 // {6-5} = type 1304 // {11-7} = imm 1305 uint32_t Binary = Rm; 1306 Binary |= Rn << 13; 1307 Binary |= SBits << 5; 1308 Binary |= ShImm << 7; 1309 if (isAdd) 1310 Binary |= 1 << 12; 1311 return Binary; 1312 } 1313 1314 uint32_t ARMMCCodeEmitter:: 1315 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, 1316 SmallVectorImpl<MCFixup> &Fixups, 1317 const MCSubtargetInfo &STI) const { 1318 // {13} 1 == imm12, 0 == Rm 1319 // {12} isAdd 1320 // {11-0} imm12/Rm 1321 const MCOperand &MO = MI.getOperand(OpIdx); 1322 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1323 unsigned Imm = MO1.getImm(); 1324 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add; 1325 bool isReg = MO.getReg() != 0; 1326 uint32_t Binary = ARM_AM::getAM2Offset(Imm); 1327 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12 1328 if (isReg) { 1329 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); 1330 Binary <<= 7; // Shift amount is bits [11:7] 1331 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5] 1332 Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0] 1333 } 1334 return Binary | (isAdd << 12) | (isReg << 13); 1335 } 1336 1337 uint32_t ARMMCCodeEmitter:: 1338 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, 1339 SmallVectorImpl<MCFixup> &Fixups, 1340 const MCSubtargetInfo &STI) const { 1341 // {4} isAdd 1342 // {3-0} Rm 1343 const MCOperand &MO = MI.getOperand(OpIdx); 1344 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1345 bool isAdd = MO1.getImm() != 0; 1346 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4); 1347 } 1348 1349 uint32_t ARMMCCodeEmitter:: 1350 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, 1351 SmallVectorImpl<MCFixup> &Fixups, 1352 const MCSubtargetInfo &STI) const { 1353 // {9} 1 == imm8, 0 == Rm 1354 // {8} isAdd 1355 // {7-4} imm7_4/zero 1356 // {3-0} imm3_0/Rm 1357 const MCOperand &MO = MI.getOperand(OpIdx); 1358 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1359 unsigned Imm = MO1.getImm(); 1360 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; 1361 bool isImm = MO.getReg() == 0; 1362 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm); 1363 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8 1364 if (!isImm) 1365 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1366 return Imm8 | (isAdd << 8) | (isImm << 9); 1367 } 1368 1369 uint32_t ARMMCCodeEmitter:: 1370 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, 1371 SmallVectorImpl<MCFixup> &Fixups, 1372 const MCSubtargetInfo &STI) const { 1373 // {13} 1 == imm8, 0 == Rm 1374 // {12-9} Rn 1375 // {8} isAdd 1376 // {7-4} imm7_4/zero 1377 // {3-0} imm3_0/Rm 1378 const MCOperand &MO = MI.getOperand(OpIdx); 1379 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1380 const MCOperand &MO2 = MI.getOperand(OpIdx+2); 1381 1382 // If The first operand isn't a register, we have a label reference. 1383 if (!MO.isReg()) { 1384 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 1385 1386 assert(MO.isExpr() && "Unexpected machine operand type!"); 1387 const MCExpr *Expr = MO.getExpr(); 1388 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled); 1389 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 1390 1391 ++MCNumCPRelocations; 1392 return (Rn << 9) | (1 << 13); 1393 } 1394 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1395 unsigned Imm = MO2.getImm(); 1396 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; 1397 bool isImm = MO1.getReg() == 0; 1398 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm); 1399 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8 1400 if (!isImm) 1401 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 1402 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13); 1403 } 1404 1405 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands. 1406 uint32_t ARMMCCodeEmitter:: 1407 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, 1408 SmallVectorImpl<MCFixup> &Fixups, 1409 const MCSubtargetInfo &STI) const { 1410 // [SP, #imm] 1411 // {7-0} = imm8 1412 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1413 assert(MI.getOperand(OpIdx).getReg() == ARM::SP && 1414 "Unexpected base register!"); 1415 1416 // The immediate is already shifted for the implicit zeroes, so no change 1417 // here. 1418 return MO1.getImm() & 0xff; 1419 } 1420 1421 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands. 1422 uint32_t ARMMCCodeEmitter:: 1423 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, 1424 SmallVectorImpl<MCFixup> &Fixups, 1425 const MCSubtargetInfo &STI) const { 1426 // [Rn, #imm] 1427 // {7-3} = imm5 1428 // {2-0} = Rn 1429 const MCOperand &MO = MI.getOperand(OpIdx); 1430 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1431 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1432 unsigned Imm5 = MO1.getImm(); 1433 return ((Imm5 & 0x1f) << 3) | Rn; 1434 } 1435 1436 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. 1437 uint32_t ARMMCCodeEmitter:: 1438 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, 1439 SmallVectorImpl<MCFixup> &Fixups, 1440 const MCSubtargetInfo &STI) const { 1441 const MCOperand MO = MI.getOperand(OpIdx); 1442 if (MO.isExpr()) 1443 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups, STI); 1444 return (MO.getImm() >> 2); 1445 } 1446 1447 /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand. 1448 uint32_t ARMMCCodeEmitter:: 1449 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, 1450 SmallVectorImpl<MCFixup> &Fixups, 1451 const MCSubtargetInfo &STI) const { 1452 // {12-9} = reg 1453 // {8} = (U)nsigned (add == '1', sub == '0') 1454 // {7-0} = imm8 1455 unsigned Reg, Imm8; 1456 bool isAdd; 1457 // If The first operand isn't a register, we have a label reference. 1458 const MCOperand &MO = MI.getOperand(OpIdx); 1459 if (!MO.isReg()) { 1460 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 1461 Imm8 = 0; 1462 isAdd = false; // 'U' bit is handled as part of the fixup. 1463 1464 assert(MO.isExpr() && "Unexpected machine operand type!"); 1465 const MCExpr *Expr = MO.getExpr(); 1466 MCFixupKind Kind; 1467 if (isThumb2(STI)) 1468 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10); 1469 else 1470 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10); 1471 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 1472 1473 ++MCNumCPRelocations; 1474 } else { 1475 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI); 1476 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add; 1477 } 1478 1479 uint32_t Binary = ARM_AM::getAM5Offset(Imm8); 1480 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 1481 if (isAdd) 1482 Binary |= (1 << 8); 1483 Binary |= (Reg << 9); 1484 return Binary; 1485 } 1486 1487 /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand. 1488 uint32_t ARMMCCodeEmitter:: 1489 getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx, 1490 SmallVectorImpl<MCFixup> &Fixups, 1491 const MCSubtargetInfo &STI) const { 1492 // {12-9} = reg 1493 // {8} = (U)nsigned (add == '1', sub == '0') 1494 // {7-0} = imm8 1495 unsigned Reg, Imm8; 1496 bool isAdd; 1497 // If The first operand isn't a register, we have a label reference. 1498 const MCOperand &MO = MI.getOperand(OpIdx); 1499 if (!MO.isReg()) { 1500 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 1501 Imm8 = 0; 1502 isAdd = false; // 'U' bit is handled as part of the fixup. 1503 1504 assert(MO.isExpr() && "Unexpected machine operand type!"); 1505 const MCExpr *Expr = MO.getExpr(); 1506 MCFixupKind Kind; 1507 if (isThumb2(STI)) 1508 Kind = MCFixupKind(ARM::fixup_t2_pcrel_9); 1509 else 1510 Kind = MCFixupKind(ARM::fixup_arm_pcrel_9); 1511 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc())); 1512 1513 ++MCNumCPRelocations; 1514 } else { 1515 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI); 1516 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add; 1517 } 1518 1519 uint32_t Binary = ARM_AM::getAM5Offset(Imm8); 1520 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 1521 if (isAdd) 1522 Binary |= (1 << 8); 1523 Binary |= (Reg << 9); 1524 return Binary; 1525 } 1526 1527 unsigned ARMMCCodeEmitter:: 1528 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx, 1529 SmallVectorImpl<MCFixup> &Fixups, 1530 const MCSubtargetInfo &STI) const { 1531 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be 1532 // shifted. The second is Rs, the amount to shift by, and the third specifies 1533 // the type of the shift. 1534 // 1535 // {3-0} = Rm. 1536 // {4} = 1 1537 // {6-5} = type 1538 // {11-8} = Rs 1539 // {7} = 0 1540 1541 const MCOperand &MO = MI.getOperand(OpIdx); 1542 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1543 const MCOperand &MO2 = MI.getOperand(OpIdx + 2); 1544 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); 1545 1546 // Encode Rm. 1547 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1548 1549 // Encode the shift opcode. 1550 unsigned SBits = 0; 1551 unsigned Rs = MO1.getReg(); 1552 if (Rs) { 1553 // Set shift operand (bit[7:4]). 1554 // LSL - 0001 1555 // LSR - 0011 1556 // ASR - 0101 1557 // ROR - 0111 1558 switch (SOpc) { 1559 default: llvm_unreachable("Unknown shift opc!"); 1560 case ARM_AM::lsl: SBits = 0x1; break; 1561 case ARM_AM::lsr: SBits = 0x3; break; 1562 case ARM_AM::asr: SBits = 0x5; break; 1563 case ARM_AM::ror: SBits = 0x7; break; 1564 } 1565 } 1566 1567 Binary |= SBits << 4; 1568 1569 // Encode the shift operation Rs. 1570 // Encode Rs bit[11:8]. 1571 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); 1572 return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift); 1573 } 1574 1575 unsigned ARMMCCodeEmitter:: 1576 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx, 1577 SmallVectorImpl<MCFixup> &Fixups, 1578 const MCSubtargetInfo &STI) const { 1579 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be 1580 // shifted. The second is the amount to shift by. 1581 // 1582 // {3-0} = Rm. 1583 // {4} = 0 1584 // {6-5} = type 1585 // {11-7} = imm 1586 1587 const MCOperand &MO = MI.getOperand(OpIdx); 1588 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1589 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); 1590 1591 // Encode Rm. 1592 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1593 1594 // Encode the shift opcode. 1595 unsigned SBits = 0; 1596 1597 // Set shift operand (bit[6:4]). 1598 // LSL - 000 1599 // LSR - 010 1600 // ASR - 100 1601 // ROR - 110 1602 // RRX - 110 and bit[11:8] clear. 1603 switch (SOpc) { 1604 default: llvm_unreachable("Unknown shift opc!"); 1605 case ARM_AM::lsl: SBits = 0x0; break; 1606 case ARM_AM::lsr: SBits = 0x2; break; 1607 case ARM_AM::asr: SBits = 0x4; break; 1608 case ARM_AM::ror: SBits = 0x6; break; 1609 case ARM_AM::rrx: 1610 Binary |= 0x60; 1611 return Binary; 1612 } 1613 1614 // Encode shift_imm bit[11:7]. 1615 Binary |= SBits << 4; 1616 unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm()); 1617 assert(Offset < 32 && "Offset must be in range 0-31!"); 1618 return Binary | (Offset << 7); 1619 } 1620 1621 1622 unsigned ARMMCCodeEmitter:: 1623 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, 1624 SmallVectorImpl<MCFixup> &Fixups, 1625 const MCSubtargetInfo &STI) const { 1626 const MCOperand &MO1 = MI.getOperand(OpNum); 1627 const MCOperand &MO2 = MI.getOperand(OpNum+1); 1628 const MCOperand &MO3 = MI.getOperand(OpNum+2); 1629 1630 // Encoded as [Rn, Rm, imm]. 1631 // FIXME: Needs fixup support. 1632 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 1633 Value <<= 4; 1634 Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); 1635 Value <<= 2; 1636 Value |= MO3.getImm(); 1637 1638 return Value; 1639 } 1640 1641 template<unsigned Bits, unsigned Shift> 1642 unsigned ARMMCCodeEmitter:: 1643 getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum, 1644 SmallVectorImpl<MCFixup> &Fixups, 1645 const MCSubtargetInfo &STI) const { 1646 const MCOperand &MO1 = MI.getOperand(OpNum); 1647 const MCOperand &MO2 = MI.getOperand(OpNum+1); 1648 1649 // FIXME: Needs fixup support. 1650 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 1651 1652 // If the immediate is B bits long, we need B+1 bits in order 1653 // to represent the (inverse of the) sign bit. 1654 Value <<= (Bits + 1); 1655 int32_t tmp = (int32_t)MO2.getImm(); 1656 if (tmp == INT32_MIN) { // represents subtracting zero rather than adding it 1657 tmp = 0; 1658 } else if (tmp < 0) { 1659 tmp = abs(tmp); 1660 } else { 1661 Value |= (1U << Bits); // Set the ADD bit 1662 } 1663 Value |= (tmp >> Shift) & ((1U << Bits) - 1); 1664 return Value; 1665 } 1666 1667 unsigned ARMMCCodeEmitter:: 1668 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, 1669 SmallVectorImpl<MCFixup> &Fixups, 1670 const MCSubtargetInfo &STI) const { 1671 const MCOperand &MO1 = MI.getOperand(OpNum); 1672 1673 // FIXME: Needs fixup support. 1674 unsigned Value = 0; 1675 auto tmp = static_cast<uint32_t>(MO1.getImm()); 1676 if (static_cast<int32_t>(tmp) < 0) 1677 tmp = -tmp; 1678 else 1679 Value |= 256; // Set the ADD bit 1680 Value |= tmp & 255; 1681 return Value; 1682 } 1683 1684 unsigned ARMMCCodeEmitter:: 1685 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx, 1686 SmallVectorImpl<MCFixup> &Fixups, 1687 const MCSubtargetInfo &STI) const { 1688 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be 1689 // shifted. The second is the amount to shift by. 1690 // 1691 // {3-0} = Rm. 1692 // {4} = 0 1693 // {6-5} = type 1694 // {11-7} = imm 1695 1696 const MCOperand &MO = MI.getOperand(OpIdx); 1697 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1698 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); 1699 1700 // Encode Rm. 1701 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1702 1703 // Encode the shift opcode. 1704 unsigned SBits = 0; 1705 // Set shift operand (bit[6:4]). 1706 // LSL - 000 1707 // LSR - 010 1708 // ASR - 100 1709 // ROR - 110 1710 switch (SOpc) { 1711 default: llvm_unreachable("Unknown shift opc!"); 1712 case ARM_AM::lsl: SBits = 0x0; break; 1713 case ARM_AM::lsr: SBits = 0x2; break; 1714 case ARM_AM::asr: SBits = 0x4; break; 1715 case ARM_AM::rrx: [[fallthrough]]; 1716 case ARM_AM::ror: SBits = 0x6; break; 1717 } 1718 1719 Binary |= SBits << 4; 1720 if (SOpc == ARM_AM::rrx) 1721 return Binary; 1722 1723 // Encode shift_imm bit[11:7]. 1724 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7; 1725 } 1726 1727 unsigned ARMMCCodeEmitter:: 1728 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, 1729 SmallVectorImpl<MCFixup> &Fixups, 1730 const MCSubtargetInfo &STI) const { 1731 // 10 bits. lower 5 bits are the lsb of the mask, high five bits are the 1732 // msb of the mask. 1733 const MCOperand &MO = MI.getOperand(Op); 1734 uint32_t v = ~MO.getImm(); 1735 uint32_t lsb = llvm::countr_zero(v); 1736 uint32_t msb = llvm::Log2_32(v); 1737 assert(v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!"); 1738 return lsb | (msb << 5); 1739 } 1740 1741 unsigned ARMMCCodeEmitter:: 1742 getRegisterListOpValue(const MCInst &MI, unsigned Op, 1743 SmallVectorImpl<MCFixup> &Fixups, 1744 const MCSubtargetInfo &STI) const { 1745 // VLDM/VSTM/VSCCLRM: 1746 // {12-8} = Vd 1747 // {7-0} = Number of registers 1748 // 1749 // LDM/STM: 1750 // {15-0} = Bitfield of GPRs. 1751 unsigned Reg = MI.getOperand(Op).getReg(); 1752 bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg); 1753 bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg); 1754 1755 unsigned Binary = 0; 1756 1757 if (SPRRegs || DPRRegs) { 1758 // VLDM/VSTM/VSCCLRM 1759 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg); 1760 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff; 1761 Binary |= (RegNo & 0x1f) << 8; 1762 1763 // Ignore VPR 1764 if (MI.getOpcode() == ARM::VSCCLRMD || MI.getOpcode() == ARM::VSCCLRMS) 1765 --NumRegs; 1766 if (SPRRegs) 1767 Binary |= NumRegs; 1768 else 1769 Binary |= NumRegs * 2; 1770 } else { 1771 const MCRegisterInfo &MRI = *CTX.getRegisterInfo(); 1772 assert(is_sorted(drop_begin(MI, Op), 1773 [&](const MCOperand &LHS, const MCOperand &RHS) { 1774 return MRI.getEncodingValue(LHS.getReg()) < 1775 MRI.getEncodingValue(RHS.getReg()); 1776 })); 1777 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) { 1778 unsigned RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg()); 1779 Binary |= 1 << RegNo; 1780 } 1781 } 1782 1783 return Binary; 1784 } 1785 1786 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along 1787 /// with the alignment operand. 1788 unsigned ARMMCCodeEmitter:: 1789 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, 1790 SmallVectorImpl<MCFixup> &Fixups, 1791 const MCSubtargetInfo &STI) const { 1792 const MCOperand &Reg = MI.getOperand(Op); 1793 const MCOperand &Imm = MI.getOperand(Op + 1); 1794 1795 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg()); 1796 unsigned Align = 0; 1797 1798 switch (Imm.getImm()) { 1799 default: break; 1800 case 2: 1801 case 4: 1802 case 8: Align = 0x01; break; 1803 case 16: Align = 0x02; break; 1804 case 32: Align = 0x03; break; 1805 } 1806 1807 return RegNo | (Align << 4); 1808 } 1809 1810 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number 1811 /// along with the alignment operand for use in VST1 and VLD1 with size 32. 1812 unsigned ARMMCCodeEmitter:: 1813 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, 1814 SmallVectorImpl<MCFixup> &Fixups, 1815 const MCSubtargetInfo &STI) const { 1816 const MCOperand &Reg = MI.getOperand(Op); 1817 const MCOperand &Imm = MI.getOperand(Op + 1); 1818 1819 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg()); 1820 unsigned Align = 0; 1821 1822 switch (Imm.getImm()) { 1823 default: break; 1824 case 8: 1825 case 16: 1826 case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes. 1827 case 2: Align = 0x00; break; 1828 case 4: Align = 0x03; break; 1829 } 1830 1831 return RegNo | (Align << 4); 1832 } 1833 1834 1835 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and 1836 /// alignment operand for use in VLD-dup instructions. This is the same as 1837 /// getAddrMode6AddressOpValue except for the alignment encoding, which is 1838 /// different for VLD4-dup. 1839 unsigned ARMMCCodeEmitter:: 1840 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, 1841 SmallVectorImpl<MCFixup> &Fixups, 1842 const MCSubtargetInfo &STI) const { 1843 const MCOperand &Reg = MI.getOperand(Op); 1844 const MCOperand &Imm = MI.getOperand(Op + 1); 1845 1846 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg()); 1847 unsigned Align = 0; 1848 1849 switch (Imm.getImm()) { 1850 default: break; 1851 case 2: 1852 case 4: 1853 case 8: Align = 0x01; break; 1854 case 16: Align = 0x03; break; 1855 } 1856 1857 return RegNo | (Align << 4); 1858 } 1859 1860 unsigned ARMMCCodeEmitter:: 1861 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, 1862 SmallVectorImpl<MCFixup> &Fixups, 1863 const MCSubtargetInfo &STI) const { 1864 const MCOperand &MO = MI.getOperand(Op); 1865 if (MO.getReg() == 0) return 0x0D; 1866 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 1867 } 1868 1869 unsigned ARMMCCodeEmitter:: 1870 getShiftRight8Imm(const MCInst &MI, unsigned Op, 1871 SmallVectorImpl<MCFixup> &Fixups, 1872 const MCSubtargetInfo &STI) const { 1873 return 8 - MI.getOperand(Op).getImm(); 1874 } 1875 1876 unsigned ARMMCCodeEmitter:: 1877 getShiftRight16Imm(const MCInst &MI, unsigned Op, 1878 SmallVectorImpl<MCFixup> &Fixups, 1879 const MCSubtargetInfo &STI) const { 1880 return 16 - MI.getOperand(Op).getImm(); 1881 } 1882 1883 unsigned ARMMCCodeEmitter:: 1884 getShiftRight32Imm(const MCInst &MI, unsigned Op, 1885 SmallVectorImpl<MCFixup> &Fixups, 1886 const MCSubtargetInfo &STI) const { 1887 return 32 - MI.getOperand(Op).getImm(); 1888 } 1889 1890 unsigned ARMMCCodeEmitter:: 1891 getShiftRight64Imm(const MCInst &MI, unsigned Op, 1892 SmallVectorImpl<MCFixup> &Fixups, 1893 const MCSubtargetInfo &STI) const { 1894 return 64 - MI.getOperand(Op).getImm(); 1895 } 1896 1897 void ARMMCCodeEmitter:: 1898 encodeInstruction(const MCInst &MI, raw_ostream &OS, 1899 SmallVectorImpl<MCFixup> &Fixups, 1900 const MCSubtargetInfo &STI) const { 1901 // Pseudo instructions don't get encoded. 1902 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 1903 uint64_t TSFlags = Desc.TSFlags; 1904 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo) 1905 return; 1906 1907 int Size; 1908 if (Desc.getSize() == 2 || Desc.getSize() == 4) 1909 Size = Desc.getSize(); 1910 else 1911 llvm_unreachable("Unexpected instruction size!"); 1912 1913 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI); 1914 // Thumb 32-bit wide instructions need to emit the high order halfword 1915 // first. 1916 if (isThumb(STI) && Size == 4) { 1917 EmitConstant(Binary >> 16, 2, OS); 1918 EmitConstant(Binary & 0xffff, 2, OS); 1919 } else 1920 EmitConstant(Binary, Size, OS); 1921 ++MCNumEmitted; // Keep track of the # of mi's emitted. 1922 } 1923 1924 template <bool isNeg, ARM::Fixups fixup> 1925 uint32_t 1926 ARMMCCodeEmitter::getBFTargetOpValue(const MCInst &MI, unsigned OpIdx, 1927 SmallVectorImpl<MCFixup> &Fixups, 1928 const MCSubtargetInfo &STI) const { 1929 const MCOperand MO = MI.getOperand(OpIdx); 1930 if (MO.isExpr()) 1931 return ::getBranchTargetOpValue(MI, OpIdx, fixup, Fixups, STI); 1932 return isNeg ? -(MO.getImm() >> 1) : (MO.getImm() >> 1); 1933 } 1934 1935 uint32_t 1936 ARMMCCodeEmitter::getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx, 1937 SmallVectorImpl<MCFixup> &Fixups, 1938 const MCSubtargetInfo &STI) const { 1939 const MCOperand MO = MI.getOperand(OpIdx); 1940 const MCOperand BranchMO = MI.getOperand(0); 1941 1942 if (MO.isExpr()) { 1943 assert(BranchMO.isExpr()); 1944 const MCExpr *DiffExpr = MCBinaryExpr::createSub( 1945 MO.getExpr(), BranchMO.getExpr(), CTX); 1946 MCFixupKind Kind = MCFixupKind(ARM::fixup_bfcsel_else_target); 1947 Fixups.push_back(llvm::MCFixup::create(0, DiffExpr, Kind, MI.getLoc())); 1948 return 0; 1949 } 1950 1951 assert(MO.isImm() && BranchMO.isImm()); 1952 int Diff = MO.getImm() - BranchMO.getImm(); 1953 assert(Diff == 4 || Diff == 2); 1954 1955 return Diff == 4; 1956 } 1957 1958 uint32_t ARMMCCodeEmitter::getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx, 1959 SmallVectorImpl<MCFixup> &Fixups, 1960 const MCSubtargetInfo &STI)const { 1961 const MCOperand MO = MI.getOperand(OpIdx); 1962 assert(MO.isImm() && "Unexpected operand type!"); 1963 1964 int Value = MO.getImm(); 1965 int Imm = 0; 1966 1967 // VPT Masks are actually encoded as a series of invert/don't invert bits, 1968 // rather than true/false bits. 1969 unsigned PrevBit = 0; 1970 for (int i = 3; i >= 0; --i) { 1971 unsigned Bit = (Value >> i) & 1; 1972 1973 // Check if we are at the end of the mask. 1974 if ((Value & ~(~0U << i)) == 0) { 1975 Imm |= (1 << i); 1976 break; 1977 } 1978 1979 // Convert the bit in the mask based on the previous bit. 1980 if (Bit != PrevBit) 1981 Imm |= (1 << i); 1982 1983 PrevBit = Bit; 1984 } 1985 1986 return Imm; 1987 } 1988 1989 uint32_t ARMMCCodeEmitter::getRestrictedCondCodeOpValue( 1990 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, 1991 const MCSubtargetInfo &STI) const { 1992 1993 const MCOperand MO = MI.getOperand(OpIdx); 1994 assert(MO.isImm() && "Unexpected operand type!"); 1995 1996 switch (MO.getImm()) { 1997 default: 1998 assert(0 && "Unexpected Condition!"); 1999 return 0; 2000 case ARMCC::HS: 2001 case ARMCC::EQ: 2002 return 0; 2003 case ARMCC::HI: 2004 case ARMCC::NE: 2005 return 1; 2006 case ARMCC::GE: 2007 return 4; 2008 case ARMCC::LT: 2009 return 5; 2010 case ARMCC::GT: 2011 return 6; 2012 case ARMCC::LE: 2013 return 7; 2014 } 2015 } 2016 2017 uint32_t ARMMCCodeEmitter:: 2018 getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx, 2019 SmallVectorImpl<MCFixup> &Fixups, 2020 const MCSubtargetInfo &STI) const { 2021 const MCOperand &MO = MI.getOperand(OpIdx); 2022 assert(MO.isImm() && "Unexpected operand type!"); 2023 return llvm::countr_zero((uint64_t)MO.getImm()); 2024 } 2025 2026 template <unsigned start> 2027 uint32_t ARMMCCodeEmitter:: 2028 getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx, 2029 SmallVectorImpl<MCFixup> &Fixups, 2030 const MCSubtargetInfo &STI) const { 2031 const MCOperand MO = MI.getOperand(OpIdx); 2032 assert(MO.isImm() && "Unexpected operand type!"); 2033 2034 int Value = MO.getImm(); 2035 return Value - start; 2036 } 2037 2038 #include "ARMGenMCCodeEmitter.inc" 2039 2040 MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII, 2041 MCContext &Ctx) { 2042 return new ARMMCCodeEmitter(MCII, Ctx, true); 2043 } 2044 2045 MCCodeEmitter *llvm::createARMBEMCCodeEmitter(const MCInstrInfo &MCII, 2046 MCContext &Ctx) { 2047 return new ARMMCCodeEmitter(MCII, Ctx, false); 2048 } 2049