1*0b57cec5SDimitry Andric //===- ARMRegisterBankInfo ---------------------------------------*- C++ -*-==// 2*0b57cec5SDimitry Andric // 3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric // 7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric /// \file 9*0b57cec5SDimitry Andric /// This file declares the targeting of the RegisterBankInfo class for ARM. 10*0b57cec5SDimitry Andric /// \todo This should be generated by TableGen. 11*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 12*0b57cec5SDimitry Andric 13*0b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_ARM_ARMREGISTERBANKINFO_H 14*0b57cec5SDimitry Andric #define LLVM_LIB_TARGET_ARM_ARMREGISTERBANKINFO_H 15*0b57cec5SDimitry Andric 16*0b57cec5SDimitry Andric #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" 17*0b57cec5SDimitry Andric 18*0b57cec5SDimitry Andric #define GET_REGBANK_DECLARATIONS 19*0b57cec5SDimitry Andric #include "ARMGenRegisterBank.inc" 20*0b57cec5SDimitry Andric 21*0b57cec5SDimitry Andric namespace llvm { 22*0b57cec5SDimitry Andric 23*0b57cec5SDimitry Andric class TargetRegisterInfo; 24*0b57cec5SDimitry Andric 25*0b57cec5SDimitry Andric class ARMGenRegisterBankInfo : public RegisterBankInfo { 26*0b57cec5SDimitry Andric #define GET_TARGET_REGBANK_CLASS 27*0b57cec5SDimitry Andric #include "ARMGenRegisterBank.inc" 28*0b57cec5SDimitry Andric }; 29*0b57cec5SDimitry Andric 30*0b57cec5SDimitry Andric /// This class provides the information for the target register banks. 31*0b57cec5SDimitry Andric class ARMRegisterBankInfo final : public ARMGenRegisterBankInfo { 32*0b57cec5SDimitry Andric public: 33*0b57cec5SDimitry Andric ARMRegisterBankInfo(const TargetRegisterInfo &TRI); 34*0b57cec5SDimitry Andric 35*0b57cec5SDimitry Andric const RegisterBank & 36*0b57cec5SDimitry Andric getRegBankFromRegClass(const TargetRegisterClass &RC) const override; 37*0b57cec5SDimitry Andric 38*0b57cec5SDimitry Andric const InstructionMapping & 39*0b57cec5SDimitry Andric getInstrMapping(const MachineInstr &MI) const override; 40*0b57cec5SDimitry Andric }; 41*0b57cec5SDimitry Andric } // End llvm namespace. 42*0b57cec5SDimitry Andric #endif 43