10b57cec5SDimitry Andric //===- ARMRegisterBankInfo ---------------------------------------*- C++ -*-==// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric /// \file 90b57cec5SDimitry Andric /// This file declares the targeting of the RegisterBankInfo class for ARM. 100b57cec5SDimitry Andric /// \todo This should be generated by TableGen. 110b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 120b57cec5SDimitry Andric 130b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_ARM_ARMREGISTERBANKINFO_H 140b57cec5SDimitry Andric #define LLVM_LIB_TARGET_ARM_ARMREGISTERBANKINFO_H 150b57cec5SDimitry Andric 16*81ad6265SDimitry Andric #include "llvm/CodeGen/RegisterBankInfo.h" 170b57cec5SDimitry Andric 180b57cec5SDimitry Andric #define GET_REGBANK_DECLARATIONS 190b57cec5SDimitry Andric #include "ARMGenRegisterBank.inc" 200b57cec5SDimitry Andric 210b57cec5SDimitry Andric namespace llvm { 220b57cec5SDimitry Andric 230b57cec5SDimitry Andric class TargetRegisterInfo; 240b57cec5SDimitry Andric 250b57cec5SDimitry Andric class ARMGenRegisterBankInfo : public RegisterBankInfo { 260b57cec5SDimitry Andric #define GET_TARGET_REGBANK_CLASS 270b57cec5SDimitry Andric #include "ARMGenRegisterBank.inc" 280b57cec5SDimitry Andric }; 290b57cec5SDimitry Andric 300b57cec5SDimitry Andric /// This class provides the information for the target register banks. 310b57cec5SDimitry Andric class ARMRegisterBankInfo final : public ARMGenRegisterBankInfo { 320b57cec5SDimitry Andric public: 330b57cec5SDimitry Andric ARMRegisterBankInfo(const TargetRegisterInfo &TRI); 340b57cec5SDimitry Andric 35480093f4SDimitry Andric const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, 36480093f4SDimitry Andric LLT) const override; 370b57cec5SDimitry Andric 380b57cec5SDimitry Andric const InstructionMapping & 390b57cec5SDimitry Andric getInstrMapping(const MachineInstr &MI) const override; 400b57cec5SDimitry Andric }; 410b57cec5SDimitry Andric } // End llvm namespace. 420b57cec5SDimitry Andric #endif 43