xref: /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ARM.td (revision cab6a39d7b343596a5823e65c0f7b426551ec22d) 
1//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12//===----------------------------------------------------------------------===//
13// Target-independent interfaces which we are implementing
14//===----------------------------------------------------------------------===//
15
16include "llvm/Target/Target.td"
17
18//===----------------------------------------------------------------------===//
19// ARM Subtarget state.
20//
21
22def ModeThumb             : SubtargetFeature<"thumb-mode", "InThumbMode",
23                                             "true", "Thumb mode">;
24
25def ModeSoftFloat         : SubtargetFeature<"soft-float","UseSoftFloat",
26                                             "true", "Use software floating "
27                                             "point features.">;
28
29
30//===----------------------------------------------------------------------===//
31// ARM Subtarget features.
32//
33
34// Floating Point, HW Division and Neon Support
35
36// FP loads/stores/moves, shared between VFP and MVE (even in the integer-only
37// version).
38def FeatureFPRegs         : SubtargetFeature<"fpregs", "HasFPRegs", "true",
39                                             "Enable FP registers">;
40
41// 16-bit FP loads/stores/moves, shared between VFP (with the v8.2A FP16
42// extension) and MVE (even in the integer-only version).
43def FeatureFPRegs16       : SubtargetFeature<"fpregs16", "HasFPRegs16", "true",
44                                             "Enable 16-bit FP registers",
45                                             [FeatureFPRegs]>;
46
47def FeatureFPRegs64       : SubtargetFeature<"fpregs64", "HasFPRegs64", "true",
48                                             "Enable 64-bit FP registers",
49                                             [FeatureFPRegs]>;
50
51def FeatureFP64           : SubtargetFeature<"fp64", "HasFP64", "true",
52                                             "Floating point unit supports "
53                                             "double precision",
54                                             [FeatureFPRegs64]>;
55
56def FeatureD32            : SubtargetFeature<"d32", "HasD32", "true",
57                                             "Extend FP to 32 double registers">;
58
59multiclass VFPver<string name, string query, string description,
60                  list<SubtargetFeature> prev,
61                  list<SubtargetFeature> otherimplies,
62                  list<SubtargetFeature> vfp2prev = []> {
63  def _D16_SP: SubtargetFeature<
64    name#"d16sp", query#"D16SP", "true",
65    description#" with only 16 d-registers and no double precision",
66    !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16_SP")) #
67      !foreach(v, vfp2prev, !cast<SubtargetFeature>(v # "_SP")) #
68      otherimplies>;
69  def _SP: SubtargetFeature<
70    name#"sp", query#"SP", "true",
71    description#" with no double precision",
72    !foreach(v, prev, !cast<SubtargetFeature>(v # "_SP")) #
73      otherimplies # [FeatureD32, !cast<SubtargetFeature>(NAME # "_D16_SP")]>;
74  def _D16: SubtargetFeature<
75    name#"d16", query#"D16", "true",
76    description#" with only 16 d-registers",
77    !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16")) #
78      vfp2prev #
79      otherimplies # [FeatureFP64, !cast<SubtargetFeature>(NAME # "_D16_SP")]>;
80  def "": SubtargetFeature<
81    name, query, "true", description,
82    prev # otherimplies # [
83        !cast<SubtargetFeature>(NAME # "_D16"),
84        !cast<SubtargetFeature>(NAME # "_SP")]>;
85}
86
87def FeatureVFP2_SP        : SubtargetFeature<"vfp2sp", "HasVFPv2SP", "true",
88                                             "Enable VFP2 instructions with "
89                                             "no double precision",
90                                             [FeatureFPRegs]>;
91
92def FeatureVFP2           : SubtargetFeature<"vfp2", "HasVFPv2", "true",
93                                             "Enable VFP2 instructions",
94                                             [FeatureFP64, FeatureVFP2_SP]>;
95
96defm FeatureVFP3: VFPver<"vfp3", "HasVFPv3", "Enable VFP3 instructions",
97                         [], [], [FeatureVFP2]>;
98
99def FeatureNEON           : SubtargetFeature<"neon", "HasNEON", "true",
100                                             "Enable NEON instructions",
101                                             [FeatureVFP3]>;
102
103def FeatureFP16           : SubtargetFeature<"fp16", "HasFP16", "true",
104                                             "Enable half-precision "
105                                             "floating point">;
106
107defm FeatureVFP4: VFPver<"vfp4", "HasVFPv4", "Enable VFP4 instructions",
108                         [FeatureVFP3], [FeatureFP16]>;
109
110defm FeatureFPARMv8: VFPver<"fp-armv8", "HasFPARMv8", "Enable ARMv8 FP",
111                         [FeatureVFP4], []>;
112
113def FeatureFullFP16       : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
114                                             "Enable full half-precision "
115                                             "floating point",
116                                             [FeatureFPARMv8_D16_SP, FeatureFPRegs16]>;
117
118def FeatureFP16FML        : SubtargetFeature<"fp16fml", "HasFP16FML", "true",
119                                             "Enable full half-precision "
120                                             "floating point fml instructions",
121                                             [FeatureFullFP16]>;
122
123def FeatureHWDivThumb     : SubtargetFeature<"hwdiv",
124                                             "HasHardwareDivideInThumb", "true",
125                                             "Enable divide instructions in Thumb">;
126
127def FeatureHWDivARM       : SubtargetFeature<"hwdiv-arm",
128                                             "HasHardwareDivideInARM", "true",
129                                             "Enable divide instructions in ARM mode">;
130
131// Atomic Support
132def FeatureDB             : SubtargetFeature<"db", "HasDataBarrier", "true",
133                                             "Has data barrier (dmb/dsb) instructions">;
134
135def FeatureV7Clrex        : SubtargetFeature<"v7clrex", "HasV7Clrex", "true",
136                                             "Has v7 clrex instruction">;
137
138def FeatureDFB  : SubtargetFeature<"dfb", "HasFullDataBarrier", "true",
139                                   "Has full data barrier (dfb) instruction">;
140
141def FeatureAcquireRelease : SubtargetFeature<"acquire-release",
142                                             "HasAcquireRelease", "true",
143                                             "Has v8 acquire/release (lda/ldaex "
144                                             " etc) instructions">;
145
146
147def FeatureSlowFPBrcc     : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
148                                             "FP compare + branch is slow">;
149
150def FeaturePerfMon        : SubtargetFeature<"perfmon", "HasPerfMon", "true",
151                                             "Enable support for Performance "
152                                             "Monitor extensions">;
153
154
155// TrustZone Security Extensions
156def FeatureTrustZone      : SubtargetFeature<"trustzone", "HasTrustZone", "true",
157                                             "Enable support for TrustZone "
158                                             "security extensions">;
159
160def Feature8MSecExt       : SubtargetFeature<"8msecext", "Has8MSecExt", "true",
161                                             "Enable support for ARMv8-M "
162                                             "Security Extensions">;
163
164def FeatureSHA2           : SubtargetFeature<"sha2", "HasSHA2", "true",
165                                             "Enable SHA1 and SHA256 support", [FeatureNEON]>;
166
167def FeatureAES            : SubtargetFeature<"aes", "HasAES", "true",
168                                             "Enable AES support", [FeatureNEON]>;
169
170def FeatureCrypto         : SubtargetFeature<"crypto", "HasCrypto", "true",
171                                             "Enable support for "
172                                             "Cryptography extensions",
173                                             [FeatureNEON, FeatureSHA2, FeatureAES]>;
174
175def FeatureCRC            : SubtargetFeature<"crc", "HasCRC", "true",
176                                             "Enable support for CRC instructions">;
177
178def FeatureDotProd        : SubtargetFeature<"dotprod", "HasDotProd", "true",
179                                             "Enable support for dot product instructions",
180                                             [FeatureNEON]>;
181
182// Not to be confused with FeatureHasRetAddrStack (return address stack)
183def FeatureRAS            : SubtargetFeature<"ras", "HasRAS", "true",
184                                             "Enable Reliability, Availability "
185                                             "and Serviceability extensions">;
186
187// Fast computation of non-negative address offsets
188def FeatureFPAO           : SubtargetFeature<"fpao", "HasFPAO", "true",
189                                             "Enable fast computation of "
190                                             "positive address offsets">;
191
192// Fast execution of AES crypto operations
193def FeatureFuseAES        : SubtargetFeature<"fuse-aes", "HasFuseAES", "true",
194                                             "CPU fuses AES crypto operations">;
195
196// Fast execution of bottom and top halves of literal generation
197def FeatureFuseLiterals   : SubtargetFeature<"fuse-literals", "HasFuseLiterals", "true",
198                                             "CPU fuses literal generation operations">;
199
200// The way of reading thread pointer
201def FeatureReadTp :  SubtargetFeature<"read-tp-hard", "ReadTPHard", "true",
202                                      "Reading thread pointer from register">;
203
204// Cyclone can zero VFP registers in 0 cycles.
205def FeatureZCZeroing      : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
206                                             "Has zero-cycle zeroing instructions">;
207
208// Whether it is profitable to unpredicate certain instructions during if-conversion
209def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr",
210                                              "IsProfitableToUnpredicate", "true",
211                                              "Is profitable to unpredicate">;
212
213// Some targets (e.g. Swift) have microcoded VGETLNi32.
214def FeatureSlowVGETLNi32  : SubtargetFeature<"slow-vgetlni32",
215                                             "HasSlowVGETLNi32", "true",
216                                             "Has slow VGETLNi32 - prefer VMOV">;
217
218// Some targets (e.g. Swift) have microcoded VDUP32.
219def FeatureSlowVDUP32     : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32",
220                                             "true",
221                                             "Has slow VDUP32 - prefer VMOV">;
222
223// Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
224// for scalar FP, as this allows more effective execution domain optimization.
225def FeaturePreferVMOVSR   : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR",
226                                             "true", "Prefer VMOVSR">;
227
228// Swift has ISHST barriers compatible with Atomic Release semantics but weaker
229// than ISH
230def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST",
231                                               "true", "Prefer ISHST barriers">;
232
233// Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU.
234def FeatureMuxedUnits     : SubtargetFeature<"muxed-units", "HasMuxedUnits",
235                                             "true",
236                                             "Has muxed AGU and NEON/FPU">;
237
238// Whether VLDM/VSTM starting with odd register number need more microops
239// than single VLDRS
240def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister",
241                                              "true", "VLDM/VSTM starting "
242                                              "with an odd register is slow">;
243
244// Some targets have a renaming dependency when loading into D subregisters.
245def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg",
246                                              "SlowLoadDSubregister", "true",
247                                              "Loading into D subregs is slow">;
248
249def FeatureUseWideStrideVFP : SubtargetFeature<"wide-stride-vfp",
250                                               "UseWideStrideVFP", "true",
251                                               "Use a wide stride when allocating VFP registers">;
252
253// Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD.
254def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs",
255                                             "DontWidenVMOVS", "true",
256                                             "Don't widen VMOVS to VMOVD">;
257
258// Some targets (e.g. Cortex-A15) prefer to avoid mixing operations on different
259// VFP register widths.
260def FeatureSplatVFPToNeon : SubtargetFeature<"splat-vfp-neon",
261                                             "SplatVFPToNeon", "true",
262                                             "Splat register from VFP to NEON",
263                                             [FeatureDontWidenVMOVS]>;
264
265// Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions.
266def FeatureExpandMLx      : SubtargetFeature<"expand-fp-mlx",
267                                             "ExpandMLx", "true",
268                                             "Expand VFP/NEON MLA/MLS instructions">;
269
270// Some targets have special RAW hazards for VFP/NEON VMLA/VMLS.
271def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards",
272                                             "true", "Has VMLx hazards">;
273
274// Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
275// VFP to NEON, as an execution domain optimization.
276def FeatureNEONForFPMovs  : SubtargetFeature<"neon-fpmovs",
277                                             "UseNEONForFPMovs", "true",
278                                             "Convert VMOVSR, VMOVRS, "
279                                             "VMOVS to NEON">;
280
281// Some processors benefit from using NEON instructions for scalar
282// single-precision FP operations. This affects instruction selection and should
283// only be enabled if the handling of denormals is not important.
284def FeatureNEONForFP      : SubtargetFeature<"neonfp",
285                                             "UseNEONForSinglePrecisionFP",
286                                             "true",
287                                             "Use NEON for single precision FP">;
288
289// On some processors, VLDn instructions that access unaligned data take one
290// extra cycle. Take that into account when computing operand latencies.
291def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign",
292                                             "true",
293                                             "Check for VLDn unaligned access">;
294
295// Some processors have a nonpipelined VFP coprocessor.
296def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp",
297                                              "NonpipelinedVFP", "true",
298                                              "VFP instructions are not pipelined">;
299
300// Some processors have FP multiply-accumulate instructions that don't
301// play nicely with other VFP / NEON instructions, and it's generally better
302// to just not use them.
303def FeatureHasSlowFPVMLx  : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
304                                             "Disable VFP / NEON MAC instructions">;
305
306// VFPv4 added VFMA instructions that can similar be fast or slow.
307def FeatureHasSlowFPVFMx  : SubtargetFeature<"slowfpvfmx", "SlowFPVFMx", "true",
308                                             "Disable VFP / NEON FMA instructions">;
309
310// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
311def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
312                                             "HasVMLxForwarding", "true",
313                                             "Has multiplier accumulator forwarding">;
314
315// Disable 32-bit to 16-bit narrowing for experimentation.
316def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
317                                             "Prefer 32-bit Thumb instrs">;
318
319def FeaturePrefLoopAlign32 : SubtargetFeature<"loop-align", "PrefLoopLogAlignment","2",
320                                              "Prefer 32-bit alignment for loops">;
321
322def FeatureMVEVectorCostFactor1 : SubtargetFeature<"mve1beat", "MVEVectorCostFactor", "1",
323                        "Model MVE instructions as a 1 beat per tick architecture">;
324
325def FeatureMVEVectorCostFactor2 : SubtargetFeature<"mve2beat", "MVEVectorCostFactor", "2",
326                        "Model MVE instructions as a 2 beats per tick architecture">;
327
328def FeatureMVEVectorCostFactor4 : SubtargetFeature<"mve4beat", "MVEVectorCostFactor", "4",
329                        "Model MVE instructions as a 4 beats per tick architecture">;
330
331/// Some instructions update CPSR partially, which can add false dependency for
332/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
333/// mapped to a separate physical register. Avoid partial CPSR update for these
334/// processors.
335def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
336                                               "AvoidCPSRPartialUpdate", "true",
337                                 "Avoid CPSR partial update for OOO execution">;
338
339/// Disable +1 predication cost for instructions updating CPSR.
340/// Enabled for Cortex-A57.
341def FeatureCheapPredicableCPSR : SubtargetFeature<"cheap-predicable-cpsr",
342                                                  "CheapPredicableCPSRDef",
343                                                  "true",
344                  "Disable +1 predication cost for instructions updating CPSR">;
345
346def FeatureAvoidMOVsShOp  : SubtargetFeature<"avoid-movs-shop",
347                                             "AvoidMOVsShifterOperand", "true",
348                                             "Avoid movs instructions with "
349                                             "shifter operand">;
350
351// Some processors perform return stack prediction. CodeGen should avoid issue
352// "normal" call instructions to callees which do not return.
353def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack",
354                                              "HasRetAddrStack", "true",
355                                              "Has return address stack">;
356
357// Some processors have no branch predictor, which changes the expected cost of
358// taking a branch which affects the choice of whether to use predicated
359// instructions.
360def FeatureHasNoBranchPredictor : SubtargetFeature<"no-branch-predictor",
361                                                   "HasBranchPredictor", "false",
362                                                   "Has no branch predictor">;
363
364/// DSP extension.
365def FeatureDSP            : SubtargetFeature<"dsp", "HasDSP", "true",
366                                             "Supports DSP instructions in "
367                                             "ARM and/or Thumb2">;
368
369// Multiprocessing extension.
370def FeatureMP             : SubtargetFeature<"mp", "HasMPExtension", "true",
371                                        "Supports Multiprocessing extension">;
372
373// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
374def FeatureVirtualization : SubtargetFeature<"virtualization",
375                                             "HasVirtualization", "true",
376                                             "Supports Virtualization extension",
377                                             [FeatureHWDivThumb, FeatureHWDivARM]>;
378
379// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
380// See ARMInstrInfo.td for details.
381def FeatureNaClTrap       : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
382                                             "NaCl trap">;
383
384def FeatureStrictAlign    : SubtargetFeature<"strict-align",
385                                             "StrictAlign", "true",
386                                             "Disallow all unaligned memory "
387                                             "access">;
388
389def FeatureLongCalls      : SubtargetFeature<"long-calls", "GenLongCalls", "true",
390                                             "Generate calls via indirect call "
391                                             "instructions">;
392
393def FeatureExecuteOnly    : SubtargetFeature<"execute-only",
394                                             "GenExecuteOnly", "true",
395                                             "Enable the generation of "
396                                             "execute only code.">;
397
398def FeatureReserveR9      : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
399                                             "Reserve R9, making it unavailable"
400                                             " as GPR">;
401
402def FeatureNoMovt         : SubtargetFeature<"no-movt", "NoMovt", "true",
403                                             "Don't use movt/movw pairs for "
404                                             "32-bit imms">;
405
406def FeatureNoNegativeImmediates
407                          : SubtargetFeature<"no-neg-immediates",
408                                             "NegativeImmediates", "false",
409                                             "Convert immediates and instructions "
410                                             "to their negated or complemented "
411                                             "equivalent when the immediate does "
412                                             "not fit in the encoding.">;
413
414// Use the MachineScheduler for instruction scheduling for the subtarget.
415def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true",
416                                        "Use the MachineScheduler">;
417
418def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler",
419    "DisablePostRAScheduler", "true",
420    "Don't schedule again after register allocation">;
421
422// Armv8.5-A extensions
423
424def FeatureSB       : SubtargetFeature<"sb", "HasSB", "true",
425  "Enable v8.5a Speculation Barrier" >;
426
427// Armv8.6-A extensions
428def FeatureBF16     : SubtargetFeature<"bf16", "HasBF16", "true",
429  "Enable support for BFloat16 instructions",  [FeatureNEON]>;
430
431def FeatureMatMulInt8 : SubtargetFeature<"i8mm", "HasMatMulInt8",
432    "true", "Enable Matrix Multiply Int8 Extension", [FeatureNEON]>;
433
434// Armv8.1-M extensions
435
436def FeatureLOB            : SubtargetFeature<"lob", "HasLOB", "true",
437                                             "Enable Low Overhead Branch "
438                                             "extensions">;
439
440//===----------------------------------------------------------------------===//
441// ARM architecture class
442//
443
444// A-series ISA
445def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
446                                     "Is application profile ('A' series)">;
447
448// R-series ISA
449def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
450                                     "Is realtime profile ('R' series)">;
451
452// M-series ISA
453def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
454                                     "Is microcontroller profile ('M' series)">;
455
456
457def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
458                                     "Enable Thumb2 instructions">;
459
460def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
461                                     "Does not support ARM mode execution">;
462
463//===----------------------------------------------------------------------===//
464// ARM ISAa.
465//
466
467def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
468                                   "Support ARM v4T instructions">;
469
470def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",
471                                   "Support ARM v5T instructions",
472                                   [HasV4TOps]>;
473
474def HasV5TEOps  : SubtargetFeature<"v5te", "HasV5TEOps", "true",
475                                   "Support ARM v5TE, v5TEj, and "
476                                   "v5TExp instructions",
477                                   [HasV5TOps]>;
478
479def HasV6Ops    : SubtargetFeature<"v6", "HasV6Ops", "true",
480                                   "Support ARM v6 instructions",
481                                   [HasV5TEOps]>;
482
483def HasV6MOps   : SubtargetFeature<"v6m", "HasV6MOps", "true",
484                                   "Support ARM v6M instructions",
485                                   [HasV6Ops]>;
486
487def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true",
488                                         "Support ARM v8M Baseline instructions",
489                                         [HasV6MOps]>;
490
491def HasV6KOps   : SubtargetFeature<"v6k", "HasV6KOps", "true",
492                                   "Support ARM v6k instructions",
493                                   [HasV6Ops]>;
494
495def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
496                                   "Support ARM v6t2 instructions",
497                                   [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>;
498
499def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
500                                   "Support ARM v7 instructions",
501                                   [HasV6T2Ops, FeaturePerfMon,
502                                    FeatureV7Clrex]>;
503
504def HasV8MMainlineOps :
505                  SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true",
506                                   "Support ARM v8M Mainline instructions",
507                                   [HasV7Ops]>;
508
509def HasV8Ops    : SubtargetFeature<"v8", "HasV8Ops", "true",
510                                   "Support ARM v8 instructions",
511                                   [HasV7Ops, FeatureAcquireRelease]>;
512
513def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
514                                   "Support ARM v8.1a instructions",
515                                   [HasV8Ops]>;
516
517def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
518                                   "Support ARM v8.2a instructions",
519                                   [HasV8_1aOps]>;
520
521def HasV8_3aOps   : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
522                                   "Support ARM v8.3a instructions",
523                                   [HasV8_2aOps]>;
524
525def HasV8_4aOps   : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
526                                   "Support ARM v8.4a instructions",
527                                   [HasV8_3aOps, FeatureDotProd]>;
528
529def HasV8_5aOps   : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true",
530                                   "Support ARM v8.5a instructions",
531                                   [HasV8_4aOps, FeatureSB]>;
532
533def HasV8_6aOps   : SubtargetFeature<"v8.6a", "HasV8_6aOps", "true",
534                                   "Support ARM v8.6a instructions",
535                                   [HasV8_5aOps, FeatureBF16,
536                                    FeatureMatMulInt8]>;
537
538def HasV8_7aOps   : SubtargetFeature<"v8.7a", "HasV8_7aOps", "true",
539                                   "Support ARM v8.7a instructions",
540                                   [HasV8_6aOps]>;
541
542def HasV8_1MMainlineOps : SubtargetFeature<
543               "v8.1m.main", "HasV8_1MMainlineOps", "true",
544               "Support ARM v8-1M Mainline instructions",
545               [HasV8MMainlineOps]>;
546def HasMVEIntegerOps : SubtargetFeature<
547               "mve", "HasMVEIntegerOps", "true",
548               "Support M-Class Vector Extension with integer ops",
549               [HasV8_1MMainlineOps, FeatureDSP, FeatureFPRegs16, FeatureFPRegs64]>;
550def HasMVEFloatOps : SubtargetFeature<
551               "mve.fp", "HasMVEFloatOps", "true",
552               "Support M-Class Vector Extension with integer and floating ops",
553               [HasMVEIntegerOps, FeatureFPARMv8_D16_SP, FeatureFullFP16]>;
554
555def HasCDEOps : SubtargetFeature<"cde", "HasCDEOps", "true",
556                                 "Support CDE instructions",
557                                 [HasV8MMainlineOps]>;
558
559foreach i = {0-7} in
560    def FeatureCoprocCDE#i : SubtargetFeature<"cdecp"#i,
561                                              "CoprocCDE["#i#"]", "true",
562                                              "Coprocessor "#i#" ISA is CDEv1",
563                                              [HasCDEOps]>;
564
565//===----------------------------------------------------------------------===//
566// Control codegen mitigation against Straight Line Speculation vulnerability.
567//===----------------------------------------------------------------------===//
568
569def FeatureHardenSlsRetBr : SubtargetFeature<"harden-sls-retbr",
570  "HardenSlsRetBr", "true",
571  "Harden against straight line speculation across RETurn and BranchRegister "
572  "instructions">;
573def FeatureHardenSlsBlr : SubtargetFeature<"harden-sls-blr",
574  "HardenSlsBlr", "true",
575  "Harden against straight line speculation across indirect calls">;
576
577
578
579//===----------------------------------------------------------------------===//
580// ARM Processor subtarget features.
581//
582
583def ProcA5      : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
584                                   "Cortex-A5 ARM processors", []>;
585def ProcA7      : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
586                                   "Cortex-A7 ARM processors", []>;
587def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
588                                   "Cortex-A8 ARM processors", []>;
589def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
590                                   "Cortex-A9 ARM processors", []>;
591def ProcA12     : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
592                                   "Cortex-A12 ARM processors", []>;
593def ProcA15     : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
594                                   "Cortex-A15 ARM processors", []>;
595def ProcA17     : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
596                                   "Cortex-A17 ARM processors", []>;
597def ProcA32     : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32",
598                                   "Cortex-A32 ARM processors", []>;
599def ProcA35     : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
600                                   "Cortex-A35 ARM processors", []>;
601def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
602                                   "Cortex-A53 ARM processors", []>;
603def ProcA55     : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
604                                   "Cortex-A55 ARM processors", []>;
605def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
606                                   "Cortex-A57 ARM processors", []>;
607def ProcA72     : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
608                                   "Cortex-A72 ARM processors", []>;
609def ProcA73     : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
610                                   "Cortex-A73 ARM processors", []>;
611def ProcA75     : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
612                                   "Cortex-A75 ARM processors", []>;
613def ProcA76     : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76",
614                                   "Cortex-A76 ARM processors", []>;
615def ProcA77     : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77",
616                                   "Cortex-A77 ARM processors", []>;
617def ProcA78     : SubtargetFeature<"cortex-a78", "ARMProcFamily", "CortexA78",
618                                   "Cortex-A78 ARM processors", []>;
619def ProcA78C    : SubtargetFeature<"a78c", "ARMProcFamily", "CortexA78C",
620                                   "Cortex-A78C ARM processors", []>;
621def ProcX1      : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1",
622                                   "Cortex-X1 ARM processors", []>;
623
624def ProcV1      : SubtargetFeature<"neoverse-v1", "ARMProcFamily",
625                                   "NeoverseV1", "Neoverse-V1 ARM processors", []>;
626
627def ProcKrait   : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
628                                   "Qualcomm Krait processors", []>;
629def ProcKryo    : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
630                                   "Qualcomm Kryo processors", []>;
631def ProcSwift   : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
632                                   "Swift ARM processors", []>;
633
634def ProcExynos  : SubtargetFeature<"exynos", "ARMProcFamily", "Exynos",
635                                   "Samsung Exynos processors",
636                                   [FeatureZCZeroing,
637                                    FeatureUseWideStrideVFP,
638                                    FeatureSplatVFPToNeon,
639                                    FeatureSlowVGETLNi32,
640                                    FeatureSlowVDUP32,
641                                    FeatureSlowFPBrcc,
642                                    FeatureProfUnpredicate,
643                                    FeatureHWDivThumb,
644                                    FeatureHWDivARM,
645                                    FeatureHasSlowFPVMLx,
646                                    FeatureHasSlowFPVFMx,
647                                    FeatureHasRetAddrStack,
648                                    FeatureFuseLiterals,
649                                    FeatureFuseAES,
650                                    FeatureExpandMLx,
651                                    FeatureCrypto,
652                                    FeatureCRC]>;
653
654def ProcR4      : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
655                                   "Cortex-R4 ARM processors", []>;
656def ProcR5      : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
657                                   "Cortex-R5 ARM processors", []>;
658def ProcR7      : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7",
659                                   "Cortex-R7 ARM processors", []>;
660def ProcR52     : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52",
661                                   "Cortex-R52 ARM processors", []>;
662
663def ProcM3      : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3",
664                                   "Cortex-M3 ARM processors", []>;
665def ProcM7      : SubtargetFeature<"m7", "ARMProcFamily", "CortexM7",
666                                   "Cortex-M7 ARM processors", []>;
667
668//===----------------------------------------------------------------------===//
669// ARM Helper classes.
670//
671
672class Architecture<string fname, string aname, list<SubtargetFeature> features>
673  : SubtargetFeature<fname, "ARMArch", aname,
674                     !strconcat(aname, " architecture"), features>;
675
676class ProcNoItin<string Name, list<SubtargetFeature> Features>
677  : Processor<Name, NoItineraries, Features>;
678
679
680//===----------------------------------------------------------------------===//
681// ARM architectures
682//
683
684def ARMv2     : Architecture<"armv2",     "ARMv2",    []>;
685
686def ARMv2a    : Architecture<"armv2a",    "ARMv2a",   []>;
687
688def ARMv3     : Architecture<"armv3",     "ARMv3",    []>;
689
690def ARMv3m    : Architecture<"armv3m",    "ARMv3m",   []>;
691
692def ARMv4     : Architecture<"armv4",     "ARMv4",    []>;
693
694def ARMv4t    : Architecture<"armv4t",    "ARMv4t",   [HasV4TOps]>;
695
696def ARMv5t    : Architecture<"armv5t",    "ARMv5t",   [HasV5TOps]>;
697
698def ARMv5te   : Architecture<"armv5te",   "ARMv5te",  [HasV5TEOps]>;
699
700def ARMv5tej  : Architecture<"armv5tej",  "ARMv5tej", [HasV5TEOps]>;
701
702def ARMv6     : Architecture<"armv6",     "ARMv6",    [HasV6Ops,
703                                                       FeatureDSP]>;
704
705def ARMv6t2   : Architecture<"armv6t2",   "ARMv6t2",  [HasV6T2Ops,
706                                                       FeatureDSP]>;
707
708def ARMv6k    : Architecture<"armv6k",    "ARMv6k",   [HasV6KOps]>;
709
710def ARMv6kz   : Architecture<"armv6kz",   "ARMv6kz",  [HasV6KOps,
711                                                       FeatureTrustZone]>;
712
713def ARMv6m    : Architecture<"armv6-m",   "ARMv6m",   [HasV6MOps,
714                                                       FeatureNoARM,
715                                                       ModeThumb,
716                                                       FeatureDB,
717                                                       FeatureMClass,
718                                                       FeatureStrictAlign]>;
719
720def ARMv6sm   : Architecture<"armv6s-m",  "ARMv6sm",  [HasV6MOps,
721                                                       FeatureNoARM,
722                                                       ModeThumb,
723                                                       FeatureDB,
724                                                       FeatureMClass,
725                                                       FeatureStrictAlign]>;
726
727def ARMv7a    : Architecture<"armv7-a",   "ARMv7a",   [HasV7Ops,
728                                                       FeatureNEON,
729                                                       FeatureDB,
730                                                       FeatureDSP,
731                                                       FeatureAClass]>;
732
733def ARMv7ve   : Architecture<"armv7ve",   "ARMv7ve",  [HasV7Ops,
734                                                       FeatureNEON,
735                                                       FeatureDB,
736                                                       FeatureDSP,
737                                                       FeatureTrustZone,
738                                                       FeatureMP,
739                                                       FeatureVirtualization,
740                                                       FeatureAClass]>;
741
742def ARMv7r    : Architecture<"armv7-r",   "ARMv7r",   [HasV7Ops,
743                                                       FeatureDB,
744                                                       FeatureDSP,
745                                                       FeatureHWDivThumb,
746                                                       FeatureRClass]>;
747
748def ARMv7m    : Architecture<"armv7-m",   "ARMv7m",   [HasV7Ops,
749                                                       FeatureThumb2,
750                                                       FeatureNoARM,
751                                                       ModeThumb,
752                                                       FeatureDB,
753                                                       FeatureHWDivThumb,
754                                                       FeatureMClass]>;
755
756def ARMv7em   : Architecture<"armv7e-m",  "ARMv7em",  [HasV7Ops,
757                                                       FeatureThumb2,
758                                                       FeatureNoARM,
759                                                       ModeThumb,
760                                                       FeatureDB,
761                                                       FeatureHWDivThumb,
762                                                       FeatureMClass,
763                                                       FeatureDSP]>;
764
765def ARMv8a    : Architecture<"armv8-a",   "ARMv8a",   [HasV8Ops,
766                                                       FeatureAClass,
767                                                       FeatureDB,
768                                                       FeatureFPARMv8,
769                                                       FeatureNEON,
770                                                       FeatureDSP,
771                                                       FeatureTrustZone,
772                                                       FeatureMP,
773                                                       FeatureVirtualization,
774                                                       FeatureCrypto,
775                                                       FeatureCRC]>;
776
777def ARMv81a   : Architecture<"armv8.1-a", "ARMv81a",  [HasV8_1aOps,
778                                                       FeatureAClass,
779                                                       FeatureDB,
780                                                       FeatureFPARMv8,
781                                                       FeatureNEON,
782                                                       FeatureDSP,
783                                                       FeatureTrustZone,
784                                                       FeatureMP,
785                                                       FeatureVirtualization,
786                                                       FeatureCrypto,
787                                                       FeatureCRC]>;
788
789def ARMv82a   : Architecture<"armv8.2-a", "ARMv82a",  [HasV8_2aOps,
790                                                       FeatureAClass,
791                                                       FeatureDB,
792                                                       FeatureFPARMv8,
793                                                       FeatureNEON,
794                                                       FeatureDSP,
795                                                       FeatureTrustZone,
796                                                       FeatureMP,
797                                                       FeatureVirtualization,
798                                                       FeatureCrypto,
799                                                       FeatureCRC,
800                                                       FeatureRAS]>;
801
802def ARMv83a   : Architecture<"armv8.3-a", "ARMv83a",  [HasV8_3aOps,
803                                                       FeatureAClass,
804                                                       FeatureDB,
805                                                       FeatureFPARMv8,
806                                                       FeatureNEON,
807                                                       FeatureDSP,
808                                                       FeatureTrustZone,
809                                                       FeatureMP,
810                                                       FeatureVirtualization,
811                                                       FeatureCrypto,
812                                                       FeatureCRC,
813                                                       FeatureRAS]>;
814
815def ARMv84a   : Architecture<"armv8.4-a", "ARMv84a",  [HasV8_4aOps,
816                                                       FeatureAClass,
817                                                       FeatureDB,
818                                                       FeatureFPARMv8,
819                                                       FeatureNEON,
820                                                       FeatureDSP,
821                                                       FeatureTrustZone,
822                                                       FeatureMP,
823                                                       FeatureVirtualization,
824                                                       FeatureCrypto,
825                                                       FeatureCRC,
826                                                       FeatureRAS,
827                                                       FeatureDotProd]>;
828
829def ARMv85a   : Architecture<"armv8.5-a", "ARMv85a",  [HasV8_5aOps,
830                                                       FeatureAClass,
831                                                       FeatureDB,
832                                                       FeatureFPARMv8,
833                                                       FeatureNEON,
834                                                       FeatureDSP,
835                                                       FeatureTrustZone,
836                                                       FeatureMP,
837                                                       FeatureVirtualization,
838                                                       FeatureCrypto,
839                                                       FeatureCRC,
840                                                       FeatureRAS,
841                                                       FeatureDotProd]>;
842def ARMv86a   : Architecture<"armv8.6-a", "ARMv86a",  [HasV8_6aOps,
843                                                       FeatureAClass,
844                                                       FeatureDB,
845                                                       FeatureFPARMv8,
846                                                       FeatureNEON,
847                                                       FeatureDSP,
848                                                       FeatureTrustZone,
849                                                       FeatureMP,
850                                                       FeatureVirtualization,
851                                                       FeatureCrypto,
852                                                       FeatureCRC,
853                                                       FeatureRAS,
854                                                       FeatureDotProd]>;
855def ARMv87a   : Architecture<"armv8.7-a", "ARMv86a",  [HasV8_7aOps,
856                                                       FeatureAClass,
857                                                       FeatureDB,
858                                                       FeatureFPARMv8,
859                                                       FeatureNEON,
860                                                       FeatureDSP,
861                                                       FeatureTrustZone,
862                                                       FeatureMP,
863                                                       FeatureVirtualization,
864                                                       FeatureCrypto,
865                                                       FeatureCRC,
866                                                       FeatureRAS,
867                                                       FeatureDotProd]>;
868
869def ARMv8r    : Architecture<"armv8-r",   "ARMv8r",   [HasV8Ops,
870                                                       FeatureRClass,
871                                                       FeatureDB,
872                                                       FeatureDFB,
873                                                       FeatureDSP,
874                                                       FeatureCRC,
875                                                       FeatureMP,
876                                                       FeatureVirtualization,
877                                                       FeatureFPARMv8,
878                                                       FeatureNEON]>;
879
880def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",
881                                                      [HasV8MBaselineOps,
882                                                       FeatureNoARM,
883                                                       ModeThumb,
884                                                       FeatureDB,
885                                                       FeatureHWDivThumb,
886                                                       FeatureV7Clrex,
887                                                       Feature8MSecExt,
888                                                       FeatureAcquireRelease,
889                                                       FeatureMClass,
890                                                       FeatureStrictAlign]>;
891
892def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline",
893                                                      [HasV8MMainlineOps,
894                                                       FeatureNoARM,
895                                                       ModeThumb,
896                                                       FeatureDB,
897                                                       FeatureHWDivThumb,
898                                                       Feature8MSecExt,
899                                                       FeatureAcquireRelease,
900                                                       FeatureMClass]>;
901
902def ARMv81mMainline : Architecture<"armv8.1-m.main", "ARMv81mMainline",
903                                                      [HasV8_1MMainlineOps,
904                                                       FeatureNoARM,
905                                                       ModeThumb,
906                                                       FeatureDB,
907                                                       FeatureHWDivThumb,
908                                                       Feature8MSecExt,
909                                                       FeatureAcquireRelease,
910                                                       FeatureMClass,
911                                                       FeatureRAS,
912                                                       FeatureLOB]>;
913
914// Aliases
915def IWMMXT   : Architecture<"iwmmxt",      "ARMv5te",  [ARMv5te]>;
916def IWMMXT2  : Architecture<"iwmmxt2",     "ARMv5te",  [ARMv5te]>;
917def XScale   : Architecture<"xscale",      "ARMv5te",  [ARMv5te]>;
918def ARMv6j   : Architecture<"armv6j",      "ARMv7a",   [ARMv6]>;
919def ARMv7k   : Architecture<"armv7k",      "ARMv7a",   [ARMv7a]>;
920def ARMv7s   : Architecture<"armv7s",      "ARMv7a",   [ARMv7a]>;
921
922//===----------------------------------------------------------------------===//
923// Register File Description
924//===----------------------------------------------------------------------===//
925
926include "ARMRegisterInfo.td"
927include "ARMRegisterBanks.td"
928include "ARMCallingConv.td"
929
930//===----------------------------------------------------------------------===//
931// ARM schedules.
932//===----------------------------------------------------------------------===//
933//
934include "ARMPredicates.td"
935include "ARMSchedule.td"
936
937//===----------------------------------------------------------------------===//
938// Instruction Descriptions
939//===----------------------------------------------------------------------===//
940
941include "ARMInstrInfo.td"
942def ARMInstrInfo : InstrInfo;
943
944//===----------------------------------------------------------------------===//
945// ARM schedules
946//
947include "ARMScheduleV6.td"
948include "ARMScheduleA8.td"
949include "ARMScheduleA9.td"
950include "ARMScheduleSwift.td"
951include "ARMScheduleR52.td"
952include "ARMScheduleA57.td"
953include "ARMScheduleM4.td"
954include "ARMScheduleM7.td"
955
956//===----------------------------------------------------------------------===//
957// ARM processors
958//
959// Dummy CPU, used to target architectures
960def : ProcessorModel<"generic",     CortexA8Model,      []>;
961
962// FIXME: Several processors below are not using their own scheduler
963// model, but one of similar/previous processor. These should be fixed.
964
965def : ProcNoItin<"arm8",                                [ARMv4]>;
966def : ProcNoItin<"arm810",                              [ARMv4]>;
967def : ProcNoItin<"strongarm",                           [ARMv4]>;
968def : ProcNoItin<"strongarm110",                        [ARMv4]>;
969def : ProcNoItin<"strongarm1100",                       [ARMv4]>;
970def : ProcNoItin<"strongarm1110",                       [ARMv4]>;
971
972def : ProcNoItin<"arm7tdmi",                            [ARMv4t]>;
973def : ProcNoItin<"arm7tdmi-s",                          [ARMv4t]>;
974def : ProcNoItin<"arm710t",                             [ARMv4t]>;
975def : ProcNoItin<"arm720t",                             [ARMv4t]>;
976def : ProcNoItin<"arm9",                                [ARMv4t]>;
977def : ProcNoItin<"arm9tdmi",                            [ARMv4t]>;
978def : ProcNoItin<"arm920",                              [ARMv4t]>;
979def : ProcNoItin<"arm920t",                             [ARMv4t]>;
980def : ProcNoItin<"arm922t",                             [ARMv4t]>;
981def : ProcNoItin<"arm940t",                             [ARMv4t]>;
982def : ProcNoItin<"ep9312",                              [ARMv4t]>;
983
984def : ProcNoItin<"arm10tdmi",                           [ARMv5t]>;
985def : ProcNoItin<"arm1020t",                            [ARMv5t]>;
986
987def : ProcNoItin<"arm9e",                               [ARMv5te]>;
988def : ProcNoItin<"arm926ej-s",                          [ARMv5te]>;
989def : ProcNoItin<"arm946e-s",                           [ARMv5te]>;
990def : ProcNoItin<"arm966e-s",                           [ARMv5te]>;
991def : ProcNoItin<"arm968e-s",                           [ARMv5te]>;
992def : ProcNoItin<"arm10e",                              [ARMv5te]>;
993def : ProcNoItin<"arm1020e",                            [ARMv5te]>;
994def : ProcNoItin<"arm1022e",                            [ARMv5te]>;
995def : ProcNoItin<"xscale",                              [ARMv5te]>;
996def : ProcNoItin<"iwmmxt",                              [ARMv5te]>;
997
998def : Processor<"arm1136j-s",       ARMV6Itineraries,   [ARMv6]>;
999def : Processor<"arm1136jf-s",      ARMV6Itineraries,   [ARMv6,
1000                                                         FeatureVFP2,
1001                                                         FeatureHasSlowFPVMLx]>;
1002
1003def : Processor<"cortex-m0",        ARMV6Itineraries,   [ARMv6m]>;
1004def : Processor<"cortex-m0plus",    ARMV6Itineraries,   [ARMv6m]>;
1005def : Processor<"cortex-m1",        ARMV6Itineraries,   [ARMv6m]>;
1006def : Processor<"sc000",            ARMV6Itineraries,   [ARMv6m]>;
1007
1008def : Processor<"arm1176j-s",       ARMV6Itineraries,   [ARMv6kz]>;
1009def : Processor<"arm1176jz-s",      ARMV6Itineraries,   [ARMv6kz]>;
1010def : Processor<"arm1176jzf-s",     ARMV6Itineraries,   [ARMv6kz,
1011                                                         FeatureVFP2,
1012                                                         FeatureHasSlowFPVMLx]>;
1013
1014def : Processor<"mpcorenovfp",      ARMV6Itineraries,   [ARMv6k]>;
1015def : Processor<"mpcore",           ARMV6Itineraries,   [ARMv6k,
1016                                                         FeatureVFP2,
1017                                                         FeatureHasSlowFPVMLx]>;
1018
1019def : Processor<"arm1156t2-s",      ARMV6Itineraries,   [ARMv6t2]>;
1020def : Processor<"arm1156t2f-s",     ARMV6Itineraries,   [ARMv6t2,
1021                                                         FeatureVFP2,
1022                                                         FeatureHasSlowFPVMLx]>;
1023
1024def : ProcessorModel<"cortex-a5",   CortexA8Model,      [ARMv7a, ProcA5,
1025                                                         FeatureHasRetAddrStack,
1026                                                         FeatureTrustZone,
1027                                                         FeatureSlowFPBrcc,
1028                                                         FeatureHasSlowFPVMLx,
1029                                                         FeatureHasSlowFPVFMx,
1030                                                         FeatureVMLxForwarding,
1031                                                         FeatureMP,
1032                                                         FeatureVFP4]>;
1033
1034def : ProcessorModel<"cortex-a7",   CortexA8Model,      [ARMv7a, ProcA7,
1035                                                         FeatureHasRetAddrStack,
1036                                                         FeatureTrustZone,
1037                                                         FeatureSlowFPBrcc,
1038                                                         FeatureHasVMLxHazards,
1039                                                         FeatureHasSlowFPVMLx,
1040                                                         FeatureHasSlowFPVFMx,
1041                                                         FeatureVMLxForwarding,
1042                                                         FeatureMP,
1043                                                         FeatureVFP4,
1044                                                         FeatureVirtualization]>;
1045
1046def : ProcessorModel<"cortex-a8",   CortexA8Model,      [ARMv7a, ProcA8,
1047                                                         FeatureHasRetAddrStack,
1048                                                         FeatureNonpipelinedVFP,
1049                                                         FeatureTrustZone,
1050                                                         FeatureSlowFPBrcc,
1051                                                         FeatureHasVMLxHazards,
1052                                                         FeatureHasSlowFPVMLx,
1053                                                         FeatureHasSlowFPVFMx,
1054                                                         FeatureVMLxForwarding]>;
1055
1056def : ProcessorModel<"cortex-a9",   CortexA9Model,      [ARMv7a, ProcA9,
1057                                                         FeatureHasRetAddrStack,
1058                                                         FeatureTrustZone,
1059                                                         FeatureHasVMLxHazards,
1060                                                         FeatureVMLxForwarding,
1061                                                         FeatureFP16,
1062                                                         FeatureAvoidPartialCPSR,
1063                                                         FeatureExpandMLx,
1064                                                         FeaturePreferVMOVSR,
1065                                                         FeatureMuxedUnits,
1066                                                         FeatureNEONForFPMovs,
1067                                                         FeatureCheckVLDnAlign,
1068                                                         FeatureMP]>;
1069
1070def : ProcessorModel<"cortex-a12",  CortexA9Model,      [ARMv7a, ProcA12,
1071                                                         FeatureHasRetAddrStack,
1072                                                         FeatureTrustZone,
1073                                                         FeatureVMLxForwarding,
1074                                                         FeatureVFP4,
1075                                                         FeatureAvoidPartialCPSR,
1076                                                         FeatureVirtualization,
1077                                                         FeatureMP]>;
1078
1079def : ProcessorModel<"cortex-a15",  CortexA9Model,      [ARMv7a, ProcA15,
1080                                                         FeatureDontWidenVMOVS,
1081                                                         FeatureSplatVFPToNeon,
1082                                                         FeatureHasRetAddrStack,
1083                                                         FeatureMuxedUnits,
1084                                                         FeatureTrustZone,
1085                                                         FeatureVFP4,
1086                                                         FeatureMP,
1087                                                         FeatureCheckVLDnAlign,
1088                                                         FeatureAvoidPartialCPSR,
1089                                                         FeatureVirtualization]>;
1090
1091def : ProcessorModel<"cortex-a17",  CortexA9Model,      [ARMv7a, ProcA17,
1092                                                         FeatureHasRetAddrStack,
1093                                                         FeatureTrustZone,
1094                                                         FeatureMP,
1095                                                         FeatureVMLxForwarding,
1096                                                         FeatureVFP4,
1097                                                         FeatureAvoidPartialCPSR,
1098                                                         FeatureVirtualization]>;
1099
1100// FIXME: krait has currently the same features as A9 plus VFP4 and  HWDiv
1101def : ProcessorModel<"krait",       CortexA9Model,      [ARMv7a, ProcKrait,
1102                                                         FeatureHasRetAddrStack,
1103                                                         FeatureMuxedUnits,
1104                                                         FeatureCheckVLDnAlign,
1105                                                         FeatureVMLxForwarding,
1106                                                         FeatureFP16,
1107                                                         FeatureAvoidPartialCPSR,
1108                                                         FeatureVFP4,
1109                                                         FeatureHWDivThumb,
1110                                                         FeatureHWDivARM]>;
1111
1112def : ProcessorModel<"swift",       SwiftModel,         [ARMv7a, ProcSwift,
1113                                                         FeatureHasRetAddrStack,
1114                                                         FeatureNEONForFP,
1115                                                         FeatureVFP4,
1116                                                         FeatureUseWideStrideVFP,
1117                                                         FeatureMP,
1118                                                         FeatureHWDivThumb,
1119                                                         FeatureHWDivARM,
1120                                                         FeatureAvoidPartialCPSR,
1121                                                         FeatureAvoidMOVsShOp,
1122                                                         FeatureHasSlowFPVMLx,
1123                                                         FeatureHasSlowFPVFMx,
1124                                                         FeatureHasVMLxHazards,
1125                                                         FeatureProfUnpredicate,
1126                                                         FeaturePrefISHSTBarrier,
1127                                                         FeatureSlowOddRegister,
1128                                                         FeatureSlowLoadDSubreg,
1129                                                         FeatureSlowVGETLNi32,
1130                                                         FeatureSlowVDUP32,
1131                                                         FeatureUseMISched,
1132                                                         FeatureNoPostRASched]>;
1133
1134def : ProcessorModel<"cortex-r4",   CortexA8Model,      [ARMv7r, ProcR4,
1135                                                         FeatureHasRetAddrStack,
1136                                                         FeatureAvoidPartialCPSR]>;
1137
1138def : ProcessorModel<"cortex-r4f",  CortexA8Model,      [ARMv7r, ProcR4,
1139                                                         FeatureHasRetAddrStack,
1140                                                         FeatureSlowFPBrcc,
1141                                                         FeatureHasSlowFPVMLx,
1142                                                         FeatureHasSlowFPVFMx,
1143                                                         FeatureVFP3_D16,
1144                                                         FeatureAvoidPartialCPSR]>;
1145
1146def : ProcessorModel<"cortex-r5",   CortexA8Model,      [ARMv7r, ProcR5,
1147                                                         FeatureHasRetAddrStack,
1148                                                         FeatureVFP3_D16,
1149                                                         FeatureSlowFPBrcc,
1150                                                         FeatureHWDivARM,
1151                                                         FeatureHasSlowFPVMLx,
1152                                                         FeatureHasSlowFPVFMx,
1153                                                         FeatureAvoidPartialCPSR]>;
1154
1155def : ProcessorModel<"cortex-r7",   CortexA8Model,      [ARMv7r, ProcR7,
1156                                                         FeatureHasRetAddrStack,
1157                                                         FeatureVFP3_D16,
1158                                                         FeatureFP16,
1159                                                         FeatureMP,
1160                                                         FeatureSlowFPBrcc,
1161                                                         FeatureHWDivARM,
1162                                                         FeatureHasSlowFPVMLx,
1163                                                         FeatureHasSlowFPVFMx,
1164                                                         FeatureAvoidPartialCPSR]>;
1165
1166def : ProcessorModel<"cortex-r8",   CortexA8Model,      [ARMv7r,
1167                                                         FeatureHasRetAddrStack,
1168                                                         FeatureVFP3_D16,
1169                                                         FeatureFP16,
1170                                                         FeatureMP,
1171                                                         FeatureSlowFPBrcc,
1172                                                         FeatureHWDivARM,
1173                                                         FeatureHasSlowFPVMLx,
1174                                                         FeatureHasSlowFPVFMx,
1175                                                         FeatureAvoidPartialCPSR]>;
1176
1177def : ProcessorModel<"cortex-m3",   CortexM4Model,      [ARMv7m,
1178                                                         ProcM3,
1179                                                         FeaturePrefLoopAlign32,
1180                                                         FeatureUseMISched,
1181                                                         FeatureHasNoBranchPredictor]>;
1182
1183def : ProcessorModel<"sc300",       CortexM4Model,      [ARMv7m,
1184                                                         ProcM3,
1185                                                         FeatureUseMISched,
1186                                                         FeatureHasNoBranchPredictor]>;
1187
1188def : ProcessorModel<"cortex-m4", CortexM4Model,        [ARMv7em,
1189                                                         FeatureVFP4_D16_SP,
1190                                                         FeaturePrefLoopAlign32,
1191                                                         FeatureHasSlowFPVMLx,
1192                                                         FeatureHasSlowFPVFMx,
1193                                                         FeatureUseMISched,
1194                                                         FeatureHasNoBranchPredictor]>;
1195
1196def : ProcessorModel<"cortex-m7", CortexM7Model,        [ARMv7em,
1197                                                         ProcM7,
1198                                                         FeatureFPARMv8_D16,
1199                                                         FeatureUseMISched]>;
1200
1201def : ProcNoItin<"cortex-m23",                          [ARMv8mBaseline,
1202                                                         FeatureNoMovt]>;
1203
1204def : ProcessorModel<"cortex-m33", CortexM4Model,       [ARMv8mMainline,
1205                                                         FeatureDSP,
1206                                                         FeatureFPARMv8_D16_SP,
1207                                                         FeaturePrefLoopAlign32,
1208                                                         FeatureHasSlowFPVMLx,
1209                                                         FeatureHasSlowFPVFMx,
1210                                                         FeatureUseMISched,
1211                                                         FeatureHasNoBranchPredictor]>;
1212
1213def : ProcessorModel<"cortex-m35p", CortexM4Model,      [ARMv8mMainline,
1214                                                         FeatureDSP,
1215                                                         FeatureFPARMv8_D16_SP,
1216                                                         FeaturePrefLoopAlign32,
1217                                                         FeatureHasSlowFPVMLx,
1218                                                         FeatureHasSlowFPVFMx,
1219                                                         FeatureUseMISched,
1220                                                         FeatureHasNoBranchPredictor]>;
1221
1222def : ProcessorModel<"cortex-m55", CortexM4Model,      [ARMv81mMainline,
1223                                                         FeatureDSP,
1224                                                         FeatureFPARMv8_D16,
1225                                                         FeatureUseMISched,
1226                                                         FeatureHasNoBranchPredictor,
1227                                                         FeaturePrefLoopAlign32,
1228                                                         FeatureHasSlowFPVMLx,
1229                                                         HasMVEFloatOps]>;
1230
1231def : ProcNoItin<"cortex-a32",                           [ARMv8a,
1232                                                         FeatureHWDivThumb,
1233                                                         FeatureHWDivARM,
1234                                                         FeatureCrypto,
1235                                                         FeatureCRC]>;
1236
1237def : ProcNoItin<"cortex-a35",                          [ARMv8a, ProcA35,
1238                                                         FeatureHWDivThumb,
1239                                                         FeatureHWDivARM,
1240                                                         FeatureCrypto,
1241                                                         FeatureCRC]>;
1242
1243def : ProcNoItin<"cortex-a53",                          [ARMv8a, ProcA53,
1244                                                         FeatureHWDivThumb,
1245                                                         FeatureHWDivARM,
1246                                                         FeatureCrypto,
1247                                                         FeatureCRC,
1248                                                         FeatureFPAO]>;
1249
1250def : ProcNoItin<"cortex-a55",                          [ARMv82a, ProcA55,
1251                                                         FeatureHWDivThumb,
1252                                                         FeatureHWDivARM,
1253                                                         FeatureDotProd]>;
1254
1255def : ProcessorModel<"cortex-a57",  CortexA57Model,     [ARMv8a, ProcA57,
1256                                                         FeatureHWDivThumb,
1257                                                         FeatureHWDivARM,
1258                                                         FeatureCrypto,
1259                                                         FeatureCRC,
1260                                                         FeatureFPAO,
1261                                                         FeatureAvoidPartialCPSR,
1262                                                         FeatureCheapPredicableCPSR]>;
1263
1264def : ProcessorModel<"cortex-a72",  CortexA57Model,     [ARMv8a, ProcA72,
1265                                                         FeatureHWDivThumb,
1266                                                         FeatureHWDivARM,
1267                                                         FeatureCrypto,
1268                                                         FeatureCRC]>;
1269
1270def : ProcNoItin<"cortex-a73",                          [ARMv8a, ProcA73,
1271                                                         FeatureHWDivThumb,
1272                                                         FeatureHWDivARM,
1273                                                         FeatureCrypto,
1274                                                         FeatureCRC]>;
1275
1276def : ProcNoItin<"cortex-a75",                          [ARMv82a, ProcA75,
1277                                                         FeatureHWDivThumb,
1278                                                         FeatureHWDivARM,
1279                                                         FeatureDotProd]>;
1280
1281def : ProcNoItin<"cortex-a76",                          [ARMv82a, ProcA76,
1282                                                         FeatureHWDivThumb,
1283                                                         FeatureHWDivARM,
1284                                                         FeatureCrypto,
1285                                                         FeatureCRC,
1286                                                         FeatureFullFP16,
1287                                                         FeatureDotProd]>;
1288
1289def : ProcNoItin<"cortex-a76ae",                        [ARMv82a, ProcA76,
1290                                                         FeatureHWDivThumb,
1291                                                         FeatureHWDivARM,
1292                                                         FeatureCrypto,
1293                                                         FeatureCRC,
1294                                                         FeatureFullFP16,
1295                                                         FeatureDotProd]>;
1296
1297def : ProcNoItin<"cortex-a77",                          [ARMv82a, ProcA77,
1298                                                         FeatureHWDivThumb,
1299                                                         FeatureHWDivARM,
1300                                                         FeatureCrypto,
1301                                                         FeatureCRC,
1302                                                         FeatureFullFP16,
1303                                                         FeatureDotProd]>;
1304
1305def : ProcNoItin<"cortex-a78",                          [ARMv82a, ProcA78,
1306                                                         FeatureHWDivThumb,
1307                                                         FeatureHWDivARM,
1308                                                         FeatureCrypto,
1309                                                         FeatureCRC,
1310                                                         FeatureFullFP16,
1311                                                         FeatureDotProd]>;
1312
1313def : ProcNoItin<"cortex-a78c",                         [ARMv82a, ProcA78C,
1314                                                         FeatureHWDivThumb,
1315                                                         FeatureHWDivARM,
1316                                                         FeatureCrypto,
1317                                                         FeatureCRC,
1318                                                         FeatureDotProd,
1319                                                         FeatureFullFP16]>;
1320
1321def : ProcNoItin<"cortex-x1",                           [ARMv82a, ProcX1,
1322                                                         FeatureHWDivThumb,
1323                                                         FeatureHWDivARM,
1324                                                         FeatureCrypto,
1325                                                         FeatureCRC,
1326                                                         FeatureFullFP16,
1327                                                         FeatureDotProd]>;
1328
1329def : ProcNoItin<"neoverse-v1",                         [ARMv84a,
1330                                                         FeatureHWDivThumb,
1331                                                         FeatureHWDivARM,
1332                                                         FeatureCrypto,
1333                                                         FeatureCRC,
1334                                                         FeatureFullFP16,
1335                                                         FeatureBF16,
1336                                                         FeatureMatMulInt8]>;
1337
1338def : ProcNoItin<"neoverse-n1",                         [ARMv82a,
1339                                                         FeatureHWDivThumb,
1340                                                         FeatureHWDivARM,
1341                                                         FeatureCrypto,
1342                                                         FeatureCRC,
1343                                                         FeatureDotProd]>;
1344
1345def : ProcNoItin<"neoverse-n2",                         [ARMv85a,
1346                                                         FeatureBF16,
1347                                                         FeatureMatMulInt8,
1348                                                         FeaturePerfMon]>;
1349
1350def : ProcessorModel<"cyclone",     SwiftModel,         [ARMv8a, ProcSwift,
1351                                                         FeatureHasRetAddrStack,
1352                                                         FeatureNEONForFP,
1353                                                         FeatureVFP4,
1354                                                         FeatureMP,
1355                                                         FeatureHWDivThumb,
1356                                                         FeatureHWDivARM,
1357                                                         FeatureAvoidPartialCPSR,
1358                                                         FeatureAvoidMOVsShOp,
1359                                                         FeatureHasSlowFPVMLx,
1360                                                         FeatureHasSlowFPVFMx,
1361                                                         FeatureCrypto,
1362                                                         FeatureUseMISched,
1363                                                         FeatureZCZeroing,
1364                                                         FeatureNoPostRASched]>;
1365
1366def : ProcNoItin<"exynos-m3",                           [ARMv8a, ProcExynos]>;
1367def : ProcNoItin<"exynos-m4",                           [ARMv82a, ProcExynos,
1368                                                         FeatureFullFP16,
1369                                                         FeatureDotProd]>;
1370def : ProcNoItin<"exynos-m5",                           [ARMv82a, ProcExynos,
1371                                                         FeatureFullFP16,
1372                                                         FeatureDotProd]>;
1373
1374def : ProcNoItin<"kryo",                                [ARMv8a, ProcKryo,
1375                                                         FeatureHWDivThumb,
1376                                                         FeatureHWDivARM,
1377                                                         FeatureCrypto,
1378                                                         FeatureCRC]>;
1379
1380def : ProcessorModel<"cortex-r52", CortexR52Model,      [ARMv8r, ProcR52,
1381                                                         FeatureUseMISched,
1382                                                         FeatureFPAO]>;
1383
1384//===----------------------------------------------------------------------===//
1385// Declare the target which we are implementing
1386//===----------------------------------------------------------------------===//
1387
1388def ARMAsmWriter : AsmWriter {
1389  string AsmWriterClassName  = "InstPrinter";
1390  int PassSubtarget = 1;
1391  int Variant = 0;
1392  bit isMCAsmWriter = 1;
1393}
1394
1395def ARMAsmParser : AsmParser {
1396  bit ReportMultipleNearMisses = 1;
1397}
1398
1399def ARMAsmParserVariant : AsmParserVariant {
1400  int Variant = 0;
1401  string Name = "ARM";
1402  string BreakCharacters = ".";
1403}
1404
1405def ARM : Target {
1406  // Pull in Instruction Info.
1407  let InstructionSet = ARMInstrInfo;
1408  let AssemblyWriters = [ARMAsmWriter];
1409  let AssemblyParsers = [ARMAsmParser];
1410  let AssemblyParserVariants = [ARMAsmParserVariant];
1411  let AllowRegisterRenaming = 1;
1412}
1413