1 //===-- SIProgramInfo.cpp ----------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// 11 /// The SIProgramInfo tracks resource usage and hardware flags for kernels and 12 /// entry functions. 13 // 14 //===----------------------------------------------------------------------===// 15 // 16 17 #include "SIProgramInfo.h" 18 #include "SIDefines.h" 19 #include "Utils/AMDGPUBaseInfo.h" 20 21 using namespace llvm; 22 23 uint64_t SIProgramInfo::getComputePGMRSrc1() const { 24 return S_00B848_VGPRS(VGPRBlocks) | S_00B848_SGPRS(SGPRBlocks) | 25 S_00B848_PRIORITY(Priority) | S_00B848_FLOAT_MODE(FloatMode) | 26 S_00B848_PRIV(Priv) | S_00B848_DX10_CLAMP(DX10Clamp) | 27 S_00B848_DEBUG_MODE(DebugMode) | S_00B848_IEEE_MODE(IEEEMode) | 28 S_00B848_WGP_MODE(WgpMode) | S_00B848_MEM_ORDERED(MemOrdered); 29 } 30 31 uint64_t SIProgramInfo::getPGMRSrc1(CallingConv::ID CC) const { 32 if (AMDGPU::isCompute(CC)) { 33 return getComputePGMRSrc1(); 34 } 35 uint64_t Reg = S_00B848_VGPRS(VGPRBlocks) | S_00B848_SGPRS(SGPRBlocks) | 36 S_00B848_PRIORITY(Priority) | S_00B848_FLOAT_MODE(FloatMode) | 37 S_00B848_PRIV(Priv) | S_00B848_DX10_CLAMP(DX10Clamp) | 38 S_00B848_DEBUG_MODE(DebugMode) | S_00B848_IEEE_MODE(IEEEMode); 39 switch (CC) { 40 case CallingConv::AMDGPU_PS: 41 Reg |= S_00B028_MEM_ORDERED(MemOrdered); 42 break; 43 case CallingConv::AMDGPU_VS: 44 Reg |= S_00B128_MEM_ORDERED(MemOrdered); 45 break; 46 case CallingConv::AMDGPU_GS: 47 Reg |= S_00B228_WGP_MODE(WgpMode) | S_00B228_MEM_ORDERED(MemOrdered); 48 break; 49 case CallingConv::AMDGPU_HS: 50 Reg |= S_00B428_WGP_MODE(WgpMode) | S_00B428_MEM_ORDERED(MemOrdered); 51 break; 52 default: 53 break; 54 } 55 return Reg; 56 } 57 58 uint64_t SIProgramInfo::getComputePGMRSrc2() const { 59 uint64_t Reg = 60 S_00B84C_SCRATCH_EN(ScratchEnable) | S_00B84C_USER_SGPR(UserSGPR) | 61 S_00B84C_TRAP_HANDLER(TrapHandlerEnable) | 62 S_00B84C_TGID_X_EN(TGIdXEnable) | S_00B84C_TGID_Y_EN(TGIdYEnable) | 63 S_00B84C_TGID_Z_EN(TGIdZEnable) | S_00B84C_TG_SIZE_EN(TGSizeEnable) | 64 S_00B84C_TIDIG_COMP_CNT(TIdIGCompCount) | 65 S_00B84C_EXCP_EN_MSB(EXCPEnMSB) | S_00B84C_LDS_SIZE(LdsSize) | 66 S_00B84C_EXCP_EN(EXCPEnable); 67 68 return Reg; 69 } 70 71 uint64_t SIProgramInfo::getPGMRSrc2(CallingConv::ID CC) const { 72 if (AMDGPU::isCompute(CC)) 73 return getComputePGMRSrc2(); 74 75 return 0; 76 } 77