1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// SI DAG Lowering interface definition 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 15 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 16 17 #include "AMDGPUISelLowering.h" 18 #include "AMDGPUArgumentUsageInfo.h" 19 #include "llvm/CodeGen/MachineFunction.h" 20 21 namespace llvm { 22 23 class GCNSubtarget; 24 class SIMachineFunctionInfo; 25 class SIRegisterInfo; 26 27 namespace AMDGPU { 28 struct ImageDimIntrinsicInfo; 29 } 30 31 class SITargetLowering final : public AMDGPUTargetLowering { 32 private: 33 const GCNSubtarget *Subtarget; 34 35 public: 36 MVT getRegisterTypeForCallingConv(LLVMContext &Context, 37 CallingConv::ID CC, 38 EVT VT) const override; 39 unsigned getNumRegistersForCallingConv(LLVMContext &Context, 40 CallingConv::ID CC, 41 EVT VT) const override; 42 43 unsigned getVectorTypeBreakdownForCallingConv( 44 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, 45 unsigned &NumIntermediates, MVT &RegisterVT) const override; 46 47 private: 48 SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL, 49 SDValue Chain, uint64_t Offset) const; 50 SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const; 51 SDValue getLDSKernelId(SelectionDAG &DAG, const SDLoc &SL) const; 52 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, 53 const SDLoc &SL, SDValue Chain, 54 uint64_t Offset, Align Alignment, 55 bool Signed, 56 const ISD::InputArg *Arg = nullptr) const; 57 SDValue loadImplicitKernelArgument(SelectionDAG &DAG, MVT VT, const SDLoc &DL, 58 Align Alignment, 59 ImplicitParameter Param) const; 60 61 SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA, 62 const SDLoc &SL, SDValue Chain, 63 const ISD::InputArg &Arg) const; 64 SDValue getPreloadedValue(SelectionDAG &DAG, 65 const SIMachineFunctionInfo &MFI, 66 EVT VT, 67 AMDGPUFunctionArgInfo::PreloadedValue) const; 68 69 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, 70 SelectionDAG &DAG) const override; 71 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op, 72 MVT VT, unsigned Offset) const; 73 SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr, 74 SelectionDAG &DAG, bool WithChain) const; 75 SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset, 76 SDValue CachePolicy, SelectionDAG &DAG) const; 77 78 SDValue lowerRawBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG, 79 unsigned NewOpcode) const; 80 SDValue lowerStructBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG, 81 unsigned NewOpcode) const; 82 83 SDValue lowerWorkitemID(SelectionDAG &DAG, SDValue Op, unsigned Dim, 84 const ArgDescriptor &ArgDesc) const; 85 86 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 87 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 88 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 89 90 // The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset 91 // (the offset that is included in bounds checking and swizzling, to be split 92 // between the instruction's voffset and immoffset fields) and soffset (the 93 // offset that is excluded from bounds checking and swizzling, to go in the 94 // instruction's soffset field). This function takes the first kind of 95 // offset and figures out how to split it between voffset and immoffset. 96 std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset, 97 SelectionDAG &DAG) const; 98 99 SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const; 100 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 101 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 102 SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const; 103 SDValue lowerFastUnsafeFDIV64(SDValue Op, SelectionDAG &DAG) const; 104 SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const; 105 SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const; 106 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const; 107 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const; 108 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const; 109 SDValue LowerFFREXP(SDValue Op, SelectionDAG &DAG) const; 110 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 111 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const; 112 SDValue lowerFSQRTF16(SDValue Op, SelectionDAG &DAG) const; 113 SDValue lowerFSQRTF32(SDValue Op, SelectionDAG &DAG) const; 114 SDValue lowerFSQRTF64(SDValue Op, SelectionDAG &DAG) const; 115 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 116 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 117 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 118 SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M, 119 SelectionDAG &DAG, ArrayRef<SDValue> Ops, 120 bool IsIntrinsic = false) const; 121 122 SDValue lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG, 123 ArrayRef<SDValue> Ops) const; 124 125 // Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to 126 // dwordx4 if on SI. 127 SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, 128 ArrayRef<SDValue> Ops, EVT MemVT, 129 MachineMemOperand *MMO, SelectionDAG &DAG) const; 130 131 SDValue handleD16VData(SDValue VData, SelectionDAG &DAG, 132 bool ImageStore = false) const; 133 134 /// Converts \p Op, which must be of floating point type, to the 135 /// floating point type \p VT, by either extending or truncating it. 136 SDValue getFPExtOrFPRound(SelectionDAG &DAG, 137 SDValue Op, 138 const SDLoc &DL, 139 EVT VT) const; 140 141 SDValue convertArgType( 142 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val, 143 bool Signed, const ISD::InputArg *Arg = nullptr) const; 144 145 /// Custom lowering for ISD::FP_ROUND for MVT::f16. 146 SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 147 SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const; 148 SDValue lowerFLDEXP(SDValue Op, SelectionDAG &DAG) const; 149 SDValue lowerMUL(SDValue Op, SelectionDAG &DAG) const; 150 SDValue lowerXMULO(SDValue Op, SelectionDAG &DAG) const; 151 SDValue lowerXMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 152 153 SDValue getSegmentAperture(unsigned AS, const SDLoc &DL, 154 SelectionDAG &DAG) const; 155 156 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const; 157 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 158 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 159 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 160 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 161 SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 162 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 163 164 SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const; 165 SDValue lowerTrapEndpgm(SDValue Op, SelectionDAG &DAG) const; 166 SDValue lowerTrapHsaQueuePtr(SDValue Op, SelectionDAG &DAG) const; 167 SDValue lowerTrapHsa(SDValue Op, SelectionDAG &DAG) const; 168 SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const; 169 170 SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const; 171 172 SDValue performUCharToFloatCombine(SDNode *N, 173 DAGCombinerInfo &DCI) const; 174 SDValue performFCopySignCombine(SDNode *N, DAGCombinerInfo &DCI) const; 175 176 SDValue performSHLPtrCombine(SDNode *N, 177 unsigned AS, 178 EVT MemVT, 179 DAGCombinerInfo &DCI) const; 180 181 SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const; 182 183 SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL, 184 unsigned Opc, SDValue LHS, 185 const ConstantSDNode *CRHS) const; 186 187 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const; 188 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const; 189 SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const; 190 SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const; 191 SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const; 192 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const; 193 SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT, 194 const APFloat &C) const; 195 SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const; 196 197 SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, 198 SDValue Op0, SDValue Op1) const; 199 SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, 200 SDValue Src, SDValue MinVal, SDValue MaxVal, 201 bool Signed) const; 202 SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const; 203 SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const; 204 SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const; 205 SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const; 206 SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const; 207 SDValue performFPRoundCombine(SDNode *N, DAGCombinerInfo &DCI) const; 208 209 SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const; 210 unsigned getFusedOpcode(const SelectionDAG &DAG, 211 const SDNode *N0, const SDNode *N1) const; 212 SDValue tryFoldToMad64_32(SDNode *N, DAGCombinerInfo &DCI) const; 213 SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; 214 SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const; 215 SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; 216 SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; 217 SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; 218 SDValue performFDivCombine(SDNode *N, DAGCombinerInfo &DCI) const; 219 SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const; 220 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const; 221 SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const; 222 SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const; 223 SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const; 224 225 bool isLegalFlatAddressingMode(const AddrMode &AM, unsigned AddrSpace, 226 uint64_t FlatVariant) const; 227 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const; 228 229 unsigned isCFIntrinsic(const SDNode *Intr) const; 230 231 public: 232 /// \returns True if fixup needs to be emitted for given global value \p GV, 233 /// false otherwise. 234 bool shouldEmitFixup(const GlobalValue *GV) const; 235 236 /// \returns True if GOT relocation needs to be emitted for given global value 237 /// \p GV, false otherwise. 238 bool shouldEmitGOTReloc(const GlobalValue *GV) const; 239 240 /// \returns True if PC-relative relocation needs to be emitted for given 241 /// global value \p GV, false otherwise. 242 bool shouldEmitPCReloc(const GlobalValue *GV) const; 243 244 /// \returns true if this should use a literal constant for an LDS address, 245 /// and not emit a relocation for an LDS global. 246 bool shouldUseLDSConstAddress(const GlobalValue *GV) const; 247 248 /// Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be 249 /// expanded into a set of cmp/select instructions. 250 static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem, 251 bool IsDivergentIdx, 252 const GCNSubtarget *Subtarget); 253 254 bool shouldExpandVectorDynExt(SDNode *N) const; 255 256 private: 257 // Analyze a combined offset from an amdgcn_buffer_ intrinsic and store the 258 // three offsets (voffset, soffset and instoffset) into the SDValue[3] array 259 // pointed to by Offsets. 260 void setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG, 261 SDValue *Offsets, Align Alignment = Align(4)) const; 262 263 // Convert the i128 that an addrspace(8) pointer is natively represented as 264 // into the v4i32 that all the buffer intrinsics expect to receive. We can't 265 // add register classes for i128 on pain of the promotion logic going haywire, 266 // so this slightly ugly hack is what we've got. If passed a non-pointer 267 // argument (as would be seen in older buffer intrinsics), does nothing. 268 SDValue bufferRsrcPtrToVector(SDValue MaybePointer, SelectionDAG &DAG) const; 269 270 // Wrap a 64-bit pointer into a v4i32 (which is how all SelectionDAG code 271 // represents ptr addrspace(8)) using the flags specified in the intrinsic. 272 SDValue lowerPointerAsRsrcIntrin(SDNode *Op, SelectionDAG &DAG) const; 273 274 // Handle 8 bit and 16 bit buffer loads 275 SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL, 276 ArrayRef<SDValue> Ops, MemSDNode *M) const; 277 278 // Handle 8 bit and 16 bit buffer stores 279 SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType, 280 SDLoc DL, SDValue Ops[], 281 MemSDNode *M) const; 282 283 public: 284 SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI); 285 286 const GCNSubtarget *getSubtarget() const; 287 288 bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, 289 EVT SrcVT) const override; 290 291 bool isFPExtFoldable(const MachineInstr &MI, unsigned Opcode, LLT DestTy, 292 LLT SrcTy) const override; 293 294 bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override; 295 296 // While address space 7 should never make it to codegen, it still needs to 297 // have a MVT to prevent some analyses that query this function from breaking, 298 // so, to work around the lack of i160, map it to v5i32. 299 MVT getPointerTy(const DataLayout &DL, unsigned AS) const override; 300 MVT getPointerMemTy(const DataLayout &DL, unsigned AS) const override; 301 302 bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, 303 MachineFunction &MF, 304 unsigned IntrinsicID) const override; 305 306 bool getAddrModeArguments(IntrinsicInst * /*I*/, 307 SmallVectorImpl<Value*> &/*Ops*/, 308 Type *&/*AccessTy*/) const override; 309 310 bool isLegalGlobalAddressingMode(const AddrMode &AM) const; 311 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 312 unsigned AS, 313 Instruction *I = nullptr) const override; 314 315 bool canMergeStoresTo(unsigned AS, EVT MemVT, 316 const MachineFunction &MF) const override; 317 318 bool allowsMisalignedMemoryAccessesImpl( 319 unsigned Size, unsigned AddrSpace, Align Alignment, 320 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 321 unsigned *IsFast = nullptr) const; 322 323 bool allowsMisalignedMemoryAccesses( 324 LLT Ty, unsigned AddrSpace, Align Alignment, 325 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 326 unsigned *IsFast = nullptr) const override { 327 if (IsFast) 328 *IsFast = 0; 329 return allowsMisalignedMemoryAccessesImpl(Ty.getSizeInBits(), AddrSpace, 330 Alignment, Flags, IsFast); 331 } 332 333 bool allowsMisalignedMemoryAccesses( 334 EVT VT, unsigned AS, Align Alignment, 335 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 336 unsigned *IsFast = nullptr) const override; 337 338 EVT getOptimalMemOpType(const MemOp &Op, 339 const AttributeList &FuncAttributes) const override; 340 341 bool isMemOpUniform(const SDNode *N) const; 342 bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const; 343 344 static bool isNonGlobalAddrSpace(unsigned AS); 345 346 bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 347 348 TargetLoweringBase::LegalizeTypeAction 349 getPreferredVectorAction(MVT VT) const override; 350 351 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 352 Type *Ty) const override; 353 354 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, 355 unsigned Index) const override; 356 357 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override; 358 359 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 360 361 unsigned combineRepeatedFPDivisors() const override { 362 // Combine multiple FDIVs with the same divisor into multiple FMULs by the 363 // reciprocal. 364 return 2; 365 } 366 367 bool supportSplitCSR(MachineFunction *MF) const override; 368 void initializeSplitCSR(MachineBasicBlock *Entry) const override; 369 void insertCopiesSplitCSR( 370 MachineBasicBlock *Entry, 371 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 372 373 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 374 bool isVarArg, 375 const SmallVectorImpl<ISD::InputArg> &Ins, 376 const SDLoc &DL, SelectionDAG &DAG, 377 SmallVectorImpl<SDValue> &InVals) const override; 378 379 bool CanLowerReturn(CallingConv::ID CallConv, 380 MachineFunction &MF, bool isVarArg, 381 const SmallVectorImpl<ISD::OutputArg> &Outs, 382 LLVMContext &Context) const override; 383 384 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 385 const SmallVectorImpl<ISD::OutputArg> &Outs, 386 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 387 SelectionDAG &DAG) const override; 388 389 void passSpecialInputs( 390 CallLoweringInfo &CLI, 391 CCState &CCInfo, 392 const SIMachineFunctionInfo &Info, 393 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass, 394 SmallVectorImpl<SDValue> &MemOpChains, 395 SDValue Chain) const; 396 397 SDValue LowerCallResult(SDValue Chain, SDValue InGlue, 398 CallingConv::ID CallConv, bool isVarArg, 399 const SmallVectorImpl<ISD::InputArg> &Ins, 400 const SDLoc &DL, SelectionDAG &DAG, 401 SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 402 SDValue ThisVal) const; 403 404 bool mayBeEmittedAsTailCall(const CallInst *) const override; 405 406 bool isEligibleForTailCallOptimization( 407 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, 408 const SmallVectorImpl<ISD::OutputArg> &Outs, 409 const SmallVectorImpl<SDValue> &OutVals, 410 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const; 411 412 SDValue LowerCall(CallLoweringInfo &CLI, 413 SmallVectorImpl<SDValue> &InVals) const override; 414 415 SDValue lowerDYNAMIC_STACKALLOCImpl(SDValue Op, SelectionDAG &DAG) const; 416 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 417 SDValue LowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const; 418 SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 419 420 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const; 421 SDValue lowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; 422 423 Register getRegisterByName(const char* RegName, LLT VT, 424 const MachineFunction &MF) const override; 425 426 MachineBasicBlock *splitKillBlock(MachineInstr &MI, 427 MachineBasicBlock *BB) const; 428 429 void bundleInstWithWaitcnt(MachineInstr &MI) const; 430 MachineBasicBlock *emitGWSMemViolTestLoop(MachineInstr &MI, 431 MachineBasicBlock *BB) const; 432 433 MachineBasicBlock * 434 EmitInstrWithCustomInserter(MachineInstr &MI, 435 MachineBasicBlock *BB) const override; 436 437 bool hasAtomicFaddRtnForTy(SDValue &Op) const; 438 bool enableAggressiveFMAFusion(EVT VT) const override; 439 bool enableAggressiveFMAFusion(LLT Ty) const override; 440 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 441 EVT VT) const override; 442 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override; 443 LLT getPreferredShiftAmountTy(LLT Ty) const override; 444 445 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 446 EVT VT) const override; 447 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 448 const LLT Ty) const override; 449 bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override; 450 bool isFMADLegal(const MachineInstr &MI, const LLT Ty) const override; 451 452 SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 453 SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 454 SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 455 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 456 457 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 458 SelectionDAG &DAG) const override; 459 460 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 461 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override; 462 void AddIMGInit(MachineInstr &MI) const; 463 void AdjustInstrPostInstrSelection(MachineInstr &MI, 464 SDNode *Node) const override; 465 466 SDNode *legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const; 467 468 MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, 469 SDValue Ptr) const; 470 MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, 471 uint32_t RsrcDword1, uint64_t RsrcDword2And3) const; 472 std::pair<unsigned, const TargetRegisterClass *> 473 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 474 StringRef Constraint, MVT VT) const override; 475 ConstraintType getConstraintType(StringRef Constraint) const override; 476 void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, 477 std::vector<SDValue> &Ops, 478 SelectionDAG &DAG) const override; 479 bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const; 480 bool checkAsmConstraintVal(SDValue Op, StringRef Constraint, 481 uint64_t Val) const; 482 bool checkAsmConstraintValA(SDValue Op, 483 uint64_t Val, 484 unsigned MaxSize = 64) const; 485 SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, 486 SDValue V) const; 487 488 void finalizeLowering(MachineFunction &MF) const override; 489 490 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, 491 const APInt &DemandedElts, 492 const SelectionDAG &DAG, 493 unsigned Depth = 0) const override; 494 void computeKnownBitsForFrameIndex(int FrameIdx, 495 KnownBits &Known, 496 const MachineFunction &MF) const override; 497 void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, Register R, 498 KnownBits &Known, 499 const APInt &DemandedElts, 500 const MachineRegisterInfo &MRI, 501 unsigned Depth = 0) const override; 502 503 Align computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R, 504 const MachineRegisterInfo &MRI, 505 unsigned Depth = 0) const override; 506 bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, 507 UniformityInfo *UA) const override; 508 509 bool hasMemSDNodeUser(SDNode *N) const; 510 511 bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, 512 SDValue N1) const override; 513 514 bool isReassocProfitable(MachineRegisterInfo &MRI, Register N0, 515 Register N1) const override; 516 517 bool isCanonicalized(SelectionDAG &DAG, SDValue Op, 518 unsigned MaxDepth = 5) const; 519 bool isCanonicalized(Register Reg, MachineFunction &MF, 520 unsigned MaxDepth = 5) const; 521 bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const; 522 bool denormalsEnabledForType(LLT Ty, MachineFunction &MF) const; 523 524 bool checkForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, 525 const TargetRegisterInfo *TRI, 526 const TargetInstrInfo *TII, unsigned &PhysReg, 527 int &Cost) const override; 528 529 bool isKnownNeverNaNForTargetNode(SDValue Op, 530 const SelectionDAG &DAG, 531 bool SNaN = false, 532 unsigned Depth = 0) const override; 533 AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override; 534 AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override; 535 AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override; 536 AtomicExpansionKind 537 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override; 538 void emitExpandAtomicRMW(AtomicRMWInst *AI) const override; 539 540 LoadInst * 541 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override; 542 543 const TargetRegisterClass *getRegClassFor(MVT VT, 544 bool isDivergent) const override; 545 bool requiresUniformRegister(MachineFunction &MF, 546 const Value *V) const override; 547 Align getPrefLoopAlignment(MachineLoop *ML) const override; 548 549 void allocateHSAUserSGPRs(CCState &CCInfo, 550 MachineFunction &MF, 551 const SIRegisterInfo &TRI, 552 SIMachineFunctionInfo &Info) const; 553 554 void allocatePreloadKernArgSGPRs(CCState &CCInfo, 555 SmallVectorImpl<CCValAssign> &ArgLocs, 556 const SmallVectorImpl<ISD::InputArg> &Ins, 557 MachineFunction &MF, 558 const SIRegisterInfo &TRI, 559 SIMachineFunctionInfo &Info) const; 560 561 void allocateLDSKernelId(CCState &CCInfo, MachineFunction &MF, 562 const SIRegisterInfo &TRI, 563 SIMachineFunctionInfo &Info) const; 564 565 void allocateSystemSGPRs(CCState &CCInfo, 566 MachineFunction &MF, 567 SIMachineFunctionInfo &Info, 568 CallingConv::ID CallConv, 569 bool IsShader) const; 570 571 void allocateSpecialEntryInputVGPRs(CCState &CCInfo, 572 MachineFunction &MF, 573 const SIRegisterInfo &TRI, 574 SIMachineFunctionInfo &Info) const; 575 void allocateSpecialInputSGPRs( 576 CCState &CCInfo, 577 MachineFunction &MF, 578 const SIRegisterInfo &TRI, 579 SIMachineFunctionInfo &Info) const; 580 581 void allocateSpecialInputVGPRs(CCState &CCInfo, 582 MachineFunction &MF, 583 const SIRegisterInfo &TRI, 584 SIMachineFunctionInfo &Info) const; 585 void allocateSpecialInputVGPRsFixed(CCState &CCInfo, 586 MachineFunction &MF, 587 const SIRegisterInfo &TRI, 588 SIMachineFunctionInfo &Info) const; 589 590 MachineMemOperand::Flags 591 getTargetMMOFlags(const Instruction &I) const override; 592 }; 593 594 // Returns true if argument is a boolean value which is not serialized into 595 // memory or argument and does not require v_cndmask_b32 to be deserialized. 596 bool isBoolSGPR(SDValue V); 597 598 } // End namespace llvm 599 600 #endif 601