1 //===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides AMDGPU specific target streamer methods. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AMDGPUTargetStreamer.h" 14 #include "AMDGPUPTNote.h" 15 #include "AMDKernelCodeT.h" 16 #include "Utils/AMDGPUBaseInfo.h" 17 #include "Utils/AMDKernelCodeTUtils.h" 18 #include "llvm/BinaryFormat/AMDGPUMetadataVerifier.h" 19 #include "llvm/BinaryFormat/ELF.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCELFStreamer.h" 22 #include "llvm/MC/MCSectionELF.h" 23 #include "llvm/Support/AMDGPUMetadata.h" 24 #include "llvm/Support/AMDHSAKernelDescriptor.h" 25 #include "llvm/Support/FormattedStream.h" 26 27 using namespace llvm; 28 using namespace llvm::AMDGPU; 29 30 //===----------------------------------------------------------------------===// 31 // AMDGPUTargetStreamer 32 //===----------------------------------------------------------------------===// 33 34 static void convertIsaVersionV2(uint32_t &Major, uint32_t &Minor, 35 uint32_t &Stepping, bool Sramecc, bool Xnack) { 36 if (Major == 9 && Minor == 0) { 37 switch (Stepping) { 38 case 0: 39 case 2: 40 case 4: 41 case 6: 42 if (Xnack) 43 Stepping++; 44 } 45 } 46 } 47 48 bool AMDGPUTargetStreamer::EmitHSAMetadataV2(StringRef HSAMetadataString) { 49 HSAMD::Metadata HSAMetadata; 50 if (HSAMD::fromString(HSAMetadataString, HSAMetadata)) 51 return false; 52 return EmitHSAMetadata(HSAMetadata); 53 } 54 55 bool AMDGPUTargetStreamer::EmitHSAMetadataV3(StringRef HSAMetadataString) { 56 msgpack::Document HSAMetadataDoc; 57 if (!HSAMetadataDoc.fromYAML(HSAMetadataString)) 58 return false; 59 return EmitHSAMetadata(HSAMetadataDoc, false); 60 } 61 62 StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) { 63 AMDGPU::GPUKind AK; 64 65 switch (ElfMach) { 66 default: llvm_unreachable("Unhandled ELF::EF_AMDGPU type"); 67 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break; 68 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break; 69 case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break; 70 case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break; 71 case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break; 72 case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break; 73 case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break; 74 case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break; 75 case ELF::EF_AMDGPU_MACH_R600_CYPRESS: AK = GK_CYPRESS; break; 76 case ELF::EF_AMDGPU_MACH_R600_JUNIPER: AK = GK_JUNIPER; break; 77 case ELF::EF_AMDGPU_MACH_R600_REDWOOD: AK = GK_REDWOOD; break; 78 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break; 79 case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break; 80 case ELF::EF_AMDGPU_MACH_R600_CAICOS: AK = GK_CAICOS; break; 81 case ELF::EF_AMDGPU_MACH_R600_CAYMAN: AK = GK_CAYMAN; break; 82 case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break; 83 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: AK = GK_GFX600; break; 84 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: AK = GK_GFX601; break; 85 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX602: AK = GK_GFX602; break; 86 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: AK = GK_GFX700; break; 87 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: AK = GK_GFX701; break; 88 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: AK = GK_GFX702; break; 89 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: AK = GK_GFX703; break; 90 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: AK = GK_GFX704; break; 91 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX705: AK = GK_GFX705; break; 92 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: AK = GK_GFX801; break; 93 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: AK = GK_GFX802; break; 94 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: AK = GK_GFX803; break; 95 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX805: AK = GK_GFX805; break; 96 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: AK = GK_GFX810; break; 97 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: AK = GK_GFX900; break; 98 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break; 99 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break; 100 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break; 101 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX908: AK = GK_GFX908; break; 102 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: AK = GK_GFX909; break; 103 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A: AK = GK_GFX90A; break; 104 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C: AK = GK_GFX90C; break; 105 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010: AK = GK_GFX1010; break; 106 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011: AK = GK_GFX1011; break; 107 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012: AK = GK_GFX1012; break; 108 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013: AK = GK_GFX1013; break; 109 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030: AK = GK_GFX1030; break; 110 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031: AK = GK_GFX1031; break; 111 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032: AK = GK_GFX1032; break; 112 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033: AK = GK_GFX1033; break; 113 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034: AK = GK_GFX1034; break; 114 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035: AK = GK_GFX1035; break; 115 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break; 116 } 117 118 StringRef GPUName = getArchNameAMDGCN(AK); 119 if (GPUName != "") 120 return GPUName; 121 return getArchNameR600(AK); 122 } 123 124 unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) { 125 AMDGPU::GPUKind AK = parseArchAMDGCN(GPU); 126 if (AK == AMDGPU::GPUKind::GK_NONE) 127 AK = parseArchR600(GPU); 128 129 switch (AK) { 130 case GK_R600: return ELF::EF_AMDGPU_MACH_R600_R600; 131 case GK_R630: return ELF::EF_AMDGPU_MACH_R600_R630; 132 case GK_RS880: return ELF::EF_AMDGPU_MACH_R600_RS880; 133 case GK_RV670: return ELF::EF_AMDGPU_MACH_R600_RV670; 134 case GK_RV710: return ELF::EF_AMDGPU_MACH_R600_RV710; 135 case GK_RV730: return ELF::EF_AMDGPU_MACH_R600_RV730; 136 case GK_RV770: return ELF::EF_AMDGPU_MACH_R600_RV770; 137 case GK_CEDAR: return ELF::EF_AMDGPU_MACH_R600_CEDAR; 138 case GK_CYPRESS: return ELF::EF_AMDGPU_MACH_R600_CYPRESS; 139 case GK_JUNIPER: return ELF::EF_AMDGPU_MACH_R600_JUNIPER; 140 case GK_REDWOOD: return ELF::EF_AMDGPU_MACH_R600_REDWOOD; 141 case GK_SUMO: return ELF::EF_AMDGPU_MACH_R600_SUMO; 142 case GK_BARTS: return ELF::EF_AMDGPU_MACH_R600_BARTS; 143 case GK_CAICOS: return ELF::EF_AMDGPU_MACH_R600_CAICOS; 144 case GK_CAYMAN: return ELF::EF_AMDGPU_MACH_R600_CAYMAN; 145 case GK_TURKS: return ELF::EF_AMDGPU_MACH_R600_TURKS; 146 case GK_GFX600: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX600; 147 case GK_GFX601: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX601; 148 case GK_GFX602: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX602; 149 case GK_GFX700: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX700; 150 case GK_GFX701: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX701; 151 case GK_GFX702: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX702; 152 case GK_GFX703: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX703; 153 case GK_GFX704: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX704; 154 case GK_GFX705: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX705; 155 case GK_GFX801: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX801; 156 case GK_GFX802: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX802; 157 case GK_GFX803: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX803; 158 case GK_GFX805: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX805; 159 case GK_GFX810: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX810; 160 case GK_GFX900: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX900; 161 case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902; 162 case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904; 163 case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906; 164 case GK_GFX908: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX908; 165 case GK_GFX909: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX909; 166 case GK_GFX90A: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A; 167 case GK_GFX90C: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C; 168 case GK_GFX1010: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010; 169 case GK_GFX1011: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011; 170 case GK_GFX1012: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012; 171 case GK_GFX1013: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013; 172 case GK_GFX1030: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030; 173 case GK_GFX1031: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031; 174 case GK_GFX1032: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032; 175 case GK_GFX1033: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033; 176 case GK_GFX1034: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034; 177 case GK_GFX1035: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035; 178 case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE; 179 } 180 181 llvm_unreachable("unknown GPU"); 182 } 183 184 //===----------------------------------------------------------------------===// 185 // AMDGPUTargetAsmStreamer 186 //===----------------------------------------------------------------------===// 187 188 AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer(MCStreamer &S, 189 formatted_raw_ostream &OS) 190 : AMDGPUTargetStreamer(S), OS(OS) { } 191 192 // A hook for emitting stuff at the end. 193 // We use it for emitting the accumulated PAL metadata as directives. 194 // The PAL metadata is reset after it is emitted. 195 void AMDGPUTargetAsmStreamer::finish() { 196 std::string S; 197 getPALMetadata()->toString(S); 198 OS << S; 199 200 // Reset the pal metadata so its data will not affect a compilation that 201 // reuses this object. 202 getPALMetadata()->reset(); 203 } 204 205 void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget() { 206 OS << "\t.amdgcn_target \"" << getTargetID()->toString() << "\"\n"; 207 } 208 209 void AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion( 210 uint32_t Major, uint32_t Minor) { 211 OS << "\t.hsa_code_object_version " << 212 Twine(Major) << "," << Twine(Minor) << '\n'; 213 } 214 215 void 216 AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISAV2(uint32_t Major, 217 uint32_t Minor, 218 uint32_t Stepping, 219 StringRef VendorName, 220 StringRef ArchName) { 221 convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny()); 222 OS << "\t.hsa_code_object_isa " << Twine(Major) << "," << Twine(Minor) << "," 223 << Twine(Stepping) << ",\"" << VendorName << "\",\"" << ArchName << "\"\n"; 224 } 225 226 void 227 AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 228 OS << "\t.amd_kernel_code_t\n"; 229 dumpAmdKernelCode(&Header, OS, "\t\t"); 230 OS << "\t.end_amd_kernel_code_t\n"; 231 } 232 233 void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 234 unsigned Type) { 235 switch (Type) { 236 default: llvm_unreachable("Invalid AMDGPU symbol type"); 237 case ELF::STT_AMDGPU_HSA_KERNEL: 238 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ; 239 break; 240 } 241 } 242 243 void AMDGPUTargetAsmStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size, 244 Align Alignment) { 245 OS << "\t.amdgpu_lds " << Symbol->getName() << ", " << Size << ", " 246 << Alignment.value() << '\n'; 247 } 248 249 bool AMDGPUTargetAsmStreamer::EmitISAVersion() { 250 OS << "\t.amd_amdgpu_isa \"" << getTargetID()->toString() << "\"\n"; 251 return true; 252 } 253 254 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 255 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 256 std::string HSAMetadataString; 257 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 258 return false; 259 260 OS << '\t' << HSAMD::AssemblerDirectiveBegin << '\n'; 261 OS << HSAMetadataString << '\n'; 262 OS << '\t' << HSAMD::AssemblerDirectiveEnd << '\n'; 263 return true; 264 } 265 266 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata( 267 msgpack::Document &HSAMetadataDoc, bool Strict) { 268 HSAMD::V3::MetadataVerifier Verifier(Strict); 269 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 270 return false; 271 272 std::string HSAMetadataString; 273 raw_string_ostream StrOS(HSAMetadataString); 274 HSAMetadataDoc.toYAML(StrOS); 275 276 OS << '\t' << HSAMD::V3::AssemblerDirectiveBegin << '\n'; 277 OS << StrOS.str() << '\n'; 278 OS << '\t' << HSAMD::V3::AssemblerDirectiveEnd << '\n'; 279 return true; 280 } 281 282 bool AMDGPUTargetAsmStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) { 283 const uint32_t Encoded_s_code_end = 0xbf9f0000; 284 const uint32_t Encoded_s_nop = 0xbf800000; 285 uint32_t Encoded_pad = Encoded_s_code_end; 286 287 // Instruction cache line size in bytes. 288 const unsigned Log2CacheLineSize = 6; 289 const unsigned CacheLineSize = 1u << Log2CacheLineSize; 290 291 // Extra padding amount in bytes to support prefetch mode 3. 292 unsigned FillSize = 3 * CacheLineSize; 293 294 if (AMDGPU::isGFX90A(STI)) { 295 Encoded_pad = Encoded_s_nop; 296 FillSize = 16 * CacheLineSize; 297 } 298 299 OS << "\t.p2alignl " << Log2CacheLineSize << ", " << Encoded_pad << '\n'; 300 OS << "\t.fill " << (FillSize / 4) << ", 4, " << Encoded_pad << '\n'; 301 return true; 302 } 303 304 void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor( 305 const MCSubtargetInfo &STI, StringRef KernelName, 306 const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR, 307 bool ReserveVCC, bool ReserveFlatScr) { 308 IsaVersion IVersion = getIsaVersion(STI.getCPU()); 309 310 OS << "\t.amdhsa_kernel " << KernelName << '\n'; 311 312 #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \ 313 STREAM << "\t\t" << DIRECTIVE << " " \ 314 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n'; 315 316 OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size 317 << '\n'; 318 OS << "\t\t.amdhsa_private_segment_fixed_size " 319 << KD.private_segment_fixed_size << '\n'; 320 OS << "\t\t.amdhsa_kernarg_size " << KD.kernarg_size << '\n'; 321 322 PRINT_FIELD(OS, ".amdhsa_user_sgpr_count", KD, 323 compute_pgm_rsrc2, 324 amdhsa::COMPUTE_PGM_RSRC2_USER_SGPR_COUNT); 325 326 if (!hasArchitectedFlatScratch(STI)) 327 PRINT_FIELD( 328 OS, ".amdhsa_user_sgpr_private_segment_buffer", KD, 329 kernel_code_properties, 330 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 331 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD, 332 kernel_code_properties, 333 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 334 PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD, 335 kernel_code_properties, 336 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 337 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD, 338 kernel_code_properties, 339 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 340 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD, 341 kernel_code_properties, 342 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 343 if (!hasArchitectedFlatScratch(STI)) 344 PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD, 345 kernel_code_properties, 346 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 347 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD, 348 kernel_code_properties, 349 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 350 if (IVersion.Major >= 10) 351 PRINT_FIELD(OS, ".amdhsa_wavefront_size32", KD, 352 kernel_code_properties, 353 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 354 PRINT_FIELD(OS, 355 (hasArchitectedFlatScratch(STI) 356 ? ".amdhsa_enable_private_segment" 357 : ".amdhsa_system_sgpr_private_segment_wavefront_offset"), 358 KD, compute_pgm_rsrc2, 359 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 360 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD, 361 compute_pgm_rsrc2, 362 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 363 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD, 364 compute_pgm_rsrc2, 365 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 366 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD, 367 compute_pgm_rsrc2, 368 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 369 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD, 370 compute_pgm_rsrc2, 371 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 372 PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD, 373 compute_pgm_rsrc2, 374 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 375 376 // These directives are required. 377 OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n'; 378 OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n'; 379 380 if (AMDGPU::isGFX90A(STI)) 381 OS << "\t\t.amdhsa_accum_offset " << 382 (AMDHSA_BITS_GET(KD.compute_pgm_rsrc3, 383 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4 384 << '\n'; 385 386 if (!ReserveVCC) 387 OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n'; 388 if (IVersion.Major >= 7 && !ReserveFlatScr && !hasArchitectedFlatScratch(STI)) 389 OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n'; 390 391 if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(&STI)) { 392 switch (*HsaAbiVer) { 393 default: 394 break; 395 case ELF::ELFABIVERSION_AMDGPU_HSA_V2: 396 break; 397 case ELF::ELFABIVERSION_AMDGPU_HSA_V3: 398 case ELF::ELFABIVERSION_AMDGPU_HSA_V4: 399 case ELF::ELFABIVERSION_AMDGPU_HSA_V5: 400 if (getTargetID()->isXnackSupported()) 401 OS << "\t\t.amdhsa_reserve_xnack_mask " << getTargetID()->isXnackOnOrAny() << '\n'; 402 break; 403 } 404 } 405 406 PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD, 407 compute_pgm_rsrc1, 408 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 409 PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD, 410 compute_pgm_rsrc1, 411 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 412 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD, 413 compute_pgm_rsrc1, 414 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 415 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD, 416 compute_pgm_rsrc1, 417 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 418 PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD, 419 compute_pgm_rsrc1, 420 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 421 PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD, 422 compute_pgm_rsrc1, 423 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 424 if (IVersion.Major >= 9) 425 PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD, 426 compute_pgm_rsrc1, 427 amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL); 428 if (AMDGPU::isGFX90A(STI)) 429 PRINT_FIELD(OS, ".amdhsa_tg_split", KD, 430 compute_pgm_rsrc3, 431 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT); 432 if (IVersion.Major >= 10) { 433 PRINT_FIELD(OS, ".amdhsa_workgroup_processor_mode", KD, 434 compute_pgm_rsrc1, 435 amdhsa::COMPUTE_PGM_RSRC1_WGP_MODE); 436 PRINT_FIELD(OS, ".amdhsa_memory_ordered", KD, 437 compute_pgm_rsrc1, 438 amdhsa::COMPUTE_PGM_RSRC1_MEM_ORDERED); 439 PRINT_FIELD(OS, ".amdhsa_forward_progress", KD, 440 compute_pgm_rsrc1, 441 amdhsa::COMPUTE_PGM_RSRC1_FWD_PROGRESS); 442 } 443 PRINT_FIELD( 444 OS, ".amdhsa_exception_fp_ieee_invalid_op", KD, 445 compute_pgm_rsrc2, 446 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 447 PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD, 448 compute_pgm_rsrc2, 449 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 450 PRINT_FIELD( 451 OS, ".amdhsa_exception_fp_ieee_div_zero", KD, 452 compute_pgm_rsrc2, 453 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 454 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD, 455 compute_pgm_rsrc2, 456 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 457 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD, 458 compute_pgm_rsrc2, 459 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 460 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD, 461 compute_pgm_rsrc2, 462 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 463 PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD, 464 compute_pgm_rsrc2, 465 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 466 #undef PRINT_FIELD 467 468 OS << "\t.end_amdhsa_kernel\n"; 469 } 470 471 //===----------------------------------------------------------------------===// 472 // AMDGPUTargetELFStreamer 473 //===----------------------------------------------------------------------===// 474 475 AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer(MCStreamer &S, 476 const MCSubtargetInfo &STI) 477 : AMDGPUTargetStreamer(S), STI(STI), Streamer(S) {} 478 479 MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() { 480 return static_cast<MCELFStreamer &>(Streamer); 481 } 482 483 // A hook for emitting stuff at the end. 484 // We use it for emitting the accumulated PAL metadata as a .note record. 485 // The PAL metadata is reset after it is emitted. 486 void AMDGPUTargetELFStreamer::finish() { 487 MCAssembler &MCA = getStreamer().getAssembler(); 488 MCA.setELFHeaderEFlags(getEFlags()); 489 490 std::string Blob; 491 const char *Vendor = getPALMetadata()->getVendor(); 492 unsigned Type = getPALMetadata()->getType(); 493 getPALMetadata()->toBlob(Type, Blob); 494 if (Blob.empty()) 495 return; 496 EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type, 497 [&](MCELFStreamer &OS) { OS.emitBytes(Blob); }); 498 499 // Reset the pal metadata so its data will not affect a compilation that 500 // reuses this object. 501 getPALMetadata()->reset(); 502 } 503 504 void AMDGPUTargetELFStreamer::EmitNote( 505 StringRef Name, const MCExpr *DescSZ, unsigned NoteType, 506 function_ref<void(MCELFStreamer &)> EmitDesc) { 507 auto &S = getStreamer(); 508 auto &Context = S.getContext(); 509 510 auto NameSZ = Name.size() + 1; 511 512 unsigned NoteFlags = 0; 513 // TODO Apparently, this is currently needed for OpenCL as mentioned in 514 // https://reviews.llvm.org/D74995 515 if (STI.getTargetTriple().getOS() == Triple::AMDHSA) 516 NoteFlags = ELF::SHF_ALLOC; 517 518 S.PushSection(); 519 S.SwitchSection( 520 Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags)); 521 S.emitInt32(NameSZ); // namesz 522 S.emitValue(DescSZ, 4); // descz 523 S.emitInt32(NoteType); // type 524 S.emitBytes(Name); // name 525 S.emitValueToAlignment(4, 0, 1, 0); // padding 0 526 EmitDesc(S); // desc 527 S.emitValueToAlignment(4, 0, 1, 0); // padding 0 528 S.PopSection(); 529 } 530 531 unsigned AMDGPUTargetELFStreamer::getEFlags() { 532 switch (STI.getTargetTriple().getArch()) { 533 default: 534 llvm_unreachable("Unsupported Arch"); 535 case Triple::r600: 536 return getEFlagsR600(); 537 case Triple::amdgcn: 538 return getEFlagsAMDGCN(); 539 } 540 } 541 542 unsigned AMDGPUTargetELFStreamer::getEFlagsR600() { 543 assert(STI.getTargetTriple().getArch() == Triple::r600); 544 545 return getElfMach(STI.getCPU()); 546 } 547 548 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDGCN() { 549 assert(STI.getTargetTriple().getArch() == Triple::amdgcn); 550 551 switch (STI.getTargetTriple().getOS()) { 552 default: 553 // TODO: Why are some tests have "mingw" listed as OS? 554 // llvm_unreachable("Unsupported OS"); 555 case Triple::UnknownOS: 556 return getEFlagsUnknownOS(); 557 case Triple::AMDHSA: 558 return getEFlagsAMDHSA(); 559 case Triple::AMDPAL: 560 return getEFlagsAMDPAL(); 561 case Triple::Mesa3D: 562 return getEFlagsMesa3D(); 563 } 564 } 565 566 unsigned AMDGPUTargetELFStreamer::getEFlagsUnknownOS() { 567 // TODO: Why are some tests have "mingw" listed as OS? 568 // assert(STI.getTargetTriple().getOS() == Triple::UnknownOS); 569 570 return getEFlagsV3(); 571 } 572 573 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDHSA() { 574 assert(STI.getTargetTriple().getOS() == Triple::AMDHSA); 575 576 if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(&STI)) { 577 switch (*HsaAbiVer) { 578 case ELF::ELFABIVERSION_AMDGPU_HSA_V2: 579 case ELF::ELFABIVERSION_AMDGPU_HSA_V3: 580 return getEFlagsV3(); 581 case ELF::ELFABIVERSION_AMDGPU_HSA_V4: 582 case ELF::ELFABIVERSION_AMDGPU_HSA_V5: 583 return getEFlagsV4(); 584 } 585 } 586 587 llvm_unreachable("HSA OS ABI Version identification must be defined"); 588 } 589 590 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDPAL() { 591 assert(STI.getTargetTriple().getOS() == Triple::AMDPAL); 592 593 return getEFlagsV3(); 594 } 595 596 unsigned AMDGPUTargetELFStreamer::getEFlagsMesa3D() { 597 assert(STI.getTargetTriple().getOS() == Triple::Mesa3D); 598 599 return getEFlagsV3(); 600 } 601 602 unsigned AMDGPUTargetELFStreamer::getEFlagsV3() { 603 unsigned EFlagsV3 = 0; 604 605 // mach. 606 EFlagsV3 |= getElfMach(STI.getCPU()); 607 608 // xnack. 609 if (getTargetID()->isXnackOnOrAny()) 610 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_XNACK_V3; 611 // sramecc. 612 if (getTargetID()->isSramEccOnOrAny()) 613 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_V3; 614 615 return EFlagsV3; 616 } 617 618 unsigned AMDGPUTargetELFStreamer::getEFlagsV4() { 619 unsigned EFlagsV4 = 0; 620 621 // mach. 622 EFlagsV4 |= getElfMach(STI.getCPU()); 623 624 // xnack. 625 switch (getTargetID()->getXnackSetting()) { 626 case AMDGPU::IsaInfo::TargetIDSetting::Unsupported: 627 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4; 628 break; 629 case AMDGPU::IsaInfo::TargetIDSetting::Any: 630 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ANY_V4; 631 break; 632 case AMDGPU::IsaInfo::TargetIDSetting::Off: 633 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_OFF_V4; 634 break; 635 case AMDGPU::IsaInfo::TargetIDSetting::On: 636 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ON_V4; 637 break; 638 } 639 // sramecc. 640 switch (getTargetID()->getSramEccSetting()) { 641 case AMDGPU::IsaInfo::TargetIDSetting::Unsupported: 642 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4; 643 break; 644 case AMDGPU::IsaInfo::TargetIDSetting::Any: 645 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ANY_V4; 646 break; 647 case AMDGPU::IsaInfo::TargetIDSetting::Off: 648 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_OFF_V4; 649 break; 650 case AMDGPU::IsaInfo::TargetIDSetting::On: 651 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ON_V4; 652 break; 653 } 654 655 return EFlagsV4; 656 } 657 658 void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget() {} 659 660 void AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion( 661 uint32_t Major, uint32_t Minor) { 662 663 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(8, getContext()), 664 ELF::NT_AMD_HSA_CODE_OBJECT_VERSION, [&](MCELFStreamer &OS) { 665 OS.emitInt32(Major); 666 OS.emitInt32(Minor); 667 }); 668 } 669 670 void 671 AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISAV2(uint32_t Major, 672 uint32_t Minor, 673 uint32_t Stepping, 674 StringRef VendorName, 675 StringRef ArchName) { 676 uint16_t VendorNameSize = VendorName.size() + 1; 677 uint16_t ArchNameSize = ArchName.size() + 1; 678 679 unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) + 680 sizeof(Major) + sizeof(Minor) + sizeof(Stepping) + 681 VendorNameSize + ArchNameSize; 682 683 convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny()); 684 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(DescSZ, getContext()), 685 ELF::NT_AMD_HSA_ISA_VERSION, [&](MCELFStreamer &OS) { 686 OS.emitInt16(VendorNameSize); 687 OS.emitInt16(ArchNameSize); 688 OS.emitInt32(Major); 689 OS.emitInt32(Minor); 690 OS.emitInt32(Stepping); 691 OS.emitBytes(VendorName); 692 OS.emitInt8(0); // NULL terminate VendorName 693 OS.emitBytes(ArchName); 694 OS.emitInt8(0); // NULL terminte ArchName 695 }); 696 } 697 698 void 699 AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) { 700 701 MCStreamer &OS = getStreamer(); 702 OS.PushSection(); 703 OS.emitBytes(StringRef((const char*)&Header, sizeof(Header))); 704 OS.PopSection(); 705 } 706 707 void AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType(StringRef SymbolName, 708 unsigned Type) { 709 MCSymbolELF *Symbol = cast<MCSymbolELF>( 710 getStreamer().getContext().getOrCreateSymbol(SymbolName)); 711 Symbol->setType(Type); 712 } 713 714 void AMDGPUTargetELFStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size, 715 Align Alignment) { 716 MCSymbolELF *SymbolELF = cast<MCSymbolELF>(Symbol); 717 SymbolELF->setType(ELF::STT_OBJECT); 718 719 if (!SymbolELF->isBindingSet()) { 720 SymbolELF->setBinding(ELF::STB_GLOBAL); 721 SymbolELF->setExternal(true); 722 } 723 724 if (SymbolELF->declareCommon(Size, Alignment.value(), true)) { 725 report_fatal_error("Symbol: " + Symbol->getName() + 726 " redeclared as different type"); 727 } 728 729 SymbolELF->setIndex(ELF::SHN_AMDGPU_LDS); 730 SymbolELF->setSize(MCConstantExpr::create(Size, getContext())); 731 } 732 733 bool AMDGPUTargetELFStreamer::EmitISAVersion() { 734 // Create two labels to mark the beginning and end of the desc field 735 // and a MCExpr to calculate the size of the desc field. 736 auto &Context = getContext(); 737 auto *DescBegin = Context.createTempSymbol(); 738 auto *DescEnd = Context.createTempSymbol(); 739 auto *DescSZ = MCBinaryExpr::createSub( 740 MCSymbolRefExpr::create(DescEnd, Context), 741 MCSymbolRefExpr::create(DescBegin, Context), Context); 742 743 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_ISA_NAME, 744 [&](MCELFStreamer &OS) { 745 OS.emitLabel(DescBegin); 746 OS.emitBytes(getTargetID()->toString()); 747 OS.emitLabel(DescEnd); 748 }); 749 return true; 750 } 751 752 bool AMDGPUTargetELFStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc, 753 bool Strict) { 754 HSAMD::V3::MetadataVerifier Verifier(Strict); 755 if (!Verifier.verify(HSAMetadataDoc.getRoot())) 756 return false; 757 758 std::string HSAMetadataString; 759 HSAMetadataDoc.writeToBlob(HSAMetadataString); 760 761 // Create two labels to mark the beginning and end of the desc field 762 // and a MCExpr to calculate the size of the desc field. 763 auto &Context = getContext(); 764 auto *DescBegin = Context.createTempSymbol(); 765 auto *DescEnd = Context.createTempSymbol(); 766 auto *DescSZ = MCBinaryExpr::createSub( 767 MCSymbolRefExpr::create(DescEnd, Context), 768 MCSymbolRefExpr::create(DescBegin, Context), Context); 769 770 EmitNote(ElfNote::NoteNameV3, DescSZ, ELF::NT_AMDGPU_METADATA, 771 [&](MCELFStreamer &OS) { 772 OS.emitLabel(DescBegin); 773 OS.emitBytes(HSAMetadataString); 774 OS.emitLabel(DescEnd); 775 }); 776 return true; 777 } 778 779 bool AMDGPUTargetELFStreamer::EmitHSAMetadata( 780 const AMDGPU::HSAMD::Metadata &HSAMetadata) { 781 std::string HSAMetadataString; 782 if (HSAMD::toString(HSAMetadata, HSAMetadataString)) 783 return false; 784 785 // Create two labels to mark the beginning and end of the desc field 786 // and a MCExpr to calculate the size of the desc field. 787 auto &Context = getContext(); 788 auto *DescBegin = Context.createTempSymbol(); 789 auto *DescEnd = Context.createTempSymbol(); 790 auto *DescSZ = MCBinaryExpr::createSub( 791 MCSymbolRefExpr::create(DescEnd, Context), 792 MCSymbolRefExpr::create(DescBegin, Context), Context); 793 794 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_METADATA, 795 [&](MCELFStreamer &OS) { 796 OS.emitLabel(DescBegin); 797 OS.emitBytes(HSAMetadataString); 798 OS.emitLabel(DescEnd); 799 }); 800 return true; 801 } 802 803 bool AMDGPUTargetELFStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) { 804 const uint32_t Encoded_s_code_end = 0xbf9f0000; 805 const uint32_t Encoded_s_nop = 0xbf800000; 806 uint32_t Encoded_pad = Encoded_s_code_end; 807 808 // Instruction cache line size in bytes. 809 const unsigned Log2CacheLineSize = 6; 810 const unsigned CacheLineSize = 1u << Log2CacheLineSize; 811 812 // Extra padding amount in bytes to support prefetch mode 3. 813 unsigned FillSize = 3 * CacheLineSize; 814 815 if (AMDGPU::isGFX90A(STI)) { 816 Encoded_pad = Encoded_s_nop; 817 FillSize = 16 * CacheLineSize; 818 } 819 820 MCStreamer &OS = getStreamer(); 821 OS.PushSection(); 822 OS.emitValueToAlignment(CacheLineSize, Encoded_pad, 4); 823 for (unsigned I = 0; I < FillSize; I += 4) 824 OS.emitInt32(Encoded_pad); 825 OS.PopSection(); 826 return true; 827 } 828 829 void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor( 830 const MCSubtargetInfo &STI, StringRef KernelName, 831 const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, 832 uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) { 833 auto &Streamer = getStreamer(); 834 auto &Context = Streamer.getContext(); 835 836 MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>( 837 Context.getOrCreateSymbol(Twine(KernelName))); 838 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>( 839 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd"))); 840 841 // Copy kernel descriptor symbol's binding, other and visibility from the 842 // kernel code symbol. 843 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding()); 844 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther()); 845 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility()); 846 // Kernel descriptor symbol's type and size are fixed. 847 KernelDescriptorSymbol->setType(ELF::STT_OBJECT); 848 KernelDescriptorSymbol->setSize( 849 MCConstantExpr::create(sizeof(KernelDescriptor), Context)); 850 851 // The visibility of the kernel code symbol must be protected or less to allow 852 // static relocations from the kernel descriptor to be used. 853 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT) 854 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED); 855 856 Streamer.emitLabel(KernelDescriptorSymbol); 857 Streamer.emitInt32(KernelDescriptor.group_segment_fixed_size); 858 Streamer.emitInt32(KernelDescriptor.private_segment_fixed_size); 859 Streamer.emitInt32(KernelDescriptor.kernarg_size); 860 861 for (uint8_t Res : KernelDescriptor.reserved0) 862 Streamer.emitInt8(Res); 863 864 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The 865 // expression being created is: 866 // (start of kernel code) - (start of kernel descriptor) 867 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64. 868 Streamer.emitValue(MCBinaryExpr::createSub( 869 MCSymbolRefExpr::create( 870 KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context), 871 MCSymbolRefExpr::create( 872 KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context), 873 Context), 874 sizeof(KernelDescriptor.kernel_code_entry_byte_offset)); 875 for (uint8_t Res : KernelDescriptor.reserved1) 876 Streamer.emitInt8(Res); 877 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc3); 878 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc1); 879 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc2); 880 Streamer.emitInt16(KernelDescriptor.kernel_code_properties); 881 for (uint8_t Res : KernelDescriptor.reserved2) 882 Streamer.emitInt8(Res); 883 } 884