1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "SIDefines.h" 22 #include "SIRegisterInfo.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/DisassemblerTypes.h" 26 #include "llvm/BinaryFormat/ELF.h" 27 #include "llvm/MC/MCAsmInfo.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCDecoderOps.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/MC/MCInstrDesc.h" 32 #include "llvm/MC/MCRegisterInfo.h" 33 #include "llvm/MC/MCSubtargetInfo.h" 34 #include "llvm/MC/TargetRegistry.h" 35 #include "llvm/Support/AMDHSAKernelDescriptor.h" 36 37 using namespace llvm; 38 39 #define DEBUG_TYPE "amdgpu-disassembler" 40 41 #define SGPR_MAX \ 42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 43 : AMDGPU::EncValues::SGPR_MAX_SI) 44 45 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 46 47 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 48 MCContext &Ctx, MCInstrInfo const *MCII) 49 : MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 50 MAI(*Ctx.getAsmInfo()), TargetMaxInstBytes(MAI.getMaxInstLength(&STI)) { 51 // ToDo: AMDGPUDisassembler supports only VI ISA. 52 if (!STI.hasFeature(AMDGPU::FeatureGCN3Encoding) && !isGFX10Plus()) 53 report_fatal_error("Disassembly not yet supported for subtarget"); 54 } 55 56 inline static MCDisassembler::DecodeStatus 57 addOperand(MCInst &Inst, const MCOperand& Opnd) { 58 Inst.addOperand(Opnd); 59 return Opnd.isValid() ? 60 MCDisassembler::Success : 61 MCDisassembler::Fail; 62 } 63 64 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 65 uint16_t NameIdx) { 66 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 67 if (OpIdx != -1) { 68 auto I = MI.begin(); 69 std::advance(I, OpIdx); 70 MI.insert(I, Op); 71 } 72 return OpIdx; 73 } 74 75 static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm, 76 uint64_t Addr, 77 const MCDisassembler *Decoder) { 78 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 79 80 // Our branches take a simm16, but we need two extra bits to account for the 81 // factor of 4. 82 APInt SignedOffset(18, Imm * 4, true); 83 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 84 85 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) 86 return MCDisassembler::Success; 87 return addOperand(Inst, MCOperand::createImm(Imm)); 88 } 89 90 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 91 const MCDisassembler *Decoder) { 92 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 93 int64_t Offset; 94 if (DAsm->isGFX12Plus()) { // GFX12 supports 24-bit signed offsets. 95 Offset = SignExtend64<24>(Imm); 96 } else if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 97 Offset = Imm & 0xFFFFF; 98 } else { // GFX9+ supports 21-bit signed offsets. 99 Offset = SignExtend64<21>(Imm); 100 } 101 return addOperand(Inst, MCOperand::createImm(Offset)); 102 } 103 104 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 105 const MCDisassembler *Decoder) { 106 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 107 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 108 } 109 110 static DecodeStatus decodeSplitBarrier(MCInst &Inst, unsigned Val, 111 uint64_t Addr, 112 const MCDisassembler *Decoder) { 113 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 114 return addOperand(Inst, DAsm->decodeSplitBarrier(Val)); 115 } 116 117 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 118 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 119 uint64_t /*Addr*/, \ 120 const MCDisassembler *Decoder) { \ 121 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 122 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 123 } 124 125 // Decoder for registers, decode directly using RegClassID. Imm(8-bit) is 126 // number of register. Used by VGPR only and AGPR only operands. 127 #define DECODE_OPERAND_REG_8(RegClass) \ 128 static DecodeStatus Decode##RegClass##RegisterClass( \ 129 MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 130 const MCDisassembler *Decoder) { \ 131 assert(Imm < (1 << 8) && "8-bit encoding"); \ 132 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 133 return addOperand( \ 134 Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \ 135 } 136 137 #define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral, \ 138 ImmWidth) \ 139 static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 140 const MCDisassembler *Decoder) { \ 141 assert(Imm < (1 << EncSize) && #EncSize "-bit encoding"); \ 142 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 143 return addOperand(Inst, \ 144 DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm, \ 145 MandatoryLiteral, ImmWidth)); \ 146 } 147 148 // Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to 149 // get register class. Used by SGPR only operands. 150 #define DECODE_OPERAND_REG_7(RegClass, OpWidth) \ 151 DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0) 152 153 // Decoder for registers. Imm(10-bit): Imm{7-0} is number of register, 154 // Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC). 155 // Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp. 156 // Used by AV_ register classes (AGPR or VGPR only register operands). 157 #define DECODE_OPERAND_REG_AV10(RegClass, OpWidth) \ 158 DECODE_SrcOp(Decode##RegClass##RegisterClass, 10, OpWidth, \ 159 Imm | AMDGPU::EncValues::IS_VGPR, false, 0) 160 161 // Decoder for Src(9-bit encoding) registers only. 162 #define DECODE_OPERAND_SRC_REG_9(RegClass, OpWidth) \ 163 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm, false, 0) 164 165 // Decoder for Src(9-bit encoding) AGPR, register number encoded in 9bits, set 166 // Imm{9} to 1 (set acc) and decode using 'enum10' from decodeSrcOp, registers 167 // only. 168 #define DECODE_OPERAND_SRC_REG_A9(RegClass, OpWidth) \ 169 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm | 512, false, 0) 170 171 // Decoder for 'enum10' from decodeSrcOp, Imm{0-8} is 9-bit Src encoding 172 // Imm{9} is acc, registers only. 173 #define DECODE_SRC_OPERAND_REG_AV10(RegClass, OpWidth) \ 174 DECODE_SrcOp(decodeOperand_##RegClass, 10, OpWidth, Imm, false, 0) 175 176 // Decoder for RegisterOperands using 9-bit Src encoding. Operand can be 177 // register from RegClass or immediate. Registers that don't belong to RegClass 178 // will be decoded and InstPrinter will report warning. Immediate will be 179 // decoded into constant of size ImmWidth, should match width of immediate used 180 // by OperandType (important for floating point types). 181 #define DECODE_OPERAND_SRC_REG_OR_IMM_9(RegClass, OpWidth, ImmWidth) \ 182 DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, Imm, \ 183 false, ImmWidth) 184 185 #define DECODE_OPERAND_SRC_REG_OR_IMM_9_TYPED(Name, OpWidth, ImmWidth) \ 186 DECODE_SrcOp(decodeOperand_##Name, 9, OpWidth, Imm, false, ImmWidth) 187 188 // Decoder for Src(9-bit encoding) AGPR or immediate. Set Imm{9} to 1 (set acc) 189 // and decode using 'enum10' from decodeSrcOp. 190 #define DECODE_OPERAND_SRC_REG_OR_IMM_A9(RegClass, OpWidth, ImmWidth) \ 191 DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, \ 192 Imm | 512, false, ImmWidth) 193 194 #define DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(RegClass, OpWidth, ImmWidth) \ 195 DECODE_SrcOp(decodeOperand_##RegClass##_Deferred##_Imm##ImmWidth, 9, \ 196 OpWidth, Imm, true, ImmWidth) 197 198 // Default decoders generated by tablegen: 'Decode<RegClass>RegisterClass' 199 // when RegisterClass is used as an operand. Most often used for destination 200 // operands. 201 202 DECODE_OPERAND_REG_8(VGPR_32) 203 DECODE_OPERAND_REG_8(VGPR_32_Lo128) 204 DECODE_OPERAND_REG_8(VReg_64) 205 DECODE_OPERAND_REG_8(VReg_96) 206 DECODE_OPERAND_REG_8(VReg_128) 207 DECODE_OPERAND_REG_8(VReg_256) 208 DECODE_OPERAND_REG_8(VReg_288) 209 DECODE_OPERAND_REG_8(VReg_352) 210 DECODE_OPERAND_REG_8(VReg_384) 211 DECODE_OPERAND_REG_8(VReg_512) 212 DECODE_OPERAND_REG_8(VReg_1024) 213 214 DECODE_OPERAND_REG_7(SReg_32, OPW32) 215 DECODE_OPERAND_REG_7(SReg_32_XEXEC, OPW32) 216 DECODE_OPERAND_REG_7(SReg_32_XM0_XEXEC, OPW32) 217 DECODE_OPERAND_REG_7(SReg_32_XEXEC_HI, OPW32) 218 DECODE_OPERAND_REG_7(SReg_64, OPW64) 219 DECODE_OPERAND_REG_7(SReg_64_XEXEC, OPW64) 220 DECODE_OPERAND_REG_7(SReg_96, OPW96) 221 DECODE_OPERAND_REG_7(SReg_128, OPW128) 222 DECODE_OPERAND_REG_7(SReg_256, OPW256) 223 DECODE_OPERAND_REG_7(SReg_512, OPW512) 224 225 DECODE_OPERAND_REG_8(AGPR_32) 226 DECODE_OPERAND_REG_8(AReg_64) 227 DECODE_OPERAND_REG_8(AReg_128) 228 DECODE_OPERAND_REG_8(AReg_256) 229 DECODE_OPERAND_REG_8(AReg_512) 230 DECODE_OPERAND_REG_8(AReg_1024) 231 232 DECODE_OPERAND_REG_AV10(AVDst_128, OPW128) 233 DECODE_OPERAND_REG_AV10(AVDst_512, OPW512) 234 235 // Decoders for register only source RegisterOperands that use use 9-bit Src 236 // encoding: 'decodeOperand_<RegClass>'. 237 238 DECODE_OPERAND_SRC_REG_9(VGPR_32, OPW32) 239 DECODE_OPERAND_SRC_REG_9(VReg_64, OPW64) 240 DECODE_OPERAND_SRC_REG_9(VReg_128, OPW128) 241 DECODE_OPERAND_SRC_REG_9(VReg_256, OPW256) 242 DECODE_OPERAND_SRC_REG_9(VRegOrLds_32, OPW32) 243 244 DECODE_OPERAND_SRC_REG_A9(AGPR_32, OPW32) 245 246 DECODE_SRC_OPERAND_REG_AV10(AV_32, OPW32) 247 DECODE_SRC_OPERAND_REG_AV10(AV_64, OPW64) 248 DECODE_SRC_OPERAND_REG_AV10(AV_128, OPW128) 249 250 // Decoders for register or immediate RegisterOperands that use 9-bit Src 251 // encoding: 'decodeOperand_<RegClass>_Imm<ImmWidth>'. 252 253 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_64, OPW64, 64) 254 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_32, OPW32, 32) 255 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_32, OPW32, 16) 256 DECODE_OPERAND_SRC_REG_OR_IMM_9(SRegOrLds_32, OPW32, 32) 257 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32_Lo128, OPW16, 16) 258 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32, OPW32, 16) 259 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32, OPW32, 32) 260 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_64, OPW64, 64) 261 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_64, OPW64, 32) 262 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_64, OPW64, 64) 263 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_128, OPW128, 32) 264 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_256, OPW256, 64) 265 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_512, OPW512, 32) 266 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_1024, OPW1024, 32) 267 268 DECODE_OPERAND_SRC_REG_OR_IMM_9_TYPED(VS_32_ImmV2I16, OPW32, 32) 269 DECODE_OPERAND_SRC_REG_OR_IMM_9_TYPED(VS_32_ImmV2F16, OPW32, 16) 270 271 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_64, OPW64, 64) 272 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_128, OPW128, 32) 273 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_256, OPW256, 64) 274 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_512, OPW512, 32) 275 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_1024, OPW1024, 32) 276 277 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32_Lo128, OPW16, 16) 278 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32, OPW16, 16) 279 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32, OPW32, 32) 280 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(SReg_32, OPW32, 32) 281 282 static DecodeStatus DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm, 283 uint64_t /*Addr*/, 284 const MCDisassembler *Decoder) { 285 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 286 assert((Imm & (1 << 8)) == 0 && "Imm{8} should not be used"); 287 288 bool IsHi = Imm & (1 << 9); 289 unsigned RegIdx = Imm & 0xff; 290 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 291 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 292 } 293 294 static DecodeStatus 295 DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, 296 const MCDisassembler *Decoder) { 297 assert(isUInt<8>(Imm) && "8-bit encoding expected"); 298 299 bool IsHi = Imm & (1 << 7); 300 unsigned RegIdx = Imm & 0x7f; 301 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 302 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 303 } 304 305 static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm, 306 uint64_t /*Addr*/, 307 const MCDisassembler *Decoder) { 308 assert(isUInt<9>(Imm) && "9-bit encoding expected"); 309 310 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 311 bool IsVGPR = Imm & (1 << 8); 312 if (IsVGPR) { 313 bool IsHi = Imm & (1 << 7); 314 unsigned RegIdx = Imm & 0x7f; 315 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 316 } 317 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16, 318 Imm & 0xFF, false, 16)); 319 } 320 321 static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm, 322 uint64_t /*Addr*/, 323 const MCDisassembler *Decoder) { 324 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 325 326 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 327 bool IsVGPR = Imm & (1 << 8); 328 if (IsVGPR) { 329 bool IsHi = Imm & (1 << 9); 330 unsigned RegIdx = Imm & 0xff; 331 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 332 } 333 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16, 334 Imm & 0xFF, false, 16)); 335 } 336 337 static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm, 338 uint64_t Addr, 339 const MCDisassembler *Decoder) { 340 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 341 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 342 } 343 344 static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, 345 uint64_t Addr, const void *Decoder) { 346 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 347 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val)); 348 } 349 350 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 351 const MCRegisterInfo *MRI) { 352 if (OpIdx < 0) 353 return false; 354 355 const MCOperand &Op = Inst.getOperand(OpIdx); 356 if (!Op.isReg()) 357 return false; 358 359 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 360 auto Reg = Sub ? Sub : Op.getReg(); 361 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 362 } 363 364 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, 365 AMDGPUDisassembler::OpWidthTy Opw, 366 const MCDisassembler *Decoder) { 367 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 368 if (!DAsm->isGFX90A()) { 369 Imm &= 511; 370 } else { 371 // If atomic has both vdata and vdst their register classes are tied. 372 // The bit is decoded along with the vdst, first operand. We need to 373 // change register class to AGPR if vdst was AGPR. 374 // If a DS instruction has both data0 and data1 their register classes 375 // are also tied. 376 unsigned Opc = Inst.getOpcode(); 377 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 378 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 379 : AMDGPU::OpName::vdata; 380 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 381 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 382 if ((int)Inst.getNumOperands() == DataIdx) { 383 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 384 if (IsAGPROperand(Inst, DstIdx, MRI)) 385 Imm |= 512; 386 } 387 388 if (TSFlags & SIInstrFlags::DS) { 389 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 390 if ((int)Inst.getNumOperands() == Data2Idx && 391 IsAGPROperand(Inst, DataIdx, MRI)) 392 Imm |= 512; 393 } 394 } 395 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 396 } 397 398 static DecodeStatus decodeOperand_VSrc_f64(MCInst &Inst, unsigned Imm, 399 uint64_t Addr, 400 const MCDisassembler *Decoder) { 401 assert(Imm < (1 << 9) && "9-bit encoding"); 402 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 403 return addOperand( 404 Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm, false, 64, true)); 405 } 406 407 static DecodeStatus 408 DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 409 const MCDisassembler *Decoder) { 410 return decodeOperand_AVLdSt_Any(Inst, Imm, 411 AMDGPUDisassembler::OPW32, Decoder); 412 } 413 414 static DecodeStatus 415 DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 416 const MCDisassembler *Decoder) { 417 return decodeOperand_AVLdSt_Any(Inst, Imm, 418 AMDGPUDisassembler::OPW64, Decoder); 419 } 420 421 static DecodeStatus 422 DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 423 const MCDisassembler *Decoder) { 424 return decodeOperand_AVLdSt_Any(Inst, Imm, 425 AMDGPUDisassembler::OPW96, Decoder); 426 } 427 428 static DecodeStatus 429 DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 430 const MCDisassembler *Decoder) { 431 return decodeOperand_AVLdSt_Any(Inst, Imm, 432 AMDGPUDisassembler::OPW128, Decoder); 433 } 434 435 static DecodeStatus 436 DecodeAVLdSt_160RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 437 const MCDisassembler *Decoder) { 438 return decodeOperand_AVLdSt_Any(Inst, Imm, AMDGPUDisassembler::OPW160, 439 Decoder); 440 } 441 442 #define DECODE_SDWA(DecName) \ 443 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 444 445 DECODE_SDWA(Src32) 446 DECODE_SDWA(Src16) 447 DECODE_SDWA(VopcDst) 448 449 #include "AMDGPUGenDisassemblerTables.inc" 450 451 //===----------------------------------------------------------------------===// 452 // 453 //===----------------------------------------------------------------------===// 454 455 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 456 assert(Bytes.size() >= sizeof(T)); 457 const auto Res = 458 support::endian::read<T, llvm::endianness::little>(Bytes.data()); 459 Bytes = Bytes.slice(sizeof(T)); 460 return Res; 461 } 462 463 static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) { 464 assert(Bytes.size() >= 12); 465 uint64_t Lo = 466 support::endian::read<uint64_t, llvm::endianness::little>(Bytes.data()); 467 Bytes = Bytes.slice(8); 468 uint64_t Hi = 469 support::endian::read<uint32_t, llvm::endianness::little>(Bytes.data()); 470 Bytes = Bytes.slice(4); 471 return DecoderUInt128(Lo, Hi); 472 } 473 474 // The disassembler is greedy, so we need to check FI operand value to 475 // not parse a dpp if the correct literal is not set. For dpp16 the 476 // autogenerated decoder checks the dpp literal 477 static bool isValidDPP8(const MCInst &MI) { 478 using namespace llvm::AMDGPU::DPP; 479 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 480 assert(FiIdx != -1); 481 if ((unsigned)FiIdx >= MI.getNumOperands()) 482 return false; 483 unsigned Fi = MI.getOperand(FiIdx).getImm(); 484 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 485 } 486 487 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 488 ArrayRef<uint8_t> Bytes_, 489 uint64_t Address, 490 raw_ostream &CS) const { 491 bool IsSDWA = false; 492 493 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 494 Bytes = Bytes_.slice(0, MaxInstBytesNum); 495 496 DecodeStatus Res = MCDisassembler::Fail; 497 do { 498 // ToDo: better to switch encoding length using some bit predicate 499 // but it is unknown yet, so try all we can 500 501 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 502 // encodings 503 if (isGFX11Plus() && Bytes.size() >= 12 ) { 504 DecoderUInt128 DecW = eat12Bytes(Bytes); 505 Res = 506 tryDecodeInst(DecoderTableDPP8GFX1196, DecoderTableDPP8GFX11_FAKE1696, 507 MI, DecW, Address, CS); 508 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 509 break; 510 MI = MCInst(); // clear 511 Res = 512 tryDecodeInst(DecoderTableDPP8GFX1296, DecoderTableDPP8GFX12_FAKE1696, 513 MI, DecW, Address, CS); 514 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 515 break; 516 MI = MCInst(); // clear 517 518 const auto convertVOPDPP = [&]() { 519 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) { 520 convertVOP3PDPPInst(MI); 521 } else if (AMDGPU::isVOPC64DPP(MI.getOpcode())) { 522 convertVOPCDPPInst(MI); // Special VOP3 case 523 } else { 524 assert(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3); 525 convertVOP3DPPInst(MI); // Regular VOP3 case 526 } 527 }; 528 Res = tryDecodeInst(DecoderTableDPPGFX1196, DecoderTableDPPGFX11_FAKE1696, 529 MI, DecW, Address, CS); 530 if (Res) { 531 convertVOPDPP(); 532 break; 533 } 534 Res = tryDecodeInst(DecoderTableDPPGFX1296, DecoderTableDPPGFX12_FAKE1696, 535 MI, DecW, Address, CS); 536 if (Res) { 537 convertVOPDPP(); 538 break; 539 } 540 Res = tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address, CS); 541 if (Res) 542 break; 543 544 Res = tryDecodeInst(DecoderTableGFX1296, MI, DecW, Address, CS); 545 if (Res) 546 break; 547 } 548 // Reinitialize Bytes 549 Bytes = Bytes_.slice(0, MaxInstBytesNum); 550 551 if (Bytes.size() >= 8) { 552 const uint64_t QW = eatBytes<uint64_t>(Bytes); 553 554 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) { 555 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address, CS); 556 if (Res) { 557 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 558 == -1) 559 break; 560 if (convertDPP8Inst(MI) == MCDisassembler::Success) 561 break; 562 MI = MCInst(); // clear 563 } 564 } 565 566 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address, CS); 567 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 568 break; 569 MI = MCInst(); // clear 570 571 Res = tryDecodeInst(DecoderTableDPP8GFX1164, 572 DecoderTableDPP8GFX11_FAKE1664, MI, QW, Address, CS); 573 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 574 break; 575 MI = MCInst(); // clear 576 577 Res = tryDecodeInst(DecoderTableDPP8GFX1264, 578 DecoderTableDPP8GFX12_FAKE1664, MI, QW, Address, CS); 579 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 580 break; 581 MI = MCInst(); // clear 582 583 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address, CS); 584 if (Res) break; 585 586 Res = tryDecodeInst(DecoderTableDPPGFX1164, DecoderTableDPPGFX11_FAKE1664, 587 MI, QW, Address, CS); 588 if (Res) { 589 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) 590 convertVOPCDPPInst(MI); 591 break; 592 } 593 594 Res = tryDecodeInst(DecoderTableDPPGFX1264, DecoderTableDPPGFX12_FAKE1664, 595 MI, QW, Address, CS); 596 if (Res) { 597 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) 598 convertVOPCDPPInst(MI); 599 break; 600 } 601 602 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address, CS); 603 if (Res) { IsSDWA = true; break; } 604 605 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address, CS); 606 if (Res) { IsSDWA = true; break; } 607 608 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address, CS); 609 if (Res) { IsSDWA = true; break; } 610 611 if (STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem)) { 612 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address, CS); 613 if (Res) 614 break; 615 } 616 617 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 618 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 619 // table first so we print the correct name. 620 if (STI.hasFeature(AMDGPU::FeatureFmaMixInsts)) { 621 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address, CS); 622 if (Res) 623 break; 624 } 625 } 626 627 // Reinitialize Bytes as DPP64 could have eaten too much 628 Bytes = Bytes_.slice(0, MaxInstBytesNum); 629 630 // Try decode 32-bit instruction 631 if (Bytes.size() < 4) break; 632 const uint32_t DW = eatBytes<uint32_t>(Bytes); 633 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address, CS); 634 if (Res) break; 635 636 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address, CS); 637 if (Res) break; 638 639 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address, CS); 640 if (Res) break; 641 642 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) { 643 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address, CS); 644 if (Res) 645 break; 646 } 647 648 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) { 649 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address, CS); 650 if (Res) break; 651 } 652 653 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address, CS); 654 if (Res) break; 655 656 Res = tryDecodeInst(DecoderTableGFX1132, DecoderTableGFX11_FAKE1632, MI, DW, 657 Address, CS); 658 if (Res) break; 659 660 Res = tryDecodeInst(DecoderTableGFX1232, DecoderTableGFX12_FAKE1632, MI, DW, 661 Address, CS); 662 if (Res) 663 break; 664 665 if (Bytes.size() < 4) break; 666 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 667 668 if (STI.hasFeature(AMDGPU::FeatureGFX940Insts)) { 669 Res = tryDecodeInst(DecoderTableGFX94064, MI, QW, Address, CS); 670 if (Res) 671 break; 672 } 673 674 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) { 675 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address, CS); 676 if (Res) 677 break; 678 } 679 680 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address, CS); 681 if (Res) break; 682 683 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address, CS); 684 if (Res) break; 685 686 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address, CS); 687 if (Res) break; 688 689 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address, CS); 690 if (Res) break; 691 692 Res = tryDecodeInst(DecoderTableGFX1264, DecoderTableGFX12_FAKE1664, MI, QW, 693 Address, CS); 694 if (Res) 695 break; 696 697 Res = tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664, MI, QW, 698 Address, CS); 699 if (Res) 700 break; 701 702 Res = tryDecodeInst(DecoderTableWMMAGFX1164, MI, QW, Address, CS); 703 } while (false); 704 705 if (Res && AMDGPU::isMAC(MI.getOpcode())) { 706 // Insert dummy unused src2_modifiers. 707 insertNamedMCOperand(MI, MCOperand::createImm(0), 708 AMDGPU::OpName::src2_modifiers); 709 } 710 711 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::DS) && 712 !AMDGPU::hasGDS(STI)) { 713 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::gds); 714 } 715 716 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 717 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 718 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 719 AMDGPU::OpName::cpol); 720 if (CPolPos != -1) { 721 unsigned CPol = 722 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 723 AMDGPU::CPol::GLC : 0; 724 if (MI.getNumOperands() <= (unsigned)CPolPos) { 725 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 726 AMDGPU::OpName::cpol); 727 } else if (CPol) { 728 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 729 } 730 } 731 } 732 733 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 734 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 735 (STI.hasFeature(AMDGPU::FeatureGFX90AInsts))) { 736 // GFX90A lost TFE, its place is occupied by ACC. 737 int TFEOpIdx = 738 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 739 if (TFEOpIdx != -1) { 740 auto TFEIter = MI.begin(); 741 std::advance(TFEIter, TFEOpIdx); 742 MI.insert(TFEIter, MCOperand::createImm(0)); 743 } 744 } 745 746 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 747 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 748 int SWZOpIdx = 749 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 750 if (SWZOpIdx != -1) { 751 auto SWZIter = MI.begin(); 752 std::advance(SWZIter, SWZOpIdx); 753 MI.insert(SWZIter, MCOperand::createImm(0)); 754 } 755 } 756 757 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 758 int VAddr0Idx = 759 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 760 int RsrcIdx = 761 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 762 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 763 if (VAddr0Idx >= 0 && NSAArgs > 0) { 764 unsigned NSAWords = (NSAArgs + 3) / 4; 765 if (Bytes.size() < 4 * NSAWords) { 766 Res = MCDisassembler::Fail; 767 } else { 768 for (unsigned i = 0; i < NSAArgs; ++i) { 769 const unsigned VAddrIdx = VAddr0Idx + 1 + i; 770 auto VAddrRCID = 771 MCII->get(MI.getOpcode()).operands()[VAddrIdx].RegClass; 772 MI.insert(MI.begin() + VAddrIdx, 773 createRegOperand(VAddrRCID, Bytes[i])); 774 } 775 Bytes = Bytes.slice(4 * NSAWords); 776 } 777 } 778 779 if (Res) 780 Res = convertMIMGInst(MI); 781 } 782 783 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 784 (SIInstrFlags::VIMAGE | SIInstrFlags::VSAMPLE))) 785 Res = convertMIMGInst(MI); 786 787 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP)) 788 Res = convertEXPInst(MI); 789 790 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP)) 791 Res = convertVINTERPInst(MI); 792 793 if (Res && IsSDWA) 794 Res = convertSDWAInst(MI); 795 796 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 797 AMDGPU::OpName::vdst_in); 798 if (VDstIn_Idx != -1) { 799 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 800 MCOI::OperandConstraint::TIED_TO); 801 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 802 !MI.getOperand(VDstIn_Idx).isReg() || 803 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 804 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 805 MI.erase(&MI.getOperand(VDstIn_Idx)); 806 insertNamedMCOperand(MI, 807 MCOperand::createReg(MI.getOperand(Tied).getReg()), 808 AMDGPU::OpName::vdst_in); 809 } 810 } 811 812 int ImmLitIdx = 813 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 814 bool IsSOPK = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SOPK; 815 if (Res && ImmLitIdx != -1 && !IsSOPK) 816 Res = convertFMAanyK(MI, ImmLitIdx); 817 818 // if the opcode was not recognized we'll assume a Size of 4 bytes 819 // (unless there are fewer bytes left) 820 Size = Res ? (MaxInstBytesNum - Bytes.size()) 821 : std::min((size_t)4, Bytes_.size()); 822 return Res; 823 } 824 825 DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 826 if (STI.hasFeature(AMDGPU::FeatureGFX11Insts)) { 827 // The MCInst still has these fields even though they are no longer encoded 828 // in the GFX11 instruction. 829 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 830 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 831 } 832 return MCDisassembler::Success; 833 } 834 835 DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { 836 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 || 837 MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx12 || 838 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 || 839 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx12 || 840 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 || 841 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx12 || 842 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11 || 843 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx12) { 844 // The MCInst has this field that is not directly encoded in the 845 // instruction. 846 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); 847 } 848 return MCDisassembler::Success; 849 } 850 851 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 852 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 853 STI.hasFeature(AMDGPU::FeatureGFX10)) { 854 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::sdst)) 855 // VOPC - insert clamp 856 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 857 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { 858 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 859 if (SDst != -1) { 860 // VOPC - insert VCC register as sdst 861 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 862 AMDGPU::OpName::sdst); 863 } else { 864 // VOP1/2 - insert omod if present in instruction 865 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 866 } 867 } 868 return MCDisassembler::Success; 869 } 870 871 struct VOPModifiers { 872 unsigned OpSel = 0; 873 unsigned OpSelHi = 0; 874 unsigned NegLo = 0; 875 unsigned NegHi = 0; 876 }; 877 878 // Reconstruct values of VOP3/VOP3P operands such as op_sel. 879 // Note that these values do not affect disassembler output, 880 // so this is only necessary for consistency with src_modifiers. 881 static VOPModifiers collectVOPModifiers(const MCInst &MI, 882 bool IsVOP3P = false) { 883 VOPModifiers Modifiers; 884 unsigned Opc = MI.getOpcode(); 885 const int ModOps[] = {AMDGPU::OpName::src0_modifiers, 886 AMDGPU::OpName::src1_modifiers, 887 AMDGPU::OpName::src2_modifiers}; 888 for (int J = 0; J < 3; ++J) { 889 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); 890 if (OpIdx == -1) 891 continue; 892 893 unsigned Val = MI.getOperand(OpIdx).getImm(); 894 895 Modifiers.OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J; 896 if (IsVOP3P) { 897 Modifiers.OpSelHi |= !!(Val & SISrcMods::OP_SEL_1) << J; 898 Modifiers.NegLo |= !!(Val & SISrcMods::NEG) << J; 899 Modifiers.NegHi |= !!(Val & SISrcMods::NEG_HI) << J; 900 } else if (J == 0) { 901 Modifiers.OpSel |= !!(Val & SISrcMods::DST_OP_SEL) << 3; 902 } 903 } 904 905 return Modifiers; 906 } 907 908 // MAC opcodes have special old and src2 operands. 909 // src2 is tied to dst, while old is not tied (but assumed to be). 910 bool AMDGPUDisassembler::isMacDPP(MCInst &MI) const { 911 constexpr int DST_IDX = 0; 912 auto Opcode = MI.getOpcode(); 913 const auto &Desc = MCII->get(Opcode); 914 auto OldIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::old); 915 916 if (OldIdx != -1 && Desc.getOperandConstraint( 917 OldIdx, MCOI::OperandConstraint::TIED_TO) == -1) { 918 assert(AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2)); 919 assert(Desc.getOperandConstraint( 920 AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2), 921 MCOI::OperandConstraint::TIED_TO) == DST_IDX); 922 (void)DST_IDX; 923 return true; 924 } 925 926 return false; 927 } 928 929 // Create dummy old operand and insert dummy unused src2_modifiers 930 void AMDGPUDisassembler::convertMacDPPInst(MCInst &MI) const { 931 assert(MI.getNumOperands() + 1 < MCII->get(MI.getOpcode()).getNumOperands()); 932 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 933 insertNamedMCOperand(MI, MCOperand::createImm(0), 934 AMDGPU::OpName::src2_modifiers); 935 } 936 937 // We must check FI == literal to reject not genuine dpp8 insts, and we must 938 // first add optional MI operands to check FI 939 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 940 unsigned Opc = MI.getOpcode(); 941 if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) { 942 convertVOP3PDPPInst(MI); 943 } else if ((MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) || 944 AMDGPU::isVOPC64DPP(Opc)) { 945 convertVOPCDPPInst(MI); 946 } else { 947 if (isMacDPP(MI)) 948 convertMacDPPInst(MI); 949 950 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 951 if (MI.getNumOperands() < DescNumOps && 952 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 953 auto Mods = collectVOPModifiers(MI); 954 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 955 AMDGPU::OpName::op_sel); 956 } else { 957 // Insert dummy unused src modifiers. 958 if (MI.getNumOperands() < DescNumOps && 959 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 960 insertNamedMCOperand(MI, MCOperand::createImm(0), 961 AMDGPU::OpName::src0_modifiers); 962 963 if (MI.getNumOperands() < DescNumOps && 964 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 965 insertNamedMCOperand(MI, MCOperand::createImm(0), 966 AMDGPU::OpName::src1_modifiers); 967 } 968 } 969 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 970 } 971 972 DecodeStatus AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const { 973 if (isMacDPP(MI)) 974 convertMacDPPInst(MI); 975 976 unsigned Opc = MI.getOpcode(); 977 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 978 if (MI.getNumOperands() < DescNumOps && 979 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 980 auto Mods = collectVOPModifiers(MI); 981 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 982 AMDGPU::OpName::op_sel); 983 } 984 return MCDisassembler::Success; 985 } 986 987 // Note that before gfx10, the MIMG encoding provided no information about 988 // VADDR size. Consequently, decoded instructions always show address as if it 989 // has 1 dword, which could be not really so. 990 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 991 auto TSFlags = MCII->get(MI.getOpcode()).TSFlags; 992 993 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 994 AMDGPU::OpName::vdst); 995 996 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 997 AMDGPU::OpName::vdata); 998 int VAddr0Idx = 999 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 1000 int RsrcOpName = TSFlags & SIInstrFlags::MIMG ? AMDGPU::OpName::srsrc 1001 : AMDGPU::OpName::rsrc; 1002 int RsrcIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), RsrcOpName); 1003 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 1004 AMDGPU::OpName::dmask); 1005 1006 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 1007 AMDGPU::OpName::tfe); 1008 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 1009 AMDGPU::OpName::d16); 1010 1011 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 1012 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 1013 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 1014 1015 assert(VDataIdx != -1); 1016 if (BaseOpcode->BVH) { 1017 // Add A16 operand for intersect_ray instructions 1018 addOperand(MI, MCOperand::createImm(BaseOpcode->A16)); 1019 return MCDisassembler::Success; 1020 } 1021 1022 bool IsAtomic = (VDstIdx != -1); 1023 bool IsGather4 = TSFlags & SIInstrFlags::Gather4; 1024 bool IsVSample = TSFlags & SIInstrFlags::VSAMPLE; 1025 bool IsNSA = false; 1026 bool IsPartialNSA = false; 1027 unsigned AddrSize = Info->VAddrDwords; 1028 1029 if (isGFX10Plus()) { 1030 unsigned DimIdx = 1031 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 1032 int A16Idx = 1033 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 1034 const AMDGPU::MIMGDimInfo *Dim = 1035 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 1036 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 1037 1038 AddrSize = 1039 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 1040 1041 // VSAMPLE insts that do not use vaddr3 behave the same as NSA forms. 1042 // VIMAGE insts other than BVH never use vaddr4. 1043 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA || 1044 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA || 1045 Info->MIMGEncoding == AMDGPU::MIMGEncGfx12; 1046 if (!IsNSA) { 1047 if (!IsVSample && AddrSize > 12) 1048 AddrSize = 16; 1049 } else { 1050 if (AddrSize > Info->VAddrDwords) { 1051 if (!STI.hasFeature(AMDGPU::FeaturePartialNSAEncoding)) { 1052 // The NSA encoding does not contain enough operands for the 1053 // combination of base opcode / dimension. Should this be an error? 1054 return MCDisassembler::Success; 1055 } 1056 IsPartialNSA = true; 1057 } 1058 } 1059 } 1060 1061 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 1062 unsigned DstSize = IsGather4 ? 4 : std::max(llvm::popcount(DMask), 1); 1063 1064 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 1065 if (D16 && AMDGPU::hasPackedD16(STI)) { 1066 DstSize = (DstSize + 1) / 2; 1067 } 1068 1069 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 1070 DstSize += 1; 1071 1072 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 1073 return MCDisassembler::Success; 1074 1075 int NewOpcode = 1076 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 1077 if (NewOpcode == -1) 1078 return MCDisassembler::Success; 1079 1080 // Widen the register to the correct number of enabled channels. 1081 unsigned NewVdata = AMDGPU::NoRegister; 1082 if (DstSize != Info->VDataDwords) { 1083 auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass; 1084 1085 // Get first subregister of VData 1086 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 1087 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 1088 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 1089 1090 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 1091 &MRI.getRegClass(DataRCID)); 1092 if (NewVdata == AMDGPU::NoRegister) { 1093 // It's possible to encode this such that the low register + enabled 1094 // components exceeds the register count. 1095 return MCDisassembler::Success; 1096 } 1097 } 1098 1099 // If not using NSA on GFX10+, widen vaddr0 address register to correct size. 1100 // If using partial NSA on GFX11+ widen last address register. 1101 int VAddrSAIdx = IsPartialNSA ? (RsrcIdx - 1) : VAddr0Idx; 1102 unsigned NewVAddrSA = AMDGPU::NoRegister; 1103 if (STI.hasFeature(AMDGPU::FeatureNSAEncoding) && (!IsNSA || IsPartialNSA) && 1104 AddrSize != Info->VAddrDwords) { 1105 unsigned VAddrSA = MI.getOperand(VAddrSAIdx).getReg(); 1106 unsigned VAddrSubSA = MRI.getSubReg(VAddrSA, AMDGPU::sub0); 1107 VAddrSA = VAddrSubSA ? VAddrSubSA : VAddrSA; 1108 1109 auto AddrRCID = MCII->get(NewOpcode).operands()[VAddrSAIdx].RegClass; 1110 NewVAddrSA = MRI.getMatchingSuperReg(VAddrSA, AMDGPU::sub0, 1111 &MRI.getRegClass(AddrRCID)); 1112 if (!NewVAddrSA) 1113 return MCDisassembler::Success; 1114 } 1115 1116 MI.setOpcode(NewOpcode); 1117 1118 if (NewVdata != AMDGPU::NoRegister) { 1119 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 1120 1121 if (IsAtomic) { 1122 // Atomic operations have an additional operand (a copy of data) 1123 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 1124 } 1125 } 1126 1127 if (NewVAddrSA) { 1128 MI.getOperand(VAddrSAIdx) = MCOperand::createReg(NewVAddrSA); 1129 } else if (IsNSA) { 1130 assert(AddrSize <= Info->VAddrDwords); 1131 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 1132 MI.begin() + VAddr0Idx + Info->VAddrDwords); 1133 } 1134 1135 return MCDisassembler::Success; 1136 } 1137 1138 // Opsel and neg bits are used in src_modifiers and standalone operands. Autogen 1139 // decoder only adds to src_modifiers, so manually add the bits to the other 1140 // operands. 1141 DecodeStatus AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const { 1142 unsigned Opc = MI.getOpcode(); 1143 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1144 auto Mods = collectVOPModifiers(MI, true); 1145 1146 if (MI.getNumOperands() < DescNumOps && 1147 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)) 1148 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in); 1149 1150 if (MI.getNumOperands() < DescNumOps && 1151 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) 1152 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 1153 AMDGPU::OpName::op_sel); 1154 if (MI.getNumOperands() < DescNumOps && 1155 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel_hi)) 1156 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSelHi), 1157 AMDGPU::OpName::op_sel_hi); 1158 if (MI.getNumOperands() < DescNumOps && 1159 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_lo)) 1160 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegLo), 1161 AMDGPU::OpName::neg_lo); 1162 if (MI.getNumOperands() < DescNumOps && 1163 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_hi)) 1164 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegHi), 1165 AMDGPU::OpName::neg_hi); 1166 1167 return MCDisassembler::Success; 1168 } 1169 1170 // Create dummy old operand and insert optional operands 1171 DecodeStatus AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const { 1172 unsigned Opc = MI.getOpcode(); 1173 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1174 1175 if (MI.getNumOperands() < DescNumOps && 1176 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::old)) 1177 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 1178 1179 if (MI.getNumOperands() < DescNumOps && 1180 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 1181 insertNamedMCOperand(MI, MCOperand::createImm(0), 1182 AMDGPU::OpName::src0_modifiers); 1183 1184 if (MI.getNumOperands() < DescNumOps && 1185 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 1186 insertNamedMCOperand(MI, MCOperand::createImm(0), 1187 AMDGPU::OpName::src1_modifiers); 1188 return MCDisassembler::Success; 1189 } 1190 1191 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 1192 int ImmLitIdx) const { 1193 assert(HasLiteral && "Should have decoded a literal"); 1194 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 1195 unsigned DescNumOps = Desc.getNumOperands(); 1196 insertNamedMCOperand(MI, MCOperand::createImm(Literal), 1197 AMDGPU::OpName::immDeferred); 1198 assert(DescNumOps == MI.getNumOperands()); 1199 for (unsigned I = 0; I < DescNumOps; ++I) { 1200 auto &Op = MI.getOperand(I); 1201 auto OpType = Desc.operands()[I].OperandType; 1202 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 1203 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 1204 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 1205 IsDeferredOp) 1206 Op.setImm(Literal); 1207 } 1208 return MCDisassembler::Success; 1209 } 1210 1211 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 1212 return getContext().getRegisterInfo()-> 1213 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 1214 } 1215 1216 inline 1217 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 1218 const Twine& ErrMsg) const { 1219 *CommentStream << "Error: " + ErrMsg; 1220 1221 // ToDo: add support for error operands to MCInst.h 1222 // return MCOperand::createError(V); 1223 return MCOperand(); 1224 } 1225 1226 inline 1227 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 1228 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 1229 } 1230 1231 inline 1232 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 1233 unsigned Val) const { 1234 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 1235 if (Val >= RegCl.getNumRegs()) 1236 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 1237 ": unknown register " + Twine(Val)); 1238 return createRegOperand(RegCl.getRegister(Val)); 1239 } 1240 1241 inline 1242 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 1243 unsigned Val) const { 1244 // ToDo: SI/CI have 104 SGPRs, VI - 102 1245 // Valery: here we accepting as much as we can, let assembler sort it out 1246 int shift = 0; 1247 switch (SRegClassID) { 1248 case AMDGPU::SGPR_32RegClassID: 1249 case AMDGPU::TTMP_32RegClassID: 1250 break; 1251 case AMDGPU::SGPR_64RegClassID: 1252 case AMDGPU::TTMP_64RegClassID: 1253 shift = 1; 1254 break; 1255 case AMDGPU::SGPR_96RegClassID: 1256 case AMDGPU::TTMP_96RegClassID: 1257 case AMDGPU::SGPR_128RegClassID: 1258 case AMDGPU::TTMP_128RegClassID: 1259 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 1260 // this bundle? 1261 case AMDGPU::SGPR_256RegClassID: 1262 case AMDGPU::TTMP_256RegClassID: 1263 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 1264 // this bundle? 1265 case AMDGPU::SGPR_288RegClassID: 1266 case AMDGPU::TTMP_288RegClassID: 1267 case AMDGPU::SGPR_320RegClassID: 1268 case AMDGPU::TTMP_320RegClassID: 1269 case AMDGPU::SGPR_352RegClassID: 1270 case AMDGPU::TTMP_352RegClassID: 1271 case AMDGPU::SGPR_384RegClassID: 1272 case AMDGPU::TTMP_384RegClassID: 1273 case AMDGPU::SGPR_512RegClassID: 1274 case AMDGPU::TTMP_512RegClassID: 1275 shift = 2; 1276 break; 1277 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 1278 // this bundle? 1279 default: 1280 llvm_unreachable("unhandled register class"); 1281 } 1282 1283 if (Val % (1 << shift)) { 1284 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 1285 << ": scalar reg isn't aligned " << Val; 1286 } 1287 1288 return createRegOperand(SRegClassID, Val >> shift); 1289 } 1290 1291 MCOperand AMDGPUDisassembler::createVGPR16Operand(unsigned RegIdx, 1292 bool IsHi) const { 1293 unsigned RegIdxInVGPR16 = RegIdx * 2 + (IsHi ? 1 : 0); 1294 return createRegOperand(AMDGPU::VGPR_16RegClassID, RegIdxInVGPR16); 1295 } 1296 1297 // Decode Literals for insts which always have a literal in the encoding 1298 MCOperand 1299 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1300 if (HasLiteral) { 1301 assert( 1302 AMDGPU::hasVOPD(STI) && 1303 "Should only decode multiple kimm with VOPD, check VSrc operand types"); 1304 if (Literal != Val) 1305 return errOperand(Val, "More than one unique literal is illegal"); 1306 } 1307 HasLiteral = true; 1308 Literal = Val; 1309 return MCOperand::createImm(Literal); 1310 } 1311 1312 MCOperand AMDGPUDisassembler::decodeLiteralConstant(bool ExtendFP64) const { 1313 // For now all literal constants are supposed to be unsigned integer 1314 // ToDo: deal with signed/unsigned 64-bit integer constants 1315 // ToDo: deal with float/double constants 1316 if (!HasLiteral) { 1317 if (Bytes.size() < 4) { 1318 return errOperand(0, "cannot read literal, inst bytes left " + 1319 Twine(Bytes.size())); 1320 } 1321 HasLiteral = true; 1322 Literal = Literal64 = eatBytes<uint32_t>(Bytes); 1323 if (ExtendFP64) 1324 Literal64 <<= 32; 1325 } 1326 return MCOperand::createImm(ExtendFP64 ? Literal64 : Literal); 1327 } 1328 1329 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1330 using namespace AMDGPU::EncValues; 1331 1332 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1333 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1334 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1335 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1336 // Cast prevents negative overflow. 1337 } 1338 1339 static int64_t getInlineImmVal32(unsigned Imm) { 1340 switch (Imm) { 1341 case 240: 1342 return llvm::bit_cast<uint32_t>(0.5f); 1343 case 241: 1344 return llvm::bit_cast<uint32_t>(-0.5f); 1345 case 242: 1346 return llvm::bit_cast<uint32_t>(1.0f); 1347 case 243: 1348 return llvm::bit_cast<uint32_t>(-1.0f); 1349 case 244: 1350 return llvm::bit_cast<uint32_t>(2.0f); 1351 case 245: 1352 return llvm::bit_cast<uint32_t>(-2.0f); 1353 case 246: 1354 return llvm::bit_cast<uint32_t>(4.0f); 1355 case 247: 1356 return llvm::bit_cast<uint32_t>(-4.0f); 1357 case 248: // 1 / (2 * PI) 1358 return 0x3e22f983; 1359 default: 1360 llvm_unreachable("invalid fp inline imm"); 1361 } 1362 } 1363 1364 static int64_t getInlineImmVal64(unsigned Imm) { 1365 switch (Imm) { 1366 case 240: 1367 return llvm::bit_cast<uint64_t>(0.5); 1368 case 241: 1369 return llvm::bit_cast<uint64_t>(-0.5); 1370 case 242: 1371 return llvm::bit_cast<uint64_t>(1.0); 1372 case 243: 1373 return llvm::bit_cast<uint64_t>(-1.0); 1374 case 244: 1375 return llvm::bit_cast<uint64_t>(2.0); 1376 case 245: 1377 return llvm::bit_cast<uint64_t>(-2.0); 1378 case 246: 1379 return llvm::bit_cast<uint64_t>(4.0); 1380 case 247: 1381 return llvm::bit_cast<uint64_t>(-4.0); 1382 case 248: // 1 / (2 * PI) 1383 return 0x3fc45f306dc9c882; 1384 default: 1385 llvm_unreachable("invalid fp inline imm"); 1386 } 1387 } 1388 1389 static int64_t getInlineImmVal16(unsigned Imm) { 1390 switch (Imm) { 1391 case 240: 1392 return 0x3800; 1393 case 241: 1394 return 0xB800; 1395 case 242: 1396 return 0x3C00; 1397 case 243: 1398 return 0xBC00; 1399 case 244: 1400 return 0x4000; 1401 case 245: 1402 return 0xC000; 1403 case 246: 1404 return 0x4400; 1405 case 247: 1406 return 0xC400; 1407 case 248: // 1 / (2 * PI) 1408 return 0x3118; 1409 default: 1410 llvm_unreachable("invalid fp inline imm"); 1411 } 1412 } 1413 1414 MCOperand AMDGPUDisassembler::decodeFPImmed(unsigned ImmWidth, unsigned Imm) { 1415 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1416 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1417 1418 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1419 // ImmWidth 0 is a default case where operand should not allow immediates. 1420 // Imm value is still decoded into 32 bit immediate operand, inst printer will 1421 // use it to print verbose error message. 1422 switch (ImmWidth) { 1423 case 0: 1424 case 32: 1425 return MCOperand::createImm(getInlineImmVal32(Imm)); 1426 case 64: 1427 return MCOperand::createImm(getInlineImmVal64(Imm)); 1428 case 16: 1429 return MCOperand::createImm(getInlineImmVal16(Imm)); 1430 default: 1431 llvm_unreachable("implement me"); 1432 } 1433 } 1434 1435 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1436 using namespace AMDGPU; 1437 1438 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1439 switch (Width) { 1440 default: // fall 1441 case OPW32: 1442 case OPW16: 1443 case OPWV216: 1444 return VGPR_32RegClassID; 1445 case OPW64: 1446 case OPWV232: return VReg_64RegClassID; 1447 case OPW96: return VReg_96RegClassID; 1448 case OPW128: return VReg_128RegClassID; 1449 case OPW160: return VReg_160RegClassID; 1450 case OPW256: return VReg_256RegClassID; 1451 case OPW288: return VReg_288RegClassID; 1452 case OPW320: return VReg_320RegClassID; 1453 case OPW352: return VReg_352RegClassID; 1454 case OPW384: return VReg_384RegClassID; 1455 case OPW512: return VReg_512RegClassID; 1456 case OPW1024: return VReg_1024RegClassID; 1457 } 1458 } 1459 1460 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1461 using namespace AMDGPU; 1462 1463 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1464 switch (Width) { 1465 default: // fall 1466 case OPW32: 1467 case OPW16: 1468 case OPWV216: 1469 return AGPR_32RegClassID; 1470 case OPW64: 1471 case OPWV232: return AReg_64RegClassID; 1472 case OPW96: return AReg_96RegClassID; 1473 case OPW128: return AReg_128RegClassID; 1474 case OPW160: return AReg_160RegClassID; 1475 case OPW256: return AReg_256RegClassID; 1476 case OPW288: return AReg_288RegClassID; 1477 case OPW320: return AReg_320RegClassID; 1478 case OPW352: return AReg_352RegClassID; 1479 case OPW384: return AReg_384RegClassID; 1480 case OPW512: return AReg_512RegClassID; 1481 case OPW1024: return AReg_1024RegClassID; 1482 } 1483 } 1484 1485 1486 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1487 using namespace AMDGPU; 1488 1489 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1490 switch (Width) { 1491 default: // fall 1492 case OPW32: 1493 case OPW16: 1494 case OPWV216: 1495 return SGPR_32RegClassID; 1496 case OPW64: 1497 case OPWV232: return SGPR_64RegClassID; 1498 case OPW96: return SGPR_96RegClassID; 1499 case OPW128: return SGPR_128RegClassID; 1500 case OPW160: return SGPR_160RegClassID; 1501 case OPW256: return SGPR_256RegClassID; 1502 case OPW288: return SGPR_288RegClassID; 1503 case OPW320: return SGPR_320RegClassID; 1504 case OPW352: return SGPR_352RegClassID; 1505 case OPW384: return SGPR_384RegClassID; 1506 case OPW512: return SGPR_512RegClassID; 1507 } 1508 } 1509 1510 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1511 using namespace AMDGPU; 1512 1513 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1514 switch (Width) { 1515 default: // fall 1516 case OPW32: 1517 case OPW16: 1518 case OPWV216: 1519 return TTMP_32RegClassID; 1520 case OPW64: 1521 case OPWV232: return TTMP_64RegClassID; 1522 case OPW128: return TTMP_128RegClassID; 1523 case OPW256: return TTMP_256RegClassID; 1524 case OPW288: return TTMP_288RegClassID; 1525 case OPW320: return TTMP_320RegClassID; 1526 case OPW352: return TTMP_352RegClassID; 1527 case OPW384: return TTMP_384RegClassID; 1528 case OPW512: return TTMP_512RegClassID; 1529 } 1530 } 1531 1532 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1533 using namespace AMDGPU::EncValues; 1534 1535 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1536 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1537 1538 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1539 } 1540 1541 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1542 bool MandatoryLiteral, 1543 unsigned ImmWidth, bool IsFP) const { 1544 using namespace AMDGPU::EncValues; 1545 1546 assert(Val < 1024); // enum10 1547 1548 bool IsAGPR = Val & 512; 1549 Val &= 511; 1550 1551 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1552 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1553 : getVgprClassId(Width), Val - VGPR_MIN); 1554 } 1555 return decodeNonVGPRSrcOp(Width, Val & 0xFF, MandatoryLiteral, ImmWidth, 1556 IsFP); 1557 } 1558 1559 MCOperand AMDGPUDisassembler::decodeNonVGPRSrcOp(const OpWidthTy Width, 1560 unsigned Val, 1561 bool MandatoryLiteral, 1562 unsigned ImmWidth, 1563 bool IsFP) const { 1564 // Cases when Val{8} is 1 (vgpr, agpr or true 16 vgpr) should have been 1565 // decoded earlier. 1566 assert(Val < (1 << 8) && "9-bit Src encoding when Val{8} is 0"); 1567 using namespace AMDGPU::EncValues; 1568 1569 if (Val <= SGPR_MAX) { 1570 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1571 static_assert(SGPR_MIN == 0); 1572 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1573 } 1574 1575 int TTmpIdx = getTTmpIdx(Val); 1576 if (TTmpIdx >= 0) { 1577 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1578 } 1579 1580 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1581 return decodeIntImmed(Val); 1582 1583 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1584 return decodeFPImmed(ImmWidth, Val); 1585 1586 if (Val == LITERAL_CONST) { 1587 if (MandatoryLiteral) 1588 // Keep a sentinel value for deferred setting 1589 return MCOperand::createImm(LITERAL_CONST); 1590 else 1591 return decodeLiteralConstant(IsFP && ImmWidth == 64); 1592 } 1593 1594 switch (Width) { 1595 case OPW32: 1596 case OPW16: 1597 case OPWV216: 1598 return decodeSpecialReg32(Val); 1599 case OPW64: 1600 case OPWV232: 1601 return decodeSpecialReg64(Val); 1602 default: 1603 llvm_unreachable("unexpected immediate type"); 1604 } 1605 } 1606 1607 // Bit 0 of DstY isn't stored in the instruction, because it's always the 1608 // opposite of bit 0 of DstX. 1609 MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst, 1610 unsigned Val) const { 1611 int VDstXInd = 1612 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX); 1613 assert(VDstXInd != -1); 1614 assert(Inst.getOperand(VDstXInd).isReg()); 1615 unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg()); 1616 Val |= ~XDstReg & 1; 1617 auto Width = llvm::AMDGPUDisassembler::OPW32; 1618 return createRegOperand(getVgprClassId(Width), Val); 1619 } 1620 1621 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1622 using namespace AMDGPU; 1623 1624 switch (Val) { 1625 // clang-format off 1626 case 102: return createRegOperand(FLAT_SCR_LO); 1627 case 103: return createRegOperand(FLAT_SCR_HI); 1628 case 104: return createRegOperand(XNACK_MASK_LO); 1629 case 105: return createRegOperand(XNACK_MASK_HI); 1630 case 106: return createRegOperand(VCC_LO); 1631 case 107: return createRegOperand(VCC_HI); 1632 case 108: return createRegOperand(TBA_LO); 1633 case 109: return createRegOperand(TBA_HI); 1634 case 110: return createRegOperand(TMA_LO); 1635 case 111: return createRegOperand(TMA_HI); 1636 case 124: 1637 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1638 case 125: 1639 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1640 case 126: return createRegOperand(EXEC_LO); 1641 case 127: return createRegOperand(EXEC_HI); 1642 case 235: return createRegOperand(SRC_SHARED_BASE_LO); 1643 case 236: return createRegOperand(SRC_SHARED_LIMIT_LO); 1644 case 237: return createRegOperand(SRC_PRIVATE_BASE_LO); 1645 case 238: return createRegOperand(SRC_PRIVATE_LIMIT_LO); 1646 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1647 case 251: return createRegOperand(SRC_VCCZ); 1648 case 252: return createRegOperand(SRC_EXECZ); 1649 case 253: return createRegOperand(SRC_SCC); 1650 case 254: return createRegOperand(LDS_DIRECT); 1651 default: break; 1652 // clang-format on 1653 } 1654 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1655 } 1656 1657 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1658 using namespace AMDGPU; 1659 1660 switch (Val) { 1661 case 102: return createRegOperand(FLAT_SCR); 1662 case 104: return createRegOperand(XNACK_MASK); 1663 case 106: return createRegOperand(VCC); 1664 case 108: return createRegOperand(TBA); 1665 case 110: return createRegOperand(TMA); 1666 case 124: 1667 if (isGFX11Plus()) 1668 return createRegOperand(SGPR_NULL); 1669 break; 1670 case 125: 1671 if (!isGFX11Plus()) 1672 return createRegOperand(SGPR_NULL); 1673 break; 1674 case 126: return createRegOperand(EXEC); 1675 case 235: return createRegOperand(SRC_SHARED_BASE); 1676 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1677 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1678 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1679 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1680 case 251: return createRegOperand(SRC_VCCZ); 1681 case 252: return createRegOperand(SRC_EXECZ); 1682 case 253: return createRegOperand(SRC_SCC); 1683 default: break; 1684 } 1685 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1686 } 1687 1688 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1689 const unsigned Val, 1690 unsigned ImmWidth) const { 1691 using namespace AMDGPU::SDWA; 1692 using namespace AMDGPU::EncValues; 1693 1694 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 1695 STI.hasFeature(AMDGPU::FeatureGFX10)) { 1696 // XXX: cast to int is needed to avoid stupid warning: 1697 // compare with unsigned is always true 1698 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1699 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1700 return createRegOperand(getVgprClassId(Width), 1701 Val - SDWA9EncValues::SRC_VGPR_MIN); 1702 } 1703 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1704 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1705 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1706 return createSRegOperand(getSgprClassId(Width), 1707 Val - SDWA9EncValues::SRC_SGPR_MIN); 1708 } 1709 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1710 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1711 return createSRegOperand(getTtmpClassId(Width), 1712 Val - SDWA9EncValues::SRC_TTMP_MIN); 1713 } 1714 1715 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1716 1717 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1718 return decodeIntImmed(SVal); 1719 1720 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1721 return decodeFPImmed(ImmWidth, SVal); 1722 1723 return decodeSpecialReg32(SVal); 1724 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { 1725 return createRegOperand(getVgprClassId(Width), Val); 1726 } 1727 llvm_unreachable("unsupported target"); 1728 } 1729 1730 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1731 return decodeSDWASrc(OPW16, Val, 16); 1732 } 1733 1734 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1735 return decodeSDWASrc(OPW32, Val, 32); 1736 } 1737 1738 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1739 using namespace AMDGPU::SDWA; 1740 1741 assert((STI.hasFeature(AMDGPU::FeatureGFX9) || 1742 STI.hasFeature(AMDGPU::FeatureGFX10)) && 1743 "SDWAVopcDst should be present only on GFX9+"); 1744 1745 bool IsWave64 = STI.hasFeature(AMDGPU::FeatureWavefrontSize64); 1746 1747 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1748 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1749 1750 int TTmpIdx = getTTmpIdx(Val); 1751 if (TTmpIdx >= 0) { 1752 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1753 return createSRegOperand(TTmpClsId, TTmpIdx); 1754 } else if (Val > SGPR_MAX) { 1755 return IsWave64 ? decodeSpecialReg64(Val) 1756 : decodeSpecialReg32(Val); 1757 } else { 1758 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1759 } 1760 } else { 1761 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1762 } 1763 } 1764 1765 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1766 return STI.hasFeature(AMDGPU::FeatureWavefrontSize64) 1767 ? decodeSrcOp(OPW64, Val) 1768 : decodeSrcOp(OPW32, Val); 1769 } 1770 1771 MCOperand AMDGPUDisassembler::decodeSplitBarrier(unsigned Val) const { 1772 return decodeSrcOp(OPW32, Val); 1773 } 1774 1775 bool AMDGPUDisassembler::isVI() const { 1776 return STI.hasFeature(AMDGPU::FeatureVolcanicIslands); 1777 } 1778 1779 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1780 1781 bool AMDGPUDisassembler::isGFX90A() const { 1782 return STI.hasFeature(AMDGPU::FeatureGFX90AInsts); 1783 } 1784 1785 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1786 1787 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1788 1789 bool AMDGPUDisassembler::isGFX10Plus() const { 1790 return AMDGPU::isGFX10Plus(STI); 1791 } 1792 1793 bool AMDGPUDisassembler::isGFX11() const { 1794 return STI.hasFeature(AMDGPU::FeatureGFX11); 1795 } 1796 1797 bool AMDGPUDisassembler::isGFX11Plus() const { 1798 return AMDGPU::isGFX11Plus(STI); 1799 } 1800 1801 bool AMDGPUDisassembler::isGFX12Plus() const { 1802 return AMDGPU::isGFX12Plus(STI); 1803 } 1804 1805 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1806 return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch); 1807 } 1808 1809 bool AMDGPUDisassembler::hasKernargPreload() const { 1810 return AMDGPU::hasKernargPreload(STI); 1811 } 1812 1813 //===----------------------------------------------------------------------===// 1814 // AMDGPU specific symbol handling 1815 //===----------------------------------------------------------------------===// 1816 #define GET_FIELD(MASK) (AMDHSA_BITS_GET(FourByteBuffer, MASK)) 1817 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1818 do { \ 1819 KdStream << Indent << DIRECTIVE " " << GET_FIELD(MASK) << '\n'; \ 1820 } while (0) 1821 #define PRINT_PSEUDO_DIRECTIVE_COMMENT(DIRECTIVE, MASK) \ 1822 do { \ 1823 KdStream << Indent << MAI.getCommentString() << ' ' << DIRECTIVE " " \ 1824 << GET_FIELD(MASK) << '\n'; \ 1825 } while (0) 1826 1827 // NOLINTNEXTLINE(readability-identifier-naming) 1828 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1829 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1830 using namespace amdhsa; 1831 StringRef Indent = "\t"; 1832 1833 // We cannot accurately backward compute #VGPRs used from 1834 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1835 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1836 // simply calculate the inverse of what the assembler does. 1837 1838 uint32_t GranulatedWorkitemVGPRCount = 1839 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT); 1840 1841 uint32_t NextFreeVGPR = 1842 (GranulatedWorkitemVGPRCount + 1) * 1843 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI, EnableWavefrontSize32); 1844 1845 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1846 1847 // We cannot backward compute values used to calculate 1848 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1849 // directives can't be computed: 1850 // .amdhsa_reserve_vcc 1851 // .amdhsa_reserve_flat_scratch 1852 // .amdhsa_reserve_xnack_mask 1853 // They take their respective default values if not specified in the assembly. 1854 // 1855 // GRANULATED_WAVEFRONT_SGPR_COUNT 1856 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1857 // 1858 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1859 // are set to 0. So while disassembling we consider that: 1860 // 1861 // GRANULATED_WAVEFRONT_SGPR_COUNT 1862 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1863 // 1864 // The disassembler cannot recover the original values of those 3 directives. 1865 1866 uint32_t GranulatedWavefrontSGPRCount = 1867 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT); 1868 1869 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1870 return MCDisassembler::Fail; 1871 1872 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1873 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1874 1875 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1876 if (!hasArchitectedFlatScratch()) 1877 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1878 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1879 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1880 1881 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1882 return MCDisassembler::Fail; 1883 1884 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1885 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1886 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1887 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1888 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1889 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1890 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1891 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1892 1893 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1894 return MCDisassembler::Fail; 1895 1896 if (!isGFX12Plus()) 1897 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", 1898 COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP); 1899 1900 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1901 return MCDisassembler::Fail; 1902 1903 if (!isGFX12Plus()) 1904 PRINT_DIRECTIVE(".amdhsa_ieee_mode", 1905 COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE); 1906 1907 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1908 return MCDisassembler::Fail; 1909 1910 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1911 return MCDisassembler::Fail; 1912 1913 if (isGFX9Plus()) 1914 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL); 1915 1916 if (!isGFX9Plus()) 1917 if (FourByteBuffer & COMPUTE_PGM_RSRC1_GFX6_GFX8_RESERVED0) 1918 return MCDisassembler::Fail; 1919 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED1) 1920 return MCDisassembler::Fail; 1921 if (!isGFX10Plus()) 1922 if (FourByteBuffer & COMPUTE_PGM_RSRC1_GFX6_GFX9_RESERVED2) 1923 return MCDisassembler::Fail; 1924 1925 if (isGFX10Plus()) { 1926 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1927 COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE); 1928 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED); 1929 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS); 1930 } 1931 1932 if (isGFX12Plus()) 1933 PRINT_DIRECTIVE(".amdhsa_round_robin_scheduling", 1934 COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN); 1935 1936 return MCDisassembler::Success; 1937 } 1938 1939 // NOLINTNEXTLINE(readability-identifier-naming) 1940 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1941 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1942 using namespace amdhsa; 1943 StringRef Indent = "\t"; 1944 if (hasArchitectedFlatScratch()) 1945 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1946 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1947 else 1948 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1949 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1950 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1951 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1952 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1953 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1954 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1955 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1956 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1957 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1958 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1959 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1960 1961 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1962 return MCDisassembler::Fail; 1963 1964 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1965 return MCDisassembler::Fail; 1966 1967 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1968 return MCDisassembler::Fail; 1969 1970 PRINT_DIRECTIVE( 1971 ".amdhsa_exception_fp_ieee_invalid_op", 1972 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1973 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1974 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1975 PRINT_DIRECTIVE( 1976 ".amdhsa_exception_fp_ieee_div_zero", 1977 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1978 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1979 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1980 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1981 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1982 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1983 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1984 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1985 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1986 1987 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1988 return MCDisassembler::Fail; 1989 1990 return MCDisassembler::Success; 1991 } 1992 1993 // NOLINTNEXTLINE(readability-identifier-naming) 1994 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3( 1995 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1996 using namespace amdhsa; 1997 StringRef Indent = "\t"; 1998 if (isGFX90A()) { 1999 KdStream << Indent << ".amdhsa_accum_offset " 2000 << (GET_FIELD(COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4 2001 << '\n'; 2002 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED0) 2003 return MCDisassembler::Fail; 2004 PRINT_DIRECTIVE(".amdhsa_tg_split", COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT); 2005 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED1) 2006 return MCDisassembler::Fail; 2007 } else if (isGFX10Plus()) { 2008 // Bits [0-3]. 2009 if (!isGFX12Plus()) { 2010 if (!EnableWavefrontSize32 || !*EnableWavefrontSize32) { 2011 PRINT_DIRECTIVE(".amdhsa_shared_vgpr_count", 2012 COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT); 2013 } else { 2014 PRINT_PSEUDO_DIRECTIVE_COMMENT( 2015 "SHARED_VGPR_COUNT", 2016 COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT); 2017 } 2018 } else { 2019 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX12_PLUS_RESERVED0) 2020 return MCDisassembler::Fail; 2021 } 2022 2023 // Bits [4-11]. 2024 if (isGFX11()) { 2025 PRINT_PSEUDO_DIRECTIVE_COMMENT("INST_PREF_SIZE", 2026 COMPUTE_PGM_RSRC3_GFX11_INST_PREF_SIZE); 2027 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_START", 2028 COMPUTE_PGM_RSRC3_GFX11_TRAP_ON_START); 2029 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_END", 2030 COMPUTE_PGM_RSRC3_GFX11_TRAP_ON_END); 2031 } else if (isGFX12Plus()) { 2032 PRINT_PSEUDO_DIRECTIVE_COMMENT( 2033 "INST_PREF_SIZE", COMPUTE_PGM_RSRC3_GFX12_PLUS_INST_PREF_SIZE); 2034 } else { 2035 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_RESERVED1) 2036 return MCDisassembler::Fail; 2037 } 2038 2039 // Bits [12]. 2040 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_PLUS_RESERVED2) 2041 return MCDisassembler::Fail; 2042 2043 // Bits [13]. 2044 if (isGFX12Plus()) { 2045 PRINT_PSEUDO_DIRECTIVE_COMMENT("GLG_EN", 2046 COMPUTE_PGM_RSRC3_GFX12_PLUS_GLG_EN); 2047 } else { 2048 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_GFX11_RESERVED3) 2049 return MCDisassembler::Fail; 2050 } 2051 2052 // Bits [14-30]. 2053 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_PLUS_RESERVED4) 2054 return MCDisassembler::Fail; 2055 2056 // Bits [31]. 2057 if (isGFX11Plus()) { 2058 PRINT_PSEUDO_DIRECTIVE_COMMENT("IMAGE_OP", 2059 COMPUTE_PGM_RSRC3_GFX11_PLUS_IMAGE_OP); 2060 } else { 2061 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_RESERVED5) 2062 return MCDisassembler::Fail; 2063 } 2064 } else if (FourByteBuffer) { 2065 return MCDisassembler::Fail; 2066 } 2067 return MCDisassembler::Success; 2068 } 2069 #undef PRINT_PSEUDO_DIRECTIVE_COMMENT 2070 #undef PRINT_DIRECTIVE 2071 #undef GET_FIELD 2072 2073 MCDisassembler::DecodeStatus 2074 AMDGPUDisassembler::decodeKernelDescriptorDirective( 2075 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 2076 raw_string_ostream &KdStream) const { 2077 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 2078 do { \ 2079 KdStream << Indent << DIRECTIVE " " \ 2080 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 2081 } while (0) 2082 2083 uint16_t TwoByteBuffer = 0; 2084 uint32_t FourByteBuffer = 0; 2085 2086 StringRef ReservedBytes; 2087 StringRef Indent = "\t"; 2088 2089 assert(Bytes.size() == 64); 2090 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 2091 2092 switch (Cursor.tell()) { 2093 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 2094 FourByteBuffer = DE.getU32(Cursor); 2095 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 2096 << '\n'; 2097 return MCDisassembler::Success; 2098 2099 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 2100 FourByteBuffer = DE.getU32(Cursor); 2101 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 2102 << FourByteBuffer << '\n'; 2103 return MCDisassembler::Success; 2104 2105 case amdhsa::KERNARG_SIZE_OFFSET: 2106 FourByteBuffer = DE.getU32(Cursor); 2107 KdStream << Indent << ".amdhsa_kernarg_size " 2108 << FourByteBuffer << '\n'; 2109 return MCDisassembler::Success; 2110 2111 case amdhsa::RESERVED0_OFFSET: 2112 // 4 reserved bytes, must be 0. 2113 ReservedBytes = DE.getBytes(Cursor, 4); 2114 for (int I = 0; I < 4; ++I) { 2115 if (ReservedBytes[I] != 0) { 2116 return MCDisassembler::Fail; 2117 } 2118 } 2119 return MCDisassembler::Success; 2120 2121 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 2122 // KERNEL_CODE_ENTRY_BYTE_OFFSET 2123 // So far no directive controls this for Code Object V3, so simply skip for 2124 // disassembly. 2125 DE.skip(Cursor, 8); 2126 return MCDisassembler::Success; 2127 2128 case amdhsa::RESERVED1_OFFSET: 2129 // 20 reserved bytes, must be 0. 2130 ReservedBytes = DE.getBytes(Cursor, 20); 2131 for (int I = 0; I < 20; ++I) { 2132 if (ReservedBytes[I] != 0) { 2133 return MCDisassembler::Fail; 2134 } 2135 } 2136 return MCDisassembler::Success; 2137 2138 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 2139 FourByteBuffer = DE.getU32(Cursor); 2140 return decodeCOMPUTE_PGM_RSRC3(FourByteBuffer, KdStream); 2141 2142 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 2143 FourByteBuffer = DE.getU32(Cursor); 2144 return decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream); 2145 2146 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 2147 FourByteBuffer = DE.getU32(Cursor); 2148 return decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream); 2149 2150 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 2151 using namespace amdhsa; 2152 TwoByteBuffer = DE.getU16(Cursor); 2153 2154 if (!hasArchitectedFlatScratch()) 2155 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 2156 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 2157 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 2158 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 2159 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 2160 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 2161 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 2162 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 2163 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 2164 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 2165 if (!hasArchitectedFlatScratch()) 2166 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 2167 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 2168 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 2169 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 2170 2171 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 2172 return MCDisassembler::Fail; 2173 2174 // Reserved for GFX9 2175 if (isGFX9() && 2176 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 2177 return MCDisassembler::Fail; 2178 } else if (isGFX10Plus()) { 2179 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 2180 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2181 } 2182 2183 if (AMDGPU::getAmdhsaCodeObjectVersion() >= AMDGPU::AMDHSA_COV5) 2184 PRINT_DIRECTIVE(".amdhsa_uses_dynamic_stack", 2185 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK); 2186 2187 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 2188 return MCDisassembler::Fail; 2189 2190 return MCDisassembler::Success; 2191 2192 case amdhsa::KERNARG_PRELOAD_OFFSET: 2193 using namespace amdhsa; 2194 TwoByteBuffer = DE.getU16(Cursor); 2195 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_LENGTH) { 2196 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_length", 2197 KERNARG_PRELOAD_SPEC_LENGTH); 2198 } 2199 2200 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_OFFSET) { 2201 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_offset", 2202 KERNARG_PRELOAD_SPEC_OFFSET); 2203 } 2204 return MCDisassembler::Success; 2205 2206 case amdhsa::RESERVED3_OFFSET: 2207 // 4 bytes from here are reserved, must be 0. 2208 ReservedBytes = DE.getBytes(Cursor, 4); 2209 for (int I = 0; I < 4; ++I) { 2210 if (ReservedBytes[I] != 0) 2211 return MCDisassembler::Fail; 2212 } 2213 return MCDisassembler::Success; 2214 2215 default: 2216 llvm_unreachable("Unhandled index. Case statements cover everything."); 2217 return MCDisassembler::Fail; 2218 } 2219 #undef PRINT_DIRECTIVE 2220 } 2221 2222 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 2223 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 2224 // CP microcode requires the kernel descriptor to be 64 aligned. 2225 if (Bytes.size() != 64 || KdAddress % 64 != 0) 2226 return MCDisassembler::Fail; 2227 2228 // FIXME: We can't actually decode "in order" as is done below, as e.g. GFX10 2229 // requires us to know the setting of .amdhsa_wavefront_size32 in order to 2230 // accurately produce .amdhsa_next_free_vgpr, and they appear in the wrong 2231 // order. Workaround this by first looking up .amdhsa_wavefront_size32 here 2232 // when required. 2233 if (isGFX10Plus()) { 2234 uint16_t KernelCodeProperties = 2235 support::endian::read16(&Bytes[amdhsa::KERNEL_CODE_PROPERTIES_OFFSET], 2236 llvm::endianness::little); 2237 EnableWavefrontSize32 = 2238 AMDHSA_BITS_GET(KernelCodeProperties, 2239 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2240 } 2241 2242 std::string Kd; 2243 raw_string_ostream KdStream(Kd); 2244 KdStream << ".amdhsa_kernel " << KdName << '\n'; 2245 2246 DataExtractor::Cursor C(0); 2247 while (C && C.tell() < Bytes.size()) { 2248 MCDisassembler::DecodeStatus Status = 2249 decodeKernelDescriptorDirective(C, Bytes, KdStream); 2250 2251 cantFail(C.takeError()); 2252 2253 if (Status == MCDisassembler::Fail) 2254 return MCDisassembler::Fail; 2255 } 2256 KdStream << ".end_amdhsa_kernel\n"; 2257 outs() << KdStream.str(); 2258 return MCDisassembler::Success; 2259 } 2260 2261 std::optional<MCDisassembler::DecodeStatus> 2262 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 2263 ArrayRef<uint8_t> Bytes, uint64_t Address, 2264 raw_ostream &CStream) const { 2265 // Right now only kernel descriptor needs to be handled. 2266 // We ignore all other symbols for target specific handling. 2267 // TODO: 2268 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 2269 // Object V2 and V3 when symbols are marked protected. 2270 2271 // amd_kernel_code_t for Code Object V2. 2272 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 2273 Size = 256; 2274 return MCDisassembler::Fail; 2275 } 2276 2277 // Code Object V3 kernel descriptors. 2278 StringRef Name = Symbol.Name; 2279 if (Symbol.Type == ELF::STT_OBJECT && Name.ends_with(StringRef(".kd"))) { 2280 Size = 64; // Size = 64 regardless of success or failure. 2281 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 2282 } 2283 return std::nullopt; 2284 } 2285 2286 //===----------------------------------------------------------------------===// 2287 // AMDGPUSymbolizer 2288 //===----------------------------------------------------------------------===// 2289 2290 // Try to find symbol name for specified label 2291 bool AMDGPUSymbolizer::tryAddingSymbolicOperand( 2292 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, 2293 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, 2294 uint64_t /*OpSize*/, uint64_t /*InstSize*/) { 2295 2296 if (!IsBranch) { 2297 return false; 2298 } 2299 2300 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 2301 if (!Symbols) 2302 return false; 2303 2304 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 2305 return Val.Addr == static_cast<uint64_t>(Value) && 2306 Val.Type == ELF::STT_NOTYPE; 2307 }); 2308 if (Result != Symbols->end()) { 2309 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 2310 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 2311 Inst.addOperand(MCOperand::createExpr(Add)); 2312 return true; 2313 } 2314 // Add to list of referenced addresses, so caller can synthesize a label. 2315 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 2316 return false; 2317 } 2318 2319 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 2320 int64_t Value, 2321 uint64_t Address) { 2322 llvm_unreachable("unimplemented"); 2323 } 2324 2325 //===----------------------------------------------------------------------===// 2326 // Initialization 2327 //===----------------------------------------------------------------------===// 2328 2329 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 2330 LLVMOpInfoCallback /*GetOpInfo*/, 2331 LLVMSymbolLookupCallback /*SymbolLookUp*/, 2332 void *DisInfo, 2333 MCContext *Ctx, 2334 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 2335 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 2336 } 2337 2338 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 2339 const MCSubtargetInfo &STI, 2340 MCContext &Ctx) { 2341 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 2342 } 2343 2344 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 2345 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 2346 createAMDGPUDisassembler); 2347 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 2348 createAMDGPUSymbolizer); 2349 } 2350