1 //===-- AArch64BranchTargets.cpp -- Harden code using v8.5-A BTI extension -==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This pass inserts BTI instructions at the start of every function and basic 10 // block which could be indirectly called. The hardware will (when enabled) 11 // trap when an indirect branch or call instruction targets an instruction 12 // which is not a valid BTI instruction. This is intended to guard against 13 // control-flow hijacking attacks. Note that this does not do anything for RET 14 // instructions, as they can be more precisely protected by return address 15 // signing. 16 // 17 //===----------------------------------------------------------------------===// 18 19 #include "AArch64MachineFunctionInfo.h" 20 #include "AArch64Subtarget.h" 21 #include "llvm/CodeGen/MachineFunctionPass.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineJumpTableInfo.h" 24 #include "llvm/CodeGen/MachineModuleInfo.h" 25 #include "llvm/Support/Debug.h" 26 27 using namespace llvm; 28 29 #define DEBUG_TYPE "aarch64-branch-targets" 30 #define AARCH64_BRANCH_TARGETS_NAME "AArch64 Branch Targets" 31 32 namespace { 33 class AArch64BranchTargets : public MachineFunctionPass { 34 public: 35 static char ID; 36 AArch64BranchTargets() : MachineFunctionPass(ID) {} 37 void getAnalysisUsage(AnalysisUsage &AU) const override; 38 bool runOnMachineFunction(MachineFunction &MF) override; 39 StringRef getPassName() const override { return AARCH64_BRANCH_TARGETS_NAME; } 40 41 private: 42 void addBTI(MachineBasicBlock &MBB, bool CouldCall, bool CouldJump); 43 }; 44 } // end anonymous namespace 45 46 char AArch64BranchTargets::ID = 0; 47 48 INITIALIZE_PASS(AArch64BranchTargets, "aarch64-branch-targets", 49 AARCH64_BRANCH_TARGETS_NAME, false, false) 50 51 void AArch64BranchTargets::getAnalysisUsage(AnalysisUsage &AU) const { 52 AU.setPreservesCFG(); 53 MachineFunctionPass::getAnalysisUsage(AU); 54 } 55 56 FunctionPass *llvm::createAArch64BranchTargetsPass() { 57 return new AArch64BranchTargets(); 58 } 59 60 bool AArch64BranchTargets::runOnMachineFunction(MachineFunction &MF) { 61 if (!MF.getInfo<AArch64FunctionInfo>()->branchTargetEnforcement()) 62 return false; 63 64 LLVM_DEBUG( 65 dbgs() << "********** AArch64 Branch Targets **********\n" 66 << "********** Function: " << MF.getName() << '\n'); 67 68 // LLVM does not consider basic blocks which are the targets of jump tables 69 // to be address-taken (the address can't escape anywhere else), but they are 70 // used for indirect branches, so need BTI instructions. 71 SmallPtrSet<MachineBasicBlock *, 8> JumpTableTargets; 72 if (auto *JTI = MF.getJumpTableInfo()) 73 for (auto &JTE : JTI->getJumpTables()) 74 for (auto *MBB : JTE.MBBs) 75 JumpTableTargets.insert(MBB); 76 77 bool MadeChange = false; 78 for (MachineBasicBlock &MBB : MF) { 79 bool CouldCall = false, CouldJump = false; 80 // Even in cases where a function has internal linkage and is only called 81 // directly in its translation unit, it can still be called indirectly if 82 // the linker decides to add a thunk to it for whatever reason (say, for 83 // example, if it is finally placed far from its call site and a BL is not 84 // long-range enough). PLT entries and tail-calls use BR, but when they are 85 // are in guarded pages should all use x16 or x17 to hold the called 86 // address, so we don't need to set CouldJump here. BR instructions in 87 // non-guarded pages (which might be non-BTI-aware code) are allowed to 88 // branch to a "BTI c" using any register. 89 if (&MBB == &*MF.begin()) 90 CouldCall = true; 91 92 // If the block itself is address-taken, it could be indirectly branched 93 // to, but not called. 94 if (MBB.hasAddressTaken() || JumpTableTargets.count(&MBB)) 95 CouldJump = true; 96 97 if (CouldCall || CouldJump) { 98 addBTI(MBB, CouldCall, CouldJump); 99 MadeChange = true; 100 } 101 } 102 103 return MadeChange; 104 } 105 106 void AArch64BranchTargets::addBTI(MachineBasicBlock &MBB, bool CouldCall, 107 bool CouldJump) { 108 LLVM_DEBUG(dbgs() << "Adding BTI " << (CouldJump ? "j" : "") 109 << (CouldCall ? "c" : "") << " to " << MBB.getName() 110 << "\n"); 111 112 const AArch64InstrInfo *TII = static_cast<const AArch64InstrInfo *>( 113 MBB.getParent()->getSubtarget().getInstrInfo()); 114 115 unsigned HintNum = 32; 116 if (CouldCall) 117 HintNum |= 2; 118 if (CouldJump) 119 HintNum |= 4; 120 assert(HintNum != 32 && "No target kinds!"); 121 122 auto MBBI = MBB.begin(); 123 124 // Skip the meta instructions, those will be removed anyway. 125 for (; MBBI != MBB.end() && 126 (MBBI->isMetaInstruction() || MBBI->getOpcode() == AArch64::EMITBKEY); 127 ++MBBI) 128 ; 129 130 // SCTLR_EL1.BT[01] is set to 0 by default which means 131 // PACI[AB]SP are implicitly BTI C so no BTI C instruction is needed there. 132 if (MBBI != MBB.end() && HintNum == 34 && 133 (MBBI->getOpcode() == AArch64::PACIASP || 134 MBBI->getOpcode() == AArch64::PACIBSP)) 135 return; 136 137 BuildMI(MBB, MBB.begin(), MBB.findDebugLoc(MBB.begin()), 138 TII->get(AArch64::HINT)) 139 .addImm(HintNum); 140 } 141