1 //===- InstrEmitter.h - Emit MachineInstrs for the SelectionDAG -*- C++ -*--==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This declares the Emit routines for the SelectionDAG class, which creates 10 // MachineInstrs based on the decisions of the SelectionDAG instruction 11 // selection. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_INSTREMITTER_H 16 #define LLVM_LIB_CODEGEN_SELECTIONDAG_INSTREMITTER_H 17 18 #include "llvm/ADT/DenseMap.h" 19 #include "llvm/CodeGen/MachineBasicBlock.h" 20 #include "llvm/CodeGen/SelectionDAGNodes.h" 21 22 namespace llvm { 23 24 class MachineInstrBuilder; 25 class MCInstrDesc; 26 class SDDbgLabel; 27 class SDDbgValue; 28 class TargetLowering; 29 30 class LLVM_LIBRARY_VISIBILITY InstrEmitter { 31 MachineFunction *MF; 32 MachineRegisterInfo *MRI; 33 const TargetInstrInfo *TII; 34 const TargetRegisterInfo *TRI; 35 const TargetLowering *TLI; 36 37 MachineBasicBlock *MBB; 38 MachineBasicBlock::iterator InsertPos; 39 40 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 41 /// implicit physical register output. 42 void EmitCopyFromReg(SDNode *Node, unsigned ResNo, 43 bool IsClone, bool IsCloned, 44 Register SrcReg, 45 DenseMap<SDValue, Register> &VRBaseMap); 46 47 void CreateVirtualRegisters(SDNode *Node, 48 MachineInstrBuilder &MIB, 49 const MCInstrDesc &II, 50 bool IsClone, bool IsCloned, 51 DenseMap<SDValue, Register> &VRBaseMap); 52 53 /// getVR - Return the virtual register corresponding to the specified result 54 /// of the specified node. 55 Register getVR(SDValue Op, 56 DenseMap<SDValue, Register> &VRBaseMap); 57 58 /// AddRegisterOperand - Add the specified register as an operand to the 59 /// specified machine instr. Insert register copies if the register is 60 /// not in the required register class. 61 void AddRegisterOperand(MachineInstrBuilder &MIB, 62 SDValue Op, 63 unsigned IIOpNum, 64 const MCInstrDesc *II, 65 DenseMap<SDValue, Register> &VRBaseMap, 66 bool IsDebug, bool IsClone, bool IsCloned); 67 68 /// AddOperand - Add the specified operand to the specified machine instr. II 69 /// specifies the instruction information for the node, and IIOpNum is the 70 /// operand number (in the II) that we are adding. IIOpNum and II are used for 71 /// assertions only. 72 void AddOperand(MachineInstrBuilder &MIB, 73 SDValue Op, 74 unsigned IIOpNum, 75 const MCInstrDesc *II, 76 DenseMap<SDValue, Register> &VRBaseMap, 77 bool IsDebug, bool IsClone, bool IsCloned); 78 79 /// ConstrainForSubReg - Try to constrain VReg to a register class that 80 /// supports SubIdx sub-registers. Emit a copy if that isn't possible. 81 /// Return the virtual register to use. 82 Register ConstrainForSubReg(Register VReg, unsigned SubIdx, MVT VT, 83 bool isDivergent, const DebugLoc &DL); 84 85 /// EmitSubregNode - Generate machine code for subreg nodes. 86 /// 87 void EmitSubregNode(SDNode *Node, DenseMap<SDValue, Register> &VRBaseMap, 88 bool IsClone, bool IsCloned); 89 90 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 91 /// COPY_TO_REGCLASS is just a normal copy, except that the destination 92 /// register is constrained to be in a particular register class. 93 /// 94 void EmitCopyToRegClassNode(SDNode *Node, 95 DenseMap<SDValue, Register> &VRBaseMap); 96 97 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes. 98 /// 99 void EmitRegSequence(SDNode *Node, DenseMap<SDValue, Register> &VRBaseMap, 100 bool IsClone, bool IsCloned); 101 public: 102 /// CountResults - The results of target nodes have register or immediate 103 /// operands first, then an optional chain, and optional flag operands 104 /// (which do not go into the machine instrs.) 105 static unsigned CountResults(SDNode *Node); 106 107 /// EmitDbgValue - Generate machine instruction for a dbg_value node. 108 /// 109 MachineInstr *EmitDbgValue(SDDbgValue *SD, 110 DenseMap<SDValue, Register> &VRBaseMap); 111 112 /// Generate machine instruction for a dbg_label node. 113 MachineInstr *EmitDbgLabel(SDDbgLabel *SD); 114 115 /// EmitNode - Generate machine code for a node and needed dependencies. 116 /// 117 void EmitNode(SDNode *Node, bool IsClone, bool IsCloned, 118 DenseMap<SDValue, Register> &VRBaseMap) { 119 if (Node->isMachineOpcode()) 120 EmitMachineNode(Node, IsClone, IsCloned, VRBaseMap); 121 else 122 EmitSpecialNode(Node, IsClone, IsCloned, VRBaseMap); 123 } 124 125 /// getBlock - Return the current basic block. 126 MachineBasicBlock *getBlock() { return MBB; } 127 128 /// getInsertPos - Return the current insertion position. 129 MachineBasicBlock::iterator getInsertPos() { return InsertPos; } 130 131 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting 132 /// at the given position in the given block. 133 InstrEmitter(MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos); 134 135 private: 136 void EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, 137 DenseMap<SDValue, Register> &VRBaseMap); 138 void EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, 139 DenseMap<SDValue, Register> &VRBaseMap); 140 }; 141 142 } 143 144 #endif 145