xref: /freebsd/contrib/llvm-project/llvm/lib/CodeGen/RegUsageInfoCollector.cpp (revision e17f5b1d307b7b8910d67883e57a9604305906d5)
1 //===-- RegUsageInfoCollector.cpp - Register Usage Information Collector --===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// This pass is required to take advantage of the interprocedural register
10 /// allocation infrastructure.
11 ///
12 /// This pass is simple MachineFunction pass which collects register usage
13 /// details by iterating through each physical registers and checking
14 /// MRI::isPhysRegUsed() then creates a RegMask based on this details.
15 /// The pass then stores this RegMask in PhysicalRegisterUsageInfo.cpp
16 ///
17 //===----------------------------------------------------------------------===//
18 
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegisterUsageInfo.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/CodeGen/TargetFrameLowering.h"
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "ip-regalloc"
34 
35 STATISTIC(NumCSROpt,
36           "Number of functions optimized for callee saved registers");
37 
38 namespace {
39 
40 class RegUsageInfoCollector : public MachineFunctionPass {
41 public:
42   RegUsageInfoCollector() : MachineFunctionPass(ID) {
43     PassRegistry &Registry = *PassRegistry::getPassRegistry();
44     initializeRegUsageInfoCollectorPass(Registry);
45   }
46 
47   StringRef getPassName() const override {
48     return "Register Usage Information Collector Pass";
49   }
50 
51   void getAnalysisUsage(AnalysisUsage &AU) const override {
52     AU.addRequired<PhysicalRegisterUsageInfo>();
53     AU.setPreservesAll();
54     MachineFunctionPass::getAnalysisUsage(AU);
55   }
56 
57   bool runOnMachineFunction(MachineFunction &MF) override;
58 
59   // Call getCalleeSaves and then also set the bits for subregs and
60   // fully saved superregs.
61   static void computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF);
62 
63   static char ID;
64 };
65 
66 } // end of anonymous namespace
67 
68 char RegUsageInfoCollector::ID = 0;
69 
70 INITIALIZE_PASS_BEGIN(RegUsageInfoCollector, "RegUsageInfoCollector",
71                       "Register Usage Information Collector", false, false)
72 INITIALIZE_PASS_DEPENDENCY(PhysicalRegisterUsageInfo)
73 INITIALIZE_PASS_END(RegUsageInfoCollector, "RegUsageInfoCollector",
74                     "Register Usage Information Collector", false, false)
75 
76 FunctionPass *llvm::createRegUsageInfoCollector() {
77   return new RegUsageInfoCollector();
78 }
79 
80 // TODO: Move to hook somwehere?
81 
82 // Return true if it is useful to track the used registers for IPRA / no CSR
83 // optimizations. This is not useful for entry points, and computing the
84 // register usage information is expensive.
85 static bool isCallableFunction(const MachineFunction &MF) {
86   switch (MF.getFunction().getCallingConv()) {
87   case CallingConv::AMDGPU_VS:
88   case CallingConv::AMDGPU_GS:
89   case CallingConv::AMDGPU_PS:
90   case CallingConv::AMDGPU_CS:
91   case CallingConv::AMDGPU_HS:
92   case CallingConv::AMDGPU_ES:
93   case CallingConv::AMDGPU_LS:
94   case CallingConv::AMDGPU_KERNEL:
95     return false;
96   default:
97     return true;
98   }
99 }
100 
101 bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) {
102   MachineRegisterInfo *MRI = &MF.getRegInfo();
103   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
104   const LLVMTargetMachine &TM = MF.getTarget();
105 
106   LLVM_DEBUG(dbgs() << " -------------------- " << getPassName()
107                     << " -------------------- \nFunction Name : "
108                     << MF.getName() << '\n');
109 
110   // Analyzing the register usage may be expensive on some targets.
111   if (!isCallableFunction(MF)) {
112     LLVM_DEBUG(dbgs() << "Not analyzing non-callable function\n");
113     return false;
114   }
115 
116   // If there are no callers, there's no point in computing more precise
117   // register usage here.
118   if (MF.getFunction().use_empty()) {
119     LLVM_DEBUG(dbgs() << "Not analyzing function with no callers\n");
120     return false;
121   }
122 
123   std::vector<uint32_t> RegMask;
124 
125   // Compute the size of the bit vector to represent all the registers.
126   // The bit vector is broken into 32-bit chunks, thus takes the ceil of
127   // the number of registers divided by 32 for the size.
128   unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
129   RegMask.resize(RegMaskSize, ~((uint32_t)0));
130 
131   const Function &F = MF.getFunction();
132 
133   PhysicalRegisterUsageInfo &PRUI = getAnalysis<PhysicalRegisterUsageInfo>();
134   PRUI.setTargetMachine(TM);
135 
136   LLVM_DEBUG(dbgs() << "Clobbered Registers: ");
137 
138   BitVector SavedRegs;
139   computeCalleeSavedRegs(SavedRegs, MF);
140 
141   const BitVector &UsedPhysRegsMask = MRI->getUsedPhysRegsMask();
142   auto SetRegAsDefined = [&RegMask] (unsigned Reg) {
143     RegMask[Reg / 32] &= ~(1u << Reg % 32);
144   };
145 
146   // Some targets can clobber registers "inside" a call, typically in
147   // linker-generated code.
148   for (const MCPhysReg Reg : TRI->getIntraCallClobberedRegs(&MF))
149     for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
150       SetRegAsDefined(*AI);
151 
152   // Scan all the physical registers. When a register is defined in the current
153   // function set it and all the aliasing registers as defined in the regmask.
154   // FIXME: Rewrite to use regunits.
155   for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
156     // Don't count registers that are saved and restored.
157     if (SavedRegs.test(PReg))
158       continue;
159     // If a register is defined by an instruction mark it as defined together
160     // with all it's unsaved aliases.
161     if (!MRI->def_empty(PReg)) {
162       for (MCRegAliasIterator AI(PReg, TRI, true); AI.isValid(); ++AI)
163         if (!SavedRegs.test(*AI))
164           SetRegAsDefined(*AI);
165       continue;
166     }
167     // If a register is in the UsedPhysRegsMask set then mark it as defined.
168     // All clobbered aliases will also be in the set, so we can skip setting
169     // as defined all the aliases here.
170     if (UsedPhysRegsMask.test(PReg))
171       SetRegAsDefined(PReg);
172   }
173 
174   if (TargetFrameLowering::isSafeForNoCSROpt(F) &&
175       MF.getSubtarget().getFrameLowering()->isProfitableForNoCSROpt(F)) {
176     ++NumCSROpt;
177     LLVM_DEBUG(dbgs() << MF.getName()
178                       << " function optimized for not having CSR.\n");
179   }
180 
181   LLVM_DEBUG(
182     for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
183       if (MachineOperand::clobbersPhysReg(&(RegMask[0]), PReg))
184         dbgs() << printReg(PReg, TRI) << " ";
185     }
186 
187     dbgs() << " \n----------------------------------------\n";
188   );
189 
190   PRUI.storeUpdateRegUsageInfo(F, RegMask);
191 
192   return false;
193 }
194 
195 void RegUsageInfoCollector::
196 computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF) {
197   const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
198   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
199 
200   // Target will return the set of registers that it saves/restores as needed.
201   SavedRegs.clear();
202   TFI.getCalleeSaves(MF, SavedRegs);
203   if (SavedRegs.none())
204     return;
205 
206   // Insert subregs.
207   const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);
208   for (unsigned i = 0; CSRegs[i]; ++i) {
209     MCPhysReg Reg = CSRegs[i];
210     if (SavedRegs.test(Reg)) {
211       // Save subregisters
212       for (MCSubRegIterator SR(Reg, &TRI); SR.isValid(); ++SR)
213         SavedRegs.set(*SR);
214     }
215   }
216 }
217