1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the class that prints out the LLVM IR and machine 10 // functions using the MIR serialization format. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/CodeGen/MIRPrinter.h" 15 #include "llvm/ADT/DenseMap.h" 16 #include "llvm/ADT/None.h" 17 #include "llvm/ADT/STLExtras.h" 18 #include "llvm/ADT/SmallBitVector.h" 19 #include "llvm/ADT/SmallPtrSet.h" 20 #include "llvm/ADT/SmallVector.h" 21 #include "llvm/ADT/StringRef.h" 22 #include "llvm/ADT/Twine.h" 23 #include "llvm/CodeGen/GlobalISel/RegisterBank.h" 24 #include "llvm/CodeGen/MIRYamlMapping.h" 25 #include "llvm/CodeGen/MachineBasicBlock.h" 26 #include "llvm/CodeGen/MachineConstantPool.h" 27 #include "llvm/CodeGen/MachineFrameInfo.h" 28 #include "llvm/CodeGen/MachineFunction.h" 29 #include "llvm/CodeGen/MachineInstr.h" 30 #include "llvm/CodeGen/MachineJumpTableInfo.h" 31 #include "llvm/CodeGen/MachineMemOperand.h" 32 #include "llvm/CodeGen/MachineOperand.h" 33 #include "llvm/CodeGen/MachineRegisterInfo.h" 34 #include "llvm/CodeGen/PseudoSourceValue.h" 35 #include "llvm/CodeGen/TargetInstrInfo.h" 36 #include "llvm/CodeGen/TargetRegisterInfo.h" 37 #include "llvm/CodeGen/TargetSubtargetInfo.h" 38 #include "llvm/CodeGen/TargetFrameLowering.h" 39 #include "llvm/IR/BasicBlock.h" 40 #include "llvm/IR/Constants.h" 41 #include "llvm/IR/DebugInfo.h" 42 #include "llvm/IR/DebugLoc.h" 43 #include "llvm/IR/Function.h" 44 #include "llvm/IR/GlobalValue.h" 45 #include "llvm/IR/IRPrintingPasses.h" 46 #include "llvm/IR/InstrTypes.h" 47 #include "llvm/IR/Instructions.h" 48 #include "llvm/IR/Intrinsics.h" 49 #include "llvm/IR/Module.h" 50 #include "llvm/IR/ModuleSlotTracker.h" 51 #include "llvm/IR/Value.h" 52 #include "llvm/MC/LaneBitmask.h" 53 #include "llvm/MC/MCContext.h" 54 #include "llvm/MC/MCDwarf.h" 55 #include "llvm/MC/MCSymbol.h" 56 #include "llvm/Support/AtomicOrdering.h" 57 #include "llvm/Support/BranchProbability.h" 58 #include "llvm/Support/Casting.h" 59 #include "llvm/Support/CommandLine.h" 60 #include "llvm/Support/ErrorHandling.h" 61 #include "llvm/Support/Format.h" 62 #include "llvm/Support/LowLevelTypeImpl.h" 63 #include "llvm/Support/YAMLTraits.h" 64 #include "llvm/Support/raw_ostream.h" 65 #include "llvm/Target/TargetIntrinsicInfo.h" 66 #include "llvm/Target/TargetMachine.h" 67 #include <algorithm> 68 #include <cassert> 69 #include <cinttypes> 70 #include <cstdint> 71 #include <iterator> 72 #include <string> 73 #include <utility> 74 #include <vector> 75 76 using namespace llvm; 77 78 static cl::opt<bool> SimplifyMIR( 79 "simplify-mir", cl::Hidden, 80 cl::desc("Leave out unnecessary information when printing MIR")); 81 82 static cl::opt<bool> PrintLocations("mir-debug-loc", cl::Hidden, cl::init(true), 83 cl::desc("Print MIR debug-locations")); 84 85 namespace { 86 87 /// This structure describes how to print out stack object references. 88 struct FrameIndexOperand { 89 std::string Name; 90 unsigned ID; 91 bool IsFixed; 92 93 FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed) 94 : Name(Name.str()), ID(ID), IsFixed(IsFixed) {} 95 96 /// Return an ordinary stack object reference. 97 static FrameIndexOperand create(StringRef Name, unsigned ID) { 98 return FrameIndexOperand(Name, ID, /*IsFixed=*/false); 99 } 100 101 /// Return a fixed stack object reference. 102 static FrameIndexOperand createFixed(unsigned ID) { 103 return FrameIndexOperand("", ID, /*IsFixed=*/true); 104 } 105 }; 106 107 } // end anonymous namespace 108 109 namespace llvm { 110 111 /// This class prints out the machine functions using the MIR serialization 112 /// format. 113 class MIRPrinter { 114 raw_ostream &OS; 115 DenseMap<const uint32_t *, unsigned> RegisterMaskIds; 116 /// Maps from stack object indices to operand indices which will be used when 117 /// printing frame index machine operands. 118 DenseMap<int, FrameIndexOperand> StackObjectOperandMapping; 119 120 public: 121 MIRPrinter(raw_ostream &OS) : OS(OS) {} 122 123 void print(const MachineFunction &MF); 124 125 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo, 126 const TargetRegisterInfo *TRI); 127 void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI, 128 const MachineFrameInfo &MFI); 129 void convert(yaml::MachineFunction &MF, 130 const MachineConstantPool &ConstantPool); 131 void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI, 132 const MachineJumpTableInfo &JTI); 133 void convertStackObjects(yaml::MachineFunction &YMF, 134 const MachineFunction &MF, ModuleSlotTracker &MST); 135 void convertCallSiteObjects(yaml::MachineFunction &YMF, 136 const MachineFunction &MF, 137 ModuleSlotTracker &MST); 138 139 private: 140 void initRegisterMaskIds(const MachineFunction &MF); 141 }; 142 143 /// This class prints out the machine instructions using the MIR serialization 144 /// format. 145 class MIPrinter { 146 raw_ostream &OS; 147 ModuleSlotTracker &MST; 148 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds; 149 const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping; 150 /// Synchronization scope names registered with LLVMContext. 151 SmallVector<StringRef, 8> SSNs; 152 153 bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const; 154 bool canPredictSuccessors(const MachineBasicBlock &MBB) const; 155 156 public: 157 MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST, 158 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds, 159 const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping) 160 : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds), 161 StackObjectOperandMapping(StackObjectOperandMapping) {} 162 163 void print(const MachineBasicBlock &MBB); 164 165 void print(const MachineInstr &MI); 166 void printStackObjectReference(int FrameIndex); 167 void print(const MachineInstr &MI, unsigned OpIdx, 168 const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, 169 bool ShouldPrintRegisterTies, LLT TypeToPrint, 170 bool PrintDef = true); 171 }; 172 173 } // end namespace llvm 174 175 namespace llvm { 176 namespace yaml { 177 178 /// This struct serializes the LLVM IR module. 179 template <> struct BlockScalarTraits<Module> { 180 static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) { 181 Mod.print(OS, nullptr); 182 } 183 184 static StringRef input(StringRef Str, void *Ctxt, Module &Mod) { 185 llvm_unreachable("LLVM Module is supposed to be parsed separately"); 186 return ""; 187 } 188 }; 189 190 } // end namespace yaml 191 } // end namespace llvm 192 193 static void printRegMIR(unsigned Reg, yaml::StringValue &Dest, 194 const TargetRegisterInfo *TRI) { 195 raw_string_ostream OS(Dest.Value); 196 OS << printReg(Reg, TRI); 197 } 198 199 void MIRPrinter::print(const MachineFunction &MF) { 200 initRegisterMaskIds(MF); 201 202 yaml::MachineFunction YamlMF; 203 YamlMF.Name = MF.getName(); 204 YamlMF.Alignment = MF.getAlignment(); 205 YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice(); 206 YamlMF.HasWinCFI = MF.hasWinCFI(); 207 208 YamlMF.Legalized = MF.getProperties().hasProperty( 209 MachineFunctionProperties::Property::Legalized); 210 YamlMF.RegBankSelected = MF.getProperties().hasProperty( 211 MachineFunctionProperties::Property::RegBankSelected); 212 YamlMF.Selected = MF.getProperties().hasProperty( 213 MachineFunctionProperties::Property::Selected); 214 YamlMF.FailedISel = MF.getProperties().hasProperty( 215 MachineFunctionProperties::Property::FailedISel); 216 217 convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo()); 218 ModuleSlotTracker MST(MF.getFunction().getParent()); 219 MST.incorporateFunction(MF.getFunction()); 220 convert(MST, YamlMF.FrameInfo, MF.getFrameInfo()); 221 convertStackObjects(YamlMF, MF, MST); 222 convertCallSiteObjects(YamlMF, MF, MST); 223 for (auto &Sub : MF.DebugValueSubstitutions) 224 YamlMF.DebugValueSubstitutions.push_back({Sub.first.first, Sub.first.second, 225 Sub.second.first, 226 Sub.second.second}); 227 if (const auto *ConstantPool = MF.getConstantPool()) 228 convert(YamlMF, *ConstantPool); 229 if (const auto *JumpTableInfo = MF.getJumpTableInfo()) 230 convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo); 231 232 const TargetMachine &TM = MF.getTarget(); 233 YamlMF.MachineFuncInfo = 234 std::unique_ptr<yaml::MachineFunctionInfo>(TM.convertFuncInfoToYAML(MF)); 235 236 raw_string_ostream StrOS(YamlMF.Body.Value.Value); 237 bool IsNewlineNeeded = false; 238 for (const auto &MBB : MF) { 239 if (IsNewlineNeeded) 240 StrOS << "\n"; 241 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping) 242 .print(MBB); 243 IsNewlineNeeded = true; 244 } 245 StrOS.flush(); 246 yaml::Output Out(OS); 247 if (!SimplifyMIR) 248 Out.setWriteDefaultValues(true); 249 Out << YamlMF; 250 } 251 252 static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS, 253 const TargetRegisterInfo *TRI) { 254 assert(RegMask && "Can't print an empty register mask"); 255 OS << StringRef("CustomRegMask("); 256 257 bool IsRegInRegMaskFound = false; 258 for (int I = 0, E = TRI->getNumRegs(); I < E; I++) { 259 // Check whether the register is asserted in regmask. 260 if (RegMask[I / 32] & (1u << (I % 32))) { 261 if (IsRegInRegMaskFound) 262 OS << ','; 263 OS << printReg(I, TRI); 264 IsRegInRegMaskFound = true; 265 } 266 } 267 268 OS << ')'; 269 } 270 271 static void printRegClassOrBank(unsigned Reg, yaml::StringValue &Dest, 272 const MachineRegisterInfo &RegInfo, 273 const TargetRegisterInfo *TRI) { 274 raw_string_ostream OS(Dest.Value); 275 OS << printRegClassOrBank(Reg, RegInfo, TRI); 276 } 277 278 template <typename T> 279 static void 280 printStackObjectDbgInfo(const MachineFunction::VariableDbgInfo &DebugVar, 281 T &Object, ModuleSlotTracker &MST) { 282 std::array<std::string *, 3> Outputs{{&Object.DebugVar.Value, 283 &Object.DebugExpr.Value, 284 &Object.DebugLoc.Value}}; 285 std::array<const Metadata *, 3> Metas{{DebugVar.Var, 286 DebugVar.Expr, 287 DebugVar.Loc}}; 288 for (unsigned i = 0; i < 3; ++i) { 289 raw_string_ostream StrOS(*Outputs[i]); 290 Metas[i]->printAsOperand(StrOS, MST); 291 } 292 } 293 294 void MIRPrinter::convert(yaml::MachineFunction &MF, 295 const MachineRegisterInfo &RegInfo, 296 const TargetRegisterInfo *TRI) { 297 MF.TracksRegLiveness = RegInfo.tracksLiveness(); 298 299 // Print the virtual register definitions. 300 for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) { 301 unsigned Reg = Register::index2VirtReg(I); 302 yaml::VirtualRegisterDefinition VReg; 303 VReg.ID = I; 304 if (RegInfo.getVRegName(Reg) != "") 305 continue; 306 ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI); 307 unsigned PreferredReg = RegInfo.getSimpleHint(Reg); 308 if (PreferredReg) 309 printRegMIR(PreferredReg, VReg.PreferredRegister, TRI); 310 MF.VirtualRegisters.push_back(VReg); 311 } 312 313 // Print the live ins. 314 for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) { 315 yaml::MachineFunctionLiveIn LiveIn; 316 printRegMIR(LI.first, LiveIn.Register, TRI); 317 if (LI.second) 318 printRegMIR(LI.second, LiveIn.VirtualRegister, TRI); 319 MF.LiveIns.push_back(LiveIn); 320 } 321 322 // Prints the callee saved registers. 323 if (RegInfo.isUpdatedCSRsInitialized()) { 324 const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs(); 325 std::vector<yaml::FlowStringValue> CalleeSavedRegisters; 326 for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) { 327 yaml::FlowStringValue Reg; 328 printRegMIR(*I, Reg, TRI); 329 CalleeSavedRegisters.push_back(Reg); 330 } 331 MF.CalleeSavedRegisters = CalleeSavedRegisters; 332 } 333 } 334 335 void MIRPrinter::convert(ModuleSlotTracker &MST, 336 yaml::MachineFrameInfo &YamlMFI, 337 const MachineFrameInfo &MFI) { 338 YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken(); 339 YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken(); 340 YamlMFI.HasStackMap = MFI.hasStackMap(); 341 YamlMFI.HasPatchPoint = MFI.hasPatchPoint(); 342 YamlMFI.StackSize = MFI.getStackSize(); 343 YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment(); 344 YamlMFI.MaxAlignment = MFI.getMaxAlign().value(); 345 YamlMFI.AdjustsStack = MFI.adjustsStack(); 346 YamlMFI.HasCalls = MFI.hasCalls(); 347 YamlMFI.MaxCallFrameSize = MFI.isMaxCallFrameSizeComputed() 348 ? MFI.getMaxCallFrameSize() : ~0u; 349 YamlMFI.CVBytesOfCalleeSavedRegisters = 350 MFI.getCVBytesOfCalleeSavedRegisters(); 351 YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment(); 352 YamlMFI.HasVAStart = MFI.hasVAStart(); 353 YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc(); 354 YamlMFI.LocalFrameSize = MFI.getLocalFrameSize(); 355 if (MFI.getSavePoint()) { 356 raw_string_ostream StrOS(YamlMFI.SavePoint.Value); 357 StrOS << printMBBReference(*MFI.getSavePoint()); 358 } 359 if (MFI.getRestorePoint()) { 360 raw_string_ostream StrOS(YamlMFI.RestorePoint.Value); 361 StrOS << printMBBReference(*MFI.getRestorePoint()); 362 } 363 } 364 365 void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF, 366 const MachineFunction &MF, 367 ModuleSlotTracker &MST) { 368 const MachineFrameInfo &MFI = MF.getFrameInfo(); 369 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); 370 371 // Process fixed stack objects. 372 assert(YMF.FixedStackObjects.empty()); 373 SmallVector<int, 32> FixedStackObjectsIdx; 374 const int BeginIdx = MFI.getObjectIndexBegin(); 375 if (BeginIdx < 0) 376 FixedStackObjectsIdx.reserve(-BeginIdx); 377 378 unsigned ID = 0; 379 for (int I = BeginIdx; I < 0; ++I, ++ID) { 380 FixedStackObjectsIdx.push_back(-1); // Fill index for possible dead. 381 if (MFI.isDeadObjectIndex(I)) 382 continue; 383 384 yaml::FixedMachineStackObject YamlObject; 385 YamlObject.ID = ID; 386 YamlObject.Type = MFI.isSpillSlotObjectIndex(I) 387 ? yaml::FixedMachineStackObject::SpillSlot 388 : yaml::FixedMachineStackObject::DefaultType; 389 YamlObject.Offset = MFI.getObjectOffset(I); 390 YamlObject.Size = MFI.getObjectSize(I); 391 YamlObject.Alignment = MFI.getObjectAlign(I); 392 YamlObject.StackID = (TargetStackID::Value)MFI.getStackID(I); 393 YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I); 394 YamlObject.IsAliased = MFI.isAliasedObjectIndex(I); 395 // Save the ID' position in FixedStackObjects storage vector. 396 FixedStackObjectsIdx[ID] = YMF.FixedStackObjects.size(); 397 YMF.FixedStackObjects.push_back(YamlObject); 398 StackObjectOperandMapping.insert( 399 std::make_pair(I, FrameIndexOperand::createFixed(ID))); 400 } 401 402 // Process ordinary stack objects. 403 assert(YMF.StackObjects.empty()); 404 SmallVector<unsigned, 32> StackObjectsIdx; 405 const int EndIdx = MFI.getObjectIndexEnd(); 406 if (EndIdx > 0) 407 StackObjectsIdx.reserve(EndIdx); 408 ID = 0; 409 for (int I = 0; I < EndIdx; ++I, ++ID) { 410 StackObjectsIdx.push_back(-1); // Fill index for possible dead. 411 if (MFI.isDeadObjectIndex(I)) 412 continue; 413 414 yaml::MachineStackObject YamlObject; 415 YamlObject.ID = ID; 416 if (const auto *Alloca = MFI.getObjectAllocation(I)) 417 YamlObject.Name.Value = std::string( 418 Alloca->hasName() ? Alloca->getName() : ""); 419 YamlObject.Type = MFI.isSpillSlotObjectIndex(I) 420 ? yaml::MachineStackObject::SpillSlot 421 : MFI.isVariableSizedObjectIndex(I) 422 ? yaml::MachineStackObject::VariableSized 423 : yaml::MachineStackObject::DefaultType; 424 YamlObject.Offset = MFI.getObjectOffset(I); 425 YamlObject.Size = MFI.getObjectSize(I); 426 YamlObject.Alignment = MFI.getObjectAlign(I); 427 YamlObject.StackID = (TargetStackID::Value)MFI.getStackID(I); 428 429 // Save the ID' position in StackObjects storage vector. 430 StackObjectsIdx[ID] = YMF.StackObjects.size(); 431 YMF.StackObjects.push_back(YamlObject); 432 StackObjectOperandMapping.insert(std::make_pair( 433 I, FrameIndexOperand::create(YamlObject.Name.Value, ID))); 434 } 435 436 for (const auto &CSInfo : MFI.getCalleeSavedInfo()) { 437 const int FrameIdx = CSInfo.getFrameIdx(); 438 if (!CSInfo.isSpilledToReg() && MFI.isDeadObjectIndex(FrameIdx)) 439 continue; 440 441 yaml::StringValue Reg; 442 printRegMIR(CSInfo.getReg(), Reg, TRI); 443 if (!CSInfo.isSpilledToReg()) { 444 assert(FrameIdx >= MFI.getObjectIndexBegin() && 445 FrameIdx < MFI.getObjectIndexEnd() && 446 "Invalid stack object index"); 447 if (FrameIdx < 0) { // Negative index means fixed objects. 448 auto &Object = 449 YMF.FixedStackObjects 450 [FixedStackObjectsIdx[FrameIdx + MFI.getNumFixedObjects()]]; 451 Object.CalleeSavedRegister = Reg; 452 Object.CalleeSavedRestored = CSInfo.isRestored(); 453 } else { 454 auto &Object = YMF.StackObjects[StackObjectsIdx[FrameIdx]]; 455 Object.CalleeSavedRegister = Reg; 456 Object.CalleeSavedRestored = CSInfo.isRestored(); 457 } 458 } 459 } 460 for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) { 461 auto LocalObject = MFI.getLocalFrameObjectMap(I); 462 assert(LocalObject.first >= 0 && "Expected a locally mapped stack object"); 463 YMF.StackObjects[StackObjectsIdx[LocalObject.first]].LocalOffset = 464 LocalObject.second; 465 } 466 467 // Print the stack object references in the frame information class after 468 // converting the stack objects. 469 if (MFI.hasStackProtectorIndex()) { 470 raw_string_ostream StrOS(YMF.FrameInfo.StackProtector.Value); 471 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping) 472 .printStackObjectReference(MFI.getStackProtectorIndex()); 473 } 474 475 // Print the debug variable information. 476 for (const MachineFunction::VariableDbgInfo &DebugVar : 477 MF.getVariableDbgInfo()) { 478 assert(DebugVar.Slot >= MFI.getObjectIndexBegin() && 479 DebugVar.Slot < MFI.getObjectIndexEnd() && 480 "Invalid stack object index"); 481 if (DebugVar.Slot < 0) { // Negative index means fixed objects. 482 auto &Object = 483 YMF.FixedStackObjects[FixedStackObjectsIdx[DebugVar.Slot + 484 MFI.getNumFixedObjects()]]; 485 printStackObjectDbgInfo(DebugVar, Object, MST); 486 } else { 487 auto &Object = YMF.StackObjects[StackObjectsIdx[DebugVar.Slot]]; 488 printStackObjectDbgInfo(DebugVar, Object, MST); 489 } 490 } 491 } 492 493 void MIRPrinter::convertCallSiteObjects(yaml::MachineFunction &YMF, 494 const MachineFunction &MF, 495 ModuleSlotTracker &MST) { 496 const auto *TRI = MF.getSubtarget().getRegisterInfo(); 497 for (auto CSInfo : MF.getCallSitesInfo()) { 498 yaml::CallSiteInfo YmlCS; 499 yaml::CallSiteInfo::MachineInstrLoc CallLocation; 500 501 // Prepare instruction position. 502 MachineBasicBlock::const_instr_iterator CallI = CSInfo.first->getIterator(); 503 CallLocation.BlockNum = CallI->getParent()->getNumber(); 504 // Get call instruction offset from the beginning of block. 505 CallLocation.Offset = 506 std::distance(CallI->getParent()->instr_begin(), CallI); 507 YmlCS.CallLocation = CallLocation; 508 // Construct call arguments and theirs forwarding register info. 509 for (auto ArgReg : CSInfo.second) { 510 yaml::CallSiteInfo::ArgRegPair YmlArgReg; 511 YmlArgReg.ArgNo = ArgReg.ArgNo; 512 printRegMIR(ArgReg.Reg, YmlArgReg.Reg, TRI); 513 YmlCS.ArgForwardingRegs.emplace_back(YmlArgReg); 514 } 515 YMF.CallSitesInfo.push_back(YmlCS); 516 } 517 518 // Sort call info by position of call instructions. 519 llvm::sort(YMF.CallSitesInfo.begin(), YMF.CallSitesInfo.end(), 520 [](yaml::CallSiteInfo A, yaml::CallSiteInfo B) { 521 if (A.CallLocation.BlockNum == B.CallLocation.BlockNum) 522 return A.CallLocation.Offset < B.CallLocation.Offset; 523 return A.CallLocation.BlockNum < B.CallLocation.BlockNum; 524 }); 525 } 526 527 void MIRPrinter::convert(yaml::MachineFunction &MF, 528 const MachineConstantPool &ConstantPool) { 529 unsigned ID = 0; 530 for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) { 531 std::string Str; 532 raw_string_ostream StrOS(Str); 533 if (Constant.isMachineConstantPoolEntry()) { 534 Constant.Val.MachineCPVal->print(StrOS); 535 } else { 536 Constant.Val.ConstVal->printAsOperand(StrOS); 537 } 538 539 yaml::MachineConstantPoolValue YamlConstant; 540 YamlConstant.ID = ID++; 541 YamlConstant.Value = StrOS.str(); 542 YamlConstant.Alignment = Constant.getAlign(); 543 YamlConstant.IsTargetSpecific = Constant.isMachineConstantPoolEntry(); 544 545 MF.Constants.push_back(YamlConstant); 546 } 547 } 548 549 void MIRPrinter::convert(ModuleSlotTracker &MST, 550 yaml::MachineJumpTable &YamlJTI, 551 const MachineJumpTableInfo &JTI) { 552 YamlJTI.Kind = JTI.getEntryKind(); 553 unsigned ID = 0; 554 for (const auto &Table : JTI.getJumpTables()) { 555 std::string Str; 556 yaml::MachineJumpTable::Entry Entry; 557 Entry.ID = ID++; 558 for (const auto *MBB : Table.MBBs) { 559 raw_string_ostream StrOS(Str); 560 StrOS << printMBBReference(*MBB); 561 Entry.Blocks.push_back(StrOS.str()); 562 Str.clear(); 563 } 564 YamlJTI.Entries.push_back(Entry); 565 } 566 } 567 568 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) { 569 const auto *TRI = MF.getSubtarget().getRegisterInfo(); 570 unsigned I = 0; 571 for (const uint32_t *Mask : TRI->getRegMasks()) 572 RegisterMaskIds.insert(std::make_pair(Mask, I++)); 573 } 574 575 void llvm::guessSuccessors(const MachineBasicBlock &MBB, 576 SmallVectorImpl<MachineBasicBlock*> &Result, 577 bool &IsFallthrough) { 578 SmallPtrSet<MachineBasicBlock*,8> Seen; 579 580 for (const MachineInstr &MI : MBB) { 581 if (MI.isPHI()) 582 continue; 583 for (const MachineOperand &MO : MI.operands()) { 584 if (!MO.isMBB()) 585 continue; 586 MachineBasicBlock *Succ = MO.getMBB(); 587 auto RP = Seen.insert(Succ); 588 if (RP.second) 589 Result.push_back(Succ); 590 } 591 } 592 MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr(); 593 IsFallthrough = I == MBB.end() || !I->isBarrier(); 594 } 595 596 bool 597 MIPrinter::canPredictBranchProbabilities(const MachineBasicBlock &MBB) const { 598 if (MBB.succ_size() <= 1) 599 return true; 600 if (!MBB.hasSuccessorProbabilities()) 601 return true; 602 603 SmallVector<BranchProbability,8> Normalized(MBB.Probs.begin(), 604 MBB.Probs.end()); 605 BranchProbability::normalizeProbabilities(Normalized.begin(), 606 Normalized.end()); 607 SmallVector<BranchProbability,8> Equal(Normalized.size()); 608 BranchProbability::normalizeProbabilities(Equal.begin(), Equal.end()); 609 610 return std::equal(Normalized.begin(), Normalized.end(), Equal.begin()); 611 } 612 613 bool MIPrinter::canPredictSuccessors(const MachineBasicBlock &MBB) const { 614 SmallVector<MachineBasicBlock*,8> GuessedSuccs; 615 bool GuessedFallthrough; 616 guessSuccessors(MBB, GuessedSuccs, GuessedFallthrough); 617 if (GuessedFallthrough) { 618 const MachineFunction &MF = *MBB.getParent(); 619 MachineFunction::const_iterator NextI = std::next(MBB.getIterator()); 620 if (NextI != MF.end()) { 621 MachineBasicBlock *Next = const_cast<MachineBasicBlock*>(&*NextI); 622 if (!is_contained(GuessedSuccs, Next)) 623 GuessedSuccs.push_back(Next); 624 } 625 } 626 if (GuessedSuccs.size() != MBB.succ_size()) 627 return false; 628 return std::equal(MBB.succ_begin(), MBB.succ_end(), GuessedSuccs.begin()); 629 } 630 631 void MIPrinter::print(const MachineBasicBlock &MBB) { 632 assert(MBB.getNumber() >= 0 && "Invalid MBB number"); 633 MBB.printName(OS, 634 MachineBasicBlock::PrintNameIr | 635 MachineBasicBlock::PrintNameAttributes, 636 &MST); 637 OS << ":\n"; 638 639 bool HasLineAttributes = false; 640 // Print the successors 641 bool canPredictProbs = canPredictBranchProbabilities(MBB); 642 // Even if the list of successors is empty, if we cannot guess it, 643 // we need to print it to tell the parser that the list is empty. 644 // This is needed, because MI model unreachable as empty blocks 645 // with an empty successor list. If the parser would see that 646 // without the successor list, it would guess the code would 647 // fallthrough. 648 if ((!MBB.succ_empty() && !SimplifyMIR) || !canPredictProbs || 649 !canPredictSuccessors(MBB)) { 650 OS.indent(2) << "successors: "; 651 for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) { 652 if (I != MBB.succ_begin()) 653 OS << ", "; 654 OS << printMBBReference(**I); 655 if (!SimplifyMIR || !canPredictProbs) 656 OS << '(' 657 << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator()) 658 << ')'; 659 } 660 OS << "\n"; 661 HasLineAttributes = true; 662 } 663 664 // Print the live in registers. 665 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 666 if (MRI.tracksLiveness() && !MBB.livein_empty()) { 667 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo(); 668 OS.indent(2) << "liveins: "; 669 bool First = true; 670 for (const auto &LI : MBB.liveins()) { 671 if (!First) 672 OS << ", "; 673 First = false; 674 OS << printReg(LI.PhysReg, &TRI); 675 if (!LI.LaneMask.all()) 676 OS << ":0x" << PrintLaneMask(LI.LaneMask); 677 } 678 OS << "\n"; 679 HasLineAttributes = true; 680 } 681 682 if (HasLineAttributes) 683 OS << "\n"; 684 bool IsInBundle = false; 685 for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) { 686 const MachineInstr &MI = *I; 687 if (IsInBundle && !MI.isInsideBundle()) { 688 OS.indent(2) << "}\n"; 689 IsInBundle = false; 690 } 691 OS.indent(IsInBundle ? 4 : 2); 692 print(MI); 693 if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) { 694 OS << " {"; 695 IsInBundle = true; 696 } 697 OS << "\n"; 698 } 699 if (IsInBundle) 700 OS.indent(2) << "}\n"; 701 } 702 703 void MIPrinter::print(const MachineInstr &MI) { 704 const auto *MF = MI.getMF(); 705 const auto &MRI = MF->getRegInfo(); 706 const auto &SubTarget = MF->getSubtarget(); 707 const auto *TRI = SubTarget.getRegisterInfo(); 708 assert(TRI && "Expected target register info"); 709 const auto *TII = SubTarget.getInstrInfo(); 710 assert(TII && "Expected target instruction info"); 711 if (MI.isCFIInstruction()) 712 assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction"); 713 714 SmallBitVector PrintedTypes(8); 715 bool ShouldPrintRegisterTies = MI.hasComplexRegisterTies(); 716 unsigned I = 0, E = MI.getNumOperands(); 717 for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() && 718 !MI.getOperand(I).isImplicit(); 719 ++I) { 720 if (I) 721 OS << ", "; 722 print(MI, I, TRI, TII, ShouldPrintRegisterTies, 723 MI.getTypeToPrint(I, PrintedTypes, MRI), 724 /*PrintDef=*/false); 725 } 726 727 if (I) 728 OS << " = "; 729 if (MI.getFlag(MachineInstr::FrameSetup)) 730 OS << "frame-setup "; 731 if (MI.getFlag(MachineInstr::FrameDestroy)) 732 OS << "frame-destroy "; 733 if (MI.getFlag(MachineInstr::FmNoNans)) 734 OS << "nnan "; 735 if (MI.getFlag(MachineInstr::FmNoInfs)) 736 OS << "ninf "; 737 if (MI.getFlag(MachineInstr::FmNsz)) 738 OS << "nsz "; 739 if (MI.getFlag(MachineInstr::FmArcp)) 740 OS << "arcp "; 741 if (MI.getFlag(MachineInstr::FmContract)) 742 OS << "contract "; 743 if (MI.getFlag(MachineInstr::FmAfn)) 744 OS << "afn "; 745 if (MI.getFlag(MachineInstr::FmReassoc)) 746 OS << "reassoc "; 747 if (MI.getFlag(MachineInstr::NoUWrap)) 748 OS << "nuw "; 749 if (MI.getFlag(MachineInstr::NoSWrap)) 750 OS << "nsw "; 751 if (MI.getFlag(MachineInstr::IsExact)) 752 OS << "exact "; 753 if (MI.getFlag(MachineInstr::NoFPExcept)) 754 OS << "nofpexcept "; 755 if (MI.getFlag(MachineInstr::NoMerge)) 756 OS << "nomerge "; 757 758 OS << TII->getName(MI.getOpcode()); 759 if (I < E) 760 OS << ' '; 761 762 bool NeedComma = false; 763 for (; I < E; ++I) { 764 if (NeedComma) 765 OS << ", "; 766 print(MI, I, TRI, TII, ShouldPrintRegisterTies, 767 MI.getTypeToPrint(I, PrintedTypes, MRI)); 768 NeedComma = true; 769 } 770 771 // Print any optional symbols attached to this instruction as-if they were 772 // operands. 773 if (MCSymbol *PreInstrSymbol = MI.getPreInstrSymbol()) { 774 if (NeedComma) 775 OS << ','; 776 OS << " pre-instr-symbol "; 777 MachineOperand::printSymbol(OS, *PreInstrSymbol); 778 NeedComma = true; 779 } 780 if (MCSymbol *PostInstrSymbol = MI.getPostInstrSymbol()) { 781 if (NeedComma) 782 OS << ','; 783 OS << " post-instr-symbol "; 784 MachineOperand::printSymbol(OS, *PostInstrSymbol); 785 NeedComma = true; 786 } 787 if (MDNode *HeapAllocMarker = MI.getHeapAllocMarker()) { 788 if (NeedComma) 789 OS << ','; 790 OS << " heap-alloc-marker "; 791 HeapAllocMarker->printAsOperand(OS, MST); 792 NeedComma = true; 793 } 794 795 if (auto Num = MI.peekDebugInstrNum()) { 796 if (NeedComma) 797 OS << ','; 798 OS << " debug-instr-number " << Num; 799 NeedComma = true; 800 } 801 802 if (PrintLocations) { 803 if (const DebugLoc &DL = MI.getDebugLoc()) { 804 if (NeedComma) 805 OS << ','; 806 OS << " debug-location "; 807 DL->printAsOperand(OS, MST); 808 } 809 } 810 811 if (!MI.memoperands_empty()) { 812 OS << " :: "; 813 const LLVMContext &Context = MF->getFunction().getContext(); 814 const MachineFrameInfo &MFI = MF->getFrameInfo(); 815 bool NeedComma = false; 816 for (const auto *Op : MI.memoperands()) { 817 if (NeedComma) 818 OS << ", "; 819 Op->print(OS, MST, SSNs, Context, &MFI, TII); 820 NeedComma = true; 821 } 822 } 823 } 824 825 void MIPrinter::printStackObjectReference(int FrameIndex) { 826 auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex); 827 assert(ObjectInfo != StackObjectOperandMapping.end() && 828 "Invalid frame index"); 829 const FrameIndexOperand &Operand = ObjectInfo->second; 830 MachineOperand::printStackObjectReference(OS, Operand.ID, Operand.IsFixed, 831 Operand.Name); 832 } 833 834 static std::string formatOperandComment(std::string Comment) { 835 if (Comment.empty()) 836 return Comment; 837 return std::string(" /* " + Comment + " */"); 838 } 839 840 void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx, 841 const TargetRegisterInfo *TRI, 842 const TargetInstrInfo *TII, 843 bool ShouldPrintRegisterTies, LLT TypeToPrint, 844 bool PrintDef) { 845 const MachineOperand &Op = MI.getOperand(OpIdx); 846 std::string MOComment = TII->createMIROperandComment(MI, Op, OpIdx, TRI); 847 848 switch (Op.getType()) { 849 case MachineOperand::MO_Immediate: 850 if (MI.isOperandSubregIdx(OpIdx)) { 851 MachineOperand::printTargetFlags(OS, Op); 852 MachineOperand::printSubRegIdx(OS, Op.getImm(), TRI); 853 break; 854 } 855 LLVM_FALLTHROUGH; 856 case MachineOperand::MO_Register: 857 case MachineOperand::MO_CImmediate: 858 case MachineOperand::MO_FPImmediate: 859 case MachineOperand::MO_MachineBasicBlock: 860 case MachineOperand::MO_ConstantPoolIndex: 861 case MachineOperand::MO_TargetIndex: 862 case MachineOperand::MO_JumpTableIndex: 863 case MachineOperand::MO_ExternalSymbol: 864 case MachineOperand::MO_GlobalAddress: 865 case MachineOperand::MO_RegisterLiveOut: 866 case MachineOperand::MO_Metadata: 867 case MachineOperand::MO_MCSymbol: 868 case MachineOperand::MO_CFIIndex: 869 case MachineOperand::MO_IntrinsicID: 870 case MachineOperand::MO_Predicate: 871 case MachineOperand::MO_BlockAddress: 872 case MachineOperand::MO_ShuffleMask: { 873 unsigned TiedOperandIdx = 0; 874 if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef()) 875 TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx); 876 const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo(); 877 Op.print(OS, MST, TypeToPrint, OpIdx, PrintDef, /*IsStandalone=*/false, 878 ShouldPrintRegisterTies, TiedOperandIdx, TRI, TII); 879 OS << formatOperandComment(MOComment); 880 break; 881 } 882 case MachineOperand::MO_FrameIndex: 883 printStackObjectReference(Op.getIndex()); 884 break; 885 case MachineOperand::MO_RegisterMask: { 886 auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask()); 887 if (RegMaskInfo != RegisterMaskIds.end()) 888 OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower(); 889 else 890 printCustomRegMask(Op.getRegMask(), OS, TRI); 891 break; 892 } 893 } 894 } 895 896 void MIRFormatter::printIRValue(raw_ostream &OS, const Value &V, 897 ModuleSlotTracker &MST) { 898 if (isa<GlobalValue>(V)) { 899 V.printAsOperand(OS, /*PrintType=*/false, MST); 900 return; 901 } 902 if (isa<Constant>(V)) { 903 // Machine memory operands can load/store to/from constant value pointers. 904 OS << '`'; 905 V.printAsOperand(OS, /*PrintType=*/true, MST); 906 OS << '`'; 907 return; 908 } 909 OS << "%ir."; 910 if (V.hasName()) { 911 printLLVMNameWithoutPrefix(OS, V.getName()); 912 return; 913 } 914 int Slot = MST.getCurrentFunction() ? MST.getLocalSlot(&V) : -1; 915 MachineOperand::printIRSlotNumber(OS, Slot); 916 } 917 918 void llvm::printMIR(raw_ostream &OS, const Module &M) { 919 yaml::Output Out(OS); 920 Out << const_cast<Module &>(M); 921 } 922 923 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) { 924 MIRPrinter Printer(OS); 925 Printer.print(MF); 926 } 927