1 //===--- SystemZ.h - Declare SystemZ target feature support -----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares SystemZ TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_SYSTEMZ_H 14 #define LLVM_CLANG_LIB_BASIC_TARGETS_SYSTEMZ_H 15 16 #include "clang/Basic/TargetInfo.h" 17 #include "clang/Basic/TargetOptions.h" 18 #include "llvm/ADT/Triple.h" 19 #include "llvm/Support/Compiler.h" 20 21 namespace clang { 22 namespace targets { 23 24 class LLVM_LIBRARY_VISIBILITY SystemZTargetInfo : public TargetInfo { 25 26 static const Builtin::Info BuiltinInfo[]; 27 static const char *const GCCRegNames[]; 28 std::string CPU; 29 int ISARevision; 30 bool HasTransactionalExecution; 31 bool HasVector; 32 bool SoftFloat; 33 34 public: 35 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 36 : TargetInfo(Triple), CPU("z10"), ISARevision(8), 37 HasTransactionalExecution(false), HasVector(false), SoftFloat(false) { 38 IntMaxType = SignedLong; 39 Int64Type = SignedLong; 40 TLSSupported = true; 41 IntWidth = IntAlign = 32; 42 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 43 PointerWidth = PointerAlign = 64; 44 LongDoubleWidth = 128; 45 LongDoubleAlign = 64; 46 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 47 DefaultAlignForAttributeAligned = 64; 48 MinGlobalAlign = 16; 49 if (Triple.isOSzOS()) { 50 // All vector types are default aligned on an 8-byte boundary, even if the 51 // vector facility is not available. That is different from Linux. 52 MaxVectorAlign = 64; 53 // Compared to Linux/ELF, the data layout differs only in some details: 54 // - name mangling is GOFF 55 // - 128 bit vector types are 64 bit aligned 56 resetDataLayout( 57 "E-m:l-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"); 58 } else 59 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 60 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 61 HasStrictFP = true; 62 } 63 64 void getTargetDefines(const LangOptions &Opts, 65 MacroBuilder &Builder) const override; 66 67 ArrayRef<Builtin::Info> getTargetBuiltins() const override; 68 69 ArrayRef<const char *> getGCCRegNames() const override; 70 71 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 72 // No aliases. 73 return None; 74 } 75 76 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override; 77 78 bool isSPRegName(StringRef RegName) const override { 79 return RegName.equals("r15"); 80 } 81 82 bool validateAsmConstraint(const char *&Name, 83 TargetInfo::ConstraintInfo &info) const override; 84 85 const char *getClobbers() const override { 86 // FIXME: Is this really right? 87 return ""; 88 } 89 90 BuiltinVaListKind getBuiltinVaListKind() const override { 91 return TargetInfo::SystemZBuiltinVaList; 92 } 93 94 int getISARevision(StringRef Name) const; 95 96 bool isValidCPUName(StringRef Name) const override { 97 return getISARevision(Name) != -1; 98 } 99 100 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override; 101 102 bool setCPU(const std::string &Name) override { 103 CPU = Name; 104 ISARevision = getISARevision(CPU); 105 return ISARevision != -1; 106 } 107 108 bool 109 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 110 StringRef CPU, 111 const std::vector<std::string> &FeaturesVec) const override { 112 int ISARevision = getISARevision(CPU); 113 if (ISARevision >= 10) 114 Features["transactional-execution"] = true; 115 if (ISARevision >= 11) 116 Features["vector"] = true; 117 if (ISARevision >= 12) 118 Features["vector-enhancements-1"] = true; 119 if (ISARevision >= 13) 120 Features["vector-enhancements-2"] = true; 121 if (ISARevision >= 14) 122 Features["nnp-assist"] = true; 123 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 124 } 125 126 bool handleTargetFeatures(std::vector<std::string> &Features, 127 DiagnosticsEngine &Diags) override { 128 HasTransactionalExecution = false; 129 HasVector = false; 130 SoftFloat = false; 131 for (const auto &Feature : Features) { 132 if (Feature == "+transactional-execution") 133 HasTransactionalExecution = true; 134 else if (Feature == "+vector") 135 HasVector = true; 136 else if (Feature == "+soft-float") 137 SoftFloat = true; 138 } 139 HasVector &= !SoftFloat; 140 141 // If we use the vector ABI, vector types are 64-bit aligned. 142 if (HasVector && !getTriple().isOSzOS()) { 143 MaxVectorAlign = 64; 144 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 145 "-v128:64-a:8:16-n32:64"); 146 } 147 return true; 148 } 149 150 bool hasFeature(StringRef Feature) const override; 151 152 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 153 switch (CC) { 154 case CC_C: 155 case CC_Swift: 156 case CC_OpenCLKernel: 157 return CCCR_OK; 158 case CC_SwiftAsync: 159 return CCCR_Error; 160 default: 161 return CCCR_Warning; 162 } 163 } 164 165 StringRef getABI() const override { 166 if (HasVector) 167 return "vector"; 168 return ""; 169 } 170 171 const char *getLongDoubleMangling() const override { return "g"; } 172 173 bool hasBitIntType() const override { return true; } 174 175 int getEHDataRegisterNumber(unsigned RegNo) const override { 176 return RegNo < 4 ? 6 + RegNo : -1; 177 } 178 }; 179 } // namespace targets 180 } // namespace clang 181 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_SYSTEMZ_H 182