xref: /freebsd/contrib/llvm-project/clang/include/clang/Basic/arm_sme.td (revision 5f757f3ff9144b609b3c433dfd370cc6bdc191ad) 
1//===--- arm_sme.td - ARM SME compiler interface ------------------------===//
2//
3//  Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4//  See https://llvm.org/LICENSE.txt for license information.
5//  SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//  This file defines the TableGen definitions from which the ARM SME header
10//  file will be generated.  See:
11//
12//      https://developer.arm.com/architectures/system-architectures/software-standards/acle
13//
14//===----------------------------------------------------------------------===//
15
16include "arm_sve_sme_incl.td"
17
18////////////////////////////////////////////////////////////////////////////////
19// Loads
20
21multiclass ZALoad<string n_suffix, string t, string i_prefix, list<ImmCheck> ch> {
22  let TargetGuard = "sme" in {
23    def NAME # _H : MInst<"svld1_hor_" # n_suffix, "vimPQ", t,
24                          [IsLoad, IsOverloadNone, IsStreaming, IsSharedZA],
25                          MemEltTyDefault, i_prefix # "_horiz", ch>;
26
27    def NAME # _H_VNUM : MInst<"svld1_hor_vnum_" # n_suffix, "vimPQl", t,
28                               [IsLoad, IsOverloadNone, IsStreaming, IsSharedZA],
29                               MemEltTyDefault, i_prefix # "_horiz", ch>;
30
31    def NAME # _V : MInst<"svld1_ver_" # n_suffix, "vimPQ", t,
32                          [IsLoad, IsOverloadNone, IsStreaming, IsSharedZA],
33                          MemEltTyDefault, i_prefix # "_vert", ch>;
34
35    def NAME # _V_VNUM : MInst<"svld1_ver_vnum_" # n_suffix, "vimPQl", t,
36                               [IsLoad, IsOverloadNone, IsStreaming, IsSharedZA],
37                               MemEltTyDefault, i_prefix # "_vert", ch>;
38  }
39}
40
41defm SVLD1_ZA8 : ZALoad<"za8", "c", "aarch64_sme_ld1b", [ImmCheck<0, ImmCheck0_0>]>;
42defm SVLD1_ZA16 : ZALoad<"za16", "s", "aarch64_sme_ld1h", [ImmCheck<0, ImmCheck0_1>]>;
43defm SVLD1_ZA32 : ZALoad<"za32", "i", "aarch64_sme_ld1w", [ImmCheck<0, ImmCheck0_3>]>;
44defm SVLD1_ZA64 : ZALoad<"za64", "l", "aarch64_sme_ld1d", [ImmCheck<0, ImmCheck0_7>]>;
45defm SVLD1_ZA128 : ZALoad<"za128", "q", "aarch64_sme_ld1q", [ImmCheck<0, ImmCheck0_15>]>;
46
47def SVLDR_VNUM_ZA : MInst<"svldr_vnum_za", "vmQl", "",
48                          [IsOverloadNone, IsStreamingCompatible, IsSharedZA],
49                          MemEltTyDefault, "aarch64_sme_ldr">;
50
51def SVLDR_ZA : MInst<"svldr_za", "vmQ", "",
52                          [IsOverloadNone, IsStreamingCompatible, IsSharedZA],
53                          MemEltTyDefault, "aarch64_sme_ldr", []>;
54
55////////////////////////////////////////////////////////////////////////////////
56// Stores
57
58multiclass ZAStore<string n_suffix, string t, string i_prefix, list<ImmCheck> ch> {
59  let TargetGuard = "sme" in {
60    def NAME # _H : MInst<"svst1_hor_" # n_suffix, "vimP%", t,
61                          [IsStore, IsOverloadNone, IsStreaming, IsSharedZA, IsPreservesZA],
62                          MemEltTyDefault, i_prefix # "_horiz", ch>;
63
64    def NAME # _H_VNUM : MInst<"svst1_hor_vnum_" # n_suffix, "vimP%l", t,
65                               [IsStore, IsOverloadNone, IsStreaming, IsSharedZA, IsPreservesZA],
66                               MemEltTyDefault, i_prefix # "_horiz", ch>;
67
68    def NAME # _V : MInst<"svst1_ver_" # n_suffix, "vimP%", t,
69                          [IsStore, IsOverloadNone, IsStreaming, IsSharedZA, IsPreservesZA],
70                          MemEltTyDefault, i_prefix # "_vert", ch>;
71
72    def NAME # _V_VNUM : MInst<"svst1_ver_vnum_" # n_suffix, "vimP%l", t,
73                               [IsStore, IsOverloadNone, IsStreaming, IsSharedZA, IsPreservesZA],
74                               MemEltTyDefault, i_prefix # "_vert", ch>;
75  }
76}
77
78defm SVST1_ZA8 : ZAStore<"za8", "c", "aarch64_sme_st1b", [ImmCheck<0, ImmCheck0_0>]>;
79defm SVST1_ZA16 : ZAStore<"za16", "s", "aarch64_sme_st1h", [ImmCheck<0, ImmCheck0_1>]>;
80defm SVST1_ZA32 : ZAStore<"za32", "i", "aarch64_sme_st1w", [ImmCheck<0, ImmCheck0_3>]>;
81defm SVST1_ZA64 : ZAStore<"za64", "l", "aarch64_sme_st1d", [ImmCheck<0, ImmCheck0_7>]>;
82defm SVST1_ZA128 : ZAStore<"za128", "q", "aarch64_sme_st1q", [ImmCheck<0, ImmCheck0_15>]>;
83
84def SVSTR_VNUM_ZA : MInst<"svstr_vnum_za", "vm%l", "",
85                          [IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA],
86                          MemEltTyDefault, "aarch64_sme_str">;
87
88def SVSTR_ZA : MInst<"svstr_za", "vm%", "",
89                      [IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA],
90                      MemEltTyDefault, "aarch64_sme_str", []>;
91
92////////////////////////////////////////////////////////////////////////////////
93// Read horizontal/vertical ZA slices
94
95multiclass ZARead<string n_suffix, string t, string i_prefix, list<ImmCheck> ch> {
96  let TargetGuard = "sme" in {
97    def NAME # _H : SInst<"svread_hor_" # n_suffix # "[_{d}]", "ddPim", t,
98                          MergeOp1, i_prefix # "_horiz",
99                          [IsReadZA, IsStreaming, IsSharedZA, IsPreservesZA], ch>;
100
101    def NAME # _V : SInst<"svread_ver_" # n_suffix # "[_{d}]", "ddPim", t,
102                          MergeOp1, i_prefix # "_vert",
103                          [IsReadZA, IsStreaming, IsSharedZA, IsPreservesZA], ch>;
104  }
105}
106
107defm SVREAD_ZA8 : ZARead<"za8", "cUc", "aarch64_sme_read", [ImmCheck<2, ImmCheck0_0>]>;
108defm SVREAD_ZA16 : ZARead<"za16", "sUshb", "aarch64_sme_read", [ImmCheck<2, ImmCheck0_1>]>;
109defm SVREAD_ZA32 : ZARead<"za32", "iUif", "aarch64_sme_read", [ImmCheck<2, ImmCheck0_3>]>;
110defm SVREAD_ZA64 : ZARead<"za64", "lUld", "aarch64_sme_read", [ImmCheck<2, ImmCheck0_7>]>;
111defm SVREAD_ZA128 : ZARead<"za128", "csilUcUsUiUlhbfd", "aarch64_sme_readq", [ImmCheck<2, ImmCheck0_15>]>;
112
113////////////////////////////////////////////////////////////////////////////////
114// Write horizontal/vertical ZA slices
115
116multiclass ZAWrite<string n_suffix, string t, string i_prefix, list<ImmCheck> ch> {
117  let TargetGuard = "sme" in {
118    def NAME # _H : SInst<"svwrite_hor_" # n_suffix # "[_{d}]", "vimPd", t,
119                          MergeOp1, i_prefix # "_horiz",
120                          [IsWriteZA, IsStreaming, IsSharedZA], ch>;
121
122    def NAME # _V : SInst<"svwrite_ver_" # n_suffix # "[_{d}]", "vimPd", t,
123                          MergeOp1, i_prefix # "_vert",
124                          [IsWriteZA, IsStreaming, IsSharedZA], ch>;
125  }
126}
127
128defm SVWRITE_ZA8 : ZAWrite<"za8", "cUc", "aarch64_sme_write", [ImmCheck<0, ImmCheck0_0>]>;
129defm SVWRITE_ZA16 : ZAWrite<"za16", "sUshb", "aarch64_sme_write", [ImmCheck<0, ImmCheck0_1>]>;
130defm SVWRITE_ZA32 : ZAWrite<"za32", "iUif", "aarch64_sme_write", [ImmCheck<0, ImmCheck0_3>]>;
131defm SVWRITE_ZA64 : ZAWrite<"za64", "lUld", "aarch64_sme_write", [ImmCheck<0, ImmCheck0_7>]>;
132defm SVWRITE_ZA128 : ZAWrite<"za128", "csilUcUsUiUlhbfd", "aarch64_sme_writeq", [ImmCheck<0, ImmCheck0_15>]>;
133
134////////////////////////////////////////////////////////////////////////////////
135// SME - Zero
136
137let TargetGuard = "sme" in {
138  def SVZERO_MASK_ZA : SInst<"svzero_mask_za", "vi", "", MergeNone, "aarch64_sme_zero",
139                             [IsOverloadNone, IsStreamingCompatible, IsSharedZA],
140                             [ImmCheck<0, ImmCheck0_255>]>;
141  def SVZERO_ZA      : SInst<"svzero_za", "v", "", MergeNone, "aarch64_sme_zero",
142                             [IsOverloadNone, IsStreamingCompatible, IsSharedZA]>;
143}
144
145////////////////////////////////////////////////////////////////////////////////
146// SME - Counting elements in a streaming vector
147
148multiclass ZACount<string n_suffix> {
149  let TargetGuard = "sme" in {
150    def NAME : SInst<"sv" # n_suffix, "nv", "", MergeNone,
151                      "aarch64_sme_" # n_suffix,
152                      [IsOverloadNone, IsStreamingCompatible, IsPreservesZA]>;
153  }
154}
155
156defm SVCNTSB : ZACount<"cntsb">;
157defm SVCNTSH : ZACount<"cntsh">;
158defm SVCNTSW : ZACount<"cntsw">;
159defm SVCNTSD : ZACount<"cntsd">;
160
161////////////////////////////////////////////////////////////////////////////////
162// SME - ADDHA/ADDVA
163
164multiclass ZAAdd<string n_suffix> {
165  let TargetGuard = "sme" in {
166    def NAME # _ZA32: SInst<"sv" # n_suffix # "_za32[_{d}]", "viPPd", "iUi", MergeOp1,
167                      "aarch64_sme_" # n_suffix, [IsStreaming, IsSharedZA],
168                      [ImmCheck<0, ImmCheck0_3>]>;
169  }
170
171  let TargetGuard = "sme-i16i64" in {
172    def NAME # _ZA64: SInst<"sv" # n_suffix # "_za64[_{d}]", "viPPd", "lUl", MergeOp1,
173                     "aarch64_sme_" # n_suffix, [IsStreaming, IsSharedZA],
174                     [ImmCheck<0, ImmCheck0_7>]>;
175  }
176}
177
178defm SVADDHA : ZAAdd<"addha">;
179defm SVADDVA : ZAAdd<"addva">;
180
181////////////////////////////////////////////////////////////////////////////////
182// SME - SMOPA, SMOPS, UMOPA, UMOPS
183
184multiclass ZAIntOuterProd<string n_suffix1, string n_suffix2> {
185  let TargetGuard = "sme" in {
186    def NAME # _ZA32_B: SInst<"sv" # n_suffix2 # "_za32[_{d}]",
187                              "viPPdd", !cond(!eq(n_suffix1, "s") : "", true: "U") # "c",
188                              MergeOp1, "aarch64_sme_" # n_suffix1 # n_suffix2 # "_wide",
189                              [IsStreaming, IsSharedZA],
190                              [ImmCheck<0, ImmCheck0_3>]>;
191  }
192
193  let TargetGuard = "sme-i16i64" in {
194    def NAME # _ZA64_H: SInst<"sv" # n_suffix2 # "_za64[_{d}]",
195                              "viPPdd", !cond(!eq(n_suffix1, "s") : "", true: "U") # "s",
196                              MergeOp1, "aarch64_sme_" # n_suffix1 # n_suffix2 # "_wide",
197                              [IsStreaming, IsSharedZA],
198                              [ImmCheck<0, ImmCheck0_7>]>;
199  }
200}
201
202defm SVSMOPA : ZAIntOuterProd<"s", "mopa">;
203defm SVSMOPS : ZAIntOuterProd<"s", "mops">;
204defm SVUMOPA : ZAIntOuterProd<"u", "mopa">;
205defm SVUMOPS : ZAIntOuterProd<"u", "mops">;
206
207////////////////////////////////////////////////////////////////////////////////
208// SME - SUMOPA, SUMOPS, USMOPA, USMOPS
209
210multiclass ZAIntOuterProdMixedSigns<string n_suffix1, string n_suffix2> {
211  let TargetGuard = "sme" in {
212    def NAME # _ZA32_B: SInst<"sv" # n_suffix1 # n_suffix2 # "_za32[_{d}]",
213                              "viPPd" # !cond(!eq(n_suffix1, "su") : "u", true: "x"),
214                              !cond(!eq(n_suffix1, "su") : "", true: "U") # "c",
215                              MergeOp1, "aarch64_sme_" # n_suffix1 # n_suffix2 # "_wide",
216                              [IsStreaming, IsSharedZA],
217                              [ImmCheck<0, ImmCheck0_3>]>;
218  }
219
220  let TargetGuard = "sme-i16i64" in {
221    def NAME # _ZA64_H: SInst<"sv" # n_suffix1 # n_suffix2 # "_za64[_{d}]",
222                              "viPPd" # !cond(!eq(n_suffix1, "su") : "u", true: "x"),
223                              !cond(!eq(n_suffix1, "su") : "", true: "U") # "s",
224                              MergeOp1, "aarch64_sme_" # n_suffix1 # n_suffix2 # "_wide",
225                              [IsStreaming, IsSharedZA],
226                              [ImmCheck<0, ImmCheck0_7>]>;
227  }
228}
229
230defm SVSUMOPA : ZAIntOuterProdMixedSigns<"su", "mopa">;
231defm SVSUMOPS : ZAIntOuterProdMixedSigns<"su", "mops">;
232defm SVUSMOPA : ZAIntOuterProdMixedSigns<"us", "mopa">;
233defm SVUSMOPS : ZAIntOuterProdMixedSigns<"us", "mops">;
234
235////////////////////////////////////////////////////////////////////////////////
236// SME - FMOPA, FMOPS
237
238multiclass ZAFPOuterProd<string n_suffix> {
239  let TargetGuard = "sme" in {
240    def NAME # _ZA32_B: SInst<"sv" # n_suffix # "_za32[_{d}]", "viPPdd", "h",
241                              MergeOp1, "aarch64_sme_" # n_suffix # "_wide",
242                              [IsStreaming, IsSharedZA],
243                              [ImmCheck<0, ImmCheck0_3>]>;
244
245    def NAME # _ZA32_H: SInst<"sv" # n_suffix # "_za32[_{d}]", "viPPdd", "b",
246                              MergeOp1, "aarch64_sme_" # n_suffix # "_wide",
247                              [IsStreaming, IsSharedZA],
248                              [ImmCheck<0, ImmCheck0_3>]>;
249
250    def NAME # _ZA32_S: SInst<"sv" # n_suffix # "_za32[_{d}]", "viPPdd", "f",
251                              MergeOp1, "aarch64_sme_" # n_suffix,
252                              [IsStreaming, IsSharedZA],
253                              [ImmCheck<0, ImmCheck0_3>]>;
254  }
255
256  let TargetGuard = "sme-f64f64" in {
257    def NAME # _ZA64_D: SInst<"sv" # n_suffix # "_za64[_{d}]", "viPPdd", "d",
258                              MergeOp1, "aarch64_sme_" # n_suffix,
259                              [IsStreaming, IsSharedZA],
260                              [ImmCheck<0, ImmCheck0_7>]>;
261  }
262}
263
264defm SVMOPA : ZAFPOuterProd<"mopa">;
265defm SVMOPS : ZAFPOuterProd<"mops">;
266
267////////////////////////////////////////////////////////////////////////////////
268// SME2 - ADD, SUB
269
270multiclass ZAAddSub<string n_suffix> {
271  let TargetGuard = "sme2" in {
272    def NAME # _WRITE_SINGLE_ZA32_VG1X2_I32 : Inst<"sv" # n_suffix # "_write[_single]_za32[_{d}]_vg1x2", "vm2d", "iUi", MergeNone, "aarch64_sme_" # n_suffix # "_write_single_za_vg1x2", [IsStreaming, IsSharedZA], []>;
273    def NAME # _WRITE_SINGLE_ZA32_VG1X4_I32 : Inst<"sv" # n_suffix # "_write[_single]_za32[_{d}]_vg1x4", "vm4d", "iUi", MergeNone, "aarch64_sme_" # n_suffix # "_write_single_za_vg1x4", [IsStreaming, IsSharedZA], []>;
274
275    def NAME # _WRITE_ZA32_VG1X2_I32 : Inst<"sv" # n_suffix # "_write_za32[_{d}]_vg1x2", "vm22", "iUi", MergeNone, "aarch64_sme_" # n_suffix # "_write_za_vg1x2", [IsStreaming, IsSharedZA], []>;
276    def NAME # _WRITE_ZA32_VG1X4_I32 : Inst<"sv" # n_suffix # "_write_za32[_{d}]_vg1x4", "vm44", "iUi", MergeNone, "aarch64_sme_" # n_suffix # "_write_za_vg1x4", [IsStreaming, IsSharedZA], []>;
277
278    def NAME # _ZA32_VG1x2_I32 : Inst<"sv" # n_suffix # "_za32[_{d}]_vg1x2", "vm2", "iUif", MergeNone, "aarch64_sme_" # n_suffix # "_za32_vg1x2", [IsStreaming, IsSharedZA], []>;
279    def NAME # _ZA32_VG1X4_I32 : Inst<"sv" # n_suffix # "_za32[_{d}]_vg1x4", "vm4", "iUif", MergeNone, "aarch64_sme_" # n_suffix # "_za32_vg1x4", [IsStreaming, IsSharedZA], []>;
280
281    let TargetGuard = "sme-i16i64" in {
282      def NAME # _WRITE_SINGLE_ZA64_VG1X2_I64 : Inst<"sv" # n_suffix # "_write[_single]_za64[_{d}]_vg1x2", "vm2d", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_write_single_za_vg1x2", [IsStreaming, IsSharedZA], []>;
283      def NAME # _WRITE_SINGLE_ZA64_VG1X4_I64 : Inst<"sv" # n_suffix # "_write[_single]_za64[_{d}]_vg1x4", "vm4d", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_write_single_za_vg1x4", [IsStreaming, IsSharedZA], []>;
284
285      def NAME # _WRITE_ZA64_VG1x2_I64 : Inst<"sv" # n_suffix # "_write_za64[_{d}]_vg1x2", "vm22", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_write_za_vg1x2", [IsStreaming, IsSharedZA], []>;
286      def NAME # _WRITE_ZA64_VG1x4_I64 : Inst<"sv" # n_suffix # "_write_za64[_{d}]_vg1x4", "vm44", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_write_za_vg1x4", [IsStreaming, IsSharedZA], []>;
287
288      def NAME # _ZA64_VG1X2_I64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x2", "vm2", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x2", [IsStreaming, IsSharedZA], []>;
289      def NAME # _ZA64_VG1X4_I64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x4", "vm4", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x4", [IsStreaming, IsSharedZA], []>;
290    }
291
292    let TargetGuard = "sme-f64f64" in {
293      def NAME # _ZA64_VG1X2_F64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x2", "vm2", "d", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x2", [IsStreaming, IsSharedZA], []>;
294      def NAME # _ZA64_VG1X4_F64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x4", "vm4", "d", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x4", [IsStreaming, IsSharedZA], []>;
295    }
296  }
297}
298
299defm SVADD : ZAAddSub<"add">;
300defm SVSUB : ZAAddSub<"sub">;
301
302//
303// Outer product and accumulate/subtract
304//
305
306let TargetGuard = "sme2" in {
307  def SVSMOPA  : Inst<"svmopa_za32[_{d}]_m", "viPPdd", "s", MergeNone, "aarch64_sme_smopa_za32", [IsSharedZA, IsStreaming], [ImmCheck<0, ImmCheck0_3>]>;
308  def SVUSMOPA : Inst<"svmopa_za32[_{d}]_m", "viPPdd", "Us", MergeNone, "aarch64_sme_umopa_za32", [IsSharedZA, IsStreaming], [ImmCheck<0, ImmCheck0_3>]>;
309
310  def SVSMOPS  : Inst<"svmops_za32[_{d}]_m", "viPPdd", "s", MergeNone, "aarch64_sme_smops_za32", [IsSharedZA, IsStreaming], [ImmCheck<0, ImmCheck0_3>]>;
311  def SVUSMOPS : Inst<"svmops_za32[_{d}]_m", "viPPdd", "Us", MergeNone, "aarch64_sme_umops_za32", [IsSharedZA, IsStreaming], [ImmCheck<0, ImmCheck0_3>]>;
312
313  def SVBMOPA : Inst<"svbmopa_za32[_{d}]_m", "viPPdd", "iUi", MergeNone, "aarch64_sme_bmopa_za32", [IsSharedZA, IsStreaming], [ImmCheck<0, ImmCheck0_3>]>;
314
315  def SVBMOPS : Inst<"svbmops_za32[_{d}]_m", "viPPdd", "iUi", MergeNone, "aarch64_sme_bmops_za32", [IsSharedZA, IsStreaming], [ImmCheck<0, ImmCheck0_3>]>;
316}
317
318//
319// Spill and fill of ZT0
320//
321let TargetGuard = "sme2" in {
322  def SVLDR_ZT : Inst<"svldr_zt", "viQ", "", MergeNone, "aarch64_sme_ldr_zt", [IsOverloadNone, IsStreamingCompatible, IsSharedZA], [ImmCheck<0, ImmCheck0_0>]>;
323  def SVSTR_ZT : Inst<"svstr_zt", "vi%", "", MergeNone, "aarch64_sme_str_zt", [IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>]>;
324}
325
326//
327// Zero ZT0
328//
329let TargetGuard = "sme2" in {
330  def SVZERO_ZT : Inst<"svzero_zt", "vi", "", MergeNone, "aarch64_sme_zero_zt", [IsOverloadNone, IsStreamingCompatible, IsSharedZA], [ImmCheck<0, ImmCheck0_0>]>;
331}
332
333//
334// lookup table expand four contiguous registers
335//
336let TargetGuard = "sme2" in {
337  def SVLUTI2_LANE_ZT_X4 : Inst<"svluti2_lane_zt_{d}_x4", "4.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x4", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>;
338  def SVLUTI4_LANE_ZT_X4 : Inst<"svluti4_lane_zt_{d}_x4", "4.di[i", "sUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x4", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_1>]>;
339}
340
341//
342// lookup table expand one register
343//
344let TargetGuard = "sme2" in {
345  def SVLUTI2_LANE_ZT : Inst<"svluti2_lane_zt_{d}", "di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_15>]>;
346  def SVLUTI4_LANE_ZT : Inst<"svluti4_lane_zt_{d}", "di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>;
347}
348
349//
350// lookup table expand two contiguous registers
351//
352let TargetGuard = "sme2" in {
353  def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>;
354  def SVLUTI4_LANE_ZT_X2 : Inst<"svluti4_lane_zt_{d}_x2", "2.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x2", [IsStreaming, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>;
355}
356