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123

/titanic_50/usr/src/cmd/mdb/sparc/v9/kmdb/
H A Dkmdb_setcontext.s52 mov %o0, %g7
54 ldx [%g7 + UC_GREG(REG_O0)], %o0
55 ldx [%g7 + UC_GREG(REG_O1)], %o1
56 ldx [%g7 + UC_GREG(REG_O2)], %o2
57 ldx [%g7 + UC_GREG(REG_O3)], %o3
58 ldx [%g7 + UC_GREG(REG_O4)], %o4
59 ldx [%g7 + UC_GREG(REG_O5)], %o5
60 ldx [%g7 + UC_GREG(REG_O6)], %o6
61 ldx [%g7 + UC_GREG(REG_O7)], %o7
63 ldx [%g7 + UC_GREG(REG_G1)], %g1
[all …]
H A Dkaif_handlers.s204 KAIF_CALL_KDI_VATOTTE(%g1, %g2, kaif_hdlr_dmiss_patch, %g3, %g7)
214 ldx [%g7 + .count-0b], %g2
216 stx %g2, [%g7 + .count-0b]
238 stx %g2, [%g7 + .daddr-0b]
239 stx %g1, [%g7 + .ecode-0b]
262 KAIF_CALL_KDI_VATOTTE(%g1, %g2, kaif_hdlr_imiss_patch, %g3, %g7)
271 ldx [%g7 + .count-0b], %g2
273 stx %g2, [%g7 + .count-0b]
H A Dkaif_invoke.s62 kreg_t g6, kreg_t g7)
142 mov %g7, %l1
143 mov %i4, %g7 ! Restore THREAD_REG for kernel call
149 mov %l1, %g7
H A Dkaif_startup.s49 set 1f, %g7; \
56 sethi %hi(1f), %g7; \
58 or %g7, %lo(1f), %g7; \
102 mov %g7, %g5 ! we'll need %g7 for the ID retriever
124 * %g7 - return address
160 stx %g7, [%o5 + KREG_OFF(KREG_G7)]
179 set 1f, %g7
391 set 1f, %g7
473 set kaif_trap_common, %g7
615 set 1f, %g7
[all …]
/titanic_50/usr/src/lib/libc/sparc/sys/
H A Dvforkx.s82 ld [%g7 + UL_SIGMASK], %o1
83 ld [%g7 + UL_SIGMASK + 4], %o2
84 ld [%g7 + UL_SIGMASK + 8], %o3
85 ld [%g7 + UL_SIGMASK + 12], %o4
100 ld [%g7 + UL_VFORK], %g1
108 st %g1, [%g7 + UL_VFORK]
113 stn %g0, [%g7 + UL_SCHEDCTL]
114 stn %g0, [%g7 + UL_SCHEDCTL_CALLED]
118 ld [%g7 + UL_SIGMASK], %o1
119 ld [%g7 + UL_SIGMASK + 4], %o2
[all …]
/titanic_50/usr/src/uts/sun4u/ml/
H A Dwbuf.s158 FAULT_WINTRACE(%g5, %g6, %g7, TT_F32_SO1)
165 add %g5, 1, %g7
166 st %g7, [%g6 + MPCB_WBCNT]
170 sll %g5, CPTRSHIFT, %g7 ! spbuf size is sizeof (caddr_t)
171 add %g6, %g7, %g7
172 stn %sp, [%g7 + MPCB_SPBUF]
173 sll %g5, RWIN32SHIFT, %g7
175 add %g5, %g7, %g7
176 SAVE_V8WINDOW(%g7)
292 FAULT_WINTRACE(%g5, %g6, %g7, TT_F64_SO1)
[all …]
H A Dtrap_table.s93 rd %pc, %g7
787 mov WSTATE_USER32, %g7 ;\
818 mov WSTATE_USER64, %g7 ;\
1084 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\
1086 cmp %g4, %g7 ;\
1119 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\
1123 cmp %g4, %g7 ;\
1175 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\
1177 cmp %g4, %g7 ;\
1212 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\
[all …]
/titanic_50/usr/src/uts/sfmmu/ml/
H A Dsfmmu_asm.s62 rd %pc, %g7
1849 rdpr %tt, %g7
1859 wrpr %g7, %tt
1898 rdpr %tt, %g7
1899 cmp %g7, FAST_IMMU_MISS_TT
1902 cmp %g7, T_INSTR_MMU_MISS
1906 cmp %g7, FAST_DMMU_MISS_TT
1908 cmp %g7, T_DATA_MMU_MISS
2430 mov %g2, %g7 ! TSB pointer macro clobbers tagacc
2437 GET_TSBE_POINTER(MMU_PAGESHIFT, %g1, %g7, %g3, %g5)
[all …]
H A Dsfmmu_kdi.s282 jmpl %g3, %g7 /* => %g1: TTE or 0 */
283 add %g7, 8, %g7
342 6: jmp %g7
/titanic_50/usr/src/uts/sun4v/ml/
H A Dwbuf.s160 FAULT_WINTRACE(%g5, %g6, %g7, TT_F32_SO1)
168 add %g5, 1, %g7
169 sta %g7, [%g6 + MPCB_WBCNT]%asi
173 sll %g5, CPTRSHIFT, %g7 ! spbuf size is sizeof (caddr_t)
174 add %g6, %g7, %g7
175 stna %sp, [%g7 + MPCB_SPBUF]%asi
176 sll %g5, RWIN32SHIFT, %g7
178 add %g5, %g7, %g7
179 SAVE_V8WINDOW_ASI(%g7)
353 FAULT_WINTRACE(%g5, %g6, %g7, TT_F64_SO1)
[all …]
H A Dmach_interrupt.s72 ! %g7 tail ptr
76 ldxa [%g4]ASI_QUEUE, %g7 ! %g7 = tail ptr
77 cmp %g6, %g7
526 set CPU_NRQ_SIZE, %g7
527 add %g4, %g7, %g7 ! %g7 = PA of ER in kernel buf
529 ldxa [%g7]ASI_MEM, %g5 ! %g5 = first 8 byte of ER buf
537 stxa %g1, [%g7 + %g5]ASI_MEM ! byte 0 - 7
540 stxa %g1, [%g7 + %g5]ASI_MEM ! byte 8 - 15
543 stxa %g1, [%g7 + %g5]ASI_MEM ! byte 16 - 23
546 stxa %g1, [%g7 + %g5]ASI_MEM ! byte 24 - 31
[all …]
H A Dtrap_table.s94 rd %pc, %g7
667 mov WSTATE_USER32, %g7 ;\
698 mov WSTATE_USER64, %g7 ;\
948 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\
955 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\
992 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\
999 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\
1435 or %g2, %g0, %g7
1498 or %g0, %g0, %g7
1555 mov %g7, %l3 ! arg2 == misaligned address
[all …]
/titanic_50/usr/src/tools/tokenize/
H A Dasmsubr.s43 .register %g7, #scratch
45 mov %g7, %o0
49 .register %g7, #scratch
51 mov %o0, %g7
/titanic_50/usr/src/stand/lib/sa/sparc/
H A D_setjmp.s113 set nwindows, %g7
114 ld [%g7], %g7
115 sub %g7, 2, %g6
120 sub %g7, 2, %g6
/titanic_50/usr/src/cmd/mdb/sun4v/v9/kmdb/
H A Dmach_asmutil.h55 mov %g7, %o3 /* %o3 is return pc now */; \
62 mov %o3, %g7 /* retore %g7 as return pc */; \
65 jmp %g7; \
/titanic_50/usr/src/uts/sun4v/vm/
H A Dmach_sfmmu_asm.s128 mov MMU_PCONTEXT, %g7
134 ldxa [%g7]ASI_MMU_CTX, %g5 /* %g5 = pri-ctx */
139 stxa %g2, [%g7]ASI_MMU_CTX /* set pri-ctx to invalid */
146 mov %o5, %g7
161 mov %g7, %o5
181 mov MMU_PCONTEXT, %g7
187 ldxa [%g7]ASI_MMU_CTX, %g4 /* %g4 = pri-ctx */
191 stxa %g2, [%g7]ASI_MMU_CTX /* set pri-ctx to invalid */
198 mov %o5, %g7
207 mov %g7, %o5
/titanic_50/usr/src/uts/sun4u/cpu/
H A Dus3_cheetah_asm.s135 ldxa [%g0]ASI_ESTATE_ERR, %g7
136 andn %g7, EN_REG_CEEN | EN_REG_NCEEN, %g5
161 stxa %g7, [%g0]ASI_ESTATE_ERR
230 rd %asi, %g7
244 wr %g0, %g7, %asi
250 wr %g0, %g7, %asi
256 wr %g0, %g7, %asi
H A Dus3_cheetahplus_asm.s206 ldxa [%g0]ASI_ESTATE_ERR, %g7
207 andn %g7, EN_REG_CEEN | EN_REG_NCEEN, %g5
233 stxa %g7, [%g0]ASI_ESTATE_ERR
309 rd %asi, %g7
323 wr %g0, %g7, %asi
329 wr %g0, %g7, %asi
335 wr %g0, %g7, %asi
821 mov %g2, %g7 ! Next we get the DTLB_1 index
825 PN_GET_TLB_INDEX(%g7, %g5) ! %g7 has the DTLB_1 index
826 sllx %g7, PN_TLB_ACC_IDX_SHIFT, %g7 ! shift the index into place
[all …]
H A Dus3_jalapeno_asm.s446 JP_FORCE_FULL_SPEED(%g2, %g3, %g6, %g7) /* %g2: saved speed */
449 ECACHE_FLUSHALL(%g4, %g5, %g6, %g7)
452 JP_RESTORE_SPEED(%g2, %g3, %g6, %g7) /* %g2: saved speed */
465 CH_DCACHE_FLUSHALL(%g5, %g6, %g7)
472 GET_CPU_PRIVATE_PTR(%g0, %g5, %g7, fast_ecc_err_4);
480 CH_ICACHE_FLUSHALL(%g5, %g6, %g7, %g4)
588 ldxa [%g0]ASI_ESTATE_ERR, %g7
589 andn %g7, EN_REG_CEEN | EN_REG_NCEEN, %g5
620 stxa %g7, [%g0]ASI_ESTATE_ERR
689 rd %asi, %g7
[all …]
/titanic_50/usr/src/cmd/mdb/sparc/kmdb/kctl/
H A Dkctl_asm.s47 mov %g7, %o0
49 mov %o1, %g7
/titanic_50/usr/src/lib/libc/sparcv9/threads/
H A Dsparcv9.il29 .register %g7, #scratch
30 mov %g7, %o0
34 .register %g7, #scratch
35 ldx [%g7 + 80], %o0 ! ul_self
/titanic_50/usr/src/lib/libc/sparc/gen/
H A D_stack_grow.s64 ldn [%g7 + UL_USTACK + SS_SP], %o1
65 ldn [%g7 + UL_USTACK + SS_SIZE], %o2
/titanic_50/usr/src/lib/libc/sparc/threads/
H A Dtls_get_addr.s71 ldn [%g7 + UL_TLSENT], %o2
72 ldn [%g7 + UL_NTLSENT], %o3
H A Dsparc.il29 .register %g7, #scratch
30 mov %g7, %o0
34 .register %g7, #scratch
35 ld [%g7 + 80], %o0 ! ul_self
/titanic_50/usr/src/uts/sparc/nskern/
H A Dnsc_asm.s123 .register %g7, #scratch
147 mov %g7, %o0

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