Home
last modified time | relevance | path

Searched refs:NXGE_REG_WR64 (Results 1 – 16 of 16) sorted by relevance

/titanic_44/usr/src/uts/common/io/nxge/
H A Dnxge_zcp.c83 NXGE_REG_WR64(handle, ZCP_CFIFO_ECC_PORT0_REG, 0); in nxge_zcp_init()
86 NXGE_REG_WR64(handle, ZCP_CFIFO_ECC_PORT1_REG, 0); in nxge_zcp_init()
89 NXGE_REG_WR64(handle, ZCP_CFIFO_ECC_PORT2_REG, 0); in nxge_zcp_init()
92 NXGE_REG_WR64(handle, ZCP_CFIFO_ECC_PORT3_REG, 0); in nxge_zcp_init()
246 NXGE_REG_WR64(handle, ZCP_CFIFO_ECC_PORT0_REG, 0); in nxge_zcp_handle_sys_errors()
249 NXGE_REG_WR64(handle, ZCP_CFIFO_ECC_PORT1_REG, 0); in nxge_zcp_handle_sys_errors()
252 NXGE_REG_WR64(handle, ZCP_CFIFO_ECC_PORT2_REG, 0); in nxge_zcp_handle_sys_errors()
255 NXGE_REG_WR64(handle, ZCP_CFIFO_ECC_PORT3_REG, 0); in nxge_zcp_handle_sys_errors()
291 NXGE_REG_WR64(nxgep->npi_handle, in nxge_zcp_inject_err()
299 NXGE_REG_WR64(nxgep->npi_handle, in nxge_zcp_inject_err()
[all …]
H A Dnxge_txc.c581 NXGE_REG_WR64(nxgep->npi_handle, TXC_INT_STAT_DBG_REG, in nxge_txc_inject_err()
H A Dnxge_rxdma.c1845 NXGE_REG_WR64(handle, in nxge_rx_intr()
1907 NXGE_REG_WR64(handle, in nxge_rx_intr()
1927 NXGE_REG_WR64(handle, in nxge_rx_intr()
2859 NXGE_REG_WR64(handle, in nxge_disable_poll()
4905 NXGE_REG_WR64(nxgep->npi_handle, in nxge_rxdma_inject_err()
H A Dnxge_intr.c1097 NXGE_REG_WR64(nxge->npi_handle, offset, mgm.value); in nxge_hio_ldgimgn()
/titanic_44/usr/src/uts/common/io/nxge/npi/
H A Dnpi_zcp.c75 NXGE_REG_WR64(handle, ZCP_CONFIG_REG, val); in npi_zcp_config()
101 NXGE_REG_WR64(handle, ZCP_CONFIG_REG, val); in npi_zcp_config()
136 NXGE_REG_WR64(handle, ZCP_INT_MASK_REG, val); in npi_zcp_iconfig()
149 NXGE_REG_WR64(handle, ZCP_INT_MASK_REG, val); in npi_zcp_iconfig()
180 NXGE_REG_WR64(handle, ZCP_INT_STAT_REG, val); in npi_zcp_clear_istatus()
203 NXGE_REG_WR64(handle, ZCP_CONFIG_REG, val); in npi_zcp_set_dma_thresh()
224 NXGE_REG_WR64(handle, ZCP_BAM4_RE_CTL_REG, region_attr->value); in npi_zcp_set_bam_region()
227 NXGE_REG_WR64(handle, ZCP_BAM8_RE_CTL_REG, region_attr->value); in npi_zcp_set_bam_region()
230 NXGE_REG_WR64(handle, ZCP_BAM16_RE_CTL_REG, region_attr->value); in npi_zcp_set_bam_region()
233 NXGE_REG_WR64(handle, ZCP_BAM32_RE_CTL_REG, region_attr->value); in npi_zcp_set_bam_region()
[all …]
H A Dnpi_vir.c305 NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); in npi_dev_func_sr_init()
307 NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); in npi_dev_func_sr_init()
364 NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); in npi_dev_func_sr_lock_enter()
428 NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); in npi_dev_func_sr_lock_free()
476 NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); in npi_dev_func_sr_funcid_get()
510 NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); in npi_dev_func_sr_sr_raw_get()
550 NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); in npi_dev_func_sr_sr_get()
592 NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); in npi_dev_func_sr_sr_get_set_clear()
622 NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); in npi_dev_func_sr_sr_set_only()
655 NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); in npi_dev_func_sr_busy()
[all …]
H A Dnpi_rxdma.c247 NXGE_REG_WR64(handle, valid_offset, page_vld.value); in npi_rxdma_cfg_logical_page_disable()
290 NXGE_REG_WR64(handle, valid_offset, page_vld.value); in npi_rxdma_cfg_logical_page()
321 NXGE_REG_WR64(handle, mask_offset, page_mask.value); in npi_rxdma_cfg_logical_page()
322 NXGE_REG_WR64(handle, value_offset, page_value.value); in npi_rxdma_cfg_logical_page()
323 NXGE_REG_WR64(handle, reloc_offset, page_reloc.value); in npi_rxdma_cfg_logical_page()
327 NXGE_REG_WR64(handle, valid_offset, page_vld.value); in npi_rxdma_cfg_logical_page()
350 NXGE_REG_WR64(handle, offset, page_hdl.value); in npi_rxdma_cfg_logical_page_handle()
516 NXGE_REG_WR64(handle, offset, cfg.value); in npi_rxdma_cfg_default_port_rdc()
880 NXGE_REG_WR64(handle, offset, cnt->value); in npi_rxdma_red_discard_stat_get()
925 NXGE_REG_WR64(handle, offset, cnt.value); in npi_rxdma_red_discard_oflow_clear()
[all …]
H A Dnpi_txc.c401 NXGE_REG_WR64(handle, TXC_CONTROL_REG, in npi_txc_control()
437 NXGE_REG_WR64(handle, TXC_CONTROL_REG, val | cntl.value); in npi_txc_global_enable()
464 NXGE_REG_WR64(handle, TXC_CONTROL_REG, val | cntl.value); in npi_txc_global_disable()
485 NXGE_REG_WR64(handle, TXC_PORT_CTL_REG, TXC_PORT_CNTL_CLEAR); in npi_txc_control_clear()
506 NXGE_REG_WR64(handle, TXC_TRAINING_REG, (uint64_t)vector); in npi_txc_training_set()
558 NXGE_REG_WR64(handle, TXC_CONTROL_REG, val | (1 << port)); in npi_txc_port_enable()
585 NXGE_REG_WR64(handle, TXC_CONTROL_REG, (val & ~(1 << port))); in npi_txc_port_disable()
733 NXGE_REG_WR64(handle, TXC_MAX_REORDER_REG, val); in npi_txc_reorder_set()
1033 NXGE_REG_WR64(handle, TXC_INT_STAT_REG, istatus); in npi_txc_global_istatus_clear()
1062 NXGE_REG_WR64(handle, TXC_INT_MASK_REG, val); in npi_txc_global_imask_set()
H A Dnpi_mac.h280 NXGE_REG_WR64(handle, XMAC_REG_ADDR((portn), (reg)), (val))
286 NXGE_REG_WR64(handle, BMAC_REG_ADDR((portn), (reg)), (val))
292 NXGE_REG_WR64(handle, PCS_REG_ADDR((portn), (reg)), (val))
298 NXGE_REG_WR64(handle, XPCS_ADDR((portn), (reg)), (val))
304 NXGE_REG_WR64(handle, MIF_ADDR((reg)), (val))
330 NXGE_REG_WR64(handle, ESR_ADDR((reg)), (val))
H A Dnpi_espc.c37 NXGE_REG_WR64(handle, ESPC_REG_ADDR(ESPC_PIO_EN_REG), 0x1); in npi_espc_pio_enable()
44 NXGE_REG_WR64(handle, ESPC_REG_ADDR(ESPC_PIO_EN_REG), 0); in npi_espc_pio_disable()
66 NXGE_REG_WR64(handle, ESPC_REG_ADDR(ESPC_PIO_STATUS_REG), val); in npi_espc_eeprom_entry()
78 NXGE_REG_WR64(handle, ESPC_REG_ADDR(ESPC_PIO_STATUS_REG), val); in npi_espc_eeprom_entry()
92 NXGE_REG_WR64(handle, ESPC_REG_ADDR(ESPC_PIO_STATUS_REG), val); in npi_espc_eeprom_entry()
H A Dnpi_txc.h72 NXGE_REG_WR64(handle, \
80 NXGE_REG_WR64(handle, \
H A Dnpi_txdma.c268 NXGE_REG_WR64(handle, TX_ADDR_MD_REG, mode32.value); in npi_txdma_mode32_set()
1616 NXGE_REG_WR64(handle, offset, 0); in npi_txdma_desc_set_zero()
1832 NXGE_REG_WR64(handle, TDMC_INJ_PAR_ERR_REG, 0); in npi_txdma_inj_par_error_clear()
1844 NXGE_REG_WR64(handle, TDMC_INJ_PAR_ERR_REG, inj.value); in npi_txdma_inj_par_error_set()
1857 NXGE_REG_WR64(handle, TDMC_INJ_PAR_ERR_REG, inj.value); in npi_txdma_inj_par_error_update()
1882 NXGE_REG_WR64(handle, TDMC_DBG_SEL_REG, dbg.value); in npi_txdma_dbg_sel_set()
1895 NXGE_REG_WR64(handle, TDMC_TRAINING_REG, vec.value); in npi_txdma_training_vector_set()
H A Dnpi_ipp.h128 NXGE_REG_WR64(handle, IPP_REG_ADDR(portn, reg), val);\
H A Dnpi_txdma.h138 NXGE_REG_WR64(handle, NXGE_TXLOG_OFFSET(reg, channel), data)
/titanic_44/usr/src/uts/common/sys/nxge/
H A Dnxge_common_impl.h335 #define NXGE_REG_WR64(handle, offset, val) {\ macro
345 #define NXGE_REG_WR64(handle, offset, val) {\ macro
350 #define NXGE_REG_WR64(handle, offset, val) {\ macro
H A Dnxge_fflp_hw.h1096 NXGE_REG_WR64((handle), (offset), (value))