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/titanic_41/usr/src/uts/common/io/cpqary3/
H A Dcpqary3.c772 uint32_t regset_index; in cpqary3_update_ctlrdetails() local
803 for (regset_index = 0; regset_index < reglen / 20; regset_index ++) { in cpqary3_update_ctlrdetails()
804 if (PCI_REG_ADDR_G(*(regp + regset_index * 5)) == 0x2) { in cpqary3_update_ctlrdetails()
806 mem_bar0 = regset_index; in cpqary3_update_ctlrdetails()
809 mem_bar1 = regset_index; in cpqary3_update_ctlrdetails()
818 for (regset_index = 0; regset_index < reglen / 20; regset_index ++) { in cpqary3_update_ctlrdetails()
819 if (PCI_REG_ADDR_G(*(regp + regset_index * 5)) == 0x3) { in cpqary3_update_ctlrdetails()
821 mem_64_bar0 = regset_index; in cpqary3_update_ctlrdetails()
824 mem_64_bar1 = regset_index; in cpqary3_update_ctlrdetails()