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/freebsd/sys/arm64/include/
H A Ddb_machdep.h68 #define inst_trap_return(ins) (0) argument
70 #define inst_return(ins) (((ins) & 0xfffffc1fu) == 0xd65f0000)
71 #define inst_call(ins) (((ins) & 0xfc000000u) == 0x94000000u || /* BL */ \ argument
72 ((ins) & 0xfffffc1fu) == 0xd63f0000u) /* BLR */
74 #define inst_load(ins) ({ \
79 #define inst_store(ins) ({ \
84 #define is_load_instr(ins) ((((ins)
65 inst_trap_return(ins) global() argument
67 inst_return(ins) global() argument
76 inst_store(ins) global() argument
81 is_load_instr(ins) global() argument
105 is_store_instr(ins) global() argument
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrConv.td15 defm I32_WRAP_I64 : I<(outs I32:$dst), (ins I64:$src), (outs), (ins),
19 defm I64_EXTEND_S_I32 : I<(outs I64:$dst), (ins I32:$src), (outs), (ins),
23 defm I64_EXTEND_U_I32 : I<(outs I64:$dst), (ins I32:$src), (outs), (ins),
29 defm I32_EXTEND8_S_I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins),
33 defm I32_EXTEND16_S_I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins),
37 defm I64_EXTEND8_S_I64 : I<(outs I64:$dst), (ins I64:$src), (outs), (ins),
41 defm I64_EXTEND16_S_I64 : I<(outs I64:$dst), (ins I64:$src), (outs), (ins),
45 defm I64_EXTEND32_S_I64 : I<(outs I64:$dst), (ins I64:$src), (outs), (ins),
58 defm I32_TRUNC_S_SAT_F32 : I<(outs I32:$dst), (ins F32:$src), (outs), (ins),
63 defm I32_TRUNC_U_SAT_F32 : I<(outs I32:$dst), (ins F32:$src), (outs), (ins),
[all …]
H A DWebAssemblyInstrControl.td16 defm BR_IF : I<(outs), (ins bb_op:$dst, I32:$cond),
17 (outs), (ins bb_op:$dst),
21 defm BR_UNLESS : I<(outs), (ins bb_op:$dst, I32:$cond),
22 (outs), (ins bb_op:$dst), []>;
24 defm BR : NRI<(outs), (ins bb_op:$dst),
50 defm BR_TABLE_I32 : I<(outs), (ins I32:$index, variable_ops),
51 (outs), (ins brlist:$brl),
58 defm BR_TABLE_I64 : I<(outs), (ins I64:$index, variable_ops),
59 (outs), (ins brlist:$brl),
67 defm NOP : NRI<(outs), (ins), [], "nop", 0x01>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430InstrFormats.td32 class MSP430Inst<dag outs, dag ins, int size, string asmstr> : Instruction {
39 dag InOperandList = ins;
47 dag outs, dag ins, string asmstr, list<dag> pattern>
48 : MSP430Inst<outs, ins, size, asmstr> {
64 dag outs, dag ins, string asmstr, list<dag> pattern>
65 : IForm<opcode, dest, 1, src, size, outs, ins, asmstr, pattern>;
68 dag outs, dag ins, string asmstr, list<dag> pattern>
69 : IForm8<opcode, DstReg, SrcReg, 2, outs, ins, asmstr, pattern> {
74 dag outs, dag ins, string asmstr, list<dag> pattern>
75 : IForm8<opcode, DstReg, SrcImm, 4, outs, ins, asmstr, pattern> {
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrSPE.td132 def BRINC : EVXForm_1<527, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
136 def EFDABS : EFXForm_2<740, (outs sperc:$RT), (ins sperc:$RA),
140 def EFDADD : EFXForm_1<736, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
144 def EFDCFS : EFXForm_2a<751, (outs sperc:$RT), (ins spe4rc:$RB),
148 def EFDCFSF : EFXForm_2a<755, (outs sperc:$RT), (ins spe4rc:$RB),
151 def EFDCFSI : EFXForm_2a<753, (outs sperc:$RT), (ins gprc:$RB),
155 def EFDCFSID : EFXForm_2a<739, (outs sperc:$RT), (ins gprc:$RB),
159 def EFDCFUF : EFXForm_2a<754, (outs sperc:$RT), (ins spe4rc:$RB),
162 def EFDCFUI : EFXForm_2a<752, (outs sperc:$RT), (ins gprc:$RB),
166 def EFDCFUID : EFXForm_2a<738, (outs sperc:$RT), (ins gprc:$RB),
[all …]
H A DPPCInstrDFP.td19 defm DADD : XForm_28r<59, 2, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
22 defm DADDQ : XForm_28r<63, 2, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
26 defm DSUB : XForm_28r<59, 514, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
29 defm DSUBQ : XForm_28r<63, 514, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
33 defm DMUL : XForm_28r<59, 34, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
36 defm DMULQ : XForm_28r<63, 34, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
40 defm DDIV : XForm_28r<59, 546, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
43 defm DDIVQ : XForm_28r<63, 546, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
47 def DCMPU : XForm_17<59, 642, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB),
50 def DCMPUQ : XForm_17<63, 642, (outs crrc:$BF), (ins fpairrc:$RA, fpairrc:$RB),
[all …]
/freebsd/sys/amd64/include/
H A Ddb_machdep.h71 #define i_calli(ins) (((ins)&0xff) == I_CALLI && ((ins)&0x3800) == 0x1000) argument
74 #define i_rex(ins) (((ins) & 0xff) == 0x41 || ((ins) & 0xff) == 0x43) argument
76 #define inst_trap_return(ins) (((ins)&0xff) == I_IRET) argument
77 #define inst_return(ins) (((ins)&0xff) == I_RET) argument
78 #define inst_call(ins) (((ins)&0xff) == I_CALL || i_calli(ins) || \ argument
79 (i_calli((ins) >> 8) && i_rex(ins)))
80 #define inst_load(ins) 0 argument
81 #define inst_store(ins) 0 argument
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreInstrFormats.td12 class InstXCore<int sz, dag outs, dag ins, string asmstr, list<dag> pattern>
18 dag InOperandList = ins;
26 class PseudoInstXCore<dag outs, dag ins, string asmstr, list<dag> pattern>
27 : InstXCore<0, outs, ins, asmstr, pattern> {
35 class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
36 : InstXCore<2, outs, ins, asmstr, pattern> {
44 class _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
45 : _F3R<opc, outs, ins, asmstr, pattern> {
49 class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
50 : InstXCore<4, outs, ins, asmstr, pattern> {
[all …]
H A DXCoreInstrInfo.td209 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
212 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
218 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
220 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
226 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
229 def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
235 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
240 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
247 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
250 def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrSystem.td17 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", []>, TB;
20 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
25 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
27 def UD1Wm : I<0xB9, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
29 def UD1Lm : I<0xB9, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
31 def UD1Qm : RI<0xB9, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
34 def UD1Wr : I<0xB9, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
36 def UD1Lr : I<0xB9, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
38 def UD1Qr : RI<0xB9, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
43 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
[all …]
H A DX86InstrControl.td23 def RET32 : I <0xC3, RawFrm, (outs), (ins variable_ops),
25 def RET64 : I <0xC3, RawFrm, (outs), (ins variable_ops),
27 def RET16 : I <0xC3, RawFrm, (outs), (ins),
29 def RETI32 : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
31 def RETI64 : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
33 def RETI16 : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
35 def LRET32 : I <0xCB, RawFrm, (outs), (ins),
37 def LRET64 : RI <0xCB, RawFrm, (outs), (ins),
39 def LRET16 : I <0xCB, RawFrm, (outs), (ins),
41 def LRETI32 : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
[all …]
H A DX86InstrFPStack.td19 def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src),
21 def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src),
23 def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src),
25 def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src),
27 def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src),
29 def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src),
31 def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src),
33 def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src),
35 def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src),
38 def FP80_ADDr : PseudoI<(outs RFP80:$dst), (ins RFP8
[all...]
H A DX86InstrShiftRotate.td348 (ins t.RegClass:$src1, t.RegClass:$src2, u8imm:$src3), m, !if(!eq(ndd, 0), triop_args, triop_ndd_args),
368 : ITy<o, MRMDestMem, t, (outs), (ins t.MemOperand:$src1, t.RegClass:$src2, u8imm:$src3),
390 : ITy<o, MRMDestMem, t, (outs t.RegClass:$dst), (ins t.MemOperand:$src1, t.RegClass:$src2, u8imm:$src3),
511 (ins GR32:$src1, u8imm:$shamt), "",
514 (ins GR64:$src1, u8imm:$shamt), "",
518 (ins GR32:$src1, u8imm:$shamt), "",
521 (ins GR64:$src1, u8imm:$shamt), "",
542 : ITy<0xF0, MRMSrcReg, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1, u8imm:$src2),
547 : ITy<0xF0, MRMSrcMem, t, (outs t.RegClass:$dst), (ins t.MemOperand:$src1, u8imm:$src2),
568 : ITy<0xF7, MRMSrcReg4VOp3, t, (outs t.RegClass:$dst), (ins
[all...]
/freebsd/sys/arm/include/
H A Ddb_machdep.h58 #define inst_trap_return(ins) (0) argument
65 #define inst_return(ins) (((ins) & 0x0e108000) == 0x08108000 || \ argument
66 ((ins) & 0x0ff0fff0) == 0x01a0f000 || \
67 ((ins) & 0x0ffffff0) == 0x012fff10) /* bx */
70 #define inst_call(ins) (((ins) & 0x0f000000) == 0x0b000000) argument
76 #define inst_branch(ins) (((ins) & 0x0f000000) == 0x0a000000 || \ argument
77 ((ins) & 0x0fdffff0) == 0x079ff100 || \
78 ((ins) & 0x0cd0f000) == 0x0490f000 || \
79 ((ins) & 0x0ffffff0) == 0x012fff30 || /* blx */ \
80 ((ins) & 0x0de0f000) == 0x0080f000)
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVInstrInfo.td18 def ASSIGN_TYPE: Pseudo<(outs ANYID:$dst_id), (ins ANYID:$src_id, TYPE:$src_ty)>;
19 def DECL_TYPE: Pseudo<(outs ANYID:$dst_id), (ins ANYID:$src_id, TYPE:$src_ty)>;
20 def GET_ID: Pseudo<(outs ID:$dst_id), (ins ANYID:$src)>;
21 def GET_ID64: Pseudo<(outs ID64:$dst_id), (ins ANYID:$src)>;
22 def GET_fID: Pseudo<(outs fID:$dst_id), (ins ANYID:$src)>;
23 def GET_fID64: Pseudo<(outs fID64:$dst_id), (ins ANYID:$src)>;
24 def GET_pID32: Pseudo<(outs pID32:$dst_id), (ins ANYID:$src)>;
25 def GET_pID64: Pseudo<(outs pID64:$dst_id), (ins ANYID:$src)>;
26 def GET_vID: Pseudo<(outs vID:$dst_id), (ins ANYID:$src)>;
27 def GET_vfID: Pseudo<(outs vfID:$dst_id), (ins ANYID:$src)>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLASXInstrFormats.td21 class Fmt1RI13_XI<bits<32> op, dag outs, dag ins, string opnstr,
23 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
34 class Fmt2R_XX<bits<32> op, dag outs, dag ins, string opnstr,
36 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
46 class Fmt2R_XR<bits<32> op, dag outs, dag ins, string opnstr,
48 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
58 class Fmt2R_CX<bits<32> op, dag outs, dag ins, string opnstr,
60 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
71 class Fmt2RI1_XXI<bits<32> op, dag outs, dag ins, string opnstr,
73 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
[all …]
H A DLoongArchLSXInstrFormats.td21 class Fmt1RI13_VI<bits<32> op, dag outs, dag ins, string opnstr,
23 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
34 class Fmt2R_VV<bits<32> op, dag outs, dag ins, string opnstr,
36 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
46 class Fmt2R_VR<bits<32> op, dag outs, dag ins, string opnstr,
48 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
58 class Fmt2R_CV<bits<32> op, dag outs, dag ins, string opnstr,
60 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
71 class Fmt2RI1_VVI<bits<32> op, dag outs, dag ins, string opnstr,
73 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
[all …]
H A DLoongArchInstrFormats.td19 class LAInst<dag outs, dag ins, string opcstr, string opnstr,
32 let InOperandList = ins;
38 class Pseudo<dag outs, dag ins, list<dag> pattern = [], string opcstr = "",
40 : LAInst<outs, ins, opcstr, opnstr, pattern> {
51 class Fmt2R<bits<32> op, dag outs, dag ins, string opnstr,
53 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
64 class Fmt3R<bits<32> op, dag outs, dag ins, string opnstr,
66 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
79 class Fmt3RI2<bits<32> op, dag outs, dag ins, string opnstr,
81 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
[all …]
/freebsd/sys/riscv/include/
H A Ddb_machdep.h70 #define inst_trap_return(ins) (ins == 0x10000073) /* eret */ argument
71 #define inst_return(ins) (ins == 0x00008067) /* ret */ argument
72 #define inst_call(ins) (((ins) & 0x7f) == 111 || \ argument
73 ((ins) & 0x7f) == 103) /* jal, jalr */
75 #define inst_load(ins) ({ \ argument
80 #define inst_store(ins) ({ \ argument
85 #define is_load_instr(ins) (((ins) & 0x7f) == 3) argument
86 #define is_store_instr(ins) (((ins) & 0x7f) == 35) argument
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrFormats.td9 class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern,
21 dag InOperandList = ins;
36 class F2<dag outs, dag ins, string asmstr, list<dag> pattern,
38 : InstSP<outs, ins, asmstr, pattern, itin> {
48 class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern,
50 : F2<outs, ins, asmstr, pattern, itin> {
58 class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr,
60 : F2<outs, ins, asmstr, pattern, itin> {
69 dag outs, dag ins, string asmstr, list<dag> pattern,
71 : InstSP<outs, ins, asmst
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrFormatsF2.td13 class CSKYInstF2<AddrMode am, dag outs, dag ins, string opcodestr,
15 : CSKY32Inst<am, 0x3d, outs, ins, opcodestr, pattern> {
20 class F2_XYZ<bits<5> datatype, bits<6> sop, string opcodestr, dag outs, dag ins,
22 : CSKYInstF2<AddrModeNone, outs, ins, opcodestr, pattern> {
36 (outs FPR32Op:$vrz), (ins FPR32Op:$vrx, FPR32Op:$vry),
40 (outs FPR64Op:$vrz), (ins FPR64Op:$vrx, FPR64Op:$vry),
47 (outs FPR32Op:$vrz), (ins FPR32Op:$vrZ, FPR32Op:$vrx, FPR32Op:$vry),
51 (outs FPR64Op:$vrz), (ins FPR64Op:$vrZ, FPR64Op:$vrx, FPR64Op:$vry),
58 (outs regtype:$vrz), (ins regtype:$vrx),
63 (outs regtype:$vrz), (ins regtype:$vrx),
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DGenericOpcodes.td46 let InOperandList = (ins type1:$src);
54 let InOperandList = (ins type1:$src);
68 let InOperandList = (ins type0:$src, untyped_imm_0:$sz);
76 let InOperandList = (ins type1:$src);
85 let InOperandList = (ins type1:$src);
91 let InOperandList = (ins);
97 let InOperandList = (ins variable_ops);
103 let InOperandList = (ins unknown:$src2);
109 let InOperandList = (ins unknown:$src);
115 let InOperandList = (ins unknown:$addr, i32imm:$key, type1:$addrdisc, i64imm:$disc);
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrFormats.td14 class AVRInst<dag outs, dag ins, string asmstr, list<dag> pattern>
19 dag InOperandList = ins;
27 class AVRInst16<dag outs, dag ins, string asmstr, list<dag> pattern>
28 : AVRInst<outs, ins, asmstr, pattern> {
35 class AVRInst32<dag outs, dag ins, string asmstr, list<dag> pattern>
36 : AVRInst<outs, ins, asmstr, pattern> {
50 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
51 : AVRInst16<outs, ins, asmstr, pattern> {
66 class FRdRr<bits<4> opcode, bits<2> f, dag outs, dag ins, string asmstr,
67 list<dag> pattern> : AVRInst16<outs, ins, asmst
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrFormats.td12 class XtensaInst<int size, dag outs, dag ins, string asmstr, list<dag> pattern,
20 let InOperandList = ins;
29 class XtensaInst24<dag outs, dag ins, string asmstr, list<dag> pattern,
31 : XtensaInst<3, outs, ins, asmstr, pattern, itin> {
37 class XtensaInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
39 : XtensaInst<2, outs, ins, asmstr, pattern, itin> {
45 class RRR_Inst<bits<4> op0, bits<4> op1, bits<4> op2, dag outs, dag ins,
47 : XtensaInst24<outs, ins, asmstr, pattern, itin> {
60 class RRI4_Inst<bits<4> op0, bits<4> op1, dag outs, dag ins,
62 : XtensaInst24<outs, ins, asmstr, pattern, itin> {
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsC.td13 class RVInst16<dag outs, dag ins, string opcodestr, string argstr,
15 : RVInstCommon<outs, ins, opcodestr, argstr, pattern, format> {
25 class RVInst16CR<bits<4> funct4, bits<2> opcode, dag outs, dag ins,
27 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCR> {
40 class RVInst16CI<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
42 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCI> {
55 class RVInst16CSS<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
57 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCSS> {
67 class RVInst16CIW<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
69 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCIW> {
[all …]

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