Searched +full:xps +full:- +full:uartlite +full:- +full:1 (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause3 ---4 $id: http://devicetree.org/schemas/serial/xlnx,opb-uartlite.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Xilinx Axi Uartlite10 - Peter Korsgaard <jacmet@sunsite.dk>16 - xlnx,xps-uartlite-1.00.a17 - xlnx,opb-uartlite-1.00.b20 maxItems: 123 maxItems: 1[all …]
10 Each IP-core has a set of parameters which the FPGA designer can use to20 properties of the device node. In general, device nodes for IP-cores23 (name): (generic-name)@(base-address) {24 compatible = "xlnx,(ip-core-name)-(HW_VER)"27 interrupt-parent = <&interrupt-controller-phandle>;29 xlnx,(parameter1) = "(string-value)";30 xlnx,(parameter2) = <(int-value)>;33 (generic-name): an open firmware-style name that describes the36 (ip-core-name): the name of the ip block (given after the BEGIN38 and all underscores '_' converted to dashes '-'.[all …]
1 // SPDX-License-Identifier: GPL-2.02 /dts-v1/;5 compatible = "jcore,j2-soc";8 #address-cells = <1>;9 #size-cells = <1>;11 interrupt-parent = <&aic>;14 #address-cells = <1>;15 #size-cells = <0>;21 clock-frequency = <50000000>;22 d-cache-size = <8192>;[all …]