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1 //==- RISCVSchedSyntacoreSCR345.td - SCR3/4/5 Sched Defs -----*- tablegen -*-=//11 // This file covers scheduling models for Syntacore SCR3, SCR4 and SCR514 // * SCR3 rv32imc and rv64imac, overview https://syntacore.com/products/scr319 // SCR3-5 are single-issue in-order processors181 // Unsupported scheduling classes for SCR3-5.275 // SCR3 scheduling model definition
458 def SYNTACORE_SCR3_RV32 : RISCVProcessorModel<"syntacore-scr3-rv32",468 def SYNTACORE_SCR3_RV64 : RISCVProcessorModel<"syntacore-scr3-rv64",
104 db_printf("scr3 = 0x%lx\n", pc->pc_saved_ucr3); in db_show_mdpcpu()
1258 * scratchb register (declared as scr0..scr3) just after the1271 #define HF_REG scr3