| /titanic_52/usr/src/uts/common/io/fibre-channel/fca/qlc/ |
| H A D | ql_isr.c | 95 * Spurious interrupt counter
111 * Interrupt or Kernel context, no mailbox commands allowed.
126 * arg2: interrupt vector.
132 * Interrupt or Kernel context, no mailbox commands allowed.
150 * intvec: interrupt vector.
156 * Interrupt or Kernel context, no mailbox commands allowed.
188 /* Acquire interrupt lock. */ in ql_isr_aif()
272 /* Check for mailbox interrupt. */ in ql_isr_aif()
290 EL(ha, "UNKNOWN interrupt " in ql_isr_aif()
321 /* Clear RISC interrupt */ in ql_isr_aif()
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| /titanic_52/usr/src/man/man9f/ |
| H A D | rwlock.9f | 128 \fBRW_DRIVER\fR. If the lock is used by the interrupt handler, the
129 type-specific argument, \fIarg\fR, should be the interrupt priority returned
131 that arg should be the value of the interrupt priority cast by calling the
132 \fBDDI_INTR_PRI\fR macro. If the lock is not used by any interrupt handler, the
243 These functions can be called from user, interrupt, or kernel context, except
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| /titanic_52/usr/src/uts/sun4/io/px/ |
| H A D | px_var.h | 84 px_ib_t *px_ib_p; /* interrupt block */
115 /* Interrupt types supported by the fabric */
119 kmutex_t px_l23ready_lock; /* used in PME_To_ACK interrupt */
139 #define PX_PMETOACK_RECVD 0x01 /* With PME_To_ACK interrupt */
140 #define PX_PME_TURNOFF_PENDING 0x02 /* With PME_To_ACK interrupt */
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| /titanic_52/usr/src/uts/i86pc/io/apix/ |
| H A D | apix.c | 34 * To understand how the apix module interacts with the interrupt subsystem read
167 apix_intr_ops, /* Advanced DDI Interrupt framework */
204 * Mapping between device interrupt and the allocated vector. Indexed
210 * when interrupt binding policy round robin with affinity is
219 * Maximum number of vectors in a CPU that can be used for interrupt
441 * Setting the 12th bit in the Spurious Interrupt Vector in apix_init_intr()
454 * cause an error interrupt, even if the entry is masked...so in apix_init_intr()
477 /* Enable performance counter overflow interrupt */ in apix_init_intr()
514 /* Enable error interrupt */ in apix_init_intr()
534 /* Enable CMCI interrupt */ in apix_init_intr()
[all...] |
| H A D | apix_irm.c | 48 * number of interrupt vectors that will be made avilable
53 * should be excluded from the global IRM pool of interrupt vectors.
104 * is loaded and APIC interrupt system is initialized.
203 * interrupt allocation requests. in apix_irm_init()
295 * Allocate a FIXED type interrupt. The procedure for this
367 * Free up the FIXED type interrupt.
429 * that CPU. For IRM perspective, the interrupt vectors on this
434 * interrupt vectors for that CPU.
441 /* Interrupt disabling for Suspend/Resume */ in apix_irm_disable_intr()
526 /* Interrupt enablin in apix_irm_enable_intr()
[all...] |
| /titanic_52/usr/src/uts/sun4/os/ |
| H A D | cpu_states.c | 71 * on interrupt stack. We work around this problem by posting a level
72 * 10 soft interrupt and then invoking the "abort_seq_handler" within
73 * that soft interrupt context.
79 * window, and the previous L1-A soft interrupt is still pending, then
84 * abort_seq_msgbuf buffer for processing by the soft interrupt.
156 * If we are on an interrupt stack and/or running at in abort_sequence_enter()
305 * interrupt request to power down, and then exit to the prom monitor. in power_down()
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| /titanic_52/usr/src/uts/common/io/fibre-channel/fca/oce/ |
| H A D | oce_intr.c | 25 * Source file interrupt registration
105 /* allocate interrupt handlers */ in oce_setup_intr()
119 * get the interrupt priority. Assumption is that all handlers have in oce_setup_intr()
176 * helper function to add ISR based on interrupt type
192 "Failed to add interrupt handlers"); in oce_setup_handlers()
296 * command interrupt handler routine added to all vectors
301 * return DDI_INTR_CLAIMED => interrupt was claimed by the ISR
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| /titanic_52/usr/src/uts/sun/sys/scsi/adapters/ |
| H A D | fasreg.h | 67 uint8_t fas_intr; /* R: interrupt status register */
119 * None generate an interrupt, per se, although if you have
121 * register, a CMD_RESET_SCSI will generate an interrupt.
139 #define CMD_EN_RESEL 0x44 /* (no interrupt generated) */
151 #define CMD_SET_ATN 0x1a /* (no interrupt generated) */
152 #define CMD_CLR_ATN 0x1b /* (no interrupt generated) */
158 #define CMD_DISCONNECT 0x27 /* (no interrupt generated) */
176 #define FAS_STAT_IPEND 0x80 /* interrupt pending */
200 * FAS interrupt status register definitions (read only)
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| /titanic_52/usr/src/uts/i86pc/ml/ |
| H A D | syscall_asm.s | 302 * gate (lcall 0x27) _and_ the interrupt gate (int 0x91). For our purposes,
303 * there are two significant differences between an interrupt gate and a call
306 * 1) An interrupt gate runs the handler with interrupts disabled, whereas a
310 * 2) An interrupt gate pushes the contents of the EFLAGS register at the time
311 * of the interrupt onto the stack, whereas a call gate does not.
314 * _both_ a call gate _and_ an interrupt gate, these two differences must be
322 * interrupt gate, we will be clobbering the EFLAGS value that was pushed by
323 * the interrupt gate. This is OK, as the only bit that was changed by the
324 * hardware was the IE (interrupt enable) bit, which for an interrupt gat
[all...] |
| /titanic_52/usr/src/cmd/mdb/common/kmdb/ |
| H A D | kmdb_promif.c | 130 * give the illusion of asynchronous interrupt delivery, this polling is
132 * the *read and *write target ops. When an interrupt check is triggered, we
133 * read through pending input, looking for interrupt characters. If we find
134 * one, we deliver an interrupt immediately.
136 * In a read context, we can deliver the interrupt character directly back to
137 * the termio handler rather than raising an interrupt.
139 * OBP doesn't have an "unget" facility. Any character read for interrupt
142 * going to save characters gathered during interrupt checking. As with
145 * after they undergo interrupt processing.
221 * Interrupt chec
[all...] |
| /titanic_52/usr/src/psm/stand/boot/sparc/common/ |
| H A D | sparcv9_subr.s | 44 * a higher-level interrupt thread that just blocked.
62 * Berkley 4.3 introduced symbolically named interrupt levels
76 * routine can call wakeup. Devices that interrupt from higher
79 * level (via software interrupt) to do the required
140 /* the standard clock interrupt priority */
241 * at any time by an interrupt routine, so we must block interrupts and
|
| /titanic_52/usr/src/man/man4/ |
| H A D | pci.4 | 110 At a high-level interrupt context, you can use the \fBddi_get*\fR and
112 access to configuration space is not allowed when running at a high-interrupt
122 This property consists of a single-integer element array. Valid interrupt
124 derived directly from the contents of the device's configuration-interrupt-pin
127 A driver should use an index value of \fB0\fR when registering its interrupt
128 handler with the DDI interrupt interfaces.
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| /titanic_52/usr/src/grub/grub-0.97/netboot/ |
| H A D | epic100.h | 17 INTSTAT= 4, /* Interrupt Status */
18 INTMASK= 8, /* Interrupt Mask */
53 /* Interrupt register bits. NI means No Interrupt generated */
61 #define INTR_INTR_ACTIVE (0x00010000) /* Interrupt active. NI */
184 #define TD_IAF (0x0004) /* Generate Interrupt after tx */
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| /titanic_52/usr/src/uts/sun4v/io/glvc/ |
| H A D | glvc.c | 62 * For interrupt mode
160 uint8_t intr_mode; /* 1 = polling mode, 2 = interrupt mode */
372 * Trigger soft interrupt to start polling device if in glvc_attach()
501 /* Now enable interrupt bits in the status register */ in glvc_add_intr_handlers()
507 " cannot enable receive interrupt\n", in glvc_add_intr_handlers()
545 * Call the interrupt handle routine to check the register in glvc_soft_intr()
663 * we miss an interrupt or in polling mode. in glvc_read()
695 /* Clear the RECV data interrupt bit on device register */ in glvc_read()
700 /* Set RECV interrupt enable bit so we can receive interrupt */ in glvc_read()
[all...] |
| /titanic_52/usr/src/uts/common/sys/usb/hcd/openhci/ |
| H A D | ohci_hub.h | 76 /* Root hub interrupt pipe handle */
79 /* Current interrupt request pointer */
82 /* Saved original interrupt request pointer */
85 /* Root hub interrupt pipe state and timer-id */
|
| /titanic_52/usr/src/uts/common/sys/ |
| H A D | pic.h | 42 /* Definitions for 8259 Programmable Interrupt Controller */
64 * Interrupt configuration information specific to a particular computer.
76 #define SLAVEBASE 8 /* slave IR0 interrupt number */
85 #define CLOCK_VECTOR 0 /* line at which clock interrupt comes */
|
| /titanic_52/usr/src/boot/sys/boot/fdt/dts/arm/ |
| H A D | exynos5420.dtsi | 50 interrupt-parent = <&GIC>;
89 interrupt-parent = <&GIC>;
98 interrupt-parent = <&GIC>;
107 interrupt-parent = <&GIC>;
|
| /titanic_52/usr/src/uts/common/io/hme/ |
| H A D | hme_mac.h | 112 uint_t intmask; /* Global Interrupt Mask Register */
176 #define HMEG_STATUS_MIF_INTR (1 << 23) /* MIF interrupt */
194 * Global Interrupt Mask register
199 * The MIF interrupt [bit 23] is not maskable here. It should be masked at the
200 * source of the interrupt in the MIF.
202 * Default value of the Global Interrupt Mask register is 0xFF7FFFFF.
230 #define HMEG_MASK_MIF_INTR (1 << 23) /* MIF interrupt */
286 * Bit 10 is used to modify the functionality of the Tx_All interrupt.
287 * If it is 0, Tx_All interrupt is generated after processing the last
290 * If it is 1, Tx_All interrupt i
[all...] |
| /titanic_52/usr/src/uts/common/io/ |
| H A D | power.c | 31 * This driver handles interrupt generated by the power button on
85 * to process power button interrupt, helps in executing platform
155 kmutex_t power_intr_mutex; /* interrupt mutex lock */
156 ddi_iblock_cookie_t soft_iblock_cookie; /* holds interrupt cookie */
157 ddi_iblock_cookie_t high_iblock_cookie; /* holds interrupt cookie */
158 ddi_softintr_t softintr_id; /* soft interrupt id */
361 " interrupt handler."); in power_attach()
382 "interrupt handler."); in power_attach()
428 * Handler for the high-level interrupt.
445 /* Check if power button interrupt i in power_high_intr()
[all...] |
| /titanic_52/usr/src/uts/i86pc/io/pcplusmp/ |
| H A D | apic_timer.c | 86 * resolution (in nanoseconds) for the hardware timer interrupt.
111 * and then determine how many APIC ticks to interrupt at the in apic_timer_init()
156 /* program the local APIC to interrupt at the given frequency */ in apic_timer_init()
259 * requested to generate an interrupt in the past in oneshot_timer_reprogram()
260 * generate an interrupt as soon as possible in oneshot_timer_reprogram()
265 * requested to generate an interrupt at a time in oneshot_timer_reprogram()
349 * generate the interrupt at.
|
| /titanic_52/usr/src/uts/sun4u/opl/io/oplpanel/ |
| H A D | oplpanel.c | 46 #define PNLIE_MASK 0x010 /* interrupt enable/disable */
206 /* enable the interrupt just in case */ in panel_attach()
244 /* setup the interrupt handler */ in panel_attach()
248 cmn_err(CE_WARN, "%s%d: cannot add interrupt handler.", in panel_attach()
258 /* turn on interrupt */ in panel_attach()
296 /* turn off interrupt */ in panel_detach()
360 /* to confirm the validity of the interrupt */ in panel_intr()
|
| /titanic_52/usr/src/uts/sun4u/montecarlo/sys/ |
| H A D | acebus.h | 45 * deal with differences in the interrupt dispatching between the prototypes
46 * and the cheerio ebus. On the prototype boards, all interrupt lines are
47 * tied together. For this case, the nexus driver uses a common interrupt
54 * ebus device interrupt info;
95 /* Interrupt support */
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| /titanic_52/usr/src/man/man3c/ |
| H A D | setjmp.3c | 137 printf("longjumped from interrupt %d\en",SIGINT);
147 printf(" waiting for you to INTERRUPT (cntrl-C) ...\en");
155 case SIGINT: ... /* process for interrupt */
169 When this example is compiled and executed, and the user sends an interrupt
175 longjumped from interrupt
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| /titanic_52/usr/src/uts/common/os/ |
| H A D | ddi_periodic.c | 36 * interrupt levels, or in kernel context.
48 * to either the taskq (for DDI_IPL_0) or to one of the soft interrupt queues
51 * While the taskq (or soft interrupt handler) is handling a particular
95 * each of the soft interrupt request queues (periodic_softint_queue).
130 * This function may be called either from a soft interrupt handler
224 * Initialise the request queue for each soft interrupt level: in ddi_periodic_init()
241 * Initialize the mutex lock used for the soft interrupt request in ddi_periodic_init()
323 * Higher priority periodics are handled by a soft interrupt in periodic_cyclic_handler()
332 * Request the execution of the soft interrupt handler for this in periodic_cyclic_handler()
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| /titanic_52/usr/src/uts/common/sys/usb/hcd/ehci/ |
| H A D | ehci_hub.h | 75 /* Root hub interrupt pipe handle */
78 /* Current interrupt request pointer */
81 /* Saved original interrupt request pointer */
84 /* Root hub interrupt pipe state and timer-id */
|