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/linux/drivers/clk/berlin/
H A Dberlin2-div.c1 // SPDX-License-Identifier: GPL-2.0
5 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
9 #include <linux/clk-provider.h>
16 #include "berlin2-div.h"
23 * +---+
24 * pll0 --------------->| 0 | +---+
25 * +---+ |(B)|--+--------------->| 0 | +---+
26 * pll1.0 -->| 0 | +-->| 1 | | +--------+ |(E)|----->| 0 | +---+
27 * pll1.1 -->| 1 | | +---+ +-->|(C) 1:M |-->| 1 | |(F)|-->|(G)|->
28 * ... -->|(A)|--+ | +--------+ +---+ +-->| 1 | +---+
[all …]
/linux/drivers/clk/sophgo/
H A Dclk-cv18xx-ip.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
11 #include "clk-cv18xx-ip.h"
25 return cv1800_clk_setbit(&gate->common, &gate->gate); in gate_enable()
32 cv1800_clk_clearbit(&gate->common, &gate->gate); in gate_disable()
39 return cv1800_clk_checkbit(&gate->common, &gate->gate); in gate_is_enabled()
51 req->rate = req->best_parent_rate; in gate_determine_rate()
72 /* DIV */
90 struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw); in div_enable() local
92 return cv1800_clk_setbit(&div->common, &div->gate); in div_enable()
[all …]
/linux/drivers/clk/imx/
H A Dclk-divider-gate.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/clk-provider.h>
21 struct clk_divider *div = to_clk_divider(hw); in to_clk_divider_gate() local
23 return container_of(div, struct clk_divider_gate, divider); in to_clk_divider_gate()
29 struct clk_divider *div = to_clk_divider(hw); in clk_divider_gate_recalc_rate_ro() local
32 val = readl(div->reg) >> div->shift; in clk_divider_gate_recalc_rate_ro()
33 val &= clk_div_mask(div->width); in clk_divider_gate_recalc_rate_ro()
37 return divider_recalc_rate(hw, parent_rate, val, div->table, in clk_divider_gate_recalc_rate_ro()
38 div->flags, div->width); in clk_divider_gate_recalc_rate_ro()
45 struct clk_divider *div = to_clk_divider(hw); in clk_divider_gate_recalc_rate() local
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/linux/drivers/clk/x86/
H A Dclk-cgu.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020-2022 MaxLinear, Inc.
8 #include <linux/clk-provider.h>
12 #include "clk-cgu.h"
14 #define GATE_HW_REG_STAT(reg) ((reg) + 0x0) argument
15 #define GATE_HW_REG_EN(reg) ((reg) + 0x4) argument
16 #define GATE_HW_REG_DIS(reg) ((reg) + 0x8) argument
29 if (list->div_flags & CLOCK_FLAG_VAL_INIT) in lgm_clk_register_fixed()
30 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, in lgm_clk_register_fixed()
31 list->div_width, list->div_val); in lgm_clk_register_fixed()
[all …]
/linux/drivers/clk/sunxi/
H A Dclk-sun9i-cpus.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
12 #include <linux/clk-provider.h>
26 #define SUN9I_CPUS_MUX_GET_PARENT(reg) ((reg & SUN9I_CPUS_MUX_MASK) >> \ argument
31 #define SUN9I_CPUS_DIV_GET(reg) ((reg & SUN9I_CPUS_DIV_MASK) >> \ argument
33 #define SUN9I_CPUS_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_DIV_MASK) | \ argument
34 (div << SUN9I_CPUS_DIV_SHIFT))
37 #define SUN9I_CPUS_PLL4_DIV_GET(reg) ((reg & SUN9I_CPUS_PLL4_DIV_MASK) >> \ argument
39 #define SUN9I_CPUS_PLL4_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_PLL4_DIV_MASK) | \ argument
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H A Dclk-sunxi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
35 u8 div; in sun4i_get_pll1_factors() local
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
45 if (req->rate >= 768000000 || req->rate == 42000000 || in sun4i_get_pll1_factors()
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H A Dclk-a10-ve.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2015 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
8 #include <linux/clk-provider.h>
12 #include <linux/reset-controller.h>
24 * sunxi_ve_reset... - reset bit in ve clk registers handling
28 void __iomem *reg; member
40 u32 reg; in sunxi_ve_reset_assert() local
42 spin_lock_irqsave(data->lock, flags); in sunxi_ve_reset_assert()
44 reg = readl(data->reg); in sunxi_ve_reset_assert()
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H A Dclk-sun8i-mbus.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2014 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
9 #include <linux/clk-provider.h>
28 const char *clk_name = node->name; in sun8i_a23_mbus_setup()
30 struct clk_divider *div; in sun8i_a23_mbus_setup() local
34 void __iomem *reg; in sun8i_a23_mbus_setup() local
41 reg = of_io_request_and_map(node, 0, of_node_full_name(node)); in sun8i_a23_mbus_setup()
42 if (IS_ERR(reg)) { in sun8i_a23_mbus_setup()
43 pr_err("Could not get registers for sun8i-mbus-clk\n"); in sun8i_a23_mbus_setup()
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/linux/drivers/clk/mxs/
H A Dclk-div.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
12 * struct clk_div - mxs integer divider clock
15 * @reg: register address
24 void __iomem *reg; member
38 struct clk_div *div = to_clk_div(hw); in clk_div_recalc_rate() local
40 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
46 struct clk_div *div = to_clk_div(hw); in clk_div_determine_rate() local
48 return div->ops->determine_rate(&div->divider.hw, req); in clk_div_determine_rate()
54 struct clk_div *div = to_clk_div(hw); in clk_div_set_rate() local
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H A Dclk-frac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
13 * struct clk_frac - mxs fractional divider clock
15 * @reg: register address
25 void __iomem *reg; member
37 u32 div; in clk_frac_recalc_rate() local
40 div = readl_relaxed(frac->reg) >> frac->shift; in clk_frac_recalc_rate()
41 div &= (1 << frac->width) - 1; in clk_frac_recalc_rate()
43 tmp_rate = (u64)parent_rate * div; in clk_frac_recalc_rate()
44 return tmp_rate >> frac->width; in clk_frac_recalc_rate()
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/linux/drivers/clk/sprd/
H A Ddiv.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
10 #include "div.h"
17 req->rate = divider_round_rate(&cd->common.hw, req->rate, in sprd_div_determine_rate()
18 &req->best_parent_rate, in sprd_div_determine_rate()
19 NULL, cd->div.width, 0); in sprd_div_determine_rate()
25 const struct sprd_div_internal *div, in sprd_div_helper_recalc_rate() argument
29 unsigned int reg; in sprd_div_helper_recalc_rate() local
31 regmap_read(common->regmap, common->reg + div->offset, &reg); in sprd_div_helper_recalc_rate()
32 val = reg >> div->shift; in sprd_div_helper_recalc_rate()
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/linux/drivers/clk/ingenic/
H A Dcgu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2013-2015 Imagination Technologies
11 #include <linux/clk-provider.h>
30 return &clk->cgu->clock_info[clk->idx]; in to_clk_info()
34 * ingenic_cgu_gate_get() - get the value of clock gate register bit
39 * caller must hold cgu->lock.
47 return !!(readl(cgu->base + info->reg) & BIT(info->bit)) in ingenic_cgu_gate_get()
48 ^ info->clear_to_gate; in ingenic_cgu_gate_get()
52 * ingenic_cgu_gate_set() - set the value of clock gate register bit
55 * @val: non-zero to gate a clock, otherwise zero
[all …]
/linux/drivers/clk/tegra/
H A Dclk-divider.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
14 #define pll_out_override(p) (BIT((p->shift - 6)))
15 #define div_mask(d) ((1 << (d->width)) - 1)
16 #define get_mul(d) (1 << d->frac_width)
24 int div; in get_div() local
26 div = div_frac_get(rate, parent_rate, divider->width, in get_div()
27 divider->frac_width, divider->flags); in get_div()
29 if (div < 0) in get_div()
32 return div; in get_div()
[all …]
H A Dclk-tegra20-emc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Based on drivers/clk/tegra/clk-emc.c
7 * Copyright (C) 2019 GRATE-DRIVER project
10 #define pr_fmt(fmt) "tegra-emc-clk: " fmt
13 #include <linux/clk-provider.h>
41 void __iomem *reg; member
58 u32 val, div; in emc_recalc_rate() local
60 val = readl_relaxed(emc->reg); in emc_recalc_rate()
61 div = val & CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK; in emc_recalc_rate()
63 return DIV_ROUND_UP(parent_rate * 2, div + 2); in emc_recalc_rate()
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/linux/drivers/clk/
H A Dclk-highbank.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
9 #include <linux/clk-provider.h>
39 void __iomem *reg; member
46 u32 reg; in clk_pll_prepare() local
48 reg = readl(hbclk->reg); in clk_pll_prepare()
49 reg &= ~HB_PLL_RESET; in clk_pll_prepare()
50 writel(reg, hbclk->reg); in clk_pll_prepare()
52 while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0) in clk_pll_prepare()
54 while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0) in clk_pll_prepare()
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H A Dclk-milbeaut.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
17 #define CLKSEL(n) (((n) - 1) * 4 + M10V_CLKSEL1)
20 #define M10V_PLL1DIV2 "pll1-2"
22 #define M10V_PLL2DIV2 "pll2-2"
24 #define M10V_PLL6DIV2 "pll6-2"
25 #define M10V_PLL6DIV3 "pll6-3"
27 #define M10V_PLL7DIV2 "pll7-2"
28 #define M10V_PLL7DIV5 "pll7-5"
31 #define M10V_PLL10DIV2 "pll10-2"
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H A Dclk-divider.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
10 #include <linux/clk-provider.h>
23 * prepare - clk_prepare only ensures that parents are prepared
24 * enable - clk_enable only ensures that parents are enabled
25 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
26 * parent - fixed parent. No clk_set_parent support
31 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) in clk_div_readl()
32 return ioread32be(divider->reg); in clk_div_readl()
34 return readl(divider->reg); in clk_div_readl()
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/linux/drivers/clk/actions/
H A Dowl-factor.c1 // SPDX-License-Identifier: GPL-2.0+
6 // Author: David Liu <liuwei@actions-semi.com>
11 #include <linux/clk-provider.h>
14 #include "owl-factor.h"
21 for (clkt = table; clkt->div; clkt++) in _get_table_maxval()
22 if (clkt->val > maxval) in _get_table_maxval()
23 maxval = clkt->val; in _get_table_maxval()
28 unsigned int val, unsigned int *mul, unsigned int *div) in _get_table_div_mul() argument
32 for (clkt = table; clkt->div; clkt++) { in _get_table_div_mul()
33 if (clkt->val == val) { in _get_table_div_mul()
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/linux/arch/arm/boot/dts/ti/omap/
H A Dam43xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 sys_clkin_ck: clock-sys-clkin-31@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <31>;
14 reg = <0x0040>;
17 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
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H A Domap54xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
16 #clock-cells = <0>;
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
20 ti,bit-shift = <8>;
21 reg = <0x0108>;
[all …]
H A Dam33xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 sys_clkin_ck: clock-sys-clkin-22@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <22>;
14 reg = <0x0040>;
17 adc_tsc_fck: clock-adc-tsc-fck {
18 #clock-cells = <0>;
19 compatible = "fixed-factor-clock";
[all …]
/linux/drivers/clk/ti/
H A Ddivider.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Tero Kristo <t-kristo@ti.com>
10 #include <linux/clk-provider.h>
26 for (clkt = table; clkt->div; clkt++) in _get_table_div()
27 if (clkt->val == val) in _get_table_div()
28 return clkt->div; in _get_table_div()
38 if (divider->table) { in _setup_mask()
41 for (clkt = divider->table; clkt->div; clkt++) in _setup_mask()
42 if (clkt->val > max_val) in _setup_mask()
43 max_val = clkt->val; in _setup_mask()
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/linux/drivers/clk/hisilicon/
H A Dclkdivider-hi6220.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
19 #define div_mask(width) ((1 << (width)) - 1)
22 * struct hi6220_clk_divider - divider clock for hi6220
24 * @hw: handle between common and hardware-specific interfaces
25 * @reg: register containing divider
29 * @table: the div table that the divider supports
34 void __iomem *reg; member
51 val = readl_relaxed(dclk->reg) >> dclk->shift; in hi6220_clkdiv_recalc_rate()
52 val &= div_mask(dclk->width); in hi6220_clkdiv_recalc_rate()
[all …]
/linux/drivers/clk/xilinx/
H A Dclk-xlnx-clock-wizard.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013 - 2021 Xilinx
14 #include <linux/clk-provider.h>
88 /* Divider limits, from UG572 Table 3-4 for Ultrascale+ */
112 #define div_mask(width) ((1 << (width)) - 1)
125 * struct clk_wzrd - Clock wizard private data structure
148 * struct clk_wzrd_divider - clock divider specific to clk_wzrd
150 * @hw: handle between common and hardware-specific interfaces
156 * @table: array of value/divider pairs, last entry should have div = 0
200 void __iomem *div_addr = divider->base + divider->offset; in clk_wzrd_recalc_rate_ver()
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/linux/drivers/clk/mvebu/
H A Dclk-cpu.c1 // SPDX-License-Identifier: GPL-2.0
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
13 #include <linux/clk-provider.h>
18 #include <linux/mvebu-pmsu.h>
52 u32 reg, div; in clk_cpu_recalc_rate() local
54 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); in clk_cpu_recalc_rate()
55 div = (reg >> (cpuclk->cpu * 8)) & SYS_CTRL_CLK_DIVIDER_MASK; in clk_cpu_recalc_rate()
56 return parent_rate / div; in clk_cpu_recalc_rate()
63 u32 div; in clk_cpu_determine_rate() local
65 div = req->best_parent_rate / req->rate; in clk_cpu_determine_rate()
[all …]

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