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/linux/drivers/clk/
H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
9 #include <linux/clk/clk-conf.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
28 #include "clk.h"
60 struct clk_core *core; member
107 #include <trace/events/clk.h>
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/linux/drivers/clk/renesas/
H A Drzg2l-cpg.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on renesas-cpg-mssr.c
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/clk/renesas.h>
31 #include <linux/reset-controller.h>
36 #include <dt-bindings/clock/renesas-cpg-mssr.h>
38 #include "rzg2l-cpg.h"
78 * struct clk_hw_data - clock hardware data
94 * struct sd_mux_hw_data - SD MUX clock hardware data
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H A Drzv2h-cpg.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on rzg2l-cpg.c
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
27 #include <linux/reset-controller.h>
30 #include <dt-bindings/clock/renesas-cpg-mssr.h>
32 #include "rzv2h-cpg.h"
46 #define CPG_BUS_MSTOP(m) (CPG_BUS_1_MSTOP + ((m) - 1) * 4)
69 * struct rzv2h_cpg_priv - Clock Pulse Generator Private Data
74 * @clks: Array containing all Core and Module Clocks
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H A Drenesas-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
15 #include <linux/clk/renesas.h>
28 #include <linux/reset-controller.h>
32 #include <dt-bindings/clock/renesas-cpg-mssr.h>
34 #include "renesas-cpg-mssr.h"
35 #include "clk-div6.h"
46 * If the registers exist, these are valid for SH-Mobile, R-Mobile,
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H A Dr9a09g077-cpg.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
16 #include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h>
17 #include "renesas-cpg-mssr.h"
74 /* Core Clock Outputs exported to DT */
80 /* Internal Core Clocks */
127 /* Internal Core Clocks */
157 /* Core output clk */
203 static struct clk * __init
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dmcp77.c42 read_div(struct mcp77_clk *clk) in read_div() argument
44 struct nvkm_device *device = clk->base.subdev.device; in read_div()
49 read_pll(struct mcp77_clk *clk, u32 base) in read_pll() argument
51 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
54 u32 ref = nvkm_clk_read(&clk->base, nv_clk_src_href); in read_pll()
83 struct mcp77_clk *clk = mcp77_clk(base); in mcp77_clk_read() local
84 struct nvkm_subdev *subdev = &clk->base.subdev; in mcp77_clk_read()
85 struct nvkm_device *device = subdev->device; in mcp77_clk_read()
91 return device->crystal; in mcp77_clk_read()
95 return nvkm_clk_read(&clk->base, nv_clk_src_href) * 4; in mcp77_clk_read()
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H A Dnv50.c32 read_div(struct nv50_clk *clk) in read_div() argument
34 struct nvkm_device *device = clk->base.subdev.device; in read_div()
35 switch (device->chipset) { in read_div()
52 read_pll_src(struct nv50_clk *clk, u32 base) in read_pll_src() argument
54 struct nvkm_subdev *subdev = &clk->base.subdev; in read_pll_src()
55 struct nvkm_device *device = subdev->device; in read_pll_src()
56 u32 coef, ref = nvkm_clk_read(&clk->base, nv_clk_src_crystal); in read_pll_src()
60 switch (device->chipset) { in read_pll_src()
103 case 1: return nvkm_clk_read(&clk->base, nv_clk_src_crystal); in read_pll_src()
104 case 2: return nvkm_clk_read(&clk->base, nv_clk_src_href); in read_pll_src()
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/linux/drivers/clk/microchip/
H A Dclk-pic32mzda.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/clock/microchip,pic32-clock.h>
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
17 #include "clk-core.h"
81 .slew_div = 2, /* step of div_4 -> div_2 -> no_div */
128 struct clk *clks[MAXCLKS];
129 struct pic32_clk_common core; member
142 if (readl(cd->core.iobase) & BIT(2)) in pic32_fscm_nmi()
143 pr_alert("pic32-clk: FSCM detected clk failure.\n"); in pic32_fscm_nmi()
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H A Dclk-core.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
12 #include <asm/mach-pic32/pic32.h>
15 #include "clk-core.h"
78 /* add instruction pipeline delay while CPU clock is in-transition. */
92 struct pic32_clk_common *core; member
101 return readl(pb->ctrl_reg) & PB_DIV_ENABLE; in pbclk_is_enabled()
108 writel(PB_DIV_ENABLE, PIC32_SET(pb->ctrl_reg)); in pbclk_enable()
116 writel(PB_DIV_ENABLE, PIC32_CLR(pb->ctrl_reg)); in pbclk_disable()
137 if (abs(rate - divided_rate_down) < abs(rate - divided_rate)) in calc_best_divided_rate()
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H A Dclk-core.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
65 struct clk *pic32_periph_clk_register(const struct pic32_periph_clk_data *data,
66 struct pic32_clk_common *core);
67 struct clk *pic32_refo_clk_register(const struct pic32_ref_osc_data *data,
68 struct pic32_clk_common *core);
69 struct clk *pic32_sys_clk_register(const struct pic32_sys_clk_data *data,
70 struct pic32_clk_common *core);
71 struct clk *pic32_spll_clk_register(const struct pic32_sys_pll_data *data,
72 struct pic32_clk_common *core);
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/linux/include/trace/events/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 #define TRACE_SYSTEM clk
15 DECLARE_EVENT_CLASS(clk,
17 TP_PROTO(struct clk_core *core),
19 TP_ARGS(core),
22 __string( name, core
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/linux/drivers/net/ipa/
H A Dipa_power.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2018-2024 Linaro Ltd.
7 #include <linux/clk.h>
25 * The IPA hardware is enabled when the IPA core clock and all the
27 * management is used to determine whether the core clock and
31 * The core clock currently runs at a fixed clock rate when enabled,
38 * struct ipa_power - IPA power management information
40 * @core: IPA core clock
47 struct clk *core; member
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/linux/rust/kernel/
H A Dclk.rs1 // SPDX-License-Identifier: GPL-2.0
5 //! C header: [`include/linux/clk.h`](srctree/include/linux/clk.h)
7 //! Reference: <https://docs.kernel.org/driver-api/clk.html>
18 /// use kernel::clk::Hertz;
38 pub const fn from_khz(khz: c_ulong) -> Self { in from_khz()
43 pub const fn from_mhz(mhz: c_ulong) -> Self { in from_mhz()
48 pub const fn from_ghz(ghz: c_ulong) -> Self { in from_ghz()
53 pub const fn as_hz(&self) -> c_ulong { in as_hz()
58 pub const fn as_khz(&self) -> c_ulong { in as_khz()
63 pub const fn as_mhz(&self) -> c_ulong { in as_mhz()
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/linux/arch/arm/mach-omap2/
H A Domap_hwmod_2xxx_interconnect_data.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx
5 * Copyright (C) 2009-2011 Nokia Corporation
9 * XXX these should be marked initdata for multi-OMAP kernels
23 /* L3 -> L4_CORE interface */
30 /* MPU -> L3 interface */
37 /* DSS -> l3 */
50 /* L4_CORE -> L4_WKUP interface */
57 /* L4 CORE -> UART1 interface */
61 .clk = "uart1_ick",
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H A Domap_hwmod_3xxx_data.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
5 * Copyright (C) 2009-2011 Nokia Corporation
12 * XXX these should be marked initdata for multi-OMAP kernels
15 #include <linux/platform_data/i2c-omap.h>
17 #include <linux/platform_data/hsmmc-omap.h>
25 #include "prm-regbits-34xx.h"
26 #include "cm-regbits-34xx.h"
36 * is driver-specific or driver-kernel integration-specific belongs
54 /* L4 CORE */
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/linux/drivers/remoteproc/
H A Dst_slim_rproc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * SLIM core rproc driver
10 #include <linux/clk.h>
20 /* SLIM core registers */
59 int clk, err; in slim_clk_get() local
61 for (clk = 0; clk < ST_SLIM_MAX_CLK; clk++) { in slim_clk_get()
62 slim_rproc->clks[clk] = of_clk_get(dev->of_node, clk); in slim_clk_get()
63 if (IS_ERR(slim_rproc->clks[clk])) { in slim_clk_get()
64 err = PTR_ERR(slim_rproc->clks[clk]); in slim_clk_get()
65 if (err == -EPROBE_DEFER) in slim_clk_get()
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/linux/drivers/clk/stm32/
H A DMakefile1 obj-$(CONFIG_COMMON_CLK_STM32MP135) += clk-stm32mp13.o clk-stm32-core.o reset-stm32.o
2 obj-$(CONFIG_COMMON_CLK_STM32MP157) += clk-stm32mp1.o reset-stm32.o
3 obj-$(CONFIG_COMMON_CLK_STM32MP215) += clk-stm32mp21.o clk-stm32-core.o reset-stm32.o
4 obj-$(CONFIG_COMMON_CLK_STM32MP257) += clk-stm32mp25.o clk-stm32-core.o reset-stm32.o
/linux/drivers/clk/versatile/
H A Dclk-versatile.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 #include "clk-icst.h"
20 /* Base offset for the core module */
59 struct clk *clk; in cm_osc_setup() local
60 const char *clk_name = np->name; in cm_osc_setup()
64 /* Remap the core module base if not done yet */ in cm_osc_setup()
69 pr_err("no parent on core module clock\n"); in cm_osc_setup()
75 pr_err("could not remap core module base\n"); in cm_osc_setup()
81 clk = icst_clk_register(NULL, desc, clk_name, parent_name, cm_base); in cm_osc_setup()
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/linux/Documentation/devicetree/bindings/sound/
H A Dfsl,rpmsg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
14 are SAI, MICFIL, DMA controlled by Cortex M core. What we see from
18 Cortex-A and Cortex-M.
21 - $ref: sound-card-common.yaml#
26 - fsl,imx7ulp-rpmsg-audio
27 - fsl,imx8mn-rpmsg-audio
28 - fsl,imx8mm-rpmsg-audio
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H A Dqcom,lpass-cpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,lpass-cpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
11 - Rohit kumar <quic_rohkumar@quicinc.com>
14 Qualcomm Technologies Inc. SOC Low-Power Audio SubSystem (LPASS) that consist
16 is a module to configure Low-Power Audio Interface(LPAIF) core registers
22 - qcom,lpass-cpu
23 - qcom,apq8016-lpass-cpu
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/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx8mm-disp-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MM DISP blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to
20 - const: fsl,imx8mm-disp-blk-ctrl
21 - const: syscon
26 '#power-domain-cells':
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/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2044.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/clock/sophgo,sg2044-pll.h>
7 #include <dt-bindings/clock/sophgo,sg2044-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/pinctrl-sg2044.h>
12 #include "sg2044-cpus.dtsi"
13 #include "sg2044-reset.h"
24 compatible = "fixed-clock";
25 clock-output-names = "osc";
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/linux/drivers/clk/ti/
H A Ddpll3xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP3/4 - specific DPLL control functions
5 * Copyright (C) 2009-2010 Texas Instruments, Inc.
6 * Copyright (C) 2009-2010 Nokia Corporation
23 #include <linux/clk.h>
27 #include <linux/clk/ti.h>
40 static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
41 static void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
42 static void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
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/linux/drivers/mmc/host/
H A Dsdhci-bcm-kona.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk.h>
14 #include <linux/mmc/slot-gpio.h>
16 #include "sdhci-pltfm.h"
52 /* This timeout should be sufficent for core to reset */ in sdhci_bcm_kona_sd_reset()
63 return -EFAULT; in sdhci_bcm_kona_sd_reset()
72 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS) in sdhci_bcm_kona_sd_reset()
73 * Back-to-Back writes to same register needs delay when SD bus clock in sdhci_bcm_kona_sd_reset()
74 * is very low w.r.t AHB clock, mainly during boot-time and during card in sdhci_bcm_kona_sd_reset()
75 * insert-removal. in sdhci_bcm_kona_sd_reset()
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/linux/drivers/mfd/
H A Dsec-common.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Samsung SxM core driver
14 #include <linux/mfd/core.h>
15 #include <linux/mfd/samsung/core.h>
24 #include "sec-core.h"
27 MFD_CELL_NAME("s5m8767-pmic"),
28 MFD_CELL_NAME("s5m-rtc"),
29 MFD_CELL_OF("s5m8767-clk", NULL, NULL, 0, 0, "samsung,s5m8767-clk"),
33 MFD_CELL_NAME("s2dos05-regulator"),
37 MFD_CELL_NAME("s2mpg10-meter"),
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