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Searched +full:cfgr +full:- +full:clk (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/pwm/
H A Dpwm-stm32-lp.c1 // SPDX-License-Identifier: GPL-2.0
3 * STM32 Low-Power Timer PWM driver
9 * Inspired by Gerald Baeza's pwm-stm32 driver
13 #include <linux/mfd/stm32-lptimer.h>
21 struct clk *clk; member
31 /* STM32 Low-Power Timer is preceded by a configurable power-of-2 prescaler */
41 if (!priv->num_cc_chans) in stm32_pwm_lp_update_allowed()
44 ret = regmap_read(priv->regmap, STM32_LPTIM_CCMR1, &ccmr1); in stm32_pwm_lp_update_allowed()
71 if (!priv->num_cc_chans) in stm32_pwm_lp_compare_channel_apply()
74 ret = regmap_read(priv->regmap, STM32_LPTIM_CCMR1, &ccmr1); in stm32_pwm_lp_compare_channel_apply()
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/linux/drivers/mmc/host/
H A Dmmci_stm32_sdmmc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
8 #include <linux/dma-mapping.h>
84 struct sdmmc_idma *idma = host->dma_priv; in sdmmc_idma_validate_data()
85 struct device *dev = mmc_dev(host->mmc); in sdmmc_idma_validate_data()
93 idma->use_bounce_buffer = false; in sdmmc_idma_validate_data()
94 for_each_sg(data->sg, sg, data->sg_len - 1, i) { in sdmmc_idma_validate_data()
95 if (!IS_ALIGNED(sg->offset, sizeof(u32)) || in sdmmc_idma_validate_data()
96 !IS_ALIGNED(sg->length, in sdmmc_idma_validate_data()
97 host->variant->stm32_idmabsize_align)) { in sdmmc_idma_validate_data()
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/linux/drivers/rtc/
H A Drtc-stm32.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
18 #include <linux/pinctrl/pinconf-generic.h>
146 u16 cfgr; member
172 struct clk *pclk;
173 struct clk *rtc_ck;
176 struct clk *clk_lsco;
189 const struct stm32_rtc_registers *regs = &rtc->data->regs; in stm32_rtc_wpr_unlock()
191 writel_relaxed(RTC_WPR_1ST_KEY, rtc->base + regs->wpr); in stm32_rtc_wpr_unlock()
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/linux/drivers/memory/
H A Dstm32-fmc2-ebi.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk.h>
195 struct clk *clk; member
206 u32 cfgr; member
210 * struct stm32_fmc2_prop - STM32 FMC2 EBI property
248 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_mux()
255 return -EINVAL; in stm32_fmc2_ebi_check_mux()
265 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_waitcfg()
272 return -EINVAL; in stm32_fmc2_ebi_check_waitcfg()
282 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_sync_trans()
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/linux/sound/soc/stm/
H A Dstm32_i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
136 #define I2S_CGFR_I2SDIV_MAX ((1 << (I2S_CGFR_I2SDIV_BIT_H -\
137 I2S_CGFR_I2SDIV_SHIFT)) - 1)
198 #define STM32_I2S_IS_MASTER(x) ((x)->ms_flg == I2S_MS_MASTER)
199 #define STM32_I2S_IS_SLAVE(x) ((x)->ms_flg == I2S_MS_SLAVE)
208 * struct stm32_i2s_data - private data of I2S
244 struct clk *i2sclk;
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/linux/arch/arc/boot/dts/
H A Dhsdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h>
18 #address-cells = <2>;
19 #size-cells = <2>;
22 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
30 #address-cells = <1>;
31 #size-cells = <0>;
62 input_clk: input-clk {
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/linux/arch/riscv/boot/dts/sophgo/
H A Dcv180x.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/clock/sophgo,cv1800.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include "cv18xx-reset.h"
13 #address-cells = <1>;
14 #size-cells = <1>;
17 compatible = "fixed-clock";
18 clock-output-names = "osc_25m";
19 #clock-cells = <0>;
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H A Dsg2044.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/clock/sophgo,sg2044-pll.h>
7 #include <dt-bindings/clock/sophgo,sg2044-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/pinctrl-sg2044.h>
12 #include "sg2044-cpus.dtsi"
13 #include "sg2044-reset.h"
24 compatible = "fixed-clock";
25 clock-output-names = "osc";
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/linux/arch/riscv/boot/dts/canaan/
H A Dk210.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
6 #include <dt-bindings/clock/k210-clk.h>
7 #include <dt-bindings/pinctrl/k210-fpioa.h>
8 #include <dt-bindings/reset/k210-rst.h>
12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
15 #address-cells = <1>;
16 #size-cells = <1>;
17 compatible = "canaan,kendryte-k210";
21 * Since this is a non-ratified draft specification, the kernel does not
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/linux/sound/soc/atmel/
H A Dmchp-pdmc.c1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (C) 2019-2022 Microchip Technology Inc. and its subsidiaries
9 #include <dt-bindings/sound/microchip,pdmc.h>
12 #include <linux/clk.h>
24 * ---- PDMC Register map ----
37 * ---- Control Register (Write-only) ----
42 * ---- Mode Register (Read/Write) ----
66 * ---- Configuration Register (Read/Write) ----
75 * ---- Interrupt Enable/Disable/Mask/Status Registers ----
85 * ---- Version Register (Read-only) ----
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/linux/drivers/net/ethernet/freescale/
H A Dfec_main.c1 // SPDX-License-Identifier: GPL-2.0+
17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
20 * Copyright (c) 2004-2006 Macq Electronique SA.
22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
29 #include <linux/clk.h>
194 { .compatible = "fsl,imx25-fec", .data = &fec_imx25_info, },
195 { .compatible = "fsl,imx27-fec", .data = &fec_imx27_info, },
196 { .compatible = "fsl,imx28-fec", .data = &fec_imx28_info, },
197 { .compatible = "fsl,imx6q-fec", .data = &fec_imx6q_info, },
198 { .compatible = "fsl,mvf600-fec", .data = &fec_mvf600_info, },
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