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/linux/Documentation/devicetree/bindings/clock/
H A Dbrcm,iproc-clocks.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/brcm,iproc-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ray Jui <rjui@broadcom.com>
11 - Scott Branden <sbranden@broadcom.com>
25 - brcm,bcm63138-armpll
26 - brcm,cygnus-armpll
27 - brcm,cygnus-genpll
28 - brcm,cygnus-lcpll0
[all …]
/linux/Documentation/devicetree/bindings/spi/
H A Dbrcm,spi-bcm-qspi.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kamal Dasu <kdasu.kdev@gmail.com>
11 - Rafał Miłecki <rafal@milecki.pl>
15 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consists
20 io with 3-byte and 4-byte addressing support.
28 - $ref: spi-controller.yaml#
33 - description: Second Instance of MSPI BRCMSTB SoCs
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-nsp.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-nsp.h>
38 #address-cells = <1>;
39 #size-cells = <1>;
40 compatible = "brcm,nsp";
42 interrupt-parent = <&gic>;
53 #address-cells = <1>;
54 #size-cells = <0>;
58 compatible = "arm,cortex-a9";
[all …]
H A Dbcm5301x.dtsi9 #include "bcm-ns.dtsi"
12 mpcore-bus@19000000 {
14 #clock-cells = <0>;
15 compatible = "brcm,nsp-armpll";
21 compatible = "arm,cortex-a9-twd-wdt";
30 #address-cells = <1>;
31 #size-cells = <1>;
35 #clock-cells = <0>;
36 compatible = "fixed-clock";
37 clock-frequency = <25000000>;
[all …]
H A Dbcm958625-meraki-mx64-a0.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
5 * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
8 /dts-v1/;
10 #include "bcm958625-meraki-kingpin.dtsi"
11 #include "bcm-nsp-ax.dtsi"
15 compatible = "meraki,mx64-a0", "brcm,bcm58625", "brcm,nsp";
18 stdout-path = "serial0:115200n8";
H A Dbcm958625-meraki-mx64w-a0.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
5 * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
8 /dts-v1/;
10 #include "bcm958625-meraki-kingpin.dtsi"
11 #include "bcm-nsp-ax.dtsi"
15 compatible = "meraki,mx64w-a0", "brcm,bcm58625", "brcm,nsp";
18 stdout-path = "serial0:115200n8";
H A Dbcm4708.dtsi5 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
20 stdout-path = "serial0:115200n8";
24 #address-cells = <1>;
25 #size-cells = <0>;
26 enable-method = "brcm,bcm-nsp-smp";
30 compatible = "arm,cortex-a9";
31 next-level-cache = <&L2>;
37 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
39 secondary-boot-reg = <0xffff0400>;
H A Dbcm-hr2.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
39 interrupt-parent = <&gic>;
40 #address-cells = <1>;
41 #size-cells = <1>;
44 #address-cells = <1>;
45 #size-cells = <0>;
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
56 compatible = "arm,cortex-a9-pmu";
[all …]
H A Dbcm958625-meraki-mx6x-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
5 * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
8 #include "bcm-nsp.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
14 pwm-leds {
15 compatible = "pwm-leds";
17 led-1 {
21 max-brightness = <255>;
[all …]
H A Dbcm-ns.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
6 #include <dt-bindings/clock/bcm-nsp.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
[all …]
/linux/Documentation/devicetree/bindings/arm/bcm/
H A Dbrcm,nsp.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/bcm/brcm,nsp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash,
18 - Ray Jui <rjui@broadcom.com>
19 - Scott Branden <sbranden@broadcom.com>
26 - description: BCM58522 based boards
28 - enum:
29 - brcm,bcm958522er
[all …]
/linux/Documentation/devicetree/bindings/rng/
H A Dbrcm,bcm2835.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stefan Wahren <stefan.wahren@i2se.com>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Herbert Xu <herbert@gondor.apana.org.au>
17 - brcm,bcm2835-rng
18 - brcm,bcm-nsp-rng
19 - brcm,bcm5301x-rng
20 - brcm,bcm6368-rng
[all …]
/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,x1e80100-rpmh.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,x1e80100-rpmh.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on X1E80100
10 - Rajendra Nayak <quic_rjendra@quicinc.com>
11 - Abel Vesa <abel.vesa@linaro.org>
15 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
16 able to communicate with the BCM through the Resource State Coordinator (RSC)
21 See also: include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h
[all …]
H A Dqcom,sc7280-rpmh.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,sc7280-rpmh.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SC7280
10 - Bjorn Andersson <andersson@kernel.org>
11 - Konrad Dybcio <konradybcio@kernel.org>
15 RPMh hardware accelerators known as Bus Clock Manager (BCM).
17 See also: include/dt-bindings/interconnect/qcom,sc7280.h
22 - qcom,sc7280-aggre1-noc
[all …]
H A Dqcom,sar2130p-rpmh.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,sar2130p-rpmh.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SAR2130P
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11 - Georgi Djakov <djakov@kernel.org>
15 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
16 able to communicate with the BCM through the Resource State Coordinator (RSC)
21 See also: include/dt-bindings/interconnect/qcom,sar2130p-rpmh.h
[all …]
H A Dqcom,milos-rpmh.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,milos-rpmh.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on Milos SoC
10 - Luca Weiss <luca.weiss@fairphone.com>
14 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
15 able to communicate with the BCM through the Resource State Coordinator (RSC)
20 See also: include/dt-bindings/interconnect/qcom,milos-rpmh.h
25 - qcom,milos-aggre1-noc
[all …]
H A Dqcom,sm8550-rpmh.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,sm8550-rpmh.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SM8550
10 - Abel Vesa <abel.vesa@linaro.org>
11 - Neil Armstrong <neil.armstrong@linaro.org>
15 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
16 able to communicate with the BCM through the Resource State Coordinator (RSC)
21 See also: include/dt-bindings/interconnect/qcom,sm8550-rpmh.h
[all …]
H A Dqcom,sm8750-rpmh.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,sm8750-rpmh.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SM8750
10 - Abel Vesa <abel.vesa@linaro.org>
11 - Neil Armstrong <neil.armstrong@linaro.org>
15 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
16 able to communicate with the BCM through the Resource State Coordinator (RSC)
21 See also: include/dt-bindings/interconnect/qcom,sm8750-rpmh.h
[all …]
H A Dqcom,sm8650-rpmh.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,sm8650-rpmh.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SM8650
10 - Abel Vesa <abel.vesa@linaro.org>
11 - Neil Armstrong <neil.armstrong@linaro.org>
15 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
16 able to communicate with the BCM through the Resource State Coordinator (RSC)
21 See also: include/dt-bindings/interconnect/qcom,sm8650-rpmh.h
[all …]
H A Dqcom,sm8450-rpmh.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,sm8450-rpmh.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SM8450
10 - Bjorn Andersson <andersson@kernel.org>
11 - Konrad Dybcio <konradybcio@kernel.org>
15 RPMh hardware accelerators known as Bus Clock Manager (BCM).
17 See also: include/dt-bindings/interconnect/qcom,sm8450.h
22 - qcom,sm8450-aggre1-noc
[all …]
/linux/drivers/clk/bcm/
H A Dclk-nsp.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-nsp.h>
12 #include "clk-iproc.h"
33 CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-armpll", nsp_armpll_init);
90 CLK_OF_DECLARE(nsp_genpll_clk, "brcm,nsp-genpll", nsp_genpll_clk_init);
129 CLK_OF_DECLARE(nsp_lcpll0_clk, "brcm,nsp-lcpll0", nsp_lcpll0_clk_init);
/linux/Documentation/devicetree/bindings/ata/
H A Dbrcm,sata-brcm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/brcm,sata-brcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 SATA nodes are defined to describe on-chip Serial ATA controllers.
14 - Florian Fainelli <f.fainelli@gmail.com>
17 - $ref: ahci-common.yaml#
22 - items:
23 - enum:
24 - brcm,bcm7216-ahci
[all …]
/linux/drivers/char/hw_random/
H A Dbcm2835-rng.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2010-2012 Broadcom. All rights reserved.
46 * peripheral registers for CPU-native byte order. in rng_readl()
49 return __raw_readl(priv->base + offset); in rng_readl()
51 return readl(priv->base + offset); in rng_readl()
58 __raw_writel(val, priv->base + offset); in rng_writel()
60 writel(val, priv->base + offset); in rng_writel()
92 ret = clk_prepare_enable(priv->clk); in bcm2835_rng_init()
96 ret = reset_control_reset(priv->reset); in bcm2835_rng_init()
98 clk_disable_unprepare(priv->clk); in bcm2835_rng_init()
[all …]
/linux/arch/arm/mach-bcm/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014-2015 Broadcom Corporation
12 #include <linux/irqchip/irq-bcm2836.h>
34 #define OF_SECONDARY_BOOT "secondary-boot-reg"
54 return -ENXIO; in scu_a9_enable()
61 return -ENOENT; in scu_a9_enable()
68 return -ENOMEM; in scu_a9_enable()
106 return -EINVAL; in nsp_write_lut()
111 pr_warn("unable to ioremap SKU-ROM LUT register for cpu %u\n", cpu); in nsp_write_lut()
112 return -ENOMEM; in nsp_write_lut()
[all …]
/linux/drivers/ata/
H A Dahci_brcm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright © 2009-2015 Broadcom Corporation
24 #define DRV_NAME "brcm-ahci"
28 #define MMIO_ENDIAN_SHIFT 0 /* CPU->AHCI */
29 #define DMADESC_ENDIAN_SHIFT 2 /* AHCI->DDR */
30 #define DMADATA_ENDIAN_SHIFT 4 /* AHCI->DDR */
51 /* On big-endian MIPS, buses are reversed to big endian, so switch them back */
53 #define DATA_ENDIAN 2 /* AHCI->DDR inbound accesses */
54 #define MMIO_ENDIAN 2 /* CPU->AHCI outbound accesses */
97 * bus endianness (i.e., big-endian CPU + big endian bus ==> native in brcm_sata_readreg()
[all …]

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