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/linux/drivers/tty/
H A Dnozomi.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * nozomi.c -- HSDPA driver Broadband Wireless Data Card - Globe Trotter
18 * --------------------------------------------------------------------------
25 * --------------------------------------------------------------------------
132 F32_2 = 2048, /* 512 bytes downlink + uplink * 2 -> 2048 */
133 F32_8 = 8192, /* 3072 bytes downl. + 1024 bytes uplink * 2 -> 8192 */
157 CTRL_ERROR = -1,
167 PORT_ERROR = -1,
176 * else A-channels must always be used.
246 * else A-channels must always be used.
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/linux/drivers/md/
H A Ddm-delay.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2005-2007 Red Hat GmbH
19 #include <linux/device-mapper.h>
59 struct delay_c *dc = timer_container_of(dc, t, delay_timer); in handle_delayed_timer() local
61 queue_work(dc->kdelayd_wq, &dc->flush_expired_bios); in handle_delayed_timer()
64 static void queue_timeout(struct delay_c *dc, unsigned long expires) in queue_timeout() argument
66 timer_reduce(&dc->delay_timer, expires); in queue_timeout()
69 static inline bool delay_is_fast(struct delay_c *dc) in delay_is_fast() argument
71 return !!dc->worker; in delay_is_fast()
79 n = bio->bi_next; in flush_bios()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.h1 // SPDX-License-Identifier: MIT
9 #include "dc.h"
14 struct dc;
36 void dcn401_init_hw(struct dc *dc);
40 bool dcn401_set_output_transfer_func(struct dc *dc,
43 void dcn401_trigger_3dlut_dma_load(struct dc *dc,
50 struct dc *dc);
52 void dcn401_populate_mcm_luts(struct dc *dc,
64 bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable);
66 void dcn401_wait_for_dcc_meta_propagation(const struct dc *dc,
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c1 /* SPDX-License-Identifier: MIT */
65 hws->ctx
67 hws->regs->reg
74 hws->shifts->field_name, hws->masks->field_name
76 static void enable_memory_low_power(struct dc *dc)
78 struct dce_hwseq *hws = dc->hwseq;
81 if (dc->debug.enable_mem_low_power.bits.dmcu) {
83 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
89 if (dc->debug.enable_mem_low_power.bits.optc) {
94 if (dc->debug.enable_mem_low_power.bits.vga) {
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H A Ddcn35_hwseq.h1 /* SPDX-License-Identifier: MIT */
32 struct dc;
34 void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
48 void dcn35_init_hw(struct dc *dc);
54 void dcn35_power_down_on_boot(struct dc *dc);
56 bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable);
58 void dcn35_z10_restore(const struct dc *dc);
60 void dcn35_init_pipes(struct dc *dc, struct dc_state *context);
61 void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);
62 void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,
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/linux/drivers/scsi/esas2r/
H A Desas2r_disc.c5 * Copyright (c) 2001-2013 ATTO Technology, Inc.
8 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
22 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
41 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
43 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
85 struct esas2r_sas_nvram *nvr = a->nvram; in esas2r_disc_initialize()
89 clear_bit(AF_DISC_IN_PROG, &a->flags); in esas2r_disc_initialize()
90 clear_bit(AF2_DEV_SCAN, &a->flags2); in esas2r_disc_initialize()
91 clear_bit(AF2_DEV_CNT_OK, &a->flags2); in esas2r_disc_initialize()
93 a->disc_start_time = jiffies_to_msecs(jiffies); in esas2r_disc_initialize()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c66 hws->ctx
68 hws->regs->reg
72 hws->shifts->field_name, hws->masks->field_name
74 void dcn20_log_color_state(struct dc *dc, in dcn20_log_color_state() argument
77 struct dc_context *dc_ctx = dc->ctx; in dcn20_log_color_state()
78 struct resource_pool *pool = dc->res_pool; in dcn20_log_color_state()
88 for (i = 0; i < pool->pipe_count; i++) { in dcn20_log_color_state()
89 struct dpp *dpp = pool->dpps[i]; in dcn20_log_color_state()
92 dpp->funcs->dpp_read_state(dpp, &s); in dcn20_log_color_state()
93 if (dpp->funcs->dpp_get_gamut_remap) { in dcn20_log_color_state()
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/linux/drivers/clk/mvebu/
H A Ddove-divider.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
15 #include "dove-divider.h"
51 static unsigned int dove_get_divider(struct dove_clk *dc) in dove_get_divider() argument
56 val = readl_relaxed(dc->base + DIV_CTRL0); in dove_get_divider()
57 val >>= dc->div_bit_start; in dove_get_divider()
59 divider = val & ~(~0 << dc->div_bit_size); in dove_get_divider()
61 if (dc->divider_table) in dove_get_divider()
62 divider = dc->divider_table[divider]; in dove_get_divider()
67 static int dove_calc_divider(const struct dove_clk *dc, unsigned long rate, in dove_calc_divider() argument
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/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc.h2 * Copyright 2012-2023 Advanced Micro Devices, Inc.
61 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC
65 * MAX_PLANES - representative of the upper bound of planes that are supported by the HW
118 // for example, 1080p -> 8K is 4.0, or 4000 raw value
126 // for example, 8K -> 1080p is 0.25, or 250 raw value
138 * DOC: color-management-caps
143 * abstracted HW. DCE 5-12 had almost no important changes, but starting with
150 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
166 * struct dpp_color_caps - color pipeline capabilities for display pipe and
171 * just plain 256-entry lookup
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource_helpers.c40 struct dc *dc, in dcn32_helper_calculate_mall_bytes_for_cursor() argument
44 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn32_helper_calculate_mall_bytes_for_cursor()
45 uint32_t cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height; in dcn32_helper_calculate_mall_bytes_for_cursor()
48 switch (pipe_ctx->stream->cursor_attributes.color_format) { in dcn32_helper_calculate_mall_bytes_for_cursor()
67 if (pipe_ctx->stream->cursor_position.enable && (ignore_cursor_buf || in dcn32_helper_calculate_mall_bytes_for_cursor()
72 cursor_mall_size_bytes = ((cursor_size + DCN3_2_MALL_MBLK_SIZE_BYTES - 1) / in dcn32_helper_calculate_mall_bytes_for_cursor()
85 * @dc: current dc state
86 * @context: new dc state
91 struct dc *dc, in dcn32_helper_calculate_num_ways_for_subvp() argument
94 if (context->bw_ctx.bw.dcn.mall_subvp_size_bytes > 0) { in dcn32_helper_calculate_num_ways_for_subvp()
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/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_vm_helper.c27 #include "dc.h"
31 struct vmid_usage vmids = vm_helper->hubp_vmid_usage[hubp_idx]; in vm_helper_mark_vmid_used()
37 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config) in dc_setup_system_context() argument
42 if (dc->hwss.init_sys_ctx) { in dc_setup_system_context()
43 num_vmids = dc->hwss.init_sys_ctx(dc->hwseq, dc, pa_config); in dc_setup_system_context()
45 /* Pre-init system aperture start/end for all HUBP instances (if not gating?) in dc_setup_system_context()
48 memcpy(&dc->vm_pa_config, pa_config, sizeof(struct dc_phy_addr_space_config)); in dc_setup_system_context()
49 dc->vm_pa_config.valid = true; in dc_setup_system_context()
50 dc->dml2_options.gpuvm_enable = true; in dc_setup_system_context()
51 dc_z10_save_init(dc); in dc_setup_system_context()
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/linux/drivers/md/bcache/
H A Dwriteback.h1 /* SPDX-License-Identifier: GPL-2.0 */
53 for (i = 0; i < d->nr_stripes; i++) in bcache_dev_sectors_dirty()
54 ret += atomic_read(d->stripe_sectors_dirty + i); in bcache_dev_sectors_dirty()
62 do_div(offset, d->stripe_size); in offset_to_stripe()
64 /* d->nr_stripes is in range [1, INT_MAX] */ in offset_to_stripe()
65 if (unlikely(offset >= d->nr_stripes)) { in offset_to_stripe()
67 offset, d->nr_stripes); in offset_to_stripe()
68 return -EINVAL; in offset_to_stripe()
78 static inline bool bcache_dev_stripe_dirty(struct cached_dev *dc, in bcache_dev_stripe_dirty() argument
82 int stripe = offset_to_stripe(&dc->disk, offset); in bcache_dev_stripe_dirty()
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H A Dsysfs.c1 // SPDX-License-Identifier: GPL-2.0
33 "meta-only",
164 out += scnprintf(out, buf + size - out, in bch_snprint_string_list()
167 out[-1] = '\n'; in bch_snprint_string_list()
168 return out - buf; in bch_snprint_string_list()
173 struct cached_dev *dc = container_of(kobj, struct cached_dev, in SHOW() local
176 int wb = dc->writeback_running; in SHOW()
178 #define var(stat) (dc->stat) in SHOW()
183 BDEV_CACHE_MODE(&dc->sb)); in SHOW()
188 dc->cache_readahead_policy); in SHOW()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/
H A Ddcn35_fpu.c1 // SPDX-License-Identifier: MIT
214 * - with passed few options from dc->config
215 * - with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might
217 * - with passed latency values (passed in ns units) in dc-> bb override for
219 * - with passed latencies from VBIOS (in 100_ns units) if available for
221 * - with number of DRAM channels from VBIOS (which differ for certain dGPU SKU
223 * - clocks levels with passed clk_table entries from Clk Mgr as reported by PM
227 void dcn35_update_bw_bounding_box_fpu(struct dc *dc, in dcn35_update_bw_bounding_box_fpu() argument
232 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn35_update_bw_bounding_box_fpu()
234 dc->scratch.update_bw_bounding_box.clock_limits; in dcn35_update_bw_bounding_box_fpu()
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/linux/drivers/gpu/ipu-v3/
H A Dipu-dc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
15 #include <video/imx-ipu-v3.h>
16 #include "ipu-prv.h"
58 #define NULL_WAVE (-1)
90 /* The display interface number assigned to this dc channel */
109 static void dc_link_event(struct ipu_dc *dc, int event, int addr, int priority) in dc_link_event() argument
113 reg = readl(dc->base + DC_RL_CH(event)); in dc_link_event()
116 writel(reg, dc->base + DC_RL_CH(event)); in dc_link_event()
119 static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand, in dc_write_tmpl() argument
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c44 hws->ctx
47 hws->regs->reg
50 dc->ctx->logger
54 hws->shifts->field_name, hws->masks->field_name
59 struct dc_plane_state *plane_state = pipe_ctx->plane_state; in patch_address_for_sbs_tb_stereo()
60 bool sec_split = pipe_ctx->top_pipe && in patch_address_for_sbs_tb_stereo()
61 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; in patch_address_for_sbs_tb_stereo()
63 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO && in patch_address_for_sbs_tb_stereo()
64 (pipe_ctx->stream->timing.timing_3d_format == in patch_address_for_sbs_tb_stereo()
66 pipe_ctx->stream->timing.timing_3d_format == in patch_address_for_sbs_tb_stereo()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/
H A Ddcn351_fpu.c1 /* SPDX-License-Identifier: MIT */
248 * - with passed few options from dc->config
249 * - with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might
251 * - with passed latency values (passed in ns units) in dc-> bb override for
253 * - with passed latencies from VBIOS (in 100_ns units) if available for
255 * - with number of DRAM channels from VBIOS (which differ for certain dGPU SKU
257 * - clocks levels with passed clk_table entries from Clk Mgr as reported by PM
261 void dcn351_update_bw_bounding_box_fpu(struct dc *dc, in dcn351_update_bw_bounding_box_fpu() argument
266 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn351_update_bw_bounding_box_fpu()
268 dc->scratch.update_bw_bounding_box.clock_limits; in dcn351_update_bw_bounding_box_fpu()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c30 #include "dc.h"
496 return &ipp->base; in dcn21_ipp_create()
511 return &dpp->base; in dcn21_dpp_create()
533 ctx->dc->caps.extended_aux_timeout_support); in dcn21_aux_engine_create()
535 return &aux_engine->base; in dcn21_aux_engine_create()
577 .num_pll = 5, // maybe 3 because the last two used for USB-c
657 for (i = 0; i < pool->base.stream_enc_count; i++) { in dcn21_resource_destruct()
658 if (pool->base.stream_enc[i] != NULL) { in dcn21_resource_destruct()
659 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); in dcn21_resource_destruct()
660 pool->base.stream_enc[i] = NULL; in dcn21_resource_destruct()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c28 #include "dc.h"
107 dc->ctx->logger
356 /* Some encoders won't be initialized here - but they're logical, not physical. */
873 .dwb_fi_phase = -1, // -1 = disable,
926 return &dpp->base; in dcn31_dpp_create()
946 return &opp->base; in dcn31_opp_create()
964 ctx->dc->caps.extended_aux_timeout_support); in dcn31_aux_engine_create()
966 return &aux_engine->base; in dcn31_aux_engine_create()
1019 return &mpc30->base; in dcn31_mpc_create()
1042 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; in dcn31_hubbub_create()
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/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra20-dc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^dc@[0-9a-f]+$"
19 - enum:
20 - nvidia,tegra20-dc
21 - nvidia,tegra30-dc
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn10/
H A Ddcn10_fpu.c1 // SPDX-License-Identifier: MIT
60 * the DC FPU interface functions, we introduce a helper that checks if the
79 .LineBufferFixedBpp = -1,
127 void dcn10_resource_construct_fp(struct dc *dc) in dcn10_resource_construct_fp() argument
130 if (dc->ctx->dce_version == DCN_VERSION_1_01) { in dcn10_resource_construct_fp()
131 struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc; in dcn10_resource_construct_fp()
132 struct dcn_ip_params *dcn_ip = dc->dcn_ip; in dcn10_resource_construct_fp()
133 struct display_mode_lib *dml = &dc->dml; in dcn10_resource_construct_fp()
135 dml->ip.max_num_dpp = 3; in dcn10_resource_construct_fp()
137 dcn_soc->dram_clock_change_latency = 23; in dcn10_resource_construct_fp()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c1 /* SPDX-License-Identifier: MIT */
28 #include "dc.h"
127 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
150 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
153 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
200 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
733 .dwb_fi_phase = -1, // -1 = disable,
828 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp); in dcn35_dpp_create()
829 return &dpp->base; in dcn35_dpp_create()
858 dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp); in dcn35_opp_create()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/
H A Ddcn36_resource.c1 /* SPDX-License-Identifier: MIT */
5 #include "dc.h"
112 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
135 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
138 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
185 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
714 .dwb_fi_phase = -1, // -1 = disable,
809 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp); in dcn35_dpp_create()
810 return &dpp->base; in dcn35_dpp_create()
839 dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp); in dcn35_opp_create()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/
H A Ddcn301_resource.c2 * Copyright 2019-2021 Advanced Micro Devices, Inc.
28 #include "dc.h"
96 dc->ctx->logger
700 .dwb_fi_phase = -1, // -1 = disable
724 return &dpp->base; in dcn301_dpp_create()
743 return &opp->base; in dcn301_opp_create()
759 ctx->dc->caps.extended_aux_timeout_support); in dcn301_aux_engine_create()
761 return &aux_engine->base; in dcn301_aux_engine_create()
811 return &mpc30->base; in dcn301_mpc_create()
831 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; in dcn301_hubbub_create()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c1 /* SPDX-License-Identifier: MIT */
6 #include "dc.h"
107 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
130 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
133 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
180 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
713 .dwb_fi_phase = -1, // -1 = disable,
808 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp); in dcn35_dpp_create()
809 return &dpp->base; in dcn35_dpp_create()
838 dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp); in dcn35_opp_create()
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