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/linux/drivers/scsi/mvsas/
H A Dmv_94xx.h75 /* ports 5-7 follow after this */
81 /* ports 5-7 follow after this */
87 /* ports 5-7 follow after this */
148 MVS_IRQ_COM_OUT_I2O_HOS3 = (1 << 7),
180 * bit 2: 6Gbps support
181 * bit 1: 3Gbps support
182 * bit 0: 1.5Gbps support
188 * bit 5: G1 (1.5Gbps) Without SSC
189 * bit 4: G1 (1.5Gbps) with SSC
190 * bit 3: G2 (3.0Gbps) Without SSC
[all …]
H A Dmv_94xx.c84 (phy_tuning.trans_emp_amp << 7) | in set_phy_tuning()
110 * FFE_FORCE [7] in set_phy_ffe_tuning()
119 tmp |= ((0x1 << 7) | in set_phy_ffe_tuning()
177 /* support 1.5 Gbps */ in set_phy_rate()
185 /* support 1.5, 3.0 Gbps */ in set_phy_rate()
192 /* support 1.5, 3.0, 6.0 Gbps */ in set_phy_rate()
193 phy_cfg.u.speed_support = 7; in set_phy_rate()
233 /*set default phy_rate = 6Gbps*/ in mvs_94xx_config_reg_from_hba()
811 u32 id_frame[7]; in mvs_94xx_get_dev_identify_frame()
813 for (i = 0; i < 7; i++) { in mvs_94xx_get_dev_identify_frame()
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dapm,xgene-phy.yaml7 title: APM X-Gene 15Gbps Multi-purpose PHY
13 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
146 0 = 1-2Gbps
147 1 = 2-4Gbps (1st tuple default)
148 2 = 4-8Gbps
149 3 = 8-15Gbps (2nd tuple default)
150 4 = 2.5-4Gbps
151 5 = 4-5Gbps
152 6 = 5-6Gbps
153 7 = 6-16Gbps (3rd tuple default).
[all …]
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_arcturus.h64 #define FEATURE_DS_GFXCLK_BIT 7
194 #define THROTTLER_TDC_GFX_BIT 7
429 XGMI_LINK_RATE_2 = 2, // 2Gbps
430 XGMI_LINK_RATE_4 = 4, // 4Gbps
431 XGMI_LINK_RATE_8 = 8, // 8Gbps
432 XGMI_LINK_RATE_12 = 12, // 12Gbps
433 XGMI_LINK_RATE_16 = 16, // 16Gbps
434 XGMI_LINK_RATE_17 = 17, // 17Gbps
435 XGMI_LINK_RATE_18 = 18, // 18Gbps
436 XGMI_LINK_RATE_19 = 19, // 19Gbps
[all …]
H A Dsmu11_driver_if_sienna_cichlid.h32 #define PPTABLE_Sienna_Cichlid_SMU_VERSION 7
83 #define FEATURE_DPM_LINK_BIT 7
202 #define THROTTLER_TEMP_VR_SOC_BIT 7
226 #define FW_DSTATE_SOC_LIV_MIN_BIT 7
524 XGMI_LINK_RATE_2 = 2, // 2Gbps
525 XGMI_LINK_RATE_4 = 4, // 4Gbps
526 XGMI_LINK_RATE_8 = 8, // 8Gbps
527 XGMI_LINK_RATE_12 = 12, // 12Gbps
528 XGMI_LINK_RATE_16 = 16, // 16Gbps
529 XGMI_LINK_RATE_17 = 17, // 17Gbps
[all …]
H A Dsmu13_driver_if_aldebaran.h45 #define FEATURE_DS_GFXCLK_BIT 7
118 #define THROTTLER_TEMP_MEM_BIT 7
358 uint8_t XgmiLinkSpeed[NUM_XGMI_DPM_LEVELS]; //Gbps [EX: 32 = 32Gbps]
554 #define TABLE_ECCINFO 7
/linux/drivers/net/ethernet/ezchip/
H A Dnps_enet.h59 /* Gbps Eth MAC Configuration 0 register masks and shifts */
75 #define CFG_0_RX_CRC_IGNORE_SHIFT 7
93 /* Gbps Eth MAC Configuration 1 register masks and shifts */
103 /* Gbps Eth MAC Configuration 2 register masks and shifts */
119 /* Gbps Eth MAC Configuration 3 register masks and shifts */
/linux/tools/testing/selftests/drivers/net/hw/
H A Ddevlink_rate_tc_bw.py39 - Total bandwidth: 1Gbps
218 {"index": 7, "bw": 0},
280 gbps = bits_per_second / 1e9
281 if gbps < min_expected_gbps:
283 f"iperf3 bandwidth too low: {gbps:.2f} Gbps "
284 f"(expected ≥ {min_expected_gbps} Gbps)"
287 return gbps
372 f"Total bandwidth {total:.2f} Gbps < minimum "
373 f"{validator.total_min_expected:.2f} Gbps; "
379 f"Total bandwidth {total:.2f} Gbps exceeds allowed ceiling "
[all …]
/linux/include/rdma/
H A Dopa_port_info.h34 #define OPA_LINKDOWN_REASON_BAD_L2 7
87 /* 3-7; 11-15 reserved; 8-15 cleared on Polling->LinkUp */
96 #define OPA_LINK_SPEED_NOP 0x0000 /* Reserved (1-5 Gbps) */
97 #define OPA_LINK_SPEED_12_5G 0x0001 /* 12.5 Gbps */
98 #define OPA_LINK_SPEED_25G 0x0002 /* 25.78125? Gbps (EDR) */
106 #define OPA_CAP_MASK3_IsSnoopSupported (1 << 7)
186 /* 7 bits reserved */
329 u8 res_drctl; /* 7 res, 1 */
/linux/drivers/gpu/drm/i915/display/
H A Dintel_cx0_phy.c543 .pll[7] = 0x46,
569 .pll[7] = 0xB3,
595 .pll[7] = 0xE9,
621 .pll[7] = 0x10,
647 .pll[7] = 0x46,
673 .pll[7] = 0xB3,
699 .pll[7] = 0x10,
725 .pll[7] = 0x54,
751 .pll[7] = 0x98,
890 .clock = 1000000, /* 10 Gbps */
[all …]
/linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/
H A Dhclge_main.h153 #define HCLGE_RESET_INT_M GENMASK(7, 5)
161 #define HCLGE_VECTOR0_IMPRESET_INT_B 7
172 #define HCLGE_TRIGGER_IMP_RESET_B 7U
195 #define HCLGE_SUPPORT_10M_BIT BIT(7)
247 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */
248 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */
249 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */
250 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */
251 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */
252 HCLGE_MAC_SPEED_100G = 100000, /* 100000 Mbps = 100 Gbps */
[all …]
/linux/drivers/usb/host/
H A Dxhci-hub.c26 0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */
27 0x000500b4, /* USB 3.0 SS Gen1x1 id:4 symmetric tx 5Gbps */
28 0x000a4035, /* USB 3.1 SSP Gen2x1 id:5 symmetric rx 10Gbps */
29 0x000a40b5, /* USB 3.1 SSP Gen2x1 id:5 symmetric tx 10Gbps */
30 0x00054036, /* USB 3.2 SSP Gen1x2 id:6 symmetric rx 5Gbps */
31 0x000540b6, /* USB 3.2 SSP Gen1x2 id:6 symmetric tx 5Gbps */
32 0x000a4037, /* USB 3.2 SSP Gen2x2 id:7 symmetric rx 10Gbps */
33 0x000a40b7, /* USB 3.2 SSP Gen2x2 id:7 symmetric tx 10Gbps */
85 ssac = 7; in xhci_create_usb3x_bos_desc()
170 /* Shift to Gbps and set SSP Link Protocol if 10Gpbs */ in xhci_create_usb3x_bos_desc()
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-8040-puzzle-m801.dts108 /* SFP+ port 2: 10 Gbps indicator */
111 gpios = <&cp1_gpio1 7 GPIO_ACTIVE_LOW>;
115 /* SFP+ port 2: 1 Gbps indicator */
122 /* SFP+ port 1: 10 Gbps indicator */
129 /* SFP+ port 1: 1 Gbps indicator */
/linux/drivers/net/ethernet/ibm/ehea/
H A Dehea_phyp.h32 #define NEQE_EVENT_CODE EHEA_BMASK_IBM(2, 7)
109 #define H_QPCB1_ALL EHEA_BMASK_IBM(0, 7)
117 #define H_QPCB1_SGEL_NB_RQ3 EHEA_BMASK_IBM(7, 7)
164 #define H_PORT_CB7 7
180 #define H_PORT_CB0_ALL EHEA_BMASK_IBM(0, 7) /* Set all bits */
183 #define H_PORT_CB0_DEFQPNARRAY EHEA_BMASK_IBM(7, 7) /* Default QPN Array */
190 #define H_SPEED_1G_F 6 /* 1 Gbps, Full Duplex */
191 #define H_SPEED_10G_F 8 /* 10 Gbps, Full Duplex */
/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c61 #define COMPHY_MODE_MASK GENMASK(7, 5)
69 #define SPEED_PLL_MASK GENMASK(7, 2)
93 #define GS2_VREG_RXTX_MAS_ISET_MASK GENMASK(8, 7)
112 #define CLK500M_EN BIT(7)
145 #define SPREAD_SPECTRUM_CLK_EN BIT(7)
163 #define PLL_READY_DLY_MASK GENMASK(7, 5)
170 #define CFG_PM_RXDLOZ_WAIT_MASK GENMASK(7, 0)
300 /* 0 1 2 3 4 5 6 7 */
608 * All PHY register values are defined in full for 3.125Gbps in comphy_gbe_phy_init()
609 * SERDES speed. The values required for 1.25 Gbps are almost in comphy_gbe_phy_init()
[all …]
/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-board.c95 /* Board has 8 RGMII ports PHYs are 0-7 */ in cvmx_helper_board_get_mii_address()
174 return 7 - ipd_port; in cvmx_helper_board_get_mii_address()
221 /* The simulator gives you a simulated 1Gbps full duplex link */ in __cvmx_helper_board_link_get()
253 case 2: /* 1 Gbps */ in __cvmx_helper_board_link_get()
H A Dcvmx-helper-rgmii.c272 /* Force 1Gbps full duplex on internal loopback */ in __cvmx_helper_rgmii_link_get()
352 CVMX_WAIT_FOR_FIELD64(CVMX_DBG_DATA, union cvmx_dbg_data, data & 7, in __cvmx_helper_rgmii_link_set()
372 /* Set the link speed. Anything unknown is set to 1Gbps */ in __cvmx_helper_rgmii_link_set()
/linux/Documentation/networking/device_drivers/ethernet/intel/
H A Dixgbe.rst111 - 82599-based QSFP+ adapters only support 4x10 Gbps connections. 1x40 Gbps
113 4x10 Gbps.
115 The link speed must be configured to either 10 Gbps or 1 Gbps to match the link
237 with a specific class based on priority, which has a value of 0 through 7 used
373 directed to 192.168.0.5, port 80, and sends it to queue 7::
376 src-port 5300 dst-port 80 action 7
381 ethtool -U enp130s0 flow-type ip4 src-ip 192.168.0.1 src-port 5300 action 7
387 ethtool -U enp130s0 flow-type ip4 src-ip 192.168.0.1 src-port 5300 action 7
404 specifies to direct traffic to Virtual Function 7 (8 minus 1) into queue 2 of
/linux/drivers/net/phy/realtek/
H A Drealtek_main.c35 #define RTL8211F_INER_PME BIT(7)
1814 .name = "RTL8226 2.5Gbps PHY",
1825 .name = "RTL8226B_RTL8221B 2.5Gbps PHY",
1837 .name = "RTL8226-CG 2.5Gbps PHY",
1847 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
1859 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)",
1872 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)",
1883 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)",
1896 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C45)",
1907 .name = "RTL8251B 5Gbps PHY",
[all …]
/linux/drivers/ata/
H A DKconfig285 tristate "APM X-Gene 6.0Gbps AHCI SATA host controller support"
303 tristate "Freescale 3.0Gbps SATA support"
307 This option enables support for Freescale 3.0Gbps SATA controller.
324 tristate "AMD Seattle 6.0Gbps AHCI SATA host controller support"
437 This option enables support for ICH5/6/7/8 Serial ATA
H A Dahci_xgene.c307 * required for each supported disk speed - Gen3 (6.0Gbps), Gen2 (3.0Gbps),
308 * and Gen1 (1.5Gbps). Otherwise during long IO stress test, the PHY will
326 * 7. Go to Alg Part 2
554 * 7. Exit
/linux/drivers/net/ethernet/ti/icssg/
H A Dicssg_config.h224 * 0xc - 1Gbps/Full duplex;
226 * or bits [7..5](slice 1) of RGMII CFG register.
302 #define ICSSG_FDB_ENTRY_VALID BIT(7)
/linux/drivers/message/fusion/
H A Dmptfc.c131 .cmd_per_lun = 7,
734 old = old_speed == MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT ? "1 Gbps" : in mptfc_display_port_link_speed()
735 old_speed == MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT ? "2 Gbps" : in mptfc_display_port_link_speed()
736 old_speed == MPI_FCPORTPAGE0_CURRENT_SPEED_4GBIT ? "4 Gbps" : in mptfc_display_port_link_speed()
738 new = new_speed == MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT ? "1 Gbps" : in mptfc_display_port_link_speed()
739 new_speed == MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT ? "2 Gbps" : in mptfc_display_port_link_speed()
740 new_speed == MPI_FCPORTPAGE0_CURRENT_SPEED_4GBIT ? "4 Gbps" : in mptfc_display_port_link_speed()
/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_core.c532 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps in analogix_dp_get_max_rx_bandwidth()
534 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps in analogix_dp_get_max_rx_bandwidth()
1316 if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) || in analogix_dp_bridge_mode_set()
1398 * containing 4 physical lanes of 2.7/1.62 Gbps/lane". in analogix_dp_dt_parse_pdata()
/linux/drivers/usb/typec/mux/
H A Dptn36502.c28 #define PTN36502_CHIP_REVISION_BASE_MASK GENMASK(7, 4)
59 #define PTN36502_DEVICE_CTRL_AUX_MONITORING_MASK GENMASK(7, 7)
189 /* DP Link rate: 5.4 Gbps (HBR2) */ in ptn36502_set()

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