| /freebsd/sys/contrib/dev/ath/ath_hal/ar9300/ |
| H A D | wasp_reg_map.h | 20 volatile char pad__0[0x4000]; /* 0x0 - 0x4000 */
21 volatile u_int32_t HOST_INTF_RESET_CONTROL; /* 0x4000 - 0x4004 */
22 volatile u_int32_t HOST_INTF_PM_CTRL; /* 0x4004 - 0x4008 */
23 volatile u_int32_t HOST_INTF_TIMEOUT; /* 0x4008 - 0x400c */
24 volatile u_int32_t HOST_INTF_SREV; /* 0x400c - 0x4010 */
25 volatile u_int32_t HOST_INTF_INTR_SYNC_CAUSE; /* 0x4010 - 0x4014 */
26 volatile u_int32_t HOST_INTF_INTR_SYNC_ENABLE; /* 0x4014 - 0x4018 */
27 volatile u_int32_t HOST_INTF_INTR_ASYNC_MASK; /* 0x4018 - 0x401c */
28 volatile u_int32_t HOST_INTF_INTR_SYNC_MASK; /* 0x401c - 0x4020 */
29 volatile u_int32_t HOST_INTF_INTR_ASYNC_CAUSE; /* 0x4020 - 0x4024 */
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | ti,j721e-system-controller.yaml | 48 "^mux-controller@[0-9a-f]+$":
53 "^clock-controller@[0-9a-f]+$":
59 "phy@[0-9a-f]+$":
65 "^chipid@[0-9a-f]+$":
84 reg = <0x00100000 0x1c000>;
91 reg = <0x00004080 0x50>;
95 <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
96 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
97 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
98 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm64/amlogic/ |
| H A D | meson-s4.dtsi | 17 #size-cells = <0>;
19 cpu0: cpu@0 {
22 reg = <0x0 0x0>;
29 reg = <0x0 0x1>;
36 reg = <0x0 0x2>;
43 reg = <0x0 0x
[all...] |
| /freebsd/contrib/ofed/libcxgb4/ |
| H A D | t4_pci_id_tbl.h | 46 * -- The PCI Function Number to use in the PCI Device ID Table. "0"
73 /* T4 and later ASICs use a PCI Device ID scheme of 0xVFPP where:
76 * F = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs
97 CH_PCI_ID_TABLE_FENTRY(0x4000), /* T440-dbg */
98 CH_PCI_ID_TABLE_FENTRY(0x4001), /* T420-cr */
99 CH_PCI_ID_TABLE_FENTRY(0x4002), /* T422-cr */
100 CH_PCI_ID_TABLE_FENTRY(0x4003), /* T440-cr */
101 CH_PCI_ID_TABLE_FENTRY(0x4004), /* T420-bch */
102 CH_PCI_ID_TABLE_FENTRY(0x4005), /* T440-bch */
103 CH_PCI_ID_TABLE_FENTRY(0x4006), /* T440-ch */
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| /freebsd/sys/dev/ntb/ntb_hw/ |
| H A D | ntb_hw_intel.h | 42 * Params: [in] P = Bit position of start of the bit field (lsb is 0).
51 #define NTB_LINK_STATUS_ACTIVE 0x2000
52 #define NTB_LINK_SPEED_MASK 0x000f
53 #define NTB_LINK_WIDTH_MASK 0x03f0
67 #define XEON_SPCICMD_OFFSET 0x0504
68 #define XEON_DEVCTRL_OFFSET 0x0598
69 #define XEON_DEVSTS_OFFSET 0x059a
70 #define XEON_LINK_STATUS_OFFSET 0x01a2
71 #define XEON_SLINK_STATUS_OFFSET 0x05a2
73 #define XEON_PBAR2LMT_OFFSET 0x0000
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| /freebsd/sys/contrib/device-tree/src/arm/nxp/mxs/ |
| H A D | imx28-pinfunc.h | 13 #define MX28_PAD_GPMI_D00__GPMI_D0 0x0000
14 #define MX28_PAD_GPMI_D01__GPMI_D1 0x0010
15 #define MX28_PAD_GPMI_D02__GPMI_D2 0x0020
16 #define MX28_PAD_GPMI_D03__GPMI_D3 0x0030
17 #define MX28_PAD_GPMI_D04__GPMI_D4 0x0040
18 #define MX28_PAD_GPMI_D05__GPMI_D5 0x0050
19 #define MX28_PAD_GPMI_D06__GPMI_D6 0x0060
20 #define MX28_PAD_GPMI_D07__GPMI_D7 0x0070
21 #define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
22 #define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
[all …]
|
| /freebsd/sys/arm/mv/ |
| H A D | mvwin.h | 45 * SoC Integrated devices: 0xF1000000, 16 MB (VA == PA)
49 #define MV_PHYS_BASE 0xF1000000
53 #define MV_CESA_SRAM_BASE 0xF1100000
56 * External devices: 0x80000000, 1 GB (VA == PA)
70 #define MV_PCI_MEM_PHYS_BASE 0x80000000
75 #define MV_PCI_IO_PHYS_BASE 0xBF000000
79 #define MV_PCI_VA_MEM_BASE 0
80 #define MV_PCI_VA_IO_BASE 0
85 #define MV_DEV_BOOT_BASE 0xF9300000
88 #define MV_DEV_CS0_BASE 0xF9400000
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|
| /freebsd/sys/i386/i386/ |
| H A D | elan-mmcr.c | 85 { 0xf0000, 0xf1000 },
87 { "Soekris", 0, 8 }, /* Soekris Engineering. */
88 { "net4", 0, 8 }, /* net45xx */
89 { "comBIOS", 0, 54 }, /* comBIOS ver. 1.26a 20040819 ... */
90 { NULL, 0, 0 },
105 v = u & 0xffff; in gpio_led()
108 v ^= 0xc; in gpio_led()
122 if (error != 0 || req->newptr == NULL) in sysctl_machdep_elan_gpio_config()
127 if (error != 0) in sysctl_machdep_elan_gpio_config()
130 np = ne = 0; in sysctl_machdep_elan_gpio_config()
[all …]
|
| /freebsd/contrib/elftoolchain/libdwarf/ |
| H A D | dwarf.h | 32 #define DW_TAG_array_type 0x01
33 #define DW_TAG_class_type 0x02
34 #define DW_TAG_entry_point 0x03
35 #define DW_TAG_enumeration_type 0x04
36 #define DW_TAG_formal_parameter 0x05
37 #define DW_TAG_imported_declaration 0x08
38 #define DW_TAG_label 0x0a
39 #define DW_TAG_lexical_block 0x0b
40 #define DW_TAG_member 0x0d
41 #define DW_TAG_pointer_type 0x0f
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| /freebsd/lib/libpmc/pmu-events/arch/x86/westmereep-dp/ |
| H A D | memory.json | 4 "Counter": "0,1,2,3",
5 "EventCode": "0x5",
8 "UMask": "0x2"
12 "Counter": "0,1,2,3",
13 "EventCode": "0xB7, 0xBB",
15 "MSRIndex": "0x1a6,0x1a7",
16 "MSRValue": "0x3011",
19 "UMask": "0x1"
23 "Counter": "0,1,2,3",
24 "EventCode": "0xB7, 0xBB",
[all …]
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| /freebsd/lib/libpmc/pmu-events/arch/x86/westmereep-sp/ |
| H A D | memory.json | 4 "Counter": "0,1,2,3",
5 "EventCode": "0xB7, 0xBB",
7 "MSRIndex": "0x1a6,0x1a7",
8 "MSRValue": "0x6011",
11 "UMask": "0x1"
15 "Counter": "0,1,2,3",
16 "EventCode": "0xB7, 0xBB",
18 "MSRIndex": "0x1a6,0x1a7",
19 "MSRValue": "0xF811",
22 "UMask": "0x1"
[all …]
|
| /freebsd/contrib/gdtoa/ |
| H A D | gdtoaimp.h | 80 * for 0 <= k <= 22).
148 * preceded by 0x or 0X) and spaces; if there is only one string
160 * by FREE_DTOA_LOCK(n) for n = 0 or 1. (The second lock, accessed
270 #define Scale_Bit 0x10
298 #define word1(x) (x)->L[0]
300 #define word0(x) (x)->L[0]
307 * #define Storeinc(a,b,c) (*a++ = b << 16 | c & 0xffff)
311 ((unsigned short *)a)[0] = (unsigned short)c, a++)
313 #define Storeinc(a,b,c) (((unsigned short *)a)[0] = (unsigned short)b, \
326 #define Exp_msk1 0x100000
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|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | AMDGPUMCCodeEmitter.cpp | 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
107 // immediate value, or 0 if it is not.
110 if (Imm >= 0 && Imm <= 64) in getIntInlineImmEncoding()
116 return 0; in getIntInlineImmEncoding()
121 if (IntImm != 0) in getLit16Encoding()
124 if (Val == 0x3800) // 0.5 in getLit16Encoding()
127 if (Val == 0xB800) // -0.5 in getLit16Encoding()
130 if (Val == 0x3C00) // 1.0 in getLit16Encoding()
133 if (Val == 0xBC00) // -1.0 in getLit16Encoding()
136 if (Val == 0x4000) // 2.0 in getLit16Encoding()
[all …]
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| /freebsd/sys/dev/ath/ath_hal/ar5416/ |
| H A D | ar5416reg.h | 27 #define AR_MIRT 0x0020 /* interrupt rate threshold */
28 #define AR_TIMT 0x0028 /* Tx Interrupt mitigation threshold */
29 #define AR_RIMT 0x002C /* Rx Interrupt mitigation threshold */
30 #define AR_GTXTO 0x0064 /* global transmit timeout */
31 #define AR_GTTM 0x0068 /* global transmit timeout mode */
32 #define AR_CST 0x006C /* carrier sense timeout */
33 #define AR_MAC_LED 0x1f04 /* LED control */
34 #define AR_WA 0x4004 /* PCIE work-arounds */
35 #define AR_PCIE_PM_CTRL 0x4014
36 #define AR_AHB_MODE 0x4024 /* AHB mode for dma */
[all …]
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| /freebsd/sys/arm64/freescale/imx/ |
| H A D | imx8mp_ccm.c | 350 FIXED(IMX8MP_CLK_DUMMY, "dummy", 0),
359 MUX(IMX8MP_AUDIO_PLL1_REF_SEL, "audio_pll1_ref_sel", pll_ref_p, 0, 0x00, 0, 2),
360 MUX(IMX8MP_AUDIO_PLL2_REF_SEL, "audio_pll2_ref_sel", pll_ref_p, 0, 0x14, 0, 2),
361 MUX(IMX8MP_VIDEO_PLL1_REF_SEL, "video_pll1_ref_sel", pll_ref_p, 0, 0x28, 0, 2),
362 MUX(IMX8MP_DRAM_PLL_REF_SEL, "dram_pll_ref_sel", pll_ref_p, 0, 0x50, 0, 2),
363 MUX(IMX8MP_GPU_PLL_REF_SEL, "gpu_pll_ref_sel", pll_ref_p, 0, 0x64, 0, 2),
364 MUX(IMX8MP_VPU_PLL_REF_SEL, "vpu_pll_ref_sel", pll_ref_p, 0, 0x74, 0, 2),
365 MUX(IMX8MP_ARM_PLL_REF_SEL, "arm_pll_ref_sel", pll_ref_p, 0, 0x84, 0, 2),
366 MUX(IMX8MP_SYS_PLL1_REF_SEL, "sys_pll1_ref_sel", pll_ref_p, 0, 0x94, 0, 2),
367 MUX(IMX8MP_SYS_PLL2_REF_SEL, "sys_pll2_ref_sel", pll_ref_p, 0, 0x104, 0, 2),
[all …]
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/BinaryFormat/ |
| H A D | Dwarf.h | 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
47 DW_TAG_invalid = ~0U, ///< Tag for invalid results.
48 DW_VIRTUALITY_invalid = ~0U, ///< Virtuality for invalid results.
49 DW_MACINFO_invalid = ~0U, ///< Macinfo type for invalid results.
54 DW_LENGTH_lo_reserved = 0xfffffff0, ///< Lower bound of the reserved range.
55 DW_LENGTH_DWARF64 = 0xffffffff, ///< Indicator of 64-bit DWARF format.
56 DW_LENGTH_hi_reserved = 0xffffffff, ///< Upper bound of the reserved range.
69 DWARF_VENDOR_DWARF = 0, ///< Defined in v2 or later of the DWARF standard.
106 DW_TAG_lo_user = 0x4080,
107 DW_TAG_hi_user = 0xffff,
[all …]
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| /freebsd/lib/libc/softfloat/ |
| H A D | timesoftfloat.c | 91 0xFFFFBB79, 0x405CF80F, 0x00000000, 0xFFFFFD04,
92 0xFFF20002, 0x0C8EF795, 0xF00011FF, 0x000006CA,
93 0x00009BFE, 0xFF4862E3, 0x9FFFEFFE, 0xFFFFFFB7,
94 0x0BFF7FFF, 0x0000F37A, 0x0011DFFE, 0x00000006,
95 0xFFF02006, 0xFFFFF7D1, 0x10200003, 0xDE8DF765,
96 0x00003E02, 0x000019E8, 0x0008FFFE, 0xFFFFFB5C,
97 0xFFDF7FFE, 0x07C42FBF, 0x0FFFE3FF, 0x040B9F13,
98 0xBFFFFFF8, 0x0001BF56, 0x000017F6, 0x000A908A
107 count = 0; in time_a_int32_z_float32()
108 inputNum = 0; in time_a_int32_z_float32()
[all …]
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| /freebsd/sys/dev/smartpqi/ |
| H A D | smartpqi_defines.h | 44 #define PQI_STATUS_SUCCESS 0
47 #define PQI_VENDOR_GENERAL_CONFIG_TABLE_UPDATE 0
65 #define INVALID_ELEM 0xffff
78 #define INT_MAX 0x7FFFFFFF
87 (offsetof(TYPE, MEMBER) + sizeof(((TYPE *)0)->MEMBER))
125 #define false 0
134 #define INTR_TYPE_NONE 0x0
135 #define INTR_TYPE_FIXED 0x1
136 #define INTR_TYPE_MSI 0x2
137 #define INTR_TYPE_MSIX 0x4
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| /freebsd/sys/dev/bxe/ |
| H A D | 57712_int_offsets.h | 31 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_SIZE
32 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_DATA_SIZE
33 { 0x28, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_SIZE
34 { 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_DATA_SIZE
35 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_DYNAMIC_HC_CONFIG_SIZE
36 { 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_MSG_SIZE
37 { 0x8, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_INDEX_SIZE
38 { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_INVALID_ASSERT_OPCODE
39 { 0x3d, 0x0, 0x0, 0x0, 0x0}, // COMMON_RAM1_TEST_EVENT_ID
40 …{ 0x3c, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_EVEN…
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.cpp | 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
66 return VersionMajor >= 11 ? 10 : 0; in getVmcntBitShiftLo()
76 return VersionMajor >= 11 ? 0 : 4; in getExpcntBitShift()
97 return (VersionMajor == 9 || VersionMajor == 10) ? 2 : 0; in getVmcntBitWidthHi()
102 return VersionMajor >= 12 ? 6 : 0; in getLoadcntBitWidth()
107 return VersionMajor >= 12 ? 6 : 0; in getSamplecntBitWidth()
112 return VersionMajor >= 12 ? 3 : 0; in getBvhcntBitWidth()
117 return VersionMajor >= 12 ? 6 : 0; in getDscntBitWidth()
121 unsigned getDscntBitShift(unsigned VersionMajor) { return 0; } in getDscntBitShift()
125 return VersionMajor >= 10 ? 6 : 0; in getStorecntBitWidth()
[all …]
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| /freebsd/sys/dev/cas/ |
| H A D | if_casreg.h | 42 #define CAS_CAW 0x0004 /* core arbitration weight */
43 #define CAS_INF_BURST 0x0008 /* infinite burst enable */
44 #define CAS_STATUS 0x000c /* interrupt status */
45 #define CAS_INTMASK 0x0010 /* interrupt mask */
46 #define CAS_CLEAR_ALIAS 0x0014 /* clear mask alias */
47 #define CAS_STATUS_ALIAS 0x001c /* interrupt status alias */
48 #define CAS_ERROR_STATUS 0x1000 /* PCI error status */
49 #define CAS_ERROR_MASK 0x1004 /* PCI error mask */
50 #define CAS_BIM_CONF 0x1008 /* BIM configuration */
51 #define CAS_BIM_DIAG 0x100c /* BIM diagnostic */
[all …]
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| /freebsd/sys/dev/ath/ath_hal/ar5212/ |
| H A D | ar5212reg.h | 27 #define AR_CR 0x0008 /* MAC control register */
28 #define AR_RXDP 0x000C /* MAC receive queue descriptor pointer */
29 #define AR_CFG 0x0014 /* MAC configuration and status register */
30 #define AR_IER 0x0024 /* MAC Interrupt enable register */
31 /* 0x28 is RTSD0 on the 5211 */
32 /* 0x2c is RTSD1 on the 5211 */
33 #define AR_TXCFG 0x0030 /* MAC tx DMA size config register */
34 #define AR_RXCFG 0x0034 /* MAC rx DMA size config register */
35 /* 0x38 is the jumbo descriptor address on the 5211 */
36 #define AR_MIBC 0x0040 /* MAC MIB control register */
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm64/ti/ |
| H A D | k3-j7200-main.dtsi | 10 #clock-cells = <0>;
18 reg = <0x00 0x70000000 0x00 0x100000>;
21 ranges = <0x00 0x00 0x70000000 0x100000>;
23 atf-sram@0 {
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| H A D | k3-am65-main.dtsi | 12 reg = <0x0 0x70000000 0x0 0x200000>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
17 atf-sram@0 {
18 reg = <0x
[all...] |
| /freebsd/sys/contrib/device-tree/src/arm/qcom/ |
| H A D | qcom-apq8064.dtsi | 25 reg = <0x80000000 0x200000>;
30 reg = <0x8f000000 0x700000>;
37 #size-cells = <0>;
39 CPU0: cpu@0 {
43 reg = <0>;
100 memory@0 {
102 reg = <0x0 0x
[all...] |