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/freebsd/contrib/ntp/sntp/libopts/
H A Dag-char-map.h51 #if 0 /* mapping specification source (from autogen.map) */
81 // oct-digit "0-7"
111 #endif /* 0 -- mapping spec. source */
116 #define IS_NEWLINE_CHAR( _c) is_ag_char_map_char((char)(_c), 0x00000001)
117 #define SPN_NEWLINE_CHARS(_s) spn_ag_char_map_chars(_s, 0)
118 #define BRK_NEWLINE_CHARS(_s) brk_ag_char_map_chars(_s, 0)
119 #define SPN_NEWLINE_BACK(s,e) spn_ag_char_map_back(s, e, 0)
120 #define BRK_NEWLINE_BACK(s,e) brk_ag_char_map_back(s, e, 0)
121 #define IS_NUL_BYTE_CHAR( _c) is_ag_char_map_char((char)(_c), 0x00000002)
126 #define IS_DIR_SEP_CHAR( _c) is_ag_char_map_char((char)(_c), 0x00000004)
[all …]
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dqcom,spi-geni-qcom.yaml87 reg = <0x00880000 0x4000>;
91 pinctrl-0 = <&qup_spi0_default>;
94 #size-cells = <0>;
97 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
98 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
107 reg = <0x00884000 0x4000>;
110 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
114 pinctrl-0 = <&qup_spi1_default>;
117 #size-cells = <0>;
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsc8180x.dtsi29 #clock-cells = <0>;
35 #clock-cells = <0>;
43 #size-cells = <0>;
45 CPU0: cpu@0 {
48 reg = <0x0 0x0>;
52 qcom,freq-domain = <&cpufreq_hw 0>;
59 clocks = <&cpufreq_hw 0>;
77 reg = <0x0 0x100>;
81 qcom,freq-domain = <&cpufreq_hw 0>;
88 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsc7180.dtsi66 #clock-cells = <0>;
72 #clock-cells = <0>;
78 #size-cells = <0>;
80 CPU0: cpu@0 {
83 reg = <0x0 0x0>;
84 clocks = <&cpufreq_hw 0>;
95 qcom,freq-domain = <&cpufreq_hw 0>;
112 reg = <0x0 0x100>;
113 clocks = <&cpufreq_hw 0>;
124 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsdm845.dtsi78 #clock-cells = <0>;
85 #clock-cells = <0>;
92 #size-cells = <0>;
94 CPU0: cpu@0 {
97 reg = <0x0 0x0>;
98 clocks = <&cpufreq_hw 0>;
102 qcom,freq-domain = <&cpufreq_hw 0>;
126 reg = <0x0 0x100>;
127 clocks = <&cpufreq_hw 0>;
131 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsdm670.dtsi33 #size-cells = <0>;
35 CPU0: cpu@0 {
38 reg = <0x0 0x0>;
42 qcom,freq-domain = <&cpufreq_hw 0>;
65 reg = <0x0 0x100>;
69 qcom,freq-domain = <&cpufreq_hw 0>;
87 reg = <0x0 0x200>;
91 qcom,freq-domain = <&cpufreq_hw 0>;
109 reg = <0x0 0x300>;
113 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsc8280xp.dtsi33 #clock-cells = <0>;
38 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
58 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8350.dtsi38 #clock-cells = <0>;
46 #clock-cells = <0>;
52 #size-cells = <0>;
54 CPU0: cpu@0 {
57 reg = <0x0 0x0>;
58 clocks = <&cpufreq_hw 0>;
61 qcom,freq-domain = <&cpufreq_hw 0>;
81 reg = <0x0 0x100>;
82 clocks = <&cpufreq_hw 0>;
85 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8150.dtsi34 #clock-cells = <0>;
41 #clock-cells = <0>;
49 #size-cells = <0>;
51 CPU0: cpu@0 {
54 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw 0>;
60 qcom,freq-domain = <&cpufreq_hw 0>;
62 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
83 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsm8550.dtsi38 #clock-cells = <0>;
43 #clock-cells = <0>;
47 #clock-cells = <0>;
55 #clock-cells = <0>;
65 #size-cells = <0>;
67 CPU0: cpu@0 {
70 reg = <0 0>;
71 clocks = <&cpufreq_hw 0>;
76 qcom,freq-domain = <&cpufreq_hw 0>;
96 reg = <0 0x100>;
[all …]
H A Dsm8450.dtsi39 #clock-cells = <0>;
45 #clock-cells = <0>;
52 #size-cells = <0>;
54 CPU0: cpu@0 {
57 reg = <0x0 0x0>;
62 qcom,freq-domain = <&cpufreq_hw 0>;
64 clocks = <&cpufreq_hw 0>;
81 reg = <0x0 0x100>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
88 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsm8650.dtsi40 #clock-cells = <0>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
59 #clock-cells = <0>;
69 #size-cells = <0>;
71 CPU0: cpu@0 {
74 reg = <0 0>;
76 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
107 reg = <0 0x100>;
[all …]
H A Dx1e80100.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
47 #clock-cells = <0>;
56 #clock-cells = <0>;
66 #size-cells = <0>;
68 CPU0: cpu@0 {
71 reg = <0x0 0x0>;
88 reg = <0x0 0x100>;
99 reg = <0x0 0x200>;
110 reg = <0x0 0x300>;
[all …]
H A Dsm8250.dtsi80 #clock-cells = <0>;
88 #clock-cells = <0>;
94 #size-cells = <0>;
96 CPU0: cpu@0 {
99 reg = <0x0 0x0>;
100 clocks = <&cpufreq_hw 0>;
107 qcom,freq-domain = <&cpufreq_hw 0>;
109 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
115 cache-size = <0x20000>;
121 cache-size = <0x400000>;
[all …]
H A Dsm6350.dtsi32 #clock-cells = <0>;
40 #clock-cells = <0>;
46 #size-cells = <0>;
48 CPU0: cpu@0 {
51 reg = <0x0 0x0>;
52 clocks = <&cpufreq_hw 0>;
57 qcom,freq-domain = <&cpufreq_hw 0>;
81 reg = <0x0 0x100>;
82 clocks = <&cpufreq_hw 0>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]