1 //===- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements NewValueJump pass in Hexagon.
10 // Ideally, we should merge this as a Peephole pass prior to register
11 // allocation, but because we have a spill in between the feeder and new value
12 // jump instructions, we are forced to write after register allocation.
13 // Having said that, we should re-attempt to pull this earlier at some point
14 // in future.
15
16 // The basic approach looks for sequence of predicated jump, compare instruction
17 // that generates the predicate and, the feeder to the predicate. Once it finds
18 // all, it collapses compare and jump instruction into a new value jump
19 // instructions.
20 //
21 //===----------------------------------------------------------------------===//
22
23 #include "llvm/InitializePasses.h"
24 #include "Hexagon.h"
25 #include "HexagonInstrInfo.h"
26 #include "HexagonRegisterInfo.h"
27 #include "HexagonSubtarget.h"
28 #include "llvm/ADT/Statistic.h"
29 #include "llvm/CodeGen/MachineBasicBlock.h"
30 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineInstr.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineOperand.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/TargetOpcodes.h"
38 #include "llvm/CodeGen/TargetRegisterInfo.h"
39 #include "llvm/CodeGen/TargetSubtargetInfo.h"
40 #include "llvm/IR/DebugLoc.h"
41 #include "llvm/MC/MCInstrDesc.h"
42 #include "llvm/Pass.h"
43 #include "llvm/Support/BranchProbability.h"
44 #include "llvm/Support/CommandLine.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/MathExtras.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include <cassert>
50 #include <cstdint>
51 #include <iterator>
52
53 using namespace llvm;
54
55 #define DEBUG_TYPE "hexagon-nvj"
56
57 STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created");
58
59 static cl::opt<int> DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden,
60 cl::desc("Maximum number of predicated jumps to be converted to "
61 "New Value Jump"));
62
63 static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden,
64 cl::desc("Disable New Value Jumps"));
65
66 namespace {
67
68 struct HexagonNewValueJump : public MachineFunctionPass {
69 static char ID;
70
HexagonNewValueJump__anon8d77136c0111::HexagonNewValueJump71 HexagonNewValueJump() : MachineFunctionPass(ID) {}
72
getAnalysisUsage__anon8d77136c0111::HexagonNewValueJump73 void getAnalysisUsage(AnalysisUsage &AU) const override {
74 AU.addRequired<MachineBranchProbabilityInfoWrapperPass>();
75 MachineFunctionPass::getAnalysisUsage(AU);
76 }
77
getPassName__anon8d77136c0111::HexagonNewValueJump78 StringRef getPassName() const override { return "Hexagon NewValueJump"; }
79
80 bool runOnMachineFunction(MachineFunction &Fn) override;
81
getRequiredProperties__anon8d77136c0111::HexagonNewValueJump82 MachineFunctionProperties getRequiredProperties() const override {
83 return MachineFunctionProperties().setNoVRegs();
84 }
85
86 private:
87 const HexagonInstrInfo *QII;
88 const HexagonRegisterInfo *QRI;
89
90 /// A handle to the branch probability pass.
91 const MachineBranchProbabilityInfo *MBPI;
92
93 bool isNewValueJumpCandidate(const MachineInstr &MI) const;
94 };
95
96 } // end anonymous namespace
97
98 char HexagonNewValueJump::ID = 0;
99
100 INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj",
101 "Hexagon NewValueJump", false, false)
INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfoWrapperPass)102 INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfoWrapperPass)
103 INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj",
104 "Hexagon NewValueJump", false, false)
105
106 // We have identified this II could be feeder to NVJ,
107 // verify that it can be.
108 static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII,
109 const TargetRegisterInfo *TRI,
110 MachineBasicBlock::iterator II,
111 MachineBasicBlock::iterator end,
112 MachineBasicBlock::iterator skip,
113 MachineFunction &MF) {
114 // Predicated instruction can not be feeder to NVJ.
115 if (QII->isPredicated(*II))
116 return false;
117
118 // Bail out if feederReg is a paired register (double regs in
119 // our case). One would think that we can check to see if a given
120 // register cmpReg1 or cmpReg2 is a sub register of feederReg
121 // using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic
122 // before the callsite of this function
123 // But we can not as it comes in the following fashion.
124 // %d0 = Hexagon_S2_lsr_r_p killed %d0, killed %r2
125 // %r0 = KILL %r0, implicit killed %d0
126 // %p0 = CMPEQri killed %r0, 0
127 // Hence, we need to check if it's a KILL instruction.
128 if (II->getOpcode() == TargetOpcode::KILL)
129 return false;
130
131 if (II->isImplicitDef())
132 return false;
133
134 if (QII->isSolo(*II))
135 return false;
136
137 if (QII->isFloat(*II))
138 return false;
139
140 // Make sure that the (unique) def operand is a register from IntRegs.
141 bool HadDef = false;
142 for (const MachineOperand &Op : II->operands()) {
143 if (!Op.isReg() || !Op.isDef())
144 continue;
145 if (HadDef)
146 return false;
147 HadDef = true;
148 if (!Hexagon::IntRegsRegClass.contains(Op.getReg()))
149 return false;
150 }
151 assert(HadDef);
152
153 // Make sure there is no 'def' or 'use' of any of the uses of
154 // feeder insn between its definition, this MI and jump, jmpInst
155 // skipping compare, cmpInst.
156 // Here's the example.
157 // r21=memub(r22+r24<<#0)
158 // p0 = cmp.eq(r21, #0)
159 // r4=memub(r3+r21<<#0)
160 // if (p0.new) jump:t .LBB29_45
161 // Without this check, it will be converted into
162 // r4=memub(r3+r21<<#0)
163 // r21=memub(r22+r24<<#0)
164 // p0 = cmp.eq(r21, #0)
165 // if (p0.new) jump:t .LBB29_45
166 // and result WAR hazards if converted to New Value Jump.
167 for (unsigned i = 0; i < II->getNumOperands(); ++i) {
168 if (II->getOperand(i).isReg() &&
169 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
170 MachineBasicBlock::iterator localII = II;
171 ++localII;
172 Register Reg = II->getOperand(i).getReg();
173 for (MachineBasicBlock::iterator localBegin = localII; localBegin != end;
174 ++localBegin) {
175 if (localBegin == skip)
176 continue;
177 // Check for Subregisters too.
178 if (localBegin->modifiesRegister(Reg, TRI) ||
179 localBegin->readsRegister(Reg, TRI))
180 return false;
181 }
182 }
183 }
184 return true;
185 }
186
187 // These are the common checks that need to performed
188 // to determine if
189 // 1. compare instruction can be moved before jump.
190 // 2. feeder to the compare instruction can be moved before jump.
commonChecksToProhibitNewValueJump(bool afterRA,MachineBasicBlock::iterator MII)191 static bool commonChecksToProhibitNewValueJump(bool afterRA,
192 MachineBasicBlock::iterator MII) {
193 // If store in path, bail out.
194 if (MII->mayStore())
195 return false;
196
197 // if call in path, bail out.
198 if (MII->isCall())
199 return false;
200
201 // if NVJ is running prior to RA, do the following checks.
202 if (!afterRA) {
203 // The following Target Opcode instructions are spurious
204 // to new value jump. If they are in the path, bail out.
205 // KILL sets kill flag on the opcode. It also sets up a
206 // single register, out of pair.
207 // %d0 = S2_lsr_r_p killed %d0, killed %r2
208 // %r0 = KILL %r0, implicit killed %d0
209 // %p0 = C2_cmpeqi killed %r0, 0
210 // PHI can be anything after RA.
211 // COPY can remateriaze things in between feeder, compare and nvj.
212 if (MII->getOpcode() == TargetOpcode::KILL ||
213 MII->getOpcode() == TargetOpcode::PHI ||
214 MII->getOpcode() == TargetOpcode::COPY)
215 return false;
216
217 // The following pseudo Hexagon instructions sets "use" and "def"
218 // of registers by individual passes in the backend. At this time,
219 // we don't know the scope of usage and definitions of these
220 // instructions.
221 if (MII->getOpcode() == Hexagon::LDriw_pred ||
222 MII->getOpcode() == Hexagon::STriw_pred)
223 return false;
224 }
225
226 return true;
227 }
228
canCompareBeNewValueJump(const HexagonInstrInfo * QII,const TargetRegisterInfo * TRI,MachineBasicBlock::iterator II,unsigned pReg,bool secondReg,bool optLocation,MachineBasicBlock::iterator end,MachineFunction & MF)229 static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
230 const TargetRegisterInfo *TRI,
231 MachineBasicBlock::iterator II,
232 unsigned pReg,
233 bool secondReg,
234 bool optLocation,
235 MachineBasicBlock::iterator end,
236 MachineFunction &MF) {
237 MachineInstr &MI = *II;
238
239 // If the second operand of the compare is an imm, make sure it's in the
240 // range specified by the arch.
241 if (!secondReg) {
242 const MachineOperand &Op2 = MI.getOperand(2);
243 if (!Op2.isImm())
244 return false;
245
246 int64_t v = Op2.getImm();
247 bool Valid = false;
248
249 switch (MI.getOpcode()) {
250 case Hexagon::C2_cmpeqi:
251 case Hexagon::C4_cmpneqi:
252 case Hexagon::C2_cmpgti:
253 case Hexagon::C4_cmpltei:
254 Valid = (isUInt<5>(v) || v == -1);
255 break;
256 case Hexagon::C2_cmpgtui:
257 case Hexagon::C4_cmplteui:
258 Valid = isUInt<5>(v);
259 break;
260 case Hexagon::S2_tstbit_i:
261 case Hexagon::S4_ntstbit_i:
262 Valid = (v == 0);
263 break;
264 }
265
266 if (!Valid)
267 return false;
268 }
269
270 unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning.
271 cmpReg1 = MI.getOperand(1).getReg();
272
273 if (secondReg) {
274 cmpOp2 = MI.getOperand(2).getReg();
275
276 // If the same register appears as both operands, we cannot generate a new
277 // value compare. Only one operand may use the .new suffix.
278 if (cmpReg1 == cmpOp2)
279 return false;
280
281 // Make sure that the second register is not from COPY
282 // at machine code level, we don't need this, but if we decide
283 // to move new value jump prior to RA, we would be needing this.
284 MachineRegisterInfo &MRI = MF.getRegInfo();
285 if (!Register::isPhysicalRegister(cmpOp2)) {
286 MachineInstr *def = MRI.getVRegDef(cmpOp2);
287 if (def->getOpcode() == TargetOpcode::COPY)
288 return false;
289 }
290 }
291
292 // Walk the instructions after the compare (predicate def) to the jump,
293 // and satisfy the following conditions.
294 ++II;
295 for (MachineBasicBlock::iterator localII = II; localII != end; ++localII) {
296 if (localII->isDebugInstr())
297 continue;
298
299 // Check 1.
300 // If "common" checks fail, bail out.
301 if (!commonChecksToProhibitNewValueJump(optLocation, localII))
302 return false;
303
304 // Check 2.
305 // If there is a def or use of predicate (result of compare), bail out.
306 if (localII->modifiesRegister(pReg, TRI) ||
307 localII->readsRegister(pReg, TRI))
308 return false;
309
310 // Check 3.
311 // If there is a def of any of the use of the compare (operands of compare),
312 // bail out.
313 // Eg.
314 // p0 = cmp.eq(r2, r0)
315 // r2 = r4
316 // if (p0.new) jump:t .LBB28_3
317 if (localII->modifiesRegister(cmpReg1, TRI) ||
318 (secondReg && localII->modifiesRegister(cmpOp2, TRI)))
319 return false;
320 }
321 return true;
322 }
323
324 // Given a compare operator, return a matching New Value Jump compare operator.
325 // Make sure that MI here is included in isNewValueJumpCandidate.
getNewValueJumpOpcode(MachineInstr * MI,int reg,bool secondRegNewified,MachineBasicBlock * jmpTarget,const MachineBranchProbabilityInfo * MBPI)326 static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg,
327 bool secondRegNewified,
328 MachineBasicBlock *jmpTarget,
329 const MachineBranchProbabilityInfo
330 *MBPI) {
331 bool taken = false;
332 MachineBasicBlock *Src = MI->getParent();
333 const BranchProbability Prediction =
334 MBPI->getEdgeProbability(Src, jmpTarget);
335
336 if (Prediction >= BranchProbability(1,2))
337 taken = true;
338
339 switch (MI->getOpcode()) {
340 case Hexagon::C2_cmpeq:
341 return taken ? Hexagon::J4_cmpeq_t_jumpnv_t
342 : Hexagon::J4_cmpeq_t_jumpnv_nt;
343
344 case Hexagon::C2_cmpeqi:
345 if (reg >= 0)
346 return taken ? Hexagon::J4_cmpeqi_t_jumpnv_t
347 : Hexagon::J4_cmpeqi_t_jumpnv_nt;
348 return taken ? Hexagon::J4_cmpeqn1_t_jumpnv_t
349 : Hexagon::J4_cmpeqn1_t_jumpnv_nt;
350
351 case Hexagon::C4_cmpneqi:
352 if (reg >= 0)
353 return taken ? Hexagon::J4_cmpeqi_f_jumpnv_t
354 : Hexagon::J4_cmpeqi_f_jumpnv_nt;
355 return taken ? Hexagon::J4_cmpeqn1_f_jumpnv_t :
356 Hexagon::J4_cmpeqn1_f_jumpnv_nt;
357
358 case Hexagon::C2_cmpgt:
359 if (secondRegNewified)
360 return taken ? Hexagon::J4_cmplt_t_jumpnv_t
361 : Hexagon::J4_cmplt_t_jumpnv_nt;
362 return taken ? Hexagon::J4_cmpgt_t_jumpnv_t
363 : Hexagon::J4_cmpgt_t_jumpnv_nt;
364
365 case Hexagon::C2_cmpgti:
366 if (reg >= 0)
367 return taken ? Hexagon::J4_cmpgti_t_jumpnv_t
368 : Hexagon::J4_cmpgti_t_jumpnv_nt;
369 return taken ? Hexagon::J4_cmpgtn1_t_jumpnv_t
370 : Hexagon::J4_cmpgtn1_t_jumpnv_nt;
371
372 case Hexagon::C2_cmpgtu:
373 if (secondRegNewified)
374 return taken ? Hexagon::J4_cmpltu_t_jumpnv_t
375 : Hexagon::J4_cmpltu_t_jumpnv_nt;
376 return taken ? Hexagon::J4_cmpgtu_t_jumpnv_t
377 : Hexagon::J4_cmpgtu_t_jumpnv_nt;
378
379 case Hexagon::C2_cmpgtui:
380 return taken ? Hexagon::J4_cmpgtui_t_jumpnv_t
381 : Hexagon::J4_cmpgtui_t_jumpnv_nt;
382
383 case Hexagon::C4_cmpneq:
384 return taken ? Hexagon::J4_cmpeq_f_jumpnv_t
385 : Hexagon::J4_cmpeq_f_jumpnv_nt;
386
387 case Hexagon::C4_cmplte:
388 if (secondRegNewified)
389 return taken ? Hexagon::J4_cmplt_f_jumpnv_t
390 : Hexagon::J4_cmplt_f_jumpnv_nt;
391 return taken ? Hexagon::J4_cmpgt_f_jumpnv_t
392 : Hexagon::J4_cmpgt_f_jumpnv_nt;
393
394 case Hexagon::C4_cmplteu:
395 if (secondRegNewified)
396 return taken ? Hexagon::J4_cmpltu_f_jumpnv_t
397 : Hexagon::J4_cmpltu_f_jumpnv_nt;
398 return taken ? Hexagon::J4_cmpgtu_f_jumpnv_t
399 : Hexagon::J4_cmpgtu_f_jumpnv_nt;
400
401 case Hexagon::C4_cmpltei:
402 if (reg >= 0)
403 return taken ? Hexagon::J4_cmpgti_f_jumpnv_t
404 : Hexagon::J4_cmpgti_f_jumpnv_nt;
405 return taken ? Hexagon::J4_cmpgtn1_f_jumpnv_t
406 : Hexagon::J4_cmpgtn1_f_jumpnv_nt;
407
408 case Hexagon::C4_cmplteui:
409 return taken ? Hexagon::J4_cmpgtui_f_jumpnv_t
410 : Hexagon::J4_cmpgtui_f_jumpnv_nt;
411
412 default:
413 llvm_unreachable("Could not find matching New Value Jump instruction.");
414 }
415 // return *some value* to avoid compiler warning
416 return 0;
417 }
418
isNewValueJumpCandidate(const MachineInstr & MI) const419 bool HexagonNewValueJump::isNewValueJumpCandidate(
420 const MachineInstr &MI) const {
421 switch (MI.getOpcode()) {
422 case Hexagon::C2_cmpeq:
423 case Hexagon::C2_cmpeqi:
424 case Hexagon::C2_cmpgt:
425 case Hexagon::C2_cmpgti:
426 case Hexagon::C2_cmpgtu:
427 case Hexagon::C2_cmpgtui:
428 case Hexagon::C4_cmpneq:
429 case Hexagon::C4_cmpneqi:
430 case Hexagon::C4_cmplte:
431 case Hexagon::C4_cmplteu:
432 case Hexagon::C4_cmpltei:
433 case Hexagon::C4_cmplteui:
434 return true;
435
436 default:
437 return false;
438 }
439 }
440
runOnMachineFunction(MachineFunction & MF)441 bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
442 LLVM_DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n"
443 << "********** Function: " << MF.getName() << "\n");
444
445 if (skipFunction(MF.getFunction()))
446 return false;
447
448 // If we move NewValueJump before register allocation we'll need live variable
449 // analysis here too.
450
451 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
452 QRI = static_cast<const HexagonRegisterInfo *>(
453 MF.getSubtarget().getRegisterInfo());
454 MBPI = &getAnalysis<MachineBranchProbabilityInfoWrapperPass>().getMBPI();
455
456 if (DisableNewValueJumps ||
457 !MF.getSubtarget<HexagonSubtarget>().useNewValueJumps())
458 return false;
459
460 int nvjCount = DbgNVJCount;
461 int nvjGenerated = 0;
462
463 // Loop through all the bb's of the function
464 for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
465 MBBb != MBBe; ++MBBb) {
466 MachineBasicBlock *MBB = &*MBBb;
467
468 LLVM_DEBUG(dbgs() << "** dumping bb ** " << MBB->getNumber() << "\n");
469 LLVM_DEBUG(MBB->dump());
470 LLVM_DEBUG(dbgs() << "\n"
471 << "********** dumping instr bottom up **********\n");
472 bool foundJump = false;
473 bool foundCompare = false;
474 bool invertPredicate = false;
475 unsigned predReg = 0; // predicate reg of the jump.
476 unsigned cmpReg1 = 0;
477 int cmpOp2 = 0;
478 MachineBasicBlock::iterator jmpPos;
479 MachineBasicBlock::iterator cmpPos;
480 MachineInstr *cmpInstr = nullptr, *jmpInstr = nullptr;
481 MachineBasicBlock *jmpTarget = nullptr;
482 bool afterRA = false;
483 bool isSecondOpReg = false;
484 bool isSecondOpNewified = false;
485 // Traverse the basic block - bottom up
486 for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
487 MII != E;) {
488 MachineInstr &MI = *--MII;
489 if (MI.isDebugInstr()) {
490 continue;
491 }
492
493 if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated))
494 break;
495
496 LLVM_DEBUG(dbgs() << "Instr: "; MI.dump(); dbgs() << "\n");
497
498 if (!foundJump && (MI.getOpcode() == Hexagon::J2_jumpt ||
499 MI.getOpcode() == Hexagon::J2_jumptpt ||
500 MI.getOpcode() == Hexagon::J2_jumpf ||
501 MI.getOpcode() == Hexagon::J2_jumpfpt ||
502 MI.getOpcode() == Hexagon::J2_jumptnewpt ||
503 MI.getOpcode() == Hexagon::J2_jumptnew ||
504 MI.getOpcode() == Hexagon::J2_jumpfnewpt ||
505 MI.getOpcode() == Hexagon::J2_jumpfnew)) {
506 // This is where you would insert your compare and
507 // instr that feeds compare
508 jmpPos = MII;
509 jmpInstr = &MI;
510 predReg = MI.getOperand(0).getReg();
511 afterRA = Register::isPhysicalRegister(predReg);
512
513 // If ifconverter had not messed up with the kill flags of the
514 // operands, the following check on the kill flag would suffice.
515 // if(!jmpInstr->getOperand(0).isKill()) break;
516
517 // This predicate register is live out of BB
518 // this would only work if we can actually use Live
519 // variable analysis on phy regs - but LLVM does not
520 // provide LV analysis on phys regs.
521 //if(LVs.isLiveOut(predReg, *MBB)) break;
522
523 // Get all the successors of this block - which will always
524 // be 2. Check if the predicate register is live-in in those
525 // successor. If yes, we can not delete the predicate -
526 // I am doing this only because LLVM does not provide LiveOut
527 // at the BB level.
528 bool predLive = false;
529 for (const MachineBasicBlock *SuccMBB : MBB->successors())
530 if (SuccMBB->isLiveIn(predReg))
531 predLive = true;
532 if (predLive)
533 break;
534
535 if (!MI.getOperand(1).isMBB())
536 continue;
537 jmpTarget = MI.getOperand(1).getMBB();
538 foundJump = true;
539 if (MI.getOpcode() == Hexagon::J2_jumpf ||
540 MI.getOpcode() == Hexagon::J2_jumpfnewpt ||
541 MI.getOpcode() == Hexagon::J2_jumpfnew) {
542 invertPredicate = true;
543 }
544 continue;
545 }
546
547 // No new value jump if there is a barrier. A barrier has to be in its
548 // own packet. A barrier has zero operands. We conservatively bail out
549 // here if we see any instruction with zero operands.
550 if (foundJump && MI.getNumOperands() == 0)
551 break;
552
553 if (foundJump && !foundCompare && MI.getOperand(0).isReg() &&
554 MI.getOperand(0).getReg() == predReg) {
555 // Not all compares can be new value compare. Arch Spec: 7.6.1.1
556 if (isNewValueJumpCandidate(MI)) {
557 assert(
558 (MI.getDesc().isCompare()) &&
559 "Only compare instruction can be collapsed into New Value Jump");
560 isSecondOpReg = MI.getOperand(2).isReg();
561
562 if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg,
563 afterRA, jmpPos, MF))
564 break;
565
566 cmpInstr = &MI;
567 cmpPos = MII;
568 foundCompare = true;
569
570 // We need cmpReg1 and cmpOp2(imm or reg) while building
571 // new value jump instruction.
572 cmpReg1 = MI.getOperand(1).getReg();
573
574 if (isSecondOpReg)
575 cmpOp2 = MI.getOperand(2).getReg();
576 else
577 cmpOp2 = MI.getOperand(2).getImm();
578 continue;
579 }
580 }
581
582 if (foundCompare && foundJump) {
583 // If "common" checks fail, bail out on this BB.
584 if (!commonChecksToProhibitNewValueJump(afterRA, MII))
585 break;
586
587 bool foundFeeder = false;
588 MachineBasicBlock::iterator feederPos = MII;
589 if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef() &&
590 (MI.getOperand(0).getReg() == cmpReg1 ||
591 (isSecondOpReg &&
592 MI.getOperand(0).getReg() == (unsigned)cmpOp2))) {
593
594 Register feederReg = MI.getOperand(0).getReg();
595
596 // First try to see if we can get the feeder from the first operand
597 // of the compare. If we can not, and if secondOpReg is true
598 // (second operand of the compare is also register), try that one.
599 // TODO: Try to come up with some heuristic to figure out which
600 // feeder would benefit.
601
602 if (feederReg == cmpReg1) {
603 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) {
604 if (!isSecondOpReg)
605 break;
606 else
607 continue;
608 } else
609 foundFeeder = true;
610 }
611
612 if (!foundFeeder && isSecondOpReg && feederReg == (unsigned)cmpOp2)
613 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF))
614 break;
615
616 if (isSecondOpReg) {
617 // In case of CMPLT, or CMPLTU, or EQ with the second register
618 // to newify, swap the operands.
619 unsigned COp = cmpInstr->getOpcode();
620 if ((COp == Hexagon::C2_cmpeq || COp == Hexagon::C4_cmpneq) &&
621 (feederReg == (unsigned)cmpOp2)) {
622 unsigned tmp = cmpReg1;
623 cmpReg1 = cmpOp2;
624 cmpOp2 = tmp;
625 }
626
627 // Now we have swapped the operands, all we need to check is,
628 // if the second operand (after swap) is the feeder.
629 // And if it is, make a note.
630 if (feederReg == (unsigned)cmpOp2)
631 isSecondOpNewified = true;
632 }
633
634 // Now that we are moving feeder close the jump,
635 // make sure we are respecting the kill values of
636 // the operands of the feeder.
637
638 auto TransferKills = [jmpPos,cmpPos] (MachineInstr &MI) {
639 for (MachineOperand &MO : MI.operands()) {
640 if (!MO.isReg() || !MO.isUse())
641 continue;
642 Register UseR = MO.getReg();
643 for (auto I = std::next(MI.getIterator()); I != jmpPos; ++I) {
644 if (I == cmpPos)
645 continue;
646 for (MachineOperand &Op : I->operands()) {
647 if (!Op.isReg() || !Op.isUse() || !Op.isKill())
648 continue;
649 if (Op.getReg() != UseR)
650 continue;
651 // We found that there is kill of a use register
652 // Set up a kill flag on the register
653 Op.setIsKill(false);
654 MO.setIsKill(true);
655 return;
656 }
657 }
658 }
659 };
660
661 TransferKills(*feederPos);
662 TransferKills(*cmpPos);
663 bool MO1IsKill = cmpPos->killsRegister(cmpReg1, QRI);
664 bool MO2IsKill = isSecondOpReg && cmpPos->killsRegister(cmpOp2, QRI);
665
666 MBB->splice(jmpPos, MI.getParent(), MI);
667 MBB->splice(jmpPos, MI.getParent(), cmpInstr);
668 DebugLoc dl = MI.getDebugLoc();
669 MachineInstr *NewMI;
670
671 assert((isNewValueJumpCandidate(*cmpInstr)) &&
672 "This compare is not a New Value Jump candidate.");
673 unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2,
674 isSecondOpNewified,
675 jmpTarget, MBPI);
676 if (invertPredicate)
677 opc = QII->getInvertedPredicatedOpcode(opc);
678
679 if (isSecondOpReg)
680 NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc))
681 .addReg(cmpReg1, getKillRegState(MO1IsKill))
682 .addReg(cmpOp2, getKillRegState(MO2IsKill))
683 .addMBB(jmpTarget);
684
685 else
686 NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc))
687 .addReg(cmpReg1, getKillRegState(MO1IsKill))
688 .addImm(cmpOp2)
689 .addMBB(jmpTarget);
690
691 assert(NewMI && "New Value Jump Instruction Not created!");
692 (void)NewMI;
693 if (cmpInstr->getOperand(0).isReg() &&
694 cmpInstr->getOperand(0).isKill())
695 cmpInstr->getOperand(0).setIsKill(false);
696 if (cmpInstr->getOperand(1).isReg() &&
697 cmpInstr->getOperand(1).isKill())
698 cmpInstr->getOperand(1).setIsKill(false);
699 cmpInstr->eraseFromParent();
700 jmpInstr->eraseFromParent();
701 ++nvjGenerated;
702 ++NumNVJGenerated;
703 break;
704 }
705 }
706 }
707 }
708
709 return true;
710 }
711
createHexagonNewValueJump()712 FunctionPass *llvm::createHexagonNewValueJump() {
713 return new HexagonNewValueJump();
714 }
715