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Searched refs:nb_number_memory_controllers (Results 1 – 5 of 5) sorted by relevance

/titanic_50/usr/src/uts/intel/io/intel_nb5000/
H A Dnb5000.h1182 (nb_number_memory_controllers == 2) ? \
1191 (nb_number_memory_controllers == 2) ? \
1199 (nb_number_memory_controllers == 2) ? \
1215 (nb_number_memory_controllers == 2) ? \
1226 } else if (nb_number_memory_controllers == 2) { \
1242 (nb_number_memory_controllers == 2) ? \
1246 (nb_number_memory_controllers == 2) ? \
1264 (nb_number_memory_controllers == 2) ? \
1268 (nb_number_memory_controllers == 2) ? \
1272 (nb_number_memory_controllers == 2) ? \
[all …]
H A Ddimm_addr.c97 last = nb_dimms_per_channel * nb_number_memory_controllers; in inb_patounum()
173 nb_number_memory_controllers * num_ranks_per_branch, KM_SLEEP); in dimm_init()
188 nb_number_memory_controllers * num_ranks_per_branch); in dimm_fini()
H A Dnb5000_init.c53 int nb_number_memory_controllers = NB_5000_MAX_MEM_CONTROLLERS; variable
245 int nchannels = nb_number_memory_controllers * nb_channels_per_branch; in nb_fini()
505 for (i = 0; i < nb_number_memory_controllers; i++) { in nb_mc_init()
631 for (i = 0; i < nb_number_memory_controllers; i++) { in find_dimms_per_channel()
793 nb_dimm_slots = nb_number_memory_controllers * nb_channels_per_branch * in nb_ddr2_dimms_init()
799 for (i = 0; i < nb_number_memory_controllers; i++) { in nb_ddr2_dimms_init()
860 nb_dimm_slots = nb_number_memory_controllers * 2 * nb_dimms_per_channel; in nb_fbd_dimms_init()
864 for (i = 0; i < nb_number_memory_controllers; i++) { in nb_fbd_dimms_init()
1539 nb_number_memory_controllers = 1; in nb_init()
1557 int nchannels = nb_number_memory_controllers * 2; in nb_dev_reinit()
H A Dintel_nbdrv.c226 int nchannels = nb_number_memory_controllers * nb_channels_per_branch; in inb_dimmlist()
313 (uint8_t)nb_number_memory_controllers); in inb_create_nvl()
H A Dnb_log.h262 extern int nb_number_memory_controllers;