1 /**************************************************************************
2 * forcedeth.c -- Etherboot device driver for the NVIDIA nForce
3 * media access controllers.
4 *
5 * Note: This driver is based on the Linux driver that was based on
6 * a cleanroom reimplementation which was based on reverse
7 * engineered documentation written by Carl-Daniel Hailfinger
8 * and Andrew de Quincey. It's neither supported nor endorsed
9 * by NVIDIA Corp. Use at your own risk.
10 *
11 * Written 2004 by Timothy Legge <tlegge@rogers.com>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 * Portions of this code based on:
28 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers:
29 *
30 * (C) 2003 Manfred Spraul
31 * See Linux Driver for full information
32 *
33 * Linux Driver Version 0.22, 19 Jan 2004
34 *
35 *
36 * REVISION HISTORY:
37 * ================
38 * v1.0 01-31-2004 timlegge Initial port of Linux driver
39 * v1.1 02-03-2004 timlegge Large Clean up, first release
40 *
41 * Indent Options: indent -kr -i8
42 ***************************************************************************/
43
44 /* to get some global routines like printf */
45 #include "etherboot.h"
46 /* to get the interface to the body of the program */
47 #include "nic.h"
48 /* to get the PCI support functions, if this is a PCI NIC */
49 #include "pci.h"
50 /* Include timer support functions */
51 #include "timer.h"
52
53 #define drv_version "v1.1"
54 #define drv_date "02-03-2004"
55
56 //#define TFTM_DEBUG
57 #ifdef TFTM_DEBUG
58 #define dprintf(x) printf x
59 #else
60 #define dprintf(x)
61 #endif
62
63 typedef unsigned char u8;
64 typedef signed char s8;
65 typedef unsigned short u16;
66 typedef signed short s16;
67 typedef unsigned int u32;
68 typedef signed int s32;
69
70 /* Condensed operations for readability. */
71 #define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
72 #define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
73
74 unsigned long BASE;
75 /* NIC specific static variables go here */
76
77
78 /*
79 * Hardware access:
80 */
81
82 #define DEV_NEED_LASTPACKET1 0x0001
83 #define DEV_IRQMASK_1 0x0002
84 #define DEV_IRQMASK_2 0x0004
85 #define DEV_NEED_TIMERIRQ 0x0008
86
87 enum {
88 NvRegIrqStatus = 0x000,
89 #define NVREG_IRQSTAT_MIIEVENT 0040
90 #define NVREG_IRQSTAT_MASK 0x1ff
91 NvRegIrqMask = 0x004,
92 #define NVREG_IRQ_RX 0x0002
93 #define NVREG_IRQ_RX_NOBUF 0x0004
94 #define NVREG_IRQ_TX_ERR 0x0008
95 #define NVREG_IRQ_TX2 0x0010
96 #define NVREG_IRQ_TIMER 0x0020
97 #define NVREG_IRQ_LINK 0x0040
98 #define NVREG_IRQ_TX1 0x0100
99 #define NVREG_IRQMASK_WANTED_1 0x005f
100 #define NVREG_IRQMASK_WANTED_2 0x0147
101 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR|NVREG_IRQ_TX2|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX1))
102
103 NvRegUnknownSetupReg6 = 0x008,
104 #define NVREG_UNKSETUP6_VAL 3
105
106 /*
107 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
108 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
109 */
110 NvRegPollingInterval = 0x00c,
111 #define NVREG_POLL_DEFAULT 970
112 NvRegMisc1 = 0x080,
113 #define NVREG_MISC1_HD 0x02
114 #define NVREG_MISC1_FORCE 0x3b0f3c
115
116 NvRegTransmitterControl = 0x084,
117 #define NVREG_XMITCTL_START 0x01
118 NvRegTransmitterStatus = 0x088,
119 #define NVREG_XMITSTAT_BUSY 0x01
120
121 NvRegPacketFilterFlags = 0x8c,
122 #define NVREG_PFF_ALWAYS 0x7F0008
123 #define NVREG_PFF_PROMISC 0x80
124 #define NVREG_PFF_MYADDR 0x20
125
126 NvRegOffloadConfig = 0x90,
127 #define NVREG_OFFLOAD_HOMEPHY 0x601
128 #define NVREG_OFFLOAD_NORMAL 0x5ee
129 NvRegReceiverControl = 0x094,
130 #define NVREG_RCVCTL_START 0x01
131 NvRegReceiverStatus = 0x98,
132 #define NVREG_RCVSTAT_BUSY 0x01
133
134 NvRegRandomSeed = 0x9c,
135 #define NVREG_RNDSEED_MASK 0x00ff
136 #define NVREG_RNDSEED_FORCE 0x7f00
137
138 NvRegUnknownSetupReg1 = 0xA0,
139 #define NVREG_UNKSETUP1_VAL 0x16070f
140 NvRegUnknownSetupReg2 = 0xA4,
141 #define NVREG_UNKSETUP2_VAL 0x16
142 NvRegMacAddrA = 0xA8,
143 NvRegMacAddrB = 0xAC,
144 NvRegMulticastAddrA = 0xB0,
145 #define NVREG_MCASTADDRA_FORCE 0x01
146 NvRegMulticastAddrB = 0xB4,
147 NvRegMulticastMaskA = 0xB8,
148 NvRegMulticastMaskB = 0xBC,
149
150 NvRegTxRingPhysAddr = 0x100,
151 NvRegRxRingPhysAddr = 0x104,
152 NvRegRingSizes = 0x108,
153 #define NVREG_RINGSZ_TXSHIFT 0
154 #define NVREG_RINGSZ_RXSHIFT 16
155 NvRegUnknownTransmitterReg = 0x10c,
156 NvRegLinkSpeed = 0x110,
157 #define NVREG_LINKSPEED_FORCE 0x10000
158 #define NVREG_LINKSPEED_10 10
159 #define NVREG_LINKSPEED_100 100
160 #define NVREG_LINKSPEED_1000 1000
161 NvRegUnknownSetupReg5 = 0x130,
162 #define NVREG_UNKSETUP5_BIT31 (1<<31)
163 NvRegUnknownSetupReg3 = 0x134,
164 #define NVREG_UNKSETUP3_VAL1 0x200010
165 NvRegTxRxControl = 0x144,
166 #define NVREG_TXRXCTL_KICK 0x0001
167 #define NVREG_TXRXCTL_BIT1 0x0002
168 #define NVREG_TXRXCTL_BIT2 0x0004
169 #define NVREG_TXRXCTL_IDLE 0x0008
170 #define NVREG_TXRXCTL_RESET 0x0010
171 NvRegMIIStatus = 0x180,
172 #define NVREG_MIISTAT_ERROR 0x0001
173 #define NVREG_MIISTAT_LINKCHANGE 0x0008
174 #define NVREG_MIISTAT_MASK 0x000f
175 #define NVREG_MIISTAT_MASK2 0x000f
176 NvRegUnknownSetupReg4 = 0x184,
177 #define NVREG_UNKSETUP4_VAL 8
178
179 NvRegAdapterControl = 0x188,
180 #define NVREG_ADAPTCTL_START 0x02
181 #define NVREG_ADAPTCTL_LINKUP 0x04
182 #define NVREG_ADAPTCTL_PHYVALID 0x4000
183 #define NVREG_ADAPTCTL_RUNNING 0x100000
184 #define NVREG_ADAPTCTL_PHYSHIFT 24
185 NvRegMIISpeed = 0x18c,
186 #define NVREG_MIISPEED_BIT8 (1<<8)
187 #define NVREG_MIIDELAY 5
188 NvRegMIIControl = 0x190,
189 #define NVREG_MIICTL_INUSE 0x10000
190 #define NVREG_MIICTL_WRITE 0x08000
191 #define NVREG_MIICTL_ADDRSHIFT 5
192 NvRegMIIData = 0x194,
193 NvRegWakeUpFlags = 0x200,
194 #define NVREG_WAKEUPFLAGS_VAL 0x7770
195 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
196 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
197 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
198 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
199 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
200 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
201 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
202 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
203 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
204
205 NvRegPatternCRC = 0x204,
206 NvRegPatternMask = 0x208,
207 NvRegPowerCap = 0x268,
208 #define NVREG_POWERCAP_D3SUPP (1<<30)
209 #define NVREG_POWERCAP_D2SUPP (1<<26)
210 #define NVREG_POWERCAP_D1SUPP (1<<25)
211 NvRegPowerState = 0x26c,
212 #define NVREG_POWERSTATE_POWEREDUP 0x8000
213 #define NVREG_POWERSTATE_VALID 0x0100
214 #define NVREG_POWERSTATE_MASK 0x0003
215 #define NVREG_POWERSTATE_D0 0x0000
216 #define NVREG_POWERSTATE_D1 0x0001
217 #define NVREG_POWERSTATE_D2 0x0002
218 #define NVREG_POWERSTATE_D3 0x0003
219 };
220
221
222
223 #define NV_TX_LASTPACKET (1<<0)
224 #define NV_TX_RETRYERROR (1<<3)
225 #define NV_TX_LASTPACKET1 (1<<8)
226 #define NV_TX_DEFERRED (1<<10)
227 #define NV_TX_CARRIERLOST (1<<11)
228 #define NV_TX_LATECOLLISION (1<<12)
229 #define NV_TX_UNDERFLOW (1<<13)
230 #define NV_TX_ERROR (1<<14)
231 #define NV_TX_VALID (1<<15)
232
233 #define NV_RX_DESCRIPTORVALID (1<<0)
234 #define NV_RX_MISSEDFRAME (1<<1)
235 #define NV_RX_SUBSTRACT1 (1<<3)
236 #define NV_RX_ERROR1 (1<<7)
237 #define NV_RX_ERROR2 (1<<8)
238 #define NV_RX_ERROR3 (1<<9)
239 #define NV_RX_ERROR4 (1<<10)
240 #define NV_RX_CRCERR (1<<11)
241 #define NV_RX_OVERFLOW (1<<12)
242 #define NV_RX_FRAMINGERR (1<<13)
243 #define NV_RX_ERROR (1<<14)
244 #define NV_RX_AVAIL (1<<15)
245
246 /* Miscelaneous hardware related defines: */
247 #define NV_PCI_REGSZ 0x270
248
249 /* various timeout delays: all in usec */
250 #define NV_TXRX_RESET_DELAY 4
251 #define NV_TXSTOP_DELAY1 10
252 #define NV_TXSTOP_DELAY1MAX 500000
253 #define NV_TXSTOP_DELAY2 100
254 #define NV_RXSTOP_DELAY1 10
255 #define NV_RXSTOP_DELAY1MAX 500000
256 #define NV_RXSTOP_DELAY2 100
257 #define NV_SETUP5_DELAY 5
258 #define NV_SETUP5_DELAYMAX 50000
259 #define NV_POWERUP_DELAY 5
260 #define NV_POWERUP_DELAYMAX 5000
261 #define NV_MIIBUSY_DELAY 50
262 #define NV_MIIPHY_DELAY 10
263 #define NV_MIIPHY_DELAYMAX 10000
264
265 #define NV_WAKEUPPATTERNS 5
266 #define NV_WAKEUPMASKENTRIES 4
267
268 /* General driver defaults */
269 #define NV_WATCHDOG_TIMEO (2*HZ)
270 #define DEFAULT_MTU 1500 /* also maximum supported, at least for now */
271
272 #define RX_RING 4
273 #define TX_RING 2
274 /* limited to 1 packet until we understand NV_TX_LASTPACKET */
275 #define TX_LIMIT_STOP 10
276 #define TX_LIMIT_START 5
277
278 /* rx/tx mac addr + type + vlan + align + slack*/
279 #define RX_NIC_BUFSIZE (DEFAULT_MTU + 64)
280 /* even more slack */
281 #define RX_ALLOC_BUFSIZE (DEFAULT_MTU + 128)
282
283 #define OOM_REFILL (1+HZ/20)
284 #define POLL_WAIT (1+HZ/100)
285
286 struct ring_desc {
287 u32 PacketBuffer;
288 u16 Length;
289 u16 Flags;
290 };
291
292
293 /* Define the TX Descriptor */
294 static struct ring_desc tx_ring[TX_RING];
295
296 /* Create a static buffer of size RX_BUF_SZ for each
297 TX Descriptor. All descriptors point to a
298 part of this buffer */
299 static unsigned char txb[TX_RING * RX_NIC_BUFSIZE];
300
301 /* Define the TX Descriptor */
302 static struct ring_desc rx_ring[RX_RING];
303
304 /* Create a static buffer of size RX_BUF_SZ for each
305 RX Descriptor All descriptors point to a
306 part of this buffer */
307 static unsigned char rxb[RX_RING * RX_NIC_BUFSIZE];
308
309 /* Private Storage for the NIC */
310 struct forcedeth_private {
311 /* General data:
312 * Locking: spin_lock(&np->lock); */
313 int in_shutdown;
314 u32 linkspeed;
315 int duplex;
316 int phyaddr;
317
318 /* General data: RO fields */
319 u8 *ring_addr;
320 u32 orig_mac[2];
321 u32 irqmask;
322 /* rx specific fields.
323 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
324 */
325 struct ring_desc *rx_ring;
326 unsigned int cur_rx, refill_rx;
327 struct sk_buff *rx_skbuff[RX_RING];
328 u32 rx_dma[RX_RING];
329 unsigned int rx_buf_sz;
330
331 /*
332 * tx specific fields.
333 */
334 struct ring_desc *tx_ring;
335 unsigned int next_tx, nic_tx;
336 struct sk_buff *tx_skbuff[TX_RING];
337 u32 tx_dma[TX_RING];
338 u16 tx_flags;
339 } npx;
340
341 static struct forcedeth_private *np;
342
pci_push(u8 * base)343 static inline void pci_push(u8 * base)
344 {
345 /* force out pending posted writes */
346 readl(base);
347 }
reg_delay(int offset,u32 mask,u32 target,int delay,int delaymax,const char * msg)348 static int reg_delay(int offset, u32 mask,
349 u32 target, int delay, int delaymax, const char *msg)
350 {
351 u8 *base = (u8 *) BASE;
352
353 pci_push(base);
354 do {
355 udelay(delay);
356 delaymax -= delay;
357 if (delaymax < 0) {
358 if (msg)
359 printf(msg);
360 return 1;
361 }
362 } while ((readl(base + offset) & mask) != target);
363 return 0;
364 }
365
366 #define MII_READ (-1)
367 #define MII_PHYSID1 0x02 /* PHYS ID 1 */
368 #define MII_PHYSID2 0x03 /* PHYS ID 2 */
369 #define MII_BMCR 0x00 /* Basic mode control register */
370 #define MII_BMSR 0x01 /* Basic mode status register */
371 #define MII_ADVERTISE 0x04 /* Advertisement control reg */
372 #define MII_LPA 0x05 /* Link partner ability reg */
373
374 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
375
376 /* Link partner ability register. */
377 #define LPA_SLCT 0x001f /* Same as advertise selector */
378 #define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
379 #define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
380 #define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
381 #define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
382 #define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
383 #define LPA_RESV 0x1c00 /* Unused... */
384 #define LPA_RFAULT 0x2000 /* Link partner faulted */
385 #define LPA_LPACK 0x4000 /* Link partner acked us */
386 #define LPA_NPAGE 0x8000 /* Next page bit */
387
388 /* mii_rw: read/write a register on the PHY.
389 *
390 * Caller must guarantee serialization
391 */
mii_rw(struct nic * nic __unused,int addr,int miireg,int value)392 static int mii_rw(struct nic *nic __unused, int addr, int miireg,
393 int value)
394 {
395 u8 *base = (u8 *) BASE;
396 int was_running;
397 u32 reg;
398 int retval;
399
400 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
401 was_running = 0;
402 reg = readl(base + NvRegAdapterControl);
403 if (reg & NVREG_ADAPTCTL_RUNNING) {
404 was_running = 1;
405 writel(reg & ~NVREG_ADAPTCTL_RUNNING,
406 base + NvRegAdapterControl);
407 }
408 reg = readl(base + NvRegMIIControl);
409 if (reg & NVREG_MIICTL_INUSE) {
410 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
411 udelay(NV_MIIBUSY_DELAY);
412 }
413
414 reg =
415 NVREG_MIICTL_INUSE | (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
416 if (value != MII_READ) {
417 writel(value, base + NvRegMIIData);
418 reg |= NVREG_MIICTL_WRITE;
419 }
420 writel(reg, base + NvRegMIIControl);
421
422 if (reg_delay(NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
423 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
424 dprintf(("mii_rw of reg %d at PHY %d timed out.\n",
425 miireg, addr));
426 retval = -1;
427 } else if (value != MII_READ) {
428 /* it was a write operation - fewer failures are detectable */
429 dprintf(("mii_rw wrote 0x%x to reg %d at PHY %d\n",
430 value, miireg, addr));
431 retval = 0;
432 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
433 dprintf(("mii_rw of reg %d at PHY %d failed.\n",
434 miireg, addr));
435 retval = -1;
436 } else {
437 /* FIXME: why is that required? */
438 udelay(50);
439 retval = readl(base + NvRegMIIData);
440 dprintf(("mii_rw read from reg %d at PHY %d: 0x%x.\n",
441 miireg, addr, retval));
442 }
443 if (was_running) {
444 reg = readl(base + NvRegAdapterControl);
445 writel(reg | NVREG_ADAPTCTL_RUNNING,
446 base + NvRegAdapterControl);
447 }
448 return retval;
449 }
450
start_rx(struct nic * nic __unused)451 static void start_rx(struct nic *nic __unused)
452 {
453 u8 *base = (u8 *) BASE;
454
455 dprintf(("start_rx\n"));
456 /* Already running? Stop it. */
457 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
458 writel(0, base + NvRegReceiverControl);
459 pci_push(base);
460 }
461 writel(np->linkspeed, base + NvRegLinkSpeed);
462 pci_push(base);
463 writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
464 pci_push(base);
465 }
466
stop_rx(void)467 static void stop_rx(void)
468 {
469 u8 *base = (u8 *) BASE;
470
471 dprintf(("stop_rx\n"));
472 writel(0, base + NvRegReceiverControl);
473 reg_delay(NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
474 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
475 "stop_rx: ReceiverStatus remained busy");
476
477 udelay(NV_RXSTOP_DELAY2);
478 writel(0, base + NvRegLinkSpeed);
479 }
480
start_tx(struct nic * nic __unused)481 static void start_tx(struct nic *nic __unused)
482 {
483 u8 *base = (u8 *) BASE;
484
485 dprintf(("start_tx\n"));
486 writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
487 pci_push(base);
488 }
489
stop_tx(void)490 static void stop_tx(void)
491 {
492 u8 *base = (u8 *) BASE;
493
494 dprintf(("stop_tx\n"));
495 writel(0, base + NvRegTransmitterControl);
496 reg_delay(NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
497 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
498 "stop_tx: TransmitterStatus remained busy");
499
500 udelay(NV_TXSTOP_DELAY2);
501 writel(0, base + NvRegUnknownTransmitterReg);
502 }
503
504
txrx_reset(struct nic * nic __unused)505 static void txrx_reset(struct nic *nic __unused)
506 {
507 u8 *base = (u8 *) BASE;
508
509 dprintf(("txrx_reset\n"));
510 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET,
511 base + NvRegTxRxControl);
512 pci_push(base);
513 udelay(NV_TXRX_RESET_DELAY);
514 writel(NVREG_TXRXCTL_BIT2, base + NvRegTxRxControl);
515 pci_push(base);
516 }
517
518 /*
519 * alloc_rx: fill rx ring entries.
520 * Return 1 if the allocations for the skbs failed and the
521 * rx engine is without Available descriptors
522 */
alloc_rx(struct nic * nic __unused)523 static int alloc_rx(struct nic *nic __unused)
524 {
525 unsigned int refill_rx = np->refill_rx;
526 int i;
527 //while (np->cur_rx != refill_rx) {
528 for (i = 0; i < RX_RING; i++) {
529 //int nr = refill_rx % RX_RING;
530 rx_ring[i].PacketBuffer =
531 virt_to_le32desc(&rxb[i * RX_NIC_BUFSIZE]);
532 rx_ring[i].Length = cpu_to_le16(RX_NIC_BUFSIZE);
533 wmb();
534 rx_ring[i].Flags = cpu_to_le16(NV_RX_AVAIL);
535 /* printf("alloc_rx: Packet %d marked as Available\n",
536 refill_rx); */
537 refill_rx++;
538 }
539 np->refill_rx = refill_rx;
540 if (np->cur_rx - refill_rx == RX_RING)
541 return 1;
542 return 0;
543 }
544
update_linkspeed(struct nic * nic)545 static int update_linkspeed(struct nic *nic)
546 {
547 int adv, lpa, newdup;
548 u32 newls;
549 adv = mii_rw(nic, np->phyaddr, MII_ADVERTISE, MII_READ);
550 lpa = mii_rw(nic, np->phyaddr, MII_LPA, MII_READ);
551 dprintf(("update_linkspeed: PHY advertises 0x%hX, lpa 0x%hX.\n",
552 adv, lpa));
553
554 /* FIXME: handle parallel detection properly, handle gigabit ethernet */
555 lpa = lpa & adv;
556 if (lpa & LPA_100FULL) {
557 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_100;
558 newdup = 1;
559 } else if (lpa & LPA_100HALF) {
560 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_100;
561 newdup = 0;
562 } else if (lpa & LPA_10FULL) {
563 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
564 newdup = 1;
565 } else if (lpa & LPA_10HALF) {
566 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
567 newdup = 0;
568 } else {
569 printf("bad ability %hX - falling back to 10HD.\n", lpa);
570 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
571 newdup = 0;
572 }
573 if (np->duplex != newdup || np->linkspeed != newls) {
574 np->duplex = newdup;
575 np->linkspeed = newls;
576 return 1;
577 }
578 return 0;
579 }
580
581
582
init_ring(struct nic * nic)583 static int init_ring(struct nic *nic)
584 {
585 int i;
586
587 np->next_tx = np->nic_tx = 0;
588 for (i = 0; i < TX_RING; i++) {
589 tx_ring[i].Flags = 0;
590 }
591
592 np->cur_rx = 0;
593 np->refill_rx = 0;
594 for (i = 0; i < RX_RING; i++) {
595 rx_ring[i].Flags = 0;
596 }
597 return alloc_rx(nic);
598 }
599
set_multicast(struct nic * nic)600 static void set_multicast(struct nic *nic)
601 {
602
603 u8 *base = (u8 *) BASE;
604 u32 addr[2];
605 u32 mask[2];
606 u32 pff;
607 u32 alwaysOff[2];
608 u32 alwaysOn[2];
609
610 memset(addr, 0, sizeof(addr));
611 memset(mask, 0, sizeof(mask));
612
613 pff = NVREG_PFF_MYADDR;
614
615 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
616
617 addr[0] = alwaysOn[0];
618 addr[1] = alwaysOn[1];
619 mask[0] = alwaysOn[0] | alwaysOff[0];
620 mask[1] = alwaysOn[1] | alwaysOff[1];
621
622 addr[0] |= NVREG_MCASTADDRA_FORCE;
623 pff |= NVREG_PFF_ALWAYS;
624 stop_rx();
625 writel(addr[0], base + NvRegMulticastAddrA);
626 writel(addr[1], base + NvRegMulticastAddrB);
627 writel(mask[0], base + NvRegMulticastMaskA);
628 writel(mask[1], base + NvRegMulticastMaskB);
629 writel(pff, base + NvRegPacketFilterFlags);
630 start_rx(nic);
631 }
632
633 /**************************************************************************
634 RESET - Reset the NIC to prepare for use
635 ***************************************************************************/
forcedeth_reset(struct nic * nic)636 static int forcedeth_reset(struct nic *nic)
637 {
638 u8 *base = (u8 *) BASE;
639 int ret, oom, i;
640 ret = 0;
641 dprintf(("forcedeth: open\n"));
642
643 /* 1) erase previous misconfiguration */
644 /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
645 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
646 writel(0, base + NvRegMulticastAddrB);
647 writel(0, base + NvRegMulticastMaskA);
648 writel(0, base + NvRegMulticastMaskB);
649 writel(0, base + NvRegPacketFilterFlags);
650 writel(0, base + NvRegAdapterControl);
651 writel(0, base + NvRegLinkSpeed);
652 writel(0, base + NvRegUnknownTransmitterReg);
653 txrx_reset(nic);
654 writel(0, base + NvRegUnknownSetupReg6);
655
656 /* 2) initialize descriptor rings */
657 np->in_shutdown = 0;
658 oom = init_ring(nic);
659
660 /* 3) set mac address */
661 {
662 u32 mac[2];
663
664 mac[0] =
665 (nic->node_addr[0] << 0) + (nic->node_addr[1] << 8) +
666 (nic->node_addr[2] << 16) + (nic->node_addr[3] << 24);
667 mac[1] =
668 (nic->node_addr[4] << 0) + (nic->node_addr[5] << 8);
669
670 writel(mac[0], base + NvRegMacAddrA);
671 writel(mac[1], base + NvRegMacAddrB);
672 }
673
674 /* 4) continue setup */
675 np->linkspeed = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
676 np->duplex = 0;
677 writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
678 writel(0, base + NvRegTxRxControl);
679 pci_push(base);
680 writel(NVREG_TXRXCTL_BIT1, base + NvRegTxRxControl);
681
682 reg_delay(NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31,
683 NVREG_UNKSETUP5_BIT31, NV_SETUP5_DELAY,
684 NV_SETUP5_DELAYMAX,
685 "open: SetupReg5, Bit 31 remained off\n");
686 writel(0, base + NvRegUnknownSetupReg4);
687
688 /* 5) Find a suitable PHY */
689 writel(NVREG_MIISPEED_BIT8 | NVREG_MIIDELAY, base + NvRegMIISpeed);
690 for (i = 1; i < 32; i++) {
691 int id1, id2;
692
693 id1 = mii_rw(nic, i, MII_PHYSID1, MII_READ);
694 if (id1 < 0)
695 continue;
696 id2 = mii_rw(nic, i, MII_PHYSID2, MII_READ);
697 if (id2 < 0)
698 continue;
699 dprintf(("open: Found PHY %04x:%04x at address %d.\n",
700 id1, id2, i));
701 np->phyaddr = i;
702
703 update_linkspeed(nic);
704
705 break;
706 }
707 if (i == 32) {
708 printf("open: failing due to lack of suitable PHY.\n");
709 ret = -1;
710 goto out_drain;
711 }
712
713 printf("%d-Mbs Link, %s-Duplex\n",
714 np->linkspeed & NVREG_LINKSPEED_10 ? 10 : 100,
715 np->duplex ? "Full" : "Half");
716 /* 6) continue setup */
717 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
718 base + NvRegMisc1);
719 writel(readl(base + NvRegTransmitterStatus),
720 base + NvRegTransmitterStatus);
721 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
722 writel(NVREG_OFFLOAD_NORMAL, base + NvRegOffloadConfig);
723
724 writel(readl(base + NvRegReceiverStatus),
725 base + NvRegReceiverStatus);
726
727 /* FIXME: I cheated and used the calculator to get a random number */
728 i = 75963081;
729 writel(NVREG_RNDSEED_FORCE | (i & NVREG_RNDSEED_MASK),
730 base + NvRegRandomSeed);
731 writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
732 writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
733 writel(NVREG_POLL_DEFAULT, base + NvRegPollingInterval);
734 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
735 writel((np->
736 phyaddr << NVREG_ADAPTCTL_PHYSHIFT) |
737 NVREG_ADAPTCTL_PHYVALID, base + NvRegAdapterControl);
738 writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
739 writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
740
741 /* 7) start packet processing */
742 writel((u32) virt_to_le32desc(&rx_ring[0]),
743 base + NvRegRxRingPhysAddr);
744 writel((u32) virt_to_le32desc(&tx_ring[0]),
745 base + NvRegTxRingPhysAddr);
746
747
748 writel(((RX_RING - 1) << NVREG_RINGSZ_RXSHIFT) +
749 ((TX_RING - 1) << NVREG_RINGSZ_TXSHIFT),
750 base + NvRegRingSizes);
751
752 i = readl(base + NvRegPowerState);
753 if ((i & NVREG_POWERSTATE_POWEREDUP) == 0) {
754 writel(NVREG_POWERSTATE_POWEREDUP | i,
755 base + NvRegPowerState);
756 }
757 pci_push(base);
758 udelay(10);
759 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID,
760 base + NvRegPowerState);
761 writel(NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
762
763 writel(0, base + NvRegIrqMask);
764 pci_push(base);
765 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
766 pci_push(base);
767 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
768 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
769 pci_push(base);
770 /*
771 writel(np->irqmask, base + NvRegIrqMask);
772 */
773 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
774 writel(0, base + NvRegMulticastAddrB);
775 writel(0, base + NvRegMulticastMaskA);
776 writel(0, base + NvRegMulticastMaskB);
777 writel(NVREG_PFF_ALWAYS | NVREG_PFF_MYADDR,
778 base + NvRegPacketFilterFlags);
779
780 set_multicast(nic);
781 //start_rx(nic);
782 start_tx(nic);
783
784 if (!
785 (mii_rw(nic, np->phyaddr, MII_BMSR, MII_READ) &
786 BMSR_ANEGCOMPLETE)) {
787 printf("no link during initialization.\n");
788 }
789
790 udelay(10000);
791 out_drain:
792 return ret;
793 }
794
795 //extern void hex_dump(const char *data, const unsigned int len);
796
797 /**************************************************************************
798 POLL - Wait for a frame
799 ***************************************************************************/
forcedeth_poll(struct nic * nic,int retrieve)800 static int forcedeth_poll(struct nic *nic, int retrieve)
801 {
802 /* return true if there's an ethernet packet ready to read */
803 /* nic->packet should contain data on return */
804 /* nic->packetlen should contain length of data */
805
806 struct ring_desc *prd;
807 int len;
808 int i;
809
810 i = np->cur_rx % RX_RING;
811 prd = &rx_ring[i];
812
813 if ( ! (prd->Flags & cpu_to_le16(NV_RX_DESCRIPTORVALID)) ) {
814 return 0;
815 }
816
817 if ( ! retrieve ) return 1;
818
819 /* got a valid packet - forward it to the network core */
820 len = cpu_to_le16(prd->Length);
821 nic->packetlen = len;
822 //hex_dump(rxb + (i * RX_NIC_BUFSIZE), len);
823 memcpy(nic->packet, rxb +
824 (i * RX_NIC_BUFSIZE), nic->packetlen);
825
826 wmb();
827 np->cur_rx++;
828 alloc_rx(nic);
829 return 1;
830 }
831
832
833 /**************************************************************************
834 TRANSMIT - Transmit a frame
835 ***************************************************************************/
forcedeth_transmit(struct nic * nic,const char * d,unsigned int t,unsigned int s,const char * p)836 static void forcedeth_transmit(struct nic *nic, const char *d, /* Destination */
837 unsigned int t, /* Type */
838 unsigned int s, /* size */
839 const char *p)
840 { /* Packet */
841 /* send the packet to destination */
842 u8 *ptxb;
843 u16 nstype;
844 //u16 status;
845 u8 *base = (u8 *) BASE;
846 int nr = np->next_tx % TX_RING;
847
848 /* point to the current txb incase multiple tx_rings are used */
849 ptxb = txb + (nr * RX_NIC_BUFSIZE);
850 //np->tx_skbuff[nr] = ptxb;
851
852 /* copy the packet to ring buffer */
853 memcpy(ptxb, d, ETH_ALEN); /* dst */
854 memcpy(ptxb + ETH_ALEN, nic->node_addr, ETH_ALEN); /* src */
855 nstype = htons((u16) t); /* type */
856 memcpy(ptxb + 2 * ETH_ALEN, (u8 *) & nstype, 2); /* type */
857 memcpy(ptxb + ETH_HLEN, p, s);
858
859 s += ETH_HLEN;
860 while (s < ETH_ZLEN) /* pad to min length */
861 ptxb[s++] = '\0';
862
863 tx_ring[nr].PacketBuffer = (u32) virt_to_le32desc(ptxb);
864 tx_ring[nr].Length = cpu_to_le16(s - 1);
865
866 wmb();
867 tx_ring[nr].Flags = np->tx_flags;
868
869 writel(NVREG_TXRXCTL_KICK, base + NvRegTxRxControl);
870 pci_push(base);
871 tx_ring[nr].Flags = np->tx_flags;
872 np->next_tx++;
873 }
874
875 /**************************************************************************
876 DISABLE - Turn off ethernet interface
877 ***************************************************************************/
forcedeth_disable(struct dev * dev __unused)878 static void forcedeth_disable(struct dev *dev __unused)
879 {
880 /* put the card in its initial state */
881 /* This function serves 3 purposes.
882 * This disables DMA and interrupts so we don't receive
883 * unexpected packets or interrupts from the card after
884 * etherboot has finished.
885 * This frees resources so etherboot may use
886 * this driver on another interface
887 * This allows etherboot to reinitialize the interface
888 * if something is something goes wrong.
889 */
890 u8 *base = (u8 *) BASE;
891 np->in_shutdown = 1;
892 stop_tx();
893 stop_rx();
894
895 /* disable interrupts on the nic or we will lock up */
896 writel(0, base + NvRegIrqMask);
897 pci_push(base);
898 dprintf(("Irqmask is zero again\n"));
899
900 /* specia op:o write back the misordered MAC address - otherwise
901 * the next probe_nic would see a wrong address.
902 */
903 writel(np->orig_mac[0], base + NvRegMacAddrA);
904 writel(np->orig_mac[1], base + NvRegMacAddrB);
905 }
906
907 /**************************************************************************
908 IRQ - Enable, Disable, or Force interrupts
909 ***************************************************************************/
forcedeth_irq(struct nic * nic __unused,irq_action_t action __unused)910 static void forcedeth_irq(struct nic *nic __unused, irq_action_t action __unused)
911 {
912 switch ( action ) {
913 case DISABLE :
914 break;
915 case ENABLE :
916 break;
917 case FORCE :
918 break;
919 }
920 }
921
922 /**************************************************************************
923 PROBE - Look for an adapter, this routine's visible to the outside
924 ***************************************************************************/
925 #define IORESOURCE_MEM 0x00000200
926 #define board_found 1
927 #define valid_link 0
forcedeth_probe(struct dev * dev,struct pci_device * pci)928 static int forcedeth_probe(struct dev *dev, struct pci_device *pci)
929 {
930 struct nic *nic = (struct nic *) dev;
931 unsigned long addr;
932 int sz;
933 u8 *base;
934
935 if (pci->ioaddr == 0)
936 return 0;
937
938 printf("forcedeth.c: Found %s, vendor=0x%hX, device=0x%hX\n",
939 pci->name, pci->vendor, pci->dev_id);
940
941 nic->irqno = 0;
942 nic->ioaddr = pci->ioaddr & ~3;
943
944 /* point to private storage */
945 np = &npx;
946
947 adjust_pci_device(pci);
948
949 addr = pci_bar_start(pci, PCI_BASE_ADDRESS_0);
950 sz = pci_bar_size(pci, PCI_BASE_ADDRESS_0);
951
952 /* BASE is used throughout to address the card */
953 BASE = (unsigned long) ioremap(addr, sz);
954 if (!BASE)
955 return 0;
956 //rx_ring[0] = rx_ring;
957 //tx_ring[0] = tx_ring;
958
959 /* read the mac address */
960 base = (u8 *) BASE;
961 np->orig_mac[0] = readl(base + NvRegMacAddrA);
962 np->orig_mac[1] = readl(base + NvRegMacAddrB);
963
964 nic->node_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
965 nic->node_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
966 nic->node_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
967 nic->node_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
968 nic->node_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
969 nic->node_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
970 #ifdef LINUX
971 if (!is_valid_ether_addr(dev->dev_addr)) {
972 /*
973 * Bad mac address. At least one bios sets the mac address
974 * to 01:23:45:67:89:ab
975 */
976 printk(KERN_ERR
977 "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
978 pci_name(pci_dev), dev->dev_addr[0],
979 dev->dev_addr[1], dev->dev_addr[2],
980 dev->dev_addr[3], dev->dev_addr[4],
981 dev->dev_addr[5]);
982 printk(KERN_ERR
983 "Please complain to your hardware vendor. Switching to a random MAC.\n");
984 dev->dev_addr[0] = 0x00;
985 dev->dev_addr[1] = 0x00;
986 dev->dev_addr[2] = 0x6c;
987 get_random_bytes(&dev->dev_addr[3], 3);
988 }
989 #endif
990 printf("%s: MAC Address %!, ", pci->name, nic->node_addr);
991
992 np->tx_flags =
993 cpu_to_le16(NV_TX_LASTPACKET | NV_TX_LASTPACKET1 |
994 NV_TX_VALID);
995 switch (pci->dev_id) {
996 case 0x01C3: // nforce
997 np->irqmask = NVREG_IRQMASK_WANTED_2;
998 np->irqmask |= NVREG_IRQ_TIMER;
999 break;
1000 case 0x0066: // nforce2
1001 np->tx_flags |= cpu_to_le16(NV_TX_LASTPACKET1);
1002 np->irqmask = NVREG_IRQMASK_WANTED_2;
1003 np->irqmask |= NVREG_IRQ_TIMER;
1004 break;
1005 case 0x00D6: // nforce3
1006 np->tx_flags |= cpu_to_le16(NV_TX_LASTPACKET1);
1007 np->irqmask = NVREG_IRQMASK_WANTED_2;
1008 np->irqmask |= NVREG_IRQ_TIMER;
1009
1010 }
1011 dprintf(("%s: forcedeth.c: subsystem: %hX:%hX bound to %s\n",
1012 pci->name, pci->vendor, pci->dev_id, pci->name));
1013
1014 forcedeth_reset(nic);
1015 // if (board_found && valid_link)
1016 /* point to NIC specific routines */
1017 dev->disable = forcedeth_disable;
1018 nic->poll = forcedeth_poll;
1019 nic->transmit = forcedeth_transmit;
1020 nic->irq = forcedeth_irq;
1021 return 1;
1022 // }
1023 /* else */
1024 }
1025
1026 static struct pci_id forcedeth_nics[] = {
1027 PCI_ROM(0x10de, 0x01C3, "nforce", "nForce Ethernet Controller"),
1028 PCI_ROM(0x10de, 0x0066, "nforce2", "nForce2 Ethernet Controller"),
1029 PCI_ROM(0x10de, 0x00D6, "nforce3", "nForce3 Ethernet Controller"),
1030 };
1031
1032 struct pci_driver forcedeth_driver = {
1033 .type = NIC_DRIVER,
1034 .name = "forcedeth",
1035 .probe = forcedeth_probe,
1036 .ids = forcedeth_nics,
1037 .id_count = sizeof(forcedeth_nics) / sizeof(forcedeth_nics[0]),
1038 .class = 0,
1039 };
1040