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Searched refs:MDIO_WC_REG_XGXSBLK1_LANECTRL2 (Results 1 – 2 of 2) sorted by relevance

/titanic_50/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A Dclc_reg.h544 #define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017 macro
/titanic_50/usr/src/uts/common/io/bnxe/577xx/common/
H A Dbnxe_clc.c4923 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00); in elink_warpcore_link_reset()
4975 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16); in elink_set_warpcore_loopback()
4980 MDIO_WC_REG_XGXSBLK1_LANECTRL2, in elink_set_warpcore_loopback()