| /titanic_50/usr/src/uts/sparc/sys/ |
| H A D | machlock.h | 63 #define SPIN_LOCK(pl) ((pl) > ipltospl(LOCK_LEVEL))
103 #define LOCK_LEVEL 10 macro
104 #define DISP_LEVEL (LOCK_LEVEL + 1)
106 #define HIGH_LEVELS (PIL_MAX - LOCK_LEVEL)
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| /titanic_50/usr/src/uts/intel/sys/ |
| H A D | machlock.h | 67 #define SPIN_LOCK(pl) ((pl) > ipltospl(LOCK_LEVEL))
112 #define LOCK_LEVEL 10 macro
113 #define DISP_LEVEL (LOCK_LEVEL + 1)
115 #define HIGH_LEVELS (PIL_MAX - LOCK_LEVEL)
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| H A D | acpica.h | 69 #define SCI_IPL (LOCK_LEVEL-1)
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| /titanic_50/usr/src/uts/sun4/os/ |
| H A D | cpu_states.c | 132 abort_seq_inum = add_softintr(LOCK_LEVEL, in abort_sequence_init()
149 on_intr = CPU_ON_INTR(CPU) || (spltoipl(s) > LOCK_LEVEL); in abort_sequence_enter()
234 if (getpil() > LOCK_LEVEL) { in debug_enter()
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| H A D | machdep.c | 535 ASSERT(t->t_pil > 0 && t->t_pil <= LOCK_LEVEL); in cpu_intr_swtch_enter()
576 ASSERT(t->t_pil > 0 && t->t_pil <= LOCK_LEVEL); in cpu_intr_swtch_exit()
887 lbolt_softint_inum = add_softintr(LOCK_LEVEL, in lbolt_softint_add()
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| /titanic_50/usr/src/uts/common/io/ |
| H A D | avintr.c | 86 struct av_head softvect[LOCK_LEVEL + 1];
257 if (((hi_pri > LOCK_LEVEL) && (lvl < LOCK_LEVEL)) || in add_avintr()
258 ((hi_pri < LOCK_LEVEL) && (lvl > LOCK_LEVEL))) { in add_avintr()
326 if (lvl <= 0 || lvl > LOCK_LEVEL) { in add_avsoftintr()
438 if (lvl <= 0 && lvl >= LOCK_LEVEL) { in av_rem_softintr()
718 if (av->av_ticksp && av->av_prilevel <= LOCK_LEVEL) in av_dispatch_autovect()
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| /titanic_50/usr/src/uts/i86pc/io/apix/ |
| H A D | apix_intr.c | 210 if (av->av_ticksp && av->av_prilevel <= LOCK_LEVEL) in apix_dispatch_pending_autovect()
450 mcpu->pil_high_start[nestpil - (LOCK_LEVEL + 1)]; in apix_hilevel_intr_prolog()
470 mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)] = now; in apix_hilevel_intr_prolog()
520 ASSERT(mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)] != 0); in apix_hilevel_intr_epilog()
522 intrtime = now - mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)]; in apix_hilevel_intr_epilog()
540 mcpu->pil_high_start[nestpil - (LOCK_LEVEL + 1)] = now; in apix_hilevel_intr_epilog()
586 ASSERT(newipl > LOCK_LEVEL && newipl > cpu->cpu_base_spl); in apix_do_pending_hilevel()
793 ASSERT(newipl <= LOCK_LEVEL); in apix_do_pending_hardint()
962 } else if (newipl > LOCK_LEVEL) { in apix_do_interrupt()
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| /titanic_50/usr/src/uts/i86pc/os/ |
| H A D | intr.c | 534 ASSERT(pil > LOCK_LEVEL); in hilevel_intr_prolog()
563 mcpu->pil_high_start[nestpil - (LOCK_LEVEL + 1)]; in hilevel_intr_prolog()
591 mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)] = now; in hilevel_intr_prolog()
653 ASSERT(mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)] != 0); in hilevel_intr_epilog()
655 intrtime = now - mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)]; in hilevel_intr_epilog()
673 mcpu->pil_high_start[nestpil - (LOCK_LEVEL + 1)] = now; in hilevel_intr_epilog()
1211 ASSERT(t->t_pil > 0 && t->t_pil <= LOCK_LEVEL); in cpu_intr_swtch_enter()
1250 ASSERT(t->t_pil > 0 && t->t_pil <= LOCK_LEVEL); in cpu_intr_swtch_exit()
1385 if (newipl > LOCK_LEVEL) { in do_interrupt()
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| H A D | mp_startup.c | 368 cp->cpu_base_spl = ipltospl(LOCK_LEVEL); in mp_cpu_configure_common()
1723 splx(ipltospl(LOCK_LEVEL)); in mp_startup_common()
1806 ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL)); in mp_startup_common()
2041 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); in cpu_sep_enable()
2050 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); in cpu_sep_disable()
2063 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); in cpu_asysc_enable()
2073 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); in cpu_asysc_disable()
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| /titanic_50/usr/src/uts/sun4/ml/ |
| H A D | interrupt.s | 149 cmp %g4, LOCK_LEVEL
150 bg,a,pt %xcc, 3f ! branch if pil > LOCK_LEVEL
940 sub %o2, LOCK_LEVEL + 1, %o5
952 sub %o2, LOCK_LEVEL + 1, %o5
1042 add %o1, LOCK_LEVEL + 1, %o1
1060 ! with %o4, which has (PIL - (LOCK_LEVEL + 1)) * 8. We need PIL * 16,
1061 ! so we shift left 1, then add (LOCK_LEVEL + 1) * 16, which is
1242 sub %o2, LOCK_LEVEL + 1, %o4 ! PIL to array index
1249 ! ASSERT(cpu.cpu_m.pil_high_start[pil - (LOCK_LEVEL + 1)] != 0)
1289 srl %l2, LOCK_LEVEL + 1, %l2
[all …]
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| H A D | genconst.c | 123 printf("#define\tCPU_INTRSTAT_LOW_PIL_OFFSET %d\n", (LOCK_LEVEL + 1) * in main()
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| /titanic_50/usr/src/uts/i86pc/sys/ |
| H A D | clock.h | 78 #define CBE_LOCK_PIL LOCK_LEVEL
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| H A D | machcpuvar.h | 152 #define NINTR_THREADS (LOCK_LEVEL-1) /* number of interrupt threads */
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| H A D | apix.h | 146 ((ipl) <= LOCK_LEVEL ? \
148 ((apixp)->x_intr_pending >> (LOCK_LEVEL + 1)))
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| /titanic_50/usr/src/uts/sun4/sys/ |
| H A D | clock.h | 75 #define CBE_LOCK_PIL LOCK_LEVEL
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| /titanic_50/usr/src/uts/common/os/ |
| H A D | mutex.c | 572 if ((intptr_t)ibc > ipltospl(LOCK_LEVEL) && ibc < (void *)KERNELBASE) { in mutex_init()
694 ASSERT(new_pil > LOCK_LEVEL); in lock_set_spl_spin()
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| H A D | panic.c | 252 cp->cpu_intr_actv &= ((1 << (LOCK_LEVEL + 1)) - 1); in panicsys()
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| /titanic_50/usr/src/cmd/mdb/i86pc/modules/common/ |
| H A D | intr_common.c | 32 static struct av_head softvec_tbl[LOCK_LEVEL + 1];
109 for (i = 0; i < LOCK_LEVEL + 1; i++) { in soft_interrupt_dump()
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| /titanic_50/usr/src/uts/i86pc/ml/ |
| H A D | genassym.c | 73 printf("#define\tLOCK_LEVEL 0x%x\n", LOCK_LEVEL); in main()
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| /titanic_50/usr/src/uts/sun4u/sys/ |
| H A D | machcpuvar.h | 148 #define NINTR_THREADS (LOCK_LEVEL) /* number of interrupt threads */
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| /titanic_50/usr/src/uts/sun4v/sys/ |
| H A D | machcpuvar.h | 191 #define NINTR_THREADS (LOCK_LEVEL) /* number of interrupt threads */
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| /titanic_50/usr/src/uts/common/ipp/ |
| H A D | ippconf.c | 278 (void *)ipltospl(LOCK_LEVEL)); in ipp_init()
1700 (void *)ipltospl(LOCK_LEVEL)); in ipp_stat_create()
3277 (void *)ipltospl(LOCK_LEVEL)); in init_mods()
3292 (void *)ipltospl(LOCK_LEVEL)); in init_mods()
3308 (void *)ipltospl(LOCK_LEVEL)); in init_actions()
3325 (void *)ipltospl(LOCK_LEVEL)); in init_actions()
3384 (void *)ipltospl(LOCK_LEVEL)); in mod_constructor()
3468 (void *)ipltospl(LOCK_LEVEL)); in action_constructor()
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| H A D | ipp_impl.h | 117 (void *)ipltospl(LOCK_LEVEL)); \
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| /titanic_50/usr/src/uts/sun4/io/px/ |
| H A D | px_debug.c | 242 if (getpil() > LOCK_LEVEL) in px_dbg()
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| /titanic_50/usr/src/uts/common/sys/ |
| H A D | cpuvar.h | 274 #define CPU_ON_INTR(cpup) ((cpup)->cpu_intr_actv >> (LOCK_LEVEL + 1))
287 ((level) <= LOCK_LEVEL ? \
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