Home
last modified time | relevance | path

Searched refs:B3_RI_WTO_XS2 (Results 1 – 2 of 2) sorted by relevance

/titanic_50/usr/src/uts/common/io/yge/
H A Dyge.h340 #define B3_RI_WTO_XS2 0x0198 /* 8 bit WR Timeout Queue XS2 (TO8) */ macro
H A Dyge.c809 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), RI_TO_53); in yge_reset()