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Searched refs:t1_write_reg_4 (Results 1 – 15 of 15) sorted by relevance

/titanic_44/usr/src/uts/common/io/chxge/com/
H A Dtp.c64 t1_write_reg_4(adapter, A_TP_PM_SIZE, p->pm_size); in tp_pm_configure()
65 t1_write_reg_4(adapter, A_TP_PM_RX_BASE, p->pm_rx_base); in tp_pm_configure()
66 t1_write_reg_4(adapter, A_TP_PM_TX_BASE, p->pm_tx_base); in tp_pm_configure()
67 t1_write_reg_4(adapter, A_TP_PM_DEFRAG_BASE, p->pm_size); in tp_pm_configure()
68 t1_write_reg_4(adapter, A_TP_PM_RX_PG_SIZE, p->pm_rx_pg_size); in tp_pm_configure()
69 t1_write_reg_4(adapter, A_TP_PM_RX_MAX_PGS, p->pm_rx_num_pgs); in tp_pm_configure()
70 t1_write_reg_4(adapter, A_TP_PM_TX_PG_SIZE, p->pm_tx_pg_size); in tp_pm_configure()
71 t1_write_reg_4(adapter, A_TP_PM_TX_MAX_PGS, p->pm_tx_num_pgs); in tp_pm_configure()
79 t1_write_reg_4(adapter, A_TP_CM_SIZE, cm_size); in tp_cm_configure()
80 t1_write_reg_4(adapter, A_TP_CM_MM_BASE, mm_base); in tp_cm_configure()
[all …]
H A Despi.c54 t1_write_reg_4(adapter, A_ESPI_CMD_ADDR, V_WRITE_DATA(wr_data) | in tricn_write()
59 t1_write_reg_4(adapter, A_ESPI_GOSTAT, 0); in tricn_write()
77 t1_write_reg_4(adapter, A_ESPI_CMD_ADDR,
82 t1_write_reg_4(adapter, A_ESPI_GOSTAT, 0);
106 t1_write_reg_4(adapter, A_ESPI_RX_RESET, F_ESPI_RX_CORE_RST); in tricn_init()
122 t1_write_reg_4(adapter, A_ESPI_RX_RESET, F_ESPI_RX_CORE_RST | F_ESPI_RX_LNK_RST); in tricn_init()
139 t1_write_reg_4(espi->adapter, A_ESPI_INTR_ENABLE, enable); in t1_espi_intr_enable()
140 t1_write_reg_4(espi->adapter, A_PL_ENABLE, pl_intr | F_PL_INTR_ESPI); in t1_espi_intr_enable()
146 t1_write_reg_4(espi->adapter, A_ESPI_INTR_STATUS, 0xffffffff); in t1_espi_intr_clear()
147 t1_write_reg_4(espi->adapter, A_PL_CAUSE, F_PL_INTR_ESPI); in t1_espi_intr_clear()
[all …]
H A Dmc5.c129 t1_write_reg_4(adapter, A_MC5_DBGI_REQ_CMD, cmd); in mc5_cmd_write()
143 t1_write_reg_4(mc5->adapter, A_MC5_ROUTING_TABLE_INDEX, rtbl_base); in set_tcam_rtbl_base()
163 t1_write_reg_4(mc5->adapter, A_MC5_SERVER_INDEX, server_base); in set_tcam_server_base()
182 t1_write_reg_4(adapter, A_MC5_DBGI_REQ_ADDR0, v1); in dbgi_wr_addr3()
183 t1_write_reg_4(adapter, A_MC5_DBGI_REQ_ADDR1, v2); in dbgi_wr_addr3()
184 t1_write_reg_4(adapter, A_MC5_DBGI_REQ_ADDR2, v3); in dbgi_wr_addr3()
189 t1_write_reg_4(adapter, A_MC5_DBGI_REQ_DATA0, v1); in dbgi_wr_data3()
190 t1_write_reg_4(adapter, A_MC5_DBGI_REQ_DATA1, v2); in dbgi_wr_data3()
191 t1_write_reg_4(adapter, A_MC5_DBGI_REQ_DATA2, v3); in dbgi_wr_data3()
208 t1_write_reg_4(adapter, A_MC5_DBGI_REQ_ADDR0, addr_lo); in mc5_write()
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H A Dmc3.c51 t1_write_reg_4(mc3->adapter, A_MC3_INT_ENABLE, MC3_INTR_MASK); in t1_mc3_intr_enable()
52 t1_write_reg_4(mc3->adapter, A_PL_ENABLE, en | F_PL_INTR_MC3); in t1_mc3_intr_enable()
55 t1_write_reg_4(mc3->adapter, FPGA_MC3_REG_INTRENABLE, in t1_mc3_intr_enable()
57 t1_write_reg_4(mc3->adapter, A_PL_ENABLE, in t1_mc3_intr_enable()
68 t1_write_reg_4(mc3->adapter, A_MC3_INT_ENABLE, 0); in t1_mc3_intr_disable()
69 t1_write_reg_4(mc3->adapter, A_PL_ENABLE, in t1_mc3_intr_disable()
73 t1_write_reg_4(mc3->adapter, FPGA_MC3_REG_INTRENABLE, 0); in t1_mc3_intr_disable()
74 t1_write_reg_4(mc3->adapter, A_PL_ENABLE, in t1_mc3_intr_disable()
91 t1_write_reg_4(mc3->adapter, A_MC3_INT_ENABLE, in t1_mc3_intr_clear()
93 t1_write_reg_4(mc3->adapter, A_MC3_INT_ENABLE, old_en); in t1_mc3_intr_clear()
[all …]
H A Dulp.c49 t1_write_reg_4(ulp->adapter, A_ULP_INT_ENABLE, ULP_INTR_MASK); in t1_ulp_intr_enable()
50 t1_write_reg_4(ulp->adapter, A_PL_ENABLE, in t1_ulp_intr_enable()
58 t1_write_reg_4(ulp->adapter, A_PL_CAUSE, F_PL_INTR_ULP); in t1_ulp_intr_clear()
59 t1_write_reg_4(ulp->adapter, A_ULP_INT_CAUSE, 0xffffffff); in t1_ulp_intr_clear()
68 t1_write_reg_4(ulp->adapter, A_PL_ENABLE, in t1_ulp_intr_disable()
70 t1_write_reg_4(ulp->adapter, A_ULP_INT_ENABLE, 0); in t1_ulp_intr_disable()
115 t1_write_reg_4(ulp->adapter, A_ULP_INT_CAUSE, cause); in t1_ulp_intr_handler()
135 t1_write_reg_4(adapter, A_ULP_HREG_INDEX, i); in t1_ulp_init()
136 t1_write_reg_4(adapter, A_ULP_HREG_DATA, 0); in t1_ulp_init()
139 t1_write_reg_4(adapter, A_ULP_ULIMIT, pm_tx_base); in t1_ulp_init()
[all …]
H A Dmc4.c68 t1_write_reg_4(adapter, addr, val); in wrreg_wait()
92 t1_write_reg_4(adapter, A_MC4_CFG, val | F_POWER_UP); in t1_mc4_init()
103 t1_write_reg_4(adapter, A_MC4_STROBE, in t1_mc4_init()
116 t1_write_reg_4(adapter, A_MC4_STROBE, in t1_mc4_init()
159 t1_write_reg_4(adapter, A_MC4_REFRESH, in t1_mc4_init()
163 t1_write_reg_4(adapter, A_MC4_ECC_CNTL, in t1_mc4_init()
167 t1_write_reg_4(adapter, A_MC4_BIST_ADDR_BEG, 0); in t1_mc4_init()
168 t1_write_reg_4(adapter, A_MC4_BIST_ADDR_END, (mc4->size << width) - 1); in t1_mc4_init()
169 t1_write_reg_4(adapter, A_MC4_BIST_DATA, 0); in t1_mc4_init()
170 t1_write_reg_4(adapter, A_MC4_BIST_OP, V_OP(1) | 0x1f0); in t1_mc4_init()
[all …]
H A Dch_mac.c94 t1_write_reg_4(mac->adapter, A_PL_ENABLE, mac_intr); in mac_intr_enable()
99 t1_write_reg_4(mac->adapter, in mac_intr_enable()
120 t1_write_reg_4(mac->adapter, A_PL_ENABLE, mac_intr); in mac_intr_disable()
125 t1_write_reg_4(mac->adapter, in mac_intr_disable()
144 t1_write_reg_4(mac->adapter, A_PL_CAUSE, in mac_intr_clear()
150 t1_write_reg_4(mac->adapter, in mac_intr_clear()
182 t1_write_reg_4(mac->adapter, MAC_REG_CSR(idx), in mac_reset()
211 t1_write_reg_4(mac->adapter, in mac_set_rx_mode()
248 t1_write_reg_4(mac->adapter, in mac_set_speed_duplex_fc()
263 t1_write_reg_4(mac->adapter, in mac_enable()
[all …]
H A Dcspi.c38 t1_write_reg_4(cspi->adapter, A_CSPI_INTR_ENABLE, 0xffffffff); in t1_cspi_intr_enable()
44 t1_write_reg_4(cspi->adapter, A_CSPI_INTR_ENABLE, 0); in t1_cspi_intr_disable()
62 t1_write_reg_4(adapter, A_CSPI_CALENDAR_LEN, 15); in t1_cspi_init()
63 t1_write_reg_4(adapter, A_CSPI_FIFO_STATUS_ENABLE, 1); in t1_cspi_init()
H A Dch_subr.c90 t1_write_reg_4(adapter, A_TPI_ADDR, addr); in __t1_tpi_write()
91 t1_write_reg_4(adapter, A_TPI_WR_DATA, value); in __t1_tpi_write()
92 t1_write_reg_4(adapter, A_TPI_CSR, F_TPIWR); in __t1_tpi_write()
121 t1_write_reg_4(adapter, A_TPI_ADDR, addr); in __t1_tpi_read()
122 t1_write_reg_4(adapter, A_TPI_CSR, 0); in __t1_tpi_read()
151 t1_write_reg_4(adapter, A_TPI_PAR, V_TPIPAR(value)); in t1_tpi_par()
217 t1_write_reg_4(adapter, FPGA_GMAC_ADDR_INTERRUPT_CAUSE, cause); in fpga_phy_intr_handler()
247 t1_write_reg_4(adapter, FPGA_TP_ADDR_INTERRUPT_CAUSE, in fpga_slow_intr()
259 t1_write_reg_4(adapter, A_PL_CAUSE, cause); in fpga_slow_intr()
270 t1_write_reg_4(adapter, A_MI0_CLK, V_MI0_CLK_DIV(3)); in fpga_mdio_init()
[all …]
H A Dpm3393.c169 t1_write_reg_4(cmac->adapter, A_PL_ENABLE, pl_intr); in pm3393_interrupt_enable()
251 t1_write_reg_4(cmac->adapter, A_PL_CAUSE, pl_intr); in pm3393_interrupt_clear()
/titanic_44/usr/src/uts/common/io/chxge/
H A Dsge.c125 t1_write_reg_4(sge->obj, A_SG_DOORBELL, control_reg); in sge_ring_doorbell()
264 t1_write_reg_4(sge->obj, A_SG_CONTROL, sge->sge_control); in sge_start()
284 t1_write_reg_4(sge->obj, A_SG_CONTROL, 0x0); in sge_stop()
290 t1_write_reg_4(sge->obj, A_SG_INT_CAUSE, status); in sge_stop()
509 t1_write_reg_4(sge->obj, A_PL_ENABLE, val & ~SGE_PL_INTR_MASK); in t1_sge_intr_disable()
510 t1_write_reg_4(sge->obj, A_SG_INT_ENABLE, 0); in t1_sge_intr_disable()
526 t1_write_reg_4(sge->obj, A_PL_ENABLE, val | SGE_PL_INTR_MASK); in t1_sge_intr_enable()
530 t1_write_reg_4(sge->obj, A_SG_INT_ENABLE, en); in t1_sge_intr_enable()
540 t1_write_reg_4(sge->obj, A_PL_CAUSE, SGE_PL_INTR_MASK); in t1_sge_intr_clear()
541 t1_write_reg_4(sge->obj, A_SG_INT_CAUSE, 0xffffffff); in t1_sge_intr_clear()
[all …]
H A Dglue.c96 t1_write_reg_4(ch_t *obj, uint32_t reg_val, uint32_t write_val) in t1_write_reg_4() function
244 t1_write_reg_4(chp, pe->addr, pe->pe_reg_val); in pe_ioctl()
H A Dpe.c1519 t1_write_reg_4(adapter, A_PL_CAUSE, F_PL_INTR_EXT); in ext_intr_task()
1521 t1_write_reg_4(adapter, A_PL_ENABLE, enable | F_PL_INTR_EXT); in ext_intr_task()
1534 t1_write_reg_4(adapter, A_PL_ENABLE, enable & ~F_PL_INTR_EXT); in t1_os_elmer0_ext_intr()
1598 t1_write_reg_4(adapter, MTUREG(i), mtu); in update_mtu_tab()
H A Dch.h286 void t1_write_reg_4(ch_t *obj, uint32_t reg_val, uint32_t write_val);
H A Dch.c768 t1_write_reg_4(chp->sge->obj, A_SG_CONTROL, 0x0); in ch_quiesce()
769 t1_write_reg_4(chp->sge->obj, A_SG_INT_CAUSE, 0x0); in ch_quiesce()