1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at 9 * http://www.opensource.org/licenses/cddl1.txt. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2004-2011 Emulex. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _EMLXS_DFC_H 28 #define _EMLXS_DFC_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #include <sys/fibre-channel/fcio.h> 35 #include <emlxs_fcio.h> 36 37 #define DFC_REV 1 38 39 #ifdef DHCHAP_SUPPORT 40 #undef DFC_REV 41 #define DFC_REV 2 /* DHCHAP_SUPPORT */ 42 #endif /* DHCHAP_SUPPORT */ 43 44 #undef DFC_REV 45 #define DFC_REV 3 /* NPIV_SUPPORT */ 46 47 48 typedef struct dfc 49 { 50 uint32_t cmd; 51 uint32_t flag; 52 53 void *buf1; 54 uint32_t buf1_size; 55 uint32_t data1; 56 57 void *buf2; 58 uint32_t buf2_size; 59 uint32_t data2; 60 61 void *buf3; 62 uint32_t buf3_size; 63 uint32_t data3; 64 65 void *buf4; 66 uint32_t buf4_size; 67 uint32_t data4; 68 } dfc_t; 69 70 71 /* 72 * 32 bit varient of dfc_t to be used only in the driver and NOT applications 73 */ 74 typedef struct dfc32 75 { 76 uint32_t cmd; 77 uint32_t flag; 78 79 uint32_t buf1; 80 uint32_t buf1_size; 81 uint32_t data1; 82 83 uint32_t buf2; 84 uint32_t buf2_size; 85 uint32_t data2; 86 87 uint32_t buf3; 88 uint32_t buf3_size; 89 uint32_t data3; 90 91 uint32_t buf4; 92 uint32_t buf4_size; 93 uint32_t data4; 94 95 } dfc32_t; 96 97 98 #ifdef SAN_DIAG_SUPPORT 99 typedef struct sd_bucket_info 100 { 101 uint16_t type; 102 uint16_t search_type; 103 uint32_t base; 104 uint32_t step; 105 uint16_t state; 106 uint64_t values[SD_IO_LATENCY_MAX_BUCKETS]; 107 } sd_bucket_info_t; 108 #endif 109 110 /* Valid dfc.dfc_cmd codes (DFC_REV=1) */ 111 #define EMLXS_GET_HBAINFO 1 112 #define EMLXS_GET_IOINFO 2 113 #define EMLXS_GET_LINKINFO 3 114 #define EMLXS_GET_NODEINFO 4 115 #define EMLXS_GET_EVENTINFO 5 116 #define EMLXS_GET_REV 6 117 #define EMLXS_GET_DUMPREGION 7 118 #define EMLXS_GET_HBASTATS 8 119 #define EMLXS_GET_DRVSTATS 9 120 121 /* FCIO_SUPPORT */ 122 #define EMLXS_FCIO_CMD 10 123 124 #define EMLXS_GET_CFG 15 125 #define EMLXS_SET_CFG 16 126 #define EMLXS_GET_EVENT 17 127 #define EMLXS_SET_EVENT 18 128 129 #define EMLXS_SEND_MBOX 20 130 #define EMLXS_SEND_ELS 21 131 #define EMLXS_SEND_CT 22 132 #define EMLXS_SEND_CT_RSP 23 133 #define EMLXS_SEND_MENLO 24 134 #define EMLXS_SEND_SCSI 25 135 136 #define EMLXS_SET_DIAG 30 137 #define EMLXS_LOOPBACK_MODE 31 138 #define EMLXS_LOOPBACK_TEST 32 139 #define EMLXS_RESET_PORT 33 140 141 #define EMLXS_READ_PCI 40 142 #define EMLXS_WRITE_PCI 41 143 #define EMLXS_WRITE_FLASH 42 144 #define EMLXS_READ_FLASH 43 145 #define EMLXS_READ_MEM 44 146 #define EMLXS_WRITE_MEM 45 147 #define EMLXS_WRITE_CTLREG 46 148 #define EMLXS_READ_CTLREG 47 149 150 151 /* NPIV_SUPPORT */ 152 #define EMLXS_CREATE_VPORT 50 153 #define EMLXS_DESTROY_VPORT 51 154 #define EMLXS_GET_VPORTINFO 52 155 #define EMLXS_NPIV_RESOURCE 53 156 #define EMLXS_NPIV_TEST 54 157 158 /* DHCHAP_SUPPORT */ 159 #define EMLXS_INIT_AUTH 60 160 #define EMLXS_GET_AUTH_CFG 61 161 #define EMLXS_SET_AUTH_CFG 62 162 #define EMLXS_GET_AUTH_PASSWORD 63 163 #define EMLXS_SET_AUTH_PASSWORD 64 164 #define EMLXS_GET_AUTH_STATUS 65 165 #define EMLXS_GET_AUTH_CFG_TABLE 66 166 #define EMLXS_GET_AUTH_KEY_TABLE 67 167 168 /* SFCT_SUPPORT */ 169 #define EMLXS_GET_FCTSTAT 70 170 171 #define EMLXS_GET_PERSIST_LINKDOWN 71 172 #define EMLXS_SET_PERSIST_LINKDOWN 72 173 174 /* FCOE_SUPPORT */ 175 #define EMLXS_GET_FCOE_FCFLIST 80 176 #define EMLXS_SEND_MBOX4 81 177 #define EMLXS_RD_BE_FCF 82 178 #define EMLXS_SET_BE_DCBX 83 179 #define EMLXS_GET_BE_DCBX 84 180 #define EMLXS_GET_QOS 85 181 182 /* SAN DIAG SUPPORT */ 183 #define EMLXS_SD_SET_BUCKET 100 184 #define EMLXS_SD_START_DATA_COLLECTION 101 185 #define EMLXS_SD_STOP_DATA_COLLECTION 102 186 #define EMLXS_SD_RESET_DATA_COLLECTION 103 187 #define EMLXS_SD_GET_DATA 104 188 #define EMLXS_SD_DESTROY_BUCKET 105 189 #define EMLXS_SD_GET_BUCKET 106 190 #define EMLXS_SD_SET_EVENT 107 191 #define EMLXS_SD_GET_EVENT 108 192 193 194 195 /* EMLXS_SET_AUTH_CFG - flags */ 196 #define EMLXS_AUTH_CFG_ADD 0 197 #define EMLXS_AUTH_CFG_DELETE 1 198 199 /* ERROR Codes */ 200 #define DFC_ERRNO_START 0x200 201 202 #define DFC_SUCCESS 0 203 #define DFC_SYS_ERROR (DFC_ERRNO_START + 1) /* General system err */ 204 #define DFC_DRV_ERROR (DFC_ERRNO_START + 2) /* General driver err */ 205 #define DFC_HBA_ERROR (DFC_ERRNO_START + 3) /* General HBA err */ 206 #define DFC_IO_ERROR (DFC_ERRNO_START + 4) /* General IO err */ 207 208 #define DFC_ARG_INVALID (DFC_ERRNO_START + 5) /* Invalid Argument */ 209 #define DFC_ARG_MISALIGNED (DFC_ERRNO_START + 6) /* Misaligned Argument */ 210 #define DFC_ARG_NULL (DFC_ERRNO_START + 7) /* NULL Argument */ 211 #define DFC_ARG_TOOSMALL (DFC_ERRNO_START + 8) /* Argument too small */ 212 #define DFC_ARG_TOOBIG (DFC_ERRNO_START + 9) /* Argument too big */ 213 214 #define DFC_COPYIN_ERROR (DFC_ERRNO_START + 10) /* DDI copyin err */ 215 #define DFC_COPYOUT_ERROR (DFC_ERRNO_START + 11) /* DDI copyout err */ 216 217 #define DFC_TIMEOUT (DFC_ERRNO_START + 12) /* Resource timeout */ 218 #define DFC_SYSRES_ERROR (DFC_ERRNO_START + 13) /* Out of sys resource */ 219 #define DFC_DRVRES_ERROR (DFC_ERRNO_START + 14) /* Out of drv resource */ 220 #define DFC_HBARES_ERROR (DFC_ERRNO_START + 15) /* Out of HBA resource */ 221 222 #define DFC_OFFLINE_ERROR (DFC_ERRNO_START + 16) /* Driver offline */ 223 #define DFC_ONLINE_ERROR (DFC_ERRNO_START + 17) /* Driver offline */ 224 225 /* NPIV_SUPPORT */ 226 #define DFC_NPIV_DISABLED (DFC_ERRNO_START + 18) /* NPIV disabled */ 227 #define DFC_NPIV_UNSUPPORTED (DFC_ERRNO_START + 19) /* NPIV not supported */ 228 #define DFC_NPIV_ACTIVE (DFC_ERRNO_START + 20) /* NPIV active */ 229 230 #define DFC_NOT_SUPPORTED (DFC_ERRNO_START + 21) /* Not supported */ 231 #define DFC_NO_DATA (DFC_ERRNO_START + 22) /* No Data to return */ 232 233 /* DHCHAP_SUPPORT */ 234 #define DFC_AUTH_NOT_CONFIGURED (DFC_ERRNO_START + 30) 235 #define DFC_AUTH_FAILED_NO_SA_FOUND (DFC_ERRNO_START + 31) 236 #define DFC_AUTH_INIT_OK_AUTH_FAILED (DFC_ERRNO_START + 32) 237 #define DFC_AUTH_COMPARE_FAILED (DFC_ERRNO_START + 33) 238 #define DFC_AUTH_WWN_NOT_FOUND (DFC_ERRNO_START + 34) 239 #define DFC_AUTH_PASSWORD_INVALID (DFC_ERRNO_START + 35) 240 #define DFC_AUTH_INVALID_ENTITY (DFC_ERRNO_START + 36) 241 #define DFC_AUTH_ENTITY_NOT_ACTIVE (DFC_ERRNO_START + 37) 242 #define DFC_AUTH_INVALID_OPERATION (DFC_ERRNO_START + 38) 243 #define DFC_AUTH_AUTHENTICATION_GOINGON (DFC_ERRNO_START + 39) 244 #define DFC_AUTH_CREATE_STORKEY_ERROR (DFC_ERRNO_START + 40) 245 #define DFC_AUTH_CREATE_PARMKEY_ERROR (DFC_ERRNO_START + 41) 246 #define DFC_AUTH_CREATE_AUTHKEY_ERROR (DFC_ERRNO_START + 42) 247 #define DFC_AUTH_CREATE_BORDKEY_ERROR (DFC_ERRNO_START + 43) 248 #define DFC_AUTH_AUTHENTICATION_NOT_SUPPORTED (DFC_ERRNO_START + 44) 249 #define DFC_AUTH_AUTHENTICATION_DISABLED (DFC_ERRNO_START + 45) 250 #define DFC_AUTH_CONFIG_NOT_FOUND (DFC_ERRNO_START + 47) 251 #define DFC_AUTH_LOCAL_REMOTE_PWD_EQUAL (DFC_ERRNO_START + 48) 252 253 /* MENLO_SUPPORT */ 254 #define DFC_INVALID_ADAPTER (DFC_ERRNO_START + 50) 255 #define DFC_RSP_BUF_OVERRUN (DFC_ERRNO_START + 51) 256 #define DFC_LINKDOWN_ERROR (DFC_ERRNO_START + 52) 257 258 /* SAN_DIAG_SUPPORT */ 259 #define DFC_SD_STAT_START (DFC_ERRNO_START + 60) 260 261 #define DFC_SD_OK (DFC_ERRNO_START + 60) 262 #define DFC_SD_ERROR_GENERIC (DFC_ERRNO_START + 61) 263 #define DFC_SD_ERROR_INVALID_ARG (DFC_ERRNO_START + 62) 264 #define DFC_SD_ERROR_INVALID_BOARD_ID (DFC_ERRNO_START + 63) 265 #define DFC_SD_ERROR_INVALID_PORT (DFC_ERRNO_START + 64) 266 #define DFC_SD_ERROR_NOT_SUPPORTED (DFC_ERRNO_START + 65) 267 #define DFC_SD_ERROR_CATEGORY_NOT_SUPPORTED (DFC_ERRNO_START + 66) 268 #define DFC_SD_ERROR_SUBCAT_NOT_SUPPORTED (DFC_ERRNO_START + 67) 269 #define DFC_SD_ERROR_MORE_DATA_AVAIL (DFC_ERRNO_START + 68) 270 #define DFC_SD_ERROR_EVENT_ALREADY_REG (DFC_ERRNO_START + 69) 271 #define DFC_SD_ERROR_NO_ACTIVE_REG (DFC_ERRNO_START + 70) 272 #define DFC_SD_ERROR_ARG_MISSING (DFC_ERRNO_START + 71) 273 #define DFC_SD_ERROR_NO_MEM (DFC_ERRNO_START + 72) 274 #define DFC_SD_ERROR_BUCKET_NOT_SET (DFC_ERRNO_START + 73) 275 #define DFC_SD_ERROR_REG_HANDLE (DFC_ERRNO_START + 74) 276 #define DFC_SD_ERROR_INVALID_SEARCH_TYPE (DFC_ERRNO_START + 75) 277 #define DFC_SD_ERROR_FUNCTION_NOT_SUPPORTED (DFC_ERRNO_START + 76) 278 #define DFC_SD_ERROR_OUT_OF_HANDLES (DFC_ERRNO_START + 77) 279 #define DFC_SD_ERROR_LIB_NOT_INIT (DFC_ERRNO_START + 78) 280 #define DFC_SD_ERROR_DATA_COLLECTION_ACTIVE (DFC_ERRNO_START + 79) 281 #define DFC_SD_ERROR_DATA_COLLECTION_NOT_ACTIVE (DFC_ERRNO_START + 80) 282 283 284 #define DFC_ERRNO_END (DFC_ERRNO_START + 128) 285 286 typedef struct dfc_hbainfo 287 { 288 char vpd_serial_num[32]; 289 char vpd_part_num[32]; 290 char vpd_port_num[20]; 291 char vpd_eng_change[32]; 292 char vpd_manufacturer[80]; 293 char vpd_model[80]; 294 char vpd_model_desc[256]; 295 char vpd_prog_types[256]; 296 char vpd_id[80]; 297 298 uint32_t flags; 299 #define HBA_FLAG_SBUS 0x00000001 300 #define HBA_FLAG_OFFLINE 0x00000002 301 #define HBA_FLAG_NPIV 0x00000004 /* Supports NPIV */ 302 #define HBA_FLAG_DHCHAP 0x00000008 /* Supports DHCHAP */ 303 #define HBA_FLAG_DYN_WWN 0x00000010 /* Supports Dynamic WWN */ 304 #define HBA_FLAG_E2E_AUTH 0x00000020 /* Supports E2E Auth */ 305 #define HBA_FLAG_TARGET_MODE 0x00000040 /* Supports Target Mode */ 306 #define HBA_FLAG_TARGET_MODE_ENA 0x00000080 /* Target Mode is enabled */ 307 #define HBA_FLAG_SAN_DIAG 0x00000100 /* Supports SAN Diags */ 308 #define HBA_FLAG_FCOE 0x00000200 /* Supports FCoE */ 309 #define HBA_FLAG_PERSISTLINK 0x00000400 /* Supports Persist Link */ 310 /* Up/Down */ 311 #define HBA_FLAG_EXT_MBOX 0x00000800 /* Supports Ext MBOX cmds */ 312 313 uint32_t device_id; 314 uint32_t vendor_id; 315 uint32_t ports; 316 uint32_t port_index; 317 318 uint32_t vpi_max; 319 uint32_t vpi_high; 320 321 char wwnn[8]; 322 char snn[256]; 323 324 char wwpn[8]; 325 char spn[256]; 326 327 char fw_version[256]; 328 char fcode_version[256]; 329 char boot_version[256]; 330 331 uint32_t biuRev; 332 uint32_t smRev; 333 uint32_t smFwRev; 334 uint32_t endecRev; 335 uint32_t rBit; 336 uint32_t fcphHigh; 337 uint32_t fcphLow; 338 uint32_t feaLevelHigh; 339 uint32_t feaLevelLow; 340 341 uint32_t kern_rev; 342 char kern_name[32]; 343 uint32_t stub_rev; 344 char stub_name[32]; 345 uint32_t sli1_rev; 346 char sli1_name[32]; 347 uint32_t sli2_rev; 348 char sli2_name[32]; 349 uint32_t sli3_rev; 350 char sli3_name[32]; 351 uint32_t sli4_rev; 352 char sli4_name[32]; 353 uint32_t sli_mode; 354 355 uint32_t drv_instance; 356 char drv_label[64]; 357 char drv_module[64]; 358 char drv_name[32]; 359 char drv_version[64]; 360 char drv_revision[64]; 361 362 char hostname[32]; 363 char os_devname[256]; 364 365 uint32_t port_id; 366 uint32_t port_type; 367 uint32_t port_state; 368 uint32_t topology; 369 uint32_t hard_alpa; 370 uint8_t alpa_count; 371 uint8_t alpa_map[128]; 372 373 uint32_t supported_cos; 374 uint32_t supported_types[8]; 375 uint32_t active_types[8]; 376 377 uint32_t supported_speeds; 378 uint32_t port_speed; 379 uint32_t max_frame_size; 380 381 uint8_t fabric_wwpn[8]; 382 uint8_t fabric_wwnn[8]; 383 uint32_t node_count; 384 385 uint8_t pci_function_number; 386 uint8_t pci_device_number; 387 uint8_t pci_bus_number; 388 } dfc_hbainfo_t; 389 390 391 392 typedef struct fc_class 393 { 394 #ifdef EMLXS_BIG_ENDIAN 395 uint8_t classValid:1; /* FC Word 0, bit 31 */ 396 uint8_t intermix:1; /* FC Word 0, bit 30 */ 397 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 398 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 399 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 400 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 401 #endif 402 #ifdef EMLXS_LITTLE_ENDIAN 403 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 404 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 405 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 406 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 407 uint8_t intermix:1; /* FC Word 0, bit 30 */ 408 uint8_t classValid:1; /* FC Word 0, bit 31 */ 409 #endif 410 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 411 #ifdef EMLXS_BIG_ENDIAN 412 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 413 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 414 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 415 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 416 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 417 #endif 418 #ifdef EMLXS_LITTLE_ENDIAN 419 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 420 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 421 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 422 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 423 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 424 #endif 425 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 426 #ifdef EMLXS_BIG_ENDIAN 427 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 428 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 429 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 430 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 431 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 432 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 433 #endif 434 #ifdef EMLXS_LITTLE_ENDIAN 435 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 436 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 437 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 438 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 439 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 440 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 441 #endif 442 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 443 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 444 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 445 446 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 447 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 448 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 449 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 450 451 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 452 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 453 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 454 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 455 } fc_class_t; 456 457 typedef struct fc_csp 458 { 459 uint8_t fcphHigh; /* FC Word 0, byte 0 */ 460 uint8_t fcphLow; /* FC Word 0, byte 1 */ 461 uint8_t bbCreditMsb; /* FC Word 0, byte 2 */ 462 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */ 463 464 #ifdef EMLXS_BIG_ENDIAN 465 uint16_t increasingOffset:1; /* FC Word 1, bit 31 */ 466 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 467 uint16_t word1Reserved2:1; /* FC Word 1, bit 29 */ 468 uint16_t fPort:1; /* FC Word 1, bit 28 */ 469 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 470 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 471 uint16_t multicast:1; /* FC Word 1, bit 25 */ 472 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 473 474 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 475 uint16_t simplex:1; /* FC Word 1, bit 22 */ 476 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 477 uint16_t dhd:1; /* FC Word 1, bit 18 */ 478 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 479 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 480 #endif 481 #ifdef EMLXS_LITTLE_ENDIAN 482 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 483 uint16_t multicast:1; /* FC Word 1, bit 25 */ 484 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 485 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 486 uint16_t fPort:1; /* FC Word 1, bit 28 */ 487 uint16_t word1Reserved2:1; /* FC Word 1, bit 29 */ 488 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 489 uint16_t increasingOffset:1; /* FC Word 1, bit 31 */ 490 491 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 492 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 493 uint16_t dhd:1; /* FC Word 1, bit 18 */ 494 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 495 uint16_t simplex:1; /* FC Word 1, bit 22 */ 496 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 497 #endif 498 499 uint8_t bbRcvSizeMsb; /* FC Word 1, byte 2 */ 500 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 501 502 union 503 { 504 struct 505 { 506 uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 507 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 508 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 509 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 510 } nPort; 511 512 uint32_t r_a_tov; /* RATOV (Big Endian) */ 513 } w2; 514 515 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */ 516 } fc_csp_t; 517 518 519 typedef struct fc_sparm 520 { 521 fc_csp_t csp; 522 523 uint8_t wwpn[8]; 524 uint8_t wwnn[8]; 525 526 fc_class_t cls1; 527 fc_class_t cls2; 528 fc_class_t cls3; 529 fc_class_t cls4; 530 531 uint8_t vendorVersion[16]; 532 } fc_sparm_t; 533 534 535 typedef struct dfc_node 536 { 537 uint32_t port_id; 538 uint32_t rpi; 539 uint32_t xri; 540 uint32_t flags; 541 542 #define PORT_FLAG_FCP_TARGET 0x00000001 543 #define PORT_FLAG_FCP_INI 0x00000002 544 #define PORT_FLAG_FCP2 0x00000004 545 #define PORT_FLAG_IP 0x00000008 546 #define PORT_FLAG_VPORT 0x00000010 547 548 #define PORT_FLAG_DFC_STATE_VALID 0x00000020 549 #define PORT_FLAG_DFC_STATE 0xF0000000 550 551 fc_sparm_t sparm; 552 553 } dfc_node_t; 554 555 556 typedef struct dfc_hbastats 557 { 558 uint32_t tx_frame_cnt; 559 uint32_t rx_frame_cnt; 560 uint32_t tx_kbyte_cnt; 561 uint32_t rx_kbyte_cnt; 562 uint32_t tx_seq_cnt; 563 uint32_t rx_seq_cnt; 564 uint32_t orig_exch_cnt; 565 uint32_t resp_exch_cnt; 566 uint32_t pbsy_cnt; 567 uint32_t fbsy_cnt; 568 uint32_t link_failure_cnt; 569 uint32_t loss_sync_cnt; 570 uint32_t loss_signal_cnt; 571 uint32_t seq_error_cnt; 572 uint32_t inval_tx_word_cnt; 573 uint32_t crc_error_cnt; 574 uint32_t seq_timeout_cnt; 575 uint32_t elastic_overrun_cnt; 576 uint32_t arb_timeout_cnt; 577 uint32_t rx_buf_credit; 578 uint32_t rx_buf_cnt; 579 uint32_t tx_buf_credit; 580 uint32_t tx_buf_cnt; 581 uint32_t EOFa_cnt; 582 uint32_t EOFdti_cnt; 583 uint32_t EOFni_cnt; 584 uint32_t SOFf_cnt; 585 uint32_t link_event_tag; 586 uint32_t last_reset_time; 587 uint32_t topology; 588 uint32_t port_type; 589 uint32_t link_speed; 590 } dfc_hbastats_t; 591 592 593 typedef struct dfc_drvstats 594 { 595 uint32_t LinkUp; 596 uint32_t LinkDown; 597 uint32_t LinkEvent; 598 uint32_t LinkMultiEvent; 599 600 uint32_t MboxIssued; 601 uint32_t MboxCompleted; /* = MboxError + MbxGood */ 602 uint32_t MboxGood; 603 uint32_t MboxError; 604 uint32_t MboxBusy; 605 uint32_t MboxInvalid; 606 607 uint32_t IocbIssued[4]; 608 uint32_t IocbReceived[4]; 609 uint32_t IocbTxPut[4]; 610 uint32_t IocbTxGet[4]; 611 uint32_t IocbRingFull[4]; 612 613 uint32_t IntrEvent[8]; 614 #define RESV_INTR 7 615 #define ERATT_INTR 6 616 #define MBATT_INTR 5 617 #define LKATT_INTR 4 618 #define R3ATT_INTR 3 619 #define R2ATT_INTR 2 620 #define R1ATT_INTR 1 621 #define R0ATT_INTR 0 622 623 uint32_t FcpIssued; 624 uint32_t FcpCompleted; /* FcpGood + FcpError */ 625 uint32_t FcpGood; 626 uint32_t FcpError; 627 628 uint32_t FcpEvent; /* FcpStray + FcpComplete */ 629 uint32_t FcpStray; 630 631 uint32_t ElsEvent; /* ElsStray + ElsComplete (cmd + rsp) */ 632 uint32_t ElsStray; 633 634 uint32_t ElsCmdIssued; 635 uint32_t ElsCmdCompleted; /* ElsCmdGood + ElsCmdError */ 636 uint32_t ElsCmdGood; 637 uint32_t ElsCmdError; 638 639 uint32_t ElsRspIssued; 640 uint32_t ElsRspCompleted; 641 642 uint32_t ElsRcvEvent; /* ElsRcvError + ElsRcvDrop + ElsCmdRcv */ 643 uint32_t ElsRcvError; 644 uint32_t ElsRcvDropped; 645 uint32_t ElsCmdReceived; /* ElsRscnRcv + ElsPlogiRcv + ... */ 646 uint32_t ElsRscnReceived; 647 uint32_t ElsPlogiReceived; 648 uint32_t ElsPrliReceived; 649 uint32_t ElsPrloReceived; 650 uint32_t ElsLogoReceived; 651 uint32_t ElsAdiscReceived; 652 uint32_t ElsGenReceived; 653 654 uint32_t CtEvent; /* CtStray + CtCmdComplete + CtRspComplete */ 655 uint32_t CtStray; 656 657 uint32_t CtCmdIssued; 658 uint32_t CtCmdCompleted; /* CtCmdGood + CtCmdError */ 659 uint32_t CtCmdGood; 660 uint32_t CtCmdError; 661 662 uint32_t CtRspIssued; 663 uint32_t CtRspCompleted; 664 665 uint32_t CtRcvEvent; /* CtRcvError + CtRcvDropp + CtCmdRcv */ 666 uint32_t CtRcvError; 667 uint32_t CtRcvDropped; 668 uint32_t CtCmdReceived; 669 670 uint32_t IpEvent; /* IpStray + IpSeqComplete + IpBcastComplete */ 671 uint32_t IpStray; 672 673 uint32_t IpSeqIssued; 674 uint32_t IpSeqCompleted; /* IpSeqGood + IpSeqError */ 675 uint32_t IpSeqGood; 676 uint32_t IpSeqError; 677 678 uint32_t IpBcastIssued; 679 uint32_t IpBcastCompleted; /* IpBcastGood + IpBcastError */ 680 uint32_t IpBcastGood; 681 uint32_t IpBcastError; 682 683 uint32_t IpRcvEvent; /* IpDrop + IpSeqRcv + IpBcastRcv */ 684 uint32_t IpDropped; 685 uint32_t IpSeqReceived; 686 uint32_t IpBcastReceived; 687 688 uint32_t IpUbPosted; 689 uint32_t ElsUbPosted; 690 uint32_t CtUbPosted; 691 692 #if (DFC_REV >= 2) 693 uint32_t IocbThrottled; 694 uint32_t ElsAuthReceived; 695 #endif 696 } dfc_drvstats_t; 697 698 #ifdef SFCT_SUPPORT 699 /* 700 * FctP2IOXcnt will count IOs by their fcpDL. Counters 701 * are for buckets of various power of 2 sizes. 702 * Bucket 0 < 512 > 0 703 * Bucket 1 >= 512 < 1024 704 * Bucket 2 >= 1024 < 2048 705 * Bucket 3 >= 2048 < 4096 706 * Bucket 4 >= 4096 < 8192 707 * Bucket 5 >= 8192 < 16K 708 * Bucket 6 >= 16K < 32K 709 * Bucket 7 >= 32K < 64K 710 * Bucket 8 >= 64K < 128K 711 * Bucket 9 >= 128K < 256K 712 * Bucket 10 >= 256K < 512K 713 * Bucket 11 >= 512K < 1MB 714 * Bucket 12 >= 1MB < 2MB 715 * Bucket 13 >= 2MB < 4MB 716 * Bucket 14 >= 4MB < 8MB 717 * Bucket 15 >= 8MB 718 */ 719 #define DFC_TGTPORT_STAT_VERSION 1 720 #define MAX_TGTPORT_IOCNT 16 721 typedef struct dfc_tgtport_stat 722 { 723 uint8_t Version; 724 uint8_t Reserved[7]; 725 726 /* IO counters */ 727 uint64_t FctP2IOWcnt[MAX_TGTPORT_IOCNT]; /* Writes */ 728 uint64_t FctP2IORcnt[MAX_TGTPORT_IOCNT]; /* Reads */ 729 uint64_t FctIOCmdCnt; /* Other, ie TUR */ 730 uint64_t FctCmdReceived; /* total I/O */ 731 uint64_t FctReadBytes; /* total read bytes */ 732 uint64_t FctWriteBytes; /* total write bytes */ 733 734 /* IOCB handling counters */ 735 uint64_t FctEvent; /* FctStray + FctCmpl */ 736 uint64_t FctCompleted; /* FctCmpl (Good+Err) */ 737 uint64_t FctCmplGood; 738 739 uint32_t FctCmplError; 740 uint32_t FctStray; 741 742 /* Fct event counters */ 743 uint32_t FctRcvDropped; 744 uint32_t FctOverQDepth; 745 uint32_t FctOutstandingIO; 746 uint32_t FctFailedPortRegister; 747 uint32_t FctPortRegister; 748 uint32_t FctPortDeregister; 749 750 uint32_t FctAbortSent; 751 uint32_t FctNoBuffer; 752 uint32_t FctScsiStatusErr; 753 uint32_t FctScsiQfullErr; 754 uint32_t FctScsiResidOver; 755 uint32_t FctScsiResidUnder; 756 uint32_t FctScsiSenseErr; 757 758 /* Additional info */ 759 uint32_t FctLinkState; 760 } dfc_tgtport_stat_t; 761 #endif /* SFCT_SUPPORT */ 762 763 /* DFC_REV >= 3 */ 764 typedef struct dfc_vportinfo 765 { 766 uint32_t flags; 767 #define VPORT_CONFIG 0x00000001 768 #define VPORT_ENABLED 0x00000002 769 #define VPORT_BOUND 0x00000004 770 #define VPORT_IP 0x00000008 771 #define VPORT_RESTRICTED 0x00000010 /* login restricted */ 772 773 uint32_t vpi; 774 uint32_t port_id; 775 uint8_t wwpn[8]; 776 uint8_t wwnn[8]; 777 778 char snn[256]; 779 char spn[256]; 780 781 uint32_t ulp_statec; 782 } dfc_vportinfo_t; 783 784 #ifdef __cplusplus 785 } 786 #endif 787 788 #endif /* _EMLXS_DFC_H */ 789