Searched refs:CPTRSIZE (Results 1 – 19 of 19) sorted by relevance
/titanic_44/usr/src/lib/brand/shared/brand/sys/ |
H A D | brand_misc.h | 78 #define EH_ARGS_SIZE (CPTRSIZE * EH_ARGS_COUNT) 79 #define EH_ARGS_OFFSET(x) (STACK_BIAS + MINFRAME + (CPTRSIZE * (x))) 81 SIZEOF_SYSRET_T + CPTRSIZE) 119 #define EH_LOCALS_SYSRET2 (EH_LOCALS_SYSRET + CPTRSIZE) 121 #define EH_LOCALS_END (EH_LOCALS_RVFLAG + CPTRSIZE)
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/titanic_44/usr/src/lib/brand/shared/brand/i386/ |
H A D | handler.s | 102 addl $CPTRSIZE, %ecx 113 xchgl CPTRSIZE(%ebp), %eax /* swap JMP table offset and ret addr */ 137 movl CPTRSIZE(%edx), %ecx /* number of args + rv flag */ 140 movl CPTRSIZE(%edx), %ecx /* number of args + rv flag */
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/titanic_44/usr/src/uts/intel/ia32/sys/ |
H A D | asm_linkage.h | 96 #define CPTRSIZE CLONGSIZE macro 99 #if CPTRSIZE != (1 << CPTRSHIFT) || CLONGSIZE != (1 << CLONGSHIFT) 103 #if CPTRMASK != (CPTRSIZE - 1) || CLONGMASK != (CLONGSIZE - 1)
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/titanic_44/usr/src/uts/sun4/ml/ |
H A D | offsets.in | 114 \#define P_UTRAP4 (UT_ILLTRAP_INSTRUCTION * CPTRSIZE) 115 \#define P_UTRAP7 (UT_FP_DISABLED * CPTRSIZE) 116 \#define P_UTRAP8 (UT_FP_EXCEPTION_IEEE_754 * CPTRSIZE) 117 \#define P_UTRAP10 (UT_TAG_OVERFLOW * CPTRSIZE) 118 \#define P_UTRAP11 (UT_DIVISION_BY_ZERO * CPTRSIZE) 119 \#define P_UTRAP15 (UT_MEM_ADDRESS_NOT_ALIGNED * CPTRSIZE) 120 \#define P_UTRAP16 (UT_PRIVILEGED_ACTION * CPTRSIZE)
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/titanic_44/usr/src/lib/brand/shared/brand/amd64/ |
H A D | handler.s | 111 addq $CPTRSIZE, %r12 125 xchgq CPTRSIZE(%rbp), %rax /* swap JMP table offset and ret addr */ 148 movq CPTRSIZE(%r11), %r12 /* number of args + rv flag */
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/titanic_44/usr/src/uts/sparc/sys/ |
H A D | asm_linkage.h | 52 #define CPTRSIZE (1<<CPTRSHIFT) macro 54 #define CPTRMASK (CPTRSIZE - 1)
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/titanic_44/usr/src/lib/brand/shared/brand/sparc/ |
H A D | runexe.s | 59 sub %o0, CPTRSIZE + WINDOWSIZE + STACK_BIAS, %sp
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H A D | crt.s | 67 add %fp, + WINDOWSIZE + CPTRSIZE + STACK_BIAS, %o1
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H A D | handler.s | 141 ldn [%l3 + CPTRSIZE], %l4 /* number of args + rv flag */
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/titanic_44/usr/src/uts/intel/ia32/ml/ |
H A D | modstubs.s | 105 .align CPTRSIZE; \ 117 .align CPTRSIZE; \ 136 .align CPTRSIZE; \ 157 .align CPTRSIZE; \ 247 .align CPTRSIZE; \ 259 .align CPTRSIZE; \ 287 .align CPTRSIZE; \ 308 .align CPTRSIZE; \
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H A D | lock_prim.s | 691 .align CPTRSIZE 714 .align CPTRSIZE 862 .align CPTRSIZE 885 .align CPTRSIZE
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H A D | i86_subr.s | 936 movq %rsi, CPTRSIZE(%rdi) /* entryp->back = predp */ 939 movq %rdi, CPTRSIZE(%rax) /* predp->forw->back = entryp */ 949 movl %edx, CPTRSIZE(%ecx) /* entryp->back = predp */ 952 movl %ecx, CPTRSIZE(%eax) /* predp->forw->back = entryp */ 976 movq CPTRSIZE(%rdi), %rdx /* entry->back */ 978 movq %rdx, CPTRSIZE(%rax) /* entry->forw->back = entry->back */ 987 movl CPTRSIZE(%ecx), %edx /* entry->back */ 989 movl %edx, CPTRSIZE(%eax) /* entry->forw->back = entry->back */
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/titanic_44/usr/src/uts/i86pc/ml/ |
H A D | syscall_asm.s | 153 movl _CONST(_MUL(callback_id, CPTRSIZE))(%ebx), %ebx ;\ 639 .align CPTRSIZE
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H A D | syscall_asm_amd64.s | 196 movq _CONST(_MUL(callback_id, CPTRSIZE))(%r15), %r15 ;\ 1255 .align CPTRSIZE
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/titanic_44/usr/src/uts/sun4v/ml/ |
H A D | mach_locore.s | 98 ….size intr_vec_table, MAXIVNUM * CPTRSIZE + MAX_RSVD_IV * IV_SIZE + MAX_RSVD_IVX * (IV_SIZE + CPTR…
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H A D | trap_table.s | 1584 smul %g1, CPTRSIZE, %g2
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/titanic_44/usr/src/uts/sun4u/ml/ |
H A D | mach_locore.s | 98 ….size intr_vec_table, MAXIVNUM * CPTRSIZE + MAX_RSVD_IV * IV_SIZE + MAX_RSVD_IVX * (IV_SIZE + CPTR…
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H A D | trap_table.s | 1811 smul %g1, CPTRSIZE, %g2
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/titanic_44/usr/src/uts/sparc/ml/ |
H A D | modstubs.s | 94 .align CPTRSIZE; \
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