xref: /linux/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_default.h (revision 4f2c0a4acffbec01079c28f839422e64ddeff004)
1 /*
2  * Copyright 2021 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #ifndef _gc_11_0_0_DEFAULT_HEADER
24 #define _gc_11_0_0_DEFAULT_HEADER
25 
26 
27 // addressBlock: gc_sdma0_sdma0dec
28 #define regSDMA0_DEC_START_DEFAULT                                                0x00000000
29 #define regSDMA0_F32_MISC_CNTL_DEFAULT                                            0x00000000
30 #define regSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT                                      0x00000000
31 #define regSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT                                      0x00000000
32 #define regSDMA0_POWER_CNTL_DEFAULT                                               0x00000000
33 #define regSDMA0_CNTL_DEFAULT                                                     0x00002440
34 #define regSDMA0_CHICKEN_BITS_DEFAULT                                             0x0107d186
35 #define regSDMA0_GB_ADDR_CONFIG_DEFAULT                                           0x00000545
36 #define regSDMA0_GB_ADDR_CONFIG_READ_DEFAULT                                      0x00000545
37 #define regSDMA0_RB_RPTR_FETCH_DEFAULT                                            0x00000000
38 #define regSDMA0_RB_RPTR_FETCH_HI_DEFAULT                                         0x00000000
39 #define regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT                                 0x00000000
40 #define regSDMA0_IB_OFFSET_FETCH_DEFAULT                                          0x00000000
41 #define regSDMA0_PROGRAM_DEFAULT                                                  0x00000000
42 #define regSDMA0_STATUS_REG_DEFAULT                                               0x46dee557
43 #define regSDMA0_STATUS1_REG_DEFAULT                                              0x000403ff
44 #define regSDMA0_CNTL1_DEFAULT                                                    0x00000c30
45 #define regSDMA0_HBM_PAGE_CONFIG_DEFAULT                                          0x00000000
46 #define regSDMA0_UCODE_CHECKSUM_DEFAULT                                           0x00000000
47 #define regSDMA0_FREEZE_DEFAULT                                                   0x00000000
48 #define regSDMA0_PROCESS_QUANTUM0_DEFAULT                                         0x00000000
49 #define regSDMA0_PROCESS_QUANTUM1_DEFAULT                                         0x00000000
50 #define regSDMA0_WATCHDOG_CNTL_DEFAULT                                            0x00000000
51 #define regSDMA0_QUEUE_STATUS0_DEFAULT                                            0x22222222
52 #define regSDMA0_EDC_CONFIG_DEFAULT                                               0x00000004
53 #define regSDMA0_BA_THRESHOLD_DEFAULT                                             0x03ff03ff
54 #define regSDMA0_ID_DEFAULT                                                       0x00000001
55 #define regSDMA0_VERSION_DEFAULT                                                  0x00000600
56 #define regSDMA0_EDC_COUNTER_DEFAULT                                              0x00000000
57 #define regSDMA0_EDC_COUNTER_CLEAR_DEFAULT                                        0x00000000
58 #define regSDMA0_STATUS2_REG_DEFAULT                                              0x00000000
59 #define regSDMA0_ATOMIC_CNTL_DEFAULT                                              0x00000200
60 #define regSDMA0_ATOMIC_PREOP_LO_DEFAULT                                          0x00000000
61 #define regSDMA0_ATOMIC_PREOP_HI_DEFAULT                                          0x00000000
62 #define regSDMA0_UTCL1_CNTL_DEFAULT                                               0x2c000288
63 #define regSDMA0_UTCL1_WATERMK_DEFAULT                                            0x00000000
64 #define regSDMA0_UTCL1_TIMEOUT_DEFAULT                                            0x00000000
65 #define regSDMA0_UTCL1_PAGE_DEFAULT                                               0x010cec00
66 #define regSDMA0_UTCL1_RD_STATUS_DEFAULT                                          0xb90700ff
67 #define regSDMA0_UTCL1_WR_STATUS_DEFAULT                                          0xf90780ff
68 #define regSDMA0_UTCL1_INV0_DEFAULT                                               0x00000000
69 #define regSDMA0_UTCL1_INV1_DEFAULT                                               0x00000000
70 #define regSDMA0_UTCL1_INV2_DEFAULT                                               0x00000000
71 #define regSDMA0_UTCL1_RD_XNACK0_DEFAULT                                          0x00000000
72 #define regSDMA0_UTCL1_RD_XNACK1_DEFAULT                                          0x00000000
73 #define regSDMA0_UTCL1_WR_XNACK0_DEFAULT                                          0x00000000
74 #define regSDMA0_UTCL1_WR_XNACK1_DEFAULT                                          0x00000000
75 #define regSDMA0_RELAX_ORDERING_LUT_DEFAULT                                       0xc0000806
76 #define regSDMA0_CHICKEN_BITS_2_DEFAULT                                           0x400007c9
77 #define regSDMA0_STATUS3_REG_DEFAULT                                              0x03f00000
78 #define regSDMA0_PHYSICAL_ADDR_LO_DEFAULT                                         0x00000000
79 #define regSDMA0_PHYSICAL_ADDR_HI_DEFAULT                                         0x00000000
80 #define regSDMA0_GLOBAL_QUANTUM_DEFAULT                                           0x00000000
81 #define regSDMA0_ERROR_LOG_DEFAULT                                                0x0000000f
82 #define regSDMA0_PUB_DUMMY_REG0_DEFAULT                                           0x00000000
83 #define regSDMA0_PUB_DUMMY_REG1_DEFAULT                                           0x00000000
84 #define regSDMA0_PUB_DUMMY_REG2_DEFAULT                                           0x00000000
85 #define regSDMA0_PUB_DUMMY_REG3_DEFAULT                                           0x00000000
86 #define regSDMA0_F32_COUNTER_DEFAULT                                              0x00000000
87 #define regSDMA0_CRD_CNTL_DEFAULT                                                 0x18694840
88 #define regSDMA0_RLC_CGCG_CTRL_DEFAULT                                            0x00400000
89 #define regSDMA0_AQL_STATUS_DEFAULT                                               0x00000003
90 #define regSDMA0_EA_DBIT_ADDR_DATA_DEFAULT                                        0x0000270d
91 #define regSDMA0_EA_DBIT_ADDR_INDEX_DEFAULT                                       0x00000000
92 #define regSDMA0_TLBI_GCR_CNTL_DEFAULT                                            0x40600454
93 #define regSDMA0_TILING_CONFIG_DEFAULT                                            0x00000000
94 #define regSDMA0_INT_STATUS_DEFAULT                                               0x00000000
95 #define regSDMA0_HOLE_ADDR_LO_DEFAULT                                             0x00000000
96 #define regSDMA0_HOLE_ADDR_HI_DEFAULT                                             0x00000000
97 #define regSDMA0_CLOCK_GATING_STATUS_DEFAULT                                      0x00000000
98 #define regSDMA0_STATUS4_REG_DEFAULT                                              0x00000001
99 #define regSDMA0_SCRATCH_RAM_DATA_DEFAULT                                         0x00000000
100 #define regSDMA0_SCRATCH_RAM_ADDR_DEFAULT                                         0x00000000
101 #define regSDMA0_TIMESTAMP_CNTL_DEFAULT                                           0x00000000
102 #define regSDMA0_STATUS5_REG_DEFAULT                                              0x00000000
103 #define regSDMA0_QUEUE_RESET_REQ_DEFAULT                                          0x00000000
104 #define regSDMA0_STATUS6_REG_DEFAULT                                              0x00000000
105 #define regSDMA0_UCODE1_CHECKSUM_DEFAULT                                          0x00000000
106 #define regSDMA0_CE_CTRL_DEFAULT                                                  0x00000000
107 #define regSDMA0_FED_STATUS_DEFAULT                                               0x00000000
108 #define regSDMA0_QUEUE0_RB_CNTL_DEFAULT                                           0x00040800
109 #define regSDMA0_QUEUE0_RB_BASE_DEFAULT                                           0x00000000
110 #define regSDMA0_QUEUE0_RB_BASE_HI_DEFAULT                                        0x00000000
111 #define regSDMA0_QUEUE0_RB_RPTR_DEFAULT                                           0x00000000
112 #define regSDMA0_QUEUE0_RB_RPTR_HI_DEFAULT                                        0x00000000
113 #define regSDMA0_QUEUE0_RB_WPTR_DEFAULT                                           0x00000000
114 #define regSDMA0_QUEUE0_RB_WPTR_HI_DEFAULT                                        0x00000000
115 #define regSDMA0_QUEUE0_RB_RPTR_ADDR_HI_DEFAULT                                   0x00000000
116 #define regSDMA0_QUEUE0_RB_RPTR_ADDR_LO_DEFAULT                                   0x00000000
117 #define regSDMA0_QUEUE0_IB_CNTL_DEFAULT                                           0x00000100
118 #define regSDMA0_QUEUE0_IB_RPTR_DEFAULT                                           0x00000000
119 #define regSDMA0_QUEUE0_IB_OFFSET_DEFAULT                                         0x00000000
120 #define regSDMA0_QUEUE0_IB_BASE_LO_DEFAULT                                        0x00000000
121 #define regSDMA0_QUEUE0_IB_BASE_HI_DEFAULT                                        0x00000000
122 #define regSDMA0_QUEUE0_IB_SIZE_DEFAULT                                           0x00000000
123 #define regSDMA0_QUEUE0_SKIP_CNTL_DEFAULT                                         0x00000000
124 #define regSDMA0_QUEUE0_CONTEXT_STATUS_DEFAULT                                    0x00000804
125 #define regSDMA0_QUEUE0_DOORBELL_DEFAULT                                          0x00000000
126 #define regSDMA0_QUEUE0_DOORBELL_LOG_DEFAULT                                      0x00000000
127 #define regSDMA0_QUEUE0_DOORBELL_OFFSET_DEFAULT                                   0x00000000
128 #define regSDMA0_QUEUE0_CSA_ADDR_LO_DEFAULT                                       0x00000000
129 #define regSDMA0_QUEUE0_CSA_ADDR_HI_DEFAULT                                       0x00000000
130 #define regSDMA0_QUEUE0_SCHEDULE_CNTL_DEFAULT                                     0x00000000
131 #define regSDMA0_QUEUE0_IB_SUB_REMAIN_DEFAULT                                     0x00000000
132 #define regSDMA0_QUEUE0_PREEMPT_DEFAULT                                           0x00000000
133 #define regSDMA0_QUEUE0_DUMMY_REG_DEFAULT                                         0x0000000f
134 #define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI_DEFAULT                              0x00000000
135 #define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO_DEFAULT                              0x00000000
136 #define regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT                                       0x00004000
137 #define regSDMA0_QUEUE0_MINOR_PTR_UPDATE_DEFAULT                                  0x00000000
138 #define regSDMA0_QUEUE0_RB_PREEMPT_DEFAULT                                        0x00000000
139 #define regSDMA0_QUEUE0_MIDCMD_DATA0_DEFAULT                                      0x00000000
140 #define regSDMA0_QUEUE0_MIDCMD_DATA1_DEFAULT                                      0x00000000
141 #define regSDMA0_QUEUE0_MIDCMD_DATA2_DEFAULT                                      0x00000000
142 #define regSDMA0_QUEUE0_MIDCMD_DATA3_DEFAULT                                      0x00000000
143 #define regSDMA0_QUEUE0_MIDCMD_DATA4_DEFAULT                                      0x00000000
144 #define regSDMA0_QUEUE0_MIDCMD_DATA5_DEFAULT                                      0x00000000
145 #define regSDMA0_QUEUE0_MIDCMD_DATA6_DEFAULT                                      0x00000000
146 #define regSDMA0_QUEUE0_MIDCMD_DATA7_DEFAULT                                      0x00000000
147 #define regSDMA0_QUEUE0_MIDCMD_DATA8_DEFAULT                                      0x00000000
148 #define regSDMA0_QUEUE0_MIDCMD_DATA9_DEFAULT                                      0x00000000
149 #define regSDMA0_QUEUE0_MIDCMD_DATA10_DEFAULT                                     0x00000000
150 #define regSDMA0_QUEUE0_MIDCMD_CNTL_DEFAULT                                       0x00000000
151 #define regSDMA0_QUEUE1_RB_CNTL_DEFAULT                                           0x00040800
152 #define regSDMA0_QUEUE1_RB_BASE_DEFAULT                                           0x00000000
153 #define regSDMA0_QUEUE1_RB_BASE_HI_DEFAULT                                        0x00000000
154 #define regSDMA0_QUEUE1_RB_RPTR_DEFAULT                                           0x00000000
155 #define regSDMA0_QUEUE1_RB_RPTR_HI_DEFAULT                                        0x00000000
156 #define regSDMA0_QUEUE1_RB_WPTR_DEFAULT                                           0x00000000
157 #define regSDMA0_QUEUE1_RB_WPTR_HI_DEFAULT                                        0x00000000
158 #define regSDMA0_QUEUE1_RB_RPTR_ADDR_HI_DEFAULT                                   0x00000000
159 #define regSDMA0_QUEUE1_RB_RPTR_ADDR_LO_DEFAULT                                   0x00000000
160 #define regSDMA0_QUEUE1_IB_CNTL_DEFAULT                                           0x00000100
161 #define regSDMA0_QUEUE1_IB_RPTR_DEFAULT                                           0x00000000
162 #define regSDMA0_QUEUE1_IB_OFFSET_DEFAULT                                         0x00000000
163 #define regSDMA0_QUEUE1_IB_BASE_LO_DEFAULT                                        0x00000000
164 #define regSDMA0_QUEUE1_IB_BASE_HI_DEFAULT                                        0x00000000
165 #define regSDMA0_QUEUE1_IB_SIZE_DEFAULT                                           0x00000000
166 #define regSDMA0_QUEUE1_SKIP_CNTL_DEFAULT                                         0x00000000
167 #define regSDMA0_QUEUE1_CONTEXT_STATUS_DEFAULT                                    0x00000804
168 #define regSDMA0_QUEUE1_DOORBELL_DEFAULT                                          0x00000000
169 #define regSDMA0_QUEUE1_DOORBELL_LOG_DEFAULT                                      0x00000000
170 #define regSDMA0_QUEUE1_DOORBELL_OFFSET_DEFAULT                                   0x00000000
171 #define regSDMA0_QUEUE1_CSA_ADDR_LO_DEFAULT                                       0x00000000
172 #define regSDMA0_QUEUE1_CSA_ADDR_HI_DEFAULT                                       0x00000000
173 #define regSDMA0_QUEUE1_SCHEDULE_CNTL_DEFAULT                                     0x00000000
174 #define regSDMA0_QUEUE1_IB_SUB_REMAIN_DEFAULT                                     0x00000000
175 #define regSDMA0_QUEUE1_PREEMPT_DEFAULT                                           0x00000000
176 #define regSDMA0_QUEUE1_DUMMY_REG_DEFAULT                                         0x0000000f
177 #define regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI_DEFAULT                              0x00000000
178 #define regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO_DEFAULT                              0x00000000
179 #define regSDMA0_QUEUE1_RB_AQL_CNTL_DEFAULT                                       0x00004000
180 #define regSDMA0_QUEUE1_MINOR_PTR_UPDATE_DEFAULT                                  0x00000000
181 #define regSDMA0_QUEUE1_RB_PREEMPT_DEFAULT                                        0x00000000
182 #define regSDMA0_QUEUE1_MIDCMD_DATA0_DEFAULT                                      0x00000000
183 #define regSDMA0_QUEUE1_MIDCMD_DATA1_DEFAULT                                      0x00000000
184 #define regSDMA0_QUEUE1_MIDCMD_DATA2_DEFAULT                                      0x00000000
185 #define regSDMA0_QUEUE1_MIDCMD_DATA3_DEFAULT                                      0x00000000
186 #define regSDMA0_QUEUE1_MIDCMD_DATA4_DEFAULT                                      0x00000000
187 #define regSDMA0_QUEUE1_MIDCMD_DATA5_DEFAULT                                      0x00000000
188 #define regSDMA0_QUEUE1_MIDCMD_DATA6_DEFAULT                                      0x00000000
189 #define regSDMA0_QUEUE1_MIDCMD_DATA7_DEFAULT                                      0x00000000
190 #define regSDMA0_QUEUE1_MIDCMD_DATA8_DEFAULT                                      0x00000000
191 #define regSDMA0_QUEUE1_MIDCMD_DATA9_DEFAULT                                      0x00000000
192 #define regSDMA0_QUEUE1_MIDCMD_DATA10_DEFAULT                                     0x00000000
193 #define regSDMA0_QUEUE1_MIDCMD_CNTL_DEFAULT                                       0x00000000
194 #define regSDMA0_QUEUE2_RB_CNTL_DEFAULT                                           0x00040800
195 #define regSDMA0_QUEUE2_RB_BASE_DEFAULT                                           0x00000000
196 #define regSDMA0_QUEUE2_RB_BASE_HI_DEFAULT                                        0x00000000
197 #define regSDMA0_QUEUE2_RB_RPTR_DEFAULT                                           0x00000000
198 #define regSDMA0_QUEUE2_RB_RPTR_HI_DEFAULT                                        0x00000000
199 #define regSDMA0_QUEUE2_RB_WPTR_DEFAULT                                           0x00000000
200 #define regSDMA0_QUEUE2_RB_WPTR_HI_DEFAULT                                        0x00000000
201 #define regSDMA0_QUEUE2_RB_RPTR_ADDR_HI_DEFAULT                                   0x00000000
202 #define regSDMA0_QUEUE2_RB_RPTR_ADDR_LO_DEFAULT                                   0x00000000
203 #define regSDMA0_QUEUE2_IB_CNTL_DEFAULT                                           0x00000100
204 #define regSDMA0_QUEUE2_IB_RPTR_DEFAULT                                           0x00000000
205 #define regSDMA0_QUEUE2_IB_OFFSET_DEFAULT                                         0x00000000
206 #define regSDMA0_QUEUE2_IB_BASE_LO_DEFAULT                                        0x00000000
207 #define regSDMA0_QUEUE2_IB_BASE_HI_DEFAULT                                        0x00000000
208 #define regSDMA0_QUEUE2_IB_SIZE_DEFAULT                                           0x00000000
209 #define regSDMA0_QUEUE2_SKIP_CNTL_DEFAULT                                         0x00000000
210 #define regSDMA0_QUEUE2_CONTEXT_STATUS_DEFAULT                                    0x00000804
211 #define regSDMA0_QUEUE2_DOORBELL_DEFAULT                                          0x00000000
212 #define regSDMA0_QUEUE2_DOORBELL_LOG_DEFAULT                                      0x00000000
213 #define regSDMA0_QUEUE2_DOORBELL_OFFSET_DEFAULT                                   0x00000000
214 #define regSDMA0_QUEUE2_CSA_ADDR_LO_DEFAULT                                       0x00000000
215 #define regSDMA0_QUEUE2_CSA_ADDR_HI_DEFAULT                                       0x00000000
216 #define regSDMA0_QUEUE2_SCHEDULE_CNTL_DEFAULT                                     0x00000000
217 #define regSDMA0_QUEUE2_IB_SUB_REMAIN_DEFAULT                                     0x00000000
218 #define regSDMA0_QUEUE2_PREEMPT_DEFAULT                                           0x00000000
219 #define regSDMA0_QUEUE2_DUMMY_REG_DEFAULT                                         0x0000000f
220 #define regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI_DEFAULT                              0x00000000
221 #define regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO_DEFAULT                              0x00000000
222 #define regSDMA0_QUEUE2_RB_AQL_CNTL_DEFAULT                                       0x00004000
223 #define regSDMA0_QUEUE2_MINOR_PTR_UPDATE_DEFAULT                                  0x00000000
224 #define regSDMA0_QUEUE2_RB_PREEMPT_DEFAULT                                        0x00000000
225 #define regSDMA0_QUEUE2_MIDCMD_DATA0_DEFAULT                                      0x00000000
226 #define regSDMA0_QUEUE2_MIDCMD_DATA1_DEFAULT                                      0x00000000
227 #define regSDMA0_QUEUE2_MIDCMD_DATA2_DEFAULT                                      0x00000000
228 #define regSDMA0_QUEUE2_MIDCMD_DATA3_DEFAULT                                      0x00000000
229 #define regSDMA0_QUEUE2_MIDCMD_DATA4_DEFAULT                                      0x00000000
230 #define regSDMA0_QUEUE2_MIDCMD_DATA5_DEFAULT                                      0x00000000
231 #define regSDMA0_QUEUE2_MIDCMD_DATA6_DEFAULT                                      0x00000000
232 #define regSDMA0_QUEUE2_MIDCMD_DATA7_DEFAULT                                      0x00000000
233 #define regSDMA0_QUEUE2_MIDCMD_DATA8_DEFAULT                                      0x00000000
234 #define regSDMA0_QUEUE2_MIDCMD_DATA9_DEFAULT                                      0x00000000
235 #define regSDMA0_QUEUE2_MIDCMD_DATA10_DEFAULT                                     0x00000000
236 #define regSDMA0_QUEUE2_MIDCMD_CNTL_DEFAULT                                       0x00000000
237 #define regSDMA0_QUEUE3_RB_CNTL_DEFAULT                                           0x00040800
238 #define regSDMA0_QUEUE3_RB_BASE_DEFAULT                                           0x00000000
239 #define regSDMA0_QUEUE3_RB_BASE_HI_DEFAULT                                        0x00000000
240 #define regSDMA0_QUEUE3_RB_RPTR_DEFAULT                                           0x00000000
241 #define regSDMA0_QUEUE3_RB_RPTR_HI_DEFAULT                                        0x00000000
242 #define regSDMA0_QUEUE3_RB_WPTR_DEFAULT                                           0x00000000
243 #define regSDMA0_QUEUE3_RB_WPTR_HI_DEFAULT                                        0x00000000
244 #define regSDMA0_QUEUE3_RB_RPTR_ADDR_HI_DEFAULT                                   0x00000000
245 #define regSDMA0_QUEUE3_RB_RPTR_ADDR_LO_DEFAULT                                   0x00000000
246 #define regSDMA0_QUEUE3_IB_CNTL_DEFAULT                                           0x00000100
247 #define regSDMA0_QUEUE3_IB_RPTR_DEFAULT                                           0x00000000
248 #define regSDMA0_QUEUE3_IB_OFFSET_DEFAULT                                         0x00000000
249 #define regSDMA0_QUEUE3_IB_BASE_LO_DEFAULT                                        0x00000000
250 #define regSDMA0_QUEUE3_IB_BASE_HI_DEFAULT                                        0x00000000
251 #define regSDMA0_QUEUE3_IB_SIZE_DEFAULT                                           0x00000000
252 #define regSDMA0_QUEUE3_SKIP_CNTL_DEFAULT                                         0x00000000
253 #define regSDMA0_QUEUE3_CONTEXT_STATUS_DEFAULT                                    0x00000804
254 #define regSDMA0_QUEUE3_DOORBELL_DEFAULT                                          0x00000000
255 #define regSDMA0_QUEUE3_DOORBELL_LOG_DEFAULT                                      0x00000000
256 #define regSDMA0_QUEUE3_DOORBELL_OFFSET_DEFAULT                                   0x00000000
257 #define regSDMA0_QUEUE3_CSA_ADDR_LO_DEFAULT                                       0x00000000
258 #define regSDMA0_QUEUE3_CSA_ADDR_HI_DEFAULT                                       0x00000000
259 #define regSDMA0_QUEUE3_SCHEDULE_CNTL_DEFAULT                                     0x00000000
260 #define regSDMA0_QUEUE3_IB_SUB_REMAIN_DEFAULT                                     0x00000000
261 #define regSDMA0_QUEUE3_PREEMPT_DEFAULT                                           0x00000000
262 #define regSDMA0_QUEUE3_DUMMY_REG_DEFAULT                                         0x0000000f
263 #define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI_DEFAULT                              0x00000000
264 #define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO_DEFAULT                              0x00000000
265 #define regSDMA0_QUEUE3_RB_AQL_CNTL_DEFAULT                                       0x00004000
266 #define regSDMA0_QUEUE3_MINOR_PTR_UPDATE_DEFAULT                                  0x00000000
267 #define regSDMA0_QUEUE3_RB_PREEMPT_DEFAULT                                        0x00000000
268 #define regSDMA0_QUEUE3_MIDCMD_DATA0_DEFAULT                                      0x00000000
269 #define regSDMA0_QUEUE3_MIDCMD_DATA1_DEFAULT                                      0x00000000
270 #define regSDMA0_QUEUE3_MIDCMD_DATA2_DEFAULT                                      0x00000000
271 #define regSDMA0_QUEUE3_MIDCMD_DATA3_DEFAULT                                      0x00000000
272 #define regSDMA0_QUEUE3_MIDCMD_DATA4_DEFAULT                                      0x00000000
273 #define regSDMA0_QUEUE3_MIDCMD_DATA5_DEFAULT                                      0x00000000
274 #define regSDMA0_QUEUE3_MIDCMD_DATA6_DEFAULT                                      0x00000000
275 #define regSDMA0_QUEUE3_MIDCMD_DATA7_DEFAULT                                      0x00000000
276 #define regSDMA0_QUEUE3_MIDCMD_DATA8_DEFAULT                                      0x00000000
277 #define regSDMA0_QUEUE3_MIDCMD_DATA9_DEFAULT                                      0x00000000
278 #define regSDMA0_QUEUE3_MIDCMD_DATA10_DEFAULT                                     0x00000000
279 #define regSDMA0_QUEUE3_MIDCMD_CNTL_DEFAULT                                       0x00000000
280 #define regSDMA0_QUEUE4_RB_CNTL_DEFAULT                                           0x00040800
281 #define regSDMA0_QUEUE4_RB_BASE_DEFAULT                                           0x00000000
282 #define regSDMA0_QUEUE4_RB_BASE_HI_DEFAULT                                        0x00000000
283 #define regSDMA0_QUEUE4_RB_RPTR_DEFAULT                                           0x00000000
284 #define regSDMA0_QUEUE4_RB_RPTR_HI_DEFAULT                                        0x00000000
285 #define regSDMA0_QUEUE4_RB_WPTR_DEFAULT                                           0x00000000
286 #define regSDMA0_QUEUE4_RB_WPTR_HI_DEFAULT                                        0x00000000
287 #define regSDMA0_QUEUE4_RB_RPTR_ADDR_HI_DEFAULT                                   0x00000000
288 #define regSDMA0_QUEUE4_RB_RPTR_ADDR_LO_DEFAULT                                   0x00000000
289 #define regSDMA0_QUEUE4_IB_CNTL_DEFAULT                                           0x00000100
290 #define regSDMA0_QUEUE4_IB_RPTR_DEFAULT                                           0x00000000
291 #define regSDMA0_QUEUE4_IB_OFFSET_DEFAULT                                         0x00000000
292 #define regSDMA0_QUEUE4_IB_BASE_LO_DEFAULT                                        0x00000000
293 #define regSDMA0_QUEUE4_IB_BASE_HI_DEFAULT                                        0x00000000
294 #define regSDMA0_QUEUE4_IB_SIZE_DEFAULT                                           0x00000000
295 #define regSDMA0_QUEUE4_SKIP_CNTL_DEFAULT                                         0x00000000
296 #define regSDMA0_QUEUE4_CONTEXT_STATUS_DEFAULT                                    0x00000804
297 #define regSDMA0_QUEUE4_DOORBELL_DEFAULT                                          0x00000000
298 #define regSDMA0_QUEUE4_DOORBELL_LOG_DEFAULT                                      0x00000000
299 #define regSDMA0_QUEUE4_DOORBELL_OFFSET_DEFAULT                                   0x00000000
300 #define regSDMA0_QUEUE4_CSA_ADDR_LO_DEFAULT                                       0x00000000
301 #define regSDMA0_QUEUE4_CSA_ADDR_HI_DEFAULT                                       0x00000000
302 #define regSDMA0_QUEUE4_SCHEDULE_CNTL_DEFAULT                                     0x00000000
303 #define regSDMA0_QUEUE4_IB_SUB_REMAIN_DEFAULT                                     0x00000000
304 #define regSDMA0_QUEUE4_PREEMPT_DEFAULT                                           0x00000000
305 #define regSDMA0_QUEUE4_DUMMY_REG_DEFAULT                                         0x0000000f
306 #define regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI_DEFAULT                              0x00000000
307 #define regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO_DEFAULT                              0x00000000
308 #define regSDMA0_QUEUE4_RB_AQL_CNTL_DEFAULT                                       0x00004000
309 #define regSDMA0_QUEUE4_MINOR_PTR_UPDATE_DEFAULT                                  0x00000000
310 #define regSDMA0_QUEUE4_RB_PREEMPT_DEFAULT                                        0x00000000
311 #define regSDMA0_QUEUE4_MIDCMD_DATA0_DEFAULT                                      0x00000000
312 #define regSDMA0_QUEUE4_MIDCMD_DATA1_DEFAULT                                      0x00000000
313 #define regSDMA0_QUEUE4_MIDCMD_DATA2_DEFAULT                                      0x00000000
314 #define regSDMA0_QUEUE4_MIDCMD_DATA3_DEFAULT                                      0x00000000
315 #define regSDMA0_QUEUE4_MIDCMD_DATA4_DEFAULT                                      0x00000000
316 #define regSDMA0_QUEUE4_MIDCMD_DATA5_DEFAULT                                      0x00000000
317 #define regSDMA0_QUEUE4_MIDCMD_DATA6_DEFAULT                                      0x00000000
318 #define regSDMA0_QUEUE4_MIDCMD_DATA7_DEFAULT                                      0x00000000
319 #define regSDMA0_QUEUE4_MIDCMD_DATA8_DEFAULT                                      0x00000000
320 #define regSDMA0_QUEUE4_MIDCMD_DATA9_DEFAULT                                      0x00000000
321 #define regSDMA0_QUEUE4_MIDCMD_DATA10_DEFAULT                                     0x00000000
322 #define regSDMA0_QUEUE4_MIDCMD_CNTL_DEFAULT                                       0x00000000
323 #define regSDMA0_QUEUE5_RB_CNTL_DEFAULT                                           0x00040800
324 #define regSDMA0_QUEUE5_RB_BASE_DEFAULT                                           0x00000000
325 #define regSDMA0_QUEUE5_RB_BASE_HI_DEFAULT                                        0x00000000
326 #define regSDMA0_QUEUE5_RB_RPTR_DEFAULT                                           0x00000000
327 #define regSDMA0_QUEUE5_RB_RPTR_HI_DEFAULT                                        0x00000000
328 #define regSDMA0_QUEUE5_RB_WPTR_DEFAULT                                           0x00000000
329 #define regSDMA0_QUEUE5_RB_WPTR_HI_DEFAULT                                        0x00000000
330 #define regSDMA0_QUEUE5_RB_RPTR_ADDR_HI_DEFAULT                                   0x00000000
331 #define regSDMA0_QUEUE5_RB_RPTR_ADDR_LO_DEFAULT                                   0x00000000
332 #define regSDMA0_QUEUE5_IB_CNTL_DEFAULT                                           0x00000100
333 #define regSDMA0_QUEUE5_IB_RPTR_DEFAULT                                           0x00000000
334 #define regSDMA0_QUEUE5_IB_OFFSET_DEFAULT                                         0x00000000
335 #define regSDMA0_QUEUE5_IB_BASE_LO_DEFAULT                                        0x00000000
336 #define regSDMA0_QUEUE5_IB_BASE_HI_DEFAULT                                        0x00000000
337 #define regSDMA0_QUEUE5_IB_SIZE_DEFAULT                                           0x00000000
338 #define regSDMA0_QUEUE5_SKIP_CNTL_DEFAULT                                         0x00000000
339 #define regSDMA0_QUEUE5_CONTEXT_STATUS_DEFAULT                                    0x00000804
340 #define regSDMA0_QUEUE5_DOORBELL_DEFAULT                                          0x00000000
341 #define regSDMA0_QUEUE5_DOORBELL_LOG_DEFAULT                                      0x00000000
342 #define regSDMA0_QUEUE5_DOORBELL_OFFSET_DEFAULT                                   0x00000000
343 #define regSDMA0_QUEUE5_CSA_ADDR_LO_DEFAULT                                       0x00000000
344 #define regSDMA0_QUEUE5_CSA_ADDR_HI_DEFAULT                                       0x00000000
345 #define regSDMA0_QUEUE5_SCHEDULE_CNTL_DEFAULT                                     0x00000000
346 #define regSDMA0_QUEUE5_IB_SUB_REMAIN_DEFAULT                                     0x00000000
347 #define regSDMA0_QUEUE5_PREEMPT_DEFAULT                                           0x00000000
348 #define regSDMA0_QUEUE5_DUMMY_REG_DEFAULT                                         0x0000000f
349 #define regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI_DEFAULT                              0x00000000
350 #define regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO_DEFAULT                              0x00000000
351 #define regSDMA0_QUEUE5_RB_AQL_CNTL_DEFAULT                                       0x00004000
352 #define regSDMA0_QUEUE5_MINOR_PTR_UPDATE_DEFAULT                                  0x00000000
353 #define regSDMA0_QUEUE5_RB_PREEMPT_DEFAULT                                        0x00000000
354 #define regSDMA0_QUEUE5_MIDCMD_DATA0_DEFAULT                                      0x00000000
355 #define regSDMA0_QUEUE5_MIDCMD_DATA1_DEFAULT                                      0x00000000
356 #define regSDMA0_QUEUE5_MIDCMD_DATA2_DEFAULT                                      0x00000000
357 #define regSDMA0_QUEUE5_MIDCMD_DATA3_DEFAULT                                      0x00000000
358 #define regSDMA0_QUEUE5_MIDCMD_DATA4_DEFAULT                                      0x00000000
359 #define regSDMA0_QUEUE5_MIDCMD_DATA5_DEFAULT                                      0x00000000
360 #define regSDMA0_QUEUE5_MIDCMD_DATA6_DEFAULT                                      0x00000000
361 #define regSDMA0_QUEUE5_MIDCMD_DATA7_DEFAULT                                      0x00000000
362 #define regSDMA0_QUEUE5_MIDCMD_DATA8_DEFAULT                                      0x00000000
363 #define regSDMA0_QUEUE5_MIDCMD_DATA9_DEFAULT                                      0x00000000
364 #define regSDMA0_QUEUE5_MIDCMD_DATA10_DEFAULT                                     0x00000000
365 #define regSDMA0_QUEUE5_MIDCMD_CNTL_DEFAULT                                       0x00000000
366 #define regSDMA0_QUEUE6_RB_CNTL_DEFAULT                                           0x00040800
367 #define regSDMA0_QUEUE6_RB_BASE_DEFAULT                                           0x00000000
368 #define regSDMA0_QUEUE6_RB_BASE_HI_DEFAULT                                        0x00000000
369 #define regSDMA0_QUEUE6_RB_RPTR_DEFAULT                                           0x00000000
370 #define regSDMA0_QUEUE6_RB_RPTR_HI_DEFAULT                                        0x00000000
371 #define regSDMA0_QUEUE6_RB_WPTR_DEFAULT                                           0x00000000
372 #define regSDMA0_QUEUE6_RB_WPTR_HI_DEFAULT                                        0x00000000
373 #define regSDMA0_QUEUE6_RB_RPTR_ADDR_HI_DEFAULT                                   0x00000000
374 #define regSDMA0_QUEUE6_RB_RPTR_ADDR_LO_DEFAULT                                   0x00000000
375 #define regSDMA0_QUEUE6_IB_CNTL_DEFAULT                                           0x00000100
376 #define regSDMA0_QUEUE6_IB_RPTR_DEFAULT                                           0x00000000
377 #define regSDMA0_QUEUE6_IB_OFFSET_DEFAULT                                         0x00000000
378 #define regSDMA0_QUEUE6_IB_BASE_LO_DEFAULT                                        0x00000000
379 #define regSDMA0_QUEUE6_IB_BASE_HI_DEFAULT                                        0x00000000
380 #define regSDMA0_QUEUE6_IB_SIZE_DEFAULT                                           0x00000000
381 #define regSDMA0_QUEUE6_SKIP_CNTL_DEFAULT                                         0x00000000
382 #define regSDMA0_QUEUE6_CONTEXT_STATUS_DEFAULT                                    0x00000804
383 #define regSDMA0_QUEUE6_DOORBELL_DEFAULT                                          0x00000000
384 #define regSDMA0_QUEUE6_DOORBELL_LOG_DEFAULT                                      0x00000000
385 #define regSDMA0_QUEUE6_DOORBELL_OFFSET_DEFAULT                                   0x00000000
386 #define regSDMA0_QUEUE6_CSA_ADDR_LO_DEFAULT                                       0x00000000
387 #define regSDMA0_QUEUE6_CSA_ADDR_HI_DEFAULT                                       0x00000000
388 #define regSDMA0_QUEUE6_SCHEDULE_CNTL_DEFAULT                                     0x00000000
389 #define regSDMA0_QUEUE6_IB_SUB_REMAIN_DEFAULT                                     0x00000000
390 #define regSDMA0_QUEUE6_PREEMPT_DEFAULT                                           0x00000000
391 #define regSDMA0_QUEUE6_DUMMY_REG_DEFAULT                                         0x0000000f
392 #define regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI_DEFAULT                              0x00000000
393 #define regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO_DEFAULT                              0x00000000
394 #define regSDMA0_QUEUE6_RB_AQL_CNTL_DEFAULT                                       0x00004000
395 #define regSDMA0_QUEUE6_MINOR_PTR_UPDATE_DEFAULT                                  0x00000000
396 #define regSDMA0_QUEUE6_RB_PREEMPT_DEFAULT                                        0x00000000
397 #define regSDMA0_QUEUE6_MIDCMD_DATA0_DEFAULT                                      0x00000000
398 #define regSDMA0_QUEUE6_MIDCMD_DATA1_DEFAULT                                      0x00000000
399 #define regSDMA0_QUEUE6_MIDCMD_DATA2_DEFAULT                                      0x00000000
400 #define regSDMA0_QUEUE6_MIDCMD_DATA3_DEFAULT                                      0x00000000
401 #define regSDMA0_QUEUE6_MIDCMD_DATA4_DEFAULT                                      0x00000000
402 #define regSDMA0_QUEUE6_MIDCMD_DATA5_DEFAULT                                      0x00000000
403 #define regSDMA0_QUEUE6_MIDCMD_DATA6_DEFAULT                                      0x00000000
404 #define regSDMA0_QUEUE6_MIDCMD_DATA7_DEFAULT                                      0x00000000
405 #define regSDMA0_QUEUE6_MIDCMD_DATA8_DEFAULT                                      0x00000000
406 #define regSDMA0_QUEUE6_MIDCMD_DATA9_DEFAULT                                      0x00000000
407 #define regSDMA0_QUEUE6_MIDCMD_DATA10_DEFAULT                                     0x00000000
408 #define regSDMA0_QUEUE6_MIDCMD_CNTL_DEFAULT                                       0x00000000
409 #define regSDMA0_QUEUE7_RB_CNTL_DEFAULT                                           0x00040800
410 #define regSDMA0_QUEUE7_RB_BASE_DEFAULT                                           0x00000000
411 #define regSDMA0_QUEUE7_RB_BASE_HI_DEFAULT                                        0x00000000
412 #define regSDMA0_QUEUE7_RB_RPTR_DEFAULT                                           0x00000000
413 #define regSDMA0_QUEUE7_RB_RPTR_HI_DEFAULT                                        0x00000000
414 #define regSDMA0_QUEUE7_RB_WPTR_DEFAULT                                           0x00000000
415 #define regSDMA0_QUEUE7_RB_WPTR_HI_DEFAULT                                        0x00000000
416 #define regSDMA0_QUEUE7_RB_RPTR_ADDR_HI_DEFAULT                                   0x00000000
417 #define regSDMA0_QUEUE7_RB_RPTR_ADDR_LO_DEFAULT                                   0x00000000
418 #define regSDMA0_QUEUE7_IB_CNTL_DEFAULT                                           0x00000100
419 #define regSDMA0_QUEUE7_IB_RPTR_DEFAULT                                           0x00000000
420 #define regSDMA0_QUEUE7_IB_OFFSET_DEFAULT                                         0x00000000
421 #define regSDMA0_QUEUE7_IB_BASE_LO_DEFAULT                                        0x00000000
422 #define regSDMA0_QUEUE7_IB_BASE_HI_DEFAULT                                        0x00000000
423 #define regSDMA0_QUEUE7_IB_SIZE_DEFAULT                                           0x00000000
424 #define regSDMA0_QUEUE7_SKIP_CNTL_DEFAULT                                         0x00000000
425 #define regSDMA0_QUEUE7_CONTEXT_STATUS_DEFAULT                                    0x00000804
426 #define regSDMA0_QUEUE7_DOORBELL_DEFAULT                                          0x00000000
427 #define regSDMA0_QUEUE7_DOORBELL_LOG_DEFAULT                                      0x00000000
428 #define regSDMA0_QUEUE7_DOORBELL_OFFSET_DEFAULT                                   0x00000000
429 #define regSDMA0_QUEUE7_CSA_ADDR_LO_DEFAULT                                       0x00000000
430 #define regSDMA0_QUEUE7_CSA_ADDR_HI_DEFAULT                                       0x00000000
431 #define regSDMA0_QUEUE7_SCHEDULE_CNTL_DEFAULT                                     0x00000000
432 #define regSDMA0_QUEUE7_IB_SUB_REMAIN_DEFAULT                                     0x00000000
433 #define regSDMA0_QUEUE7_PREEMPT_DEFAULT                                           0x00000000
434 #define regSDMA0_QUEUE7_DUMMY_REG_DEFAULT                                         0x0000000f
435 #define regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI_DEFAULT                              0x00000000
436 #define regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO_DEFAULT                              0x00000000
437 #define regSDMA0_QUEUE7_RB_AQL_CNTL_DEFAULT                                       0x00004000
438 #define regSDMA0_QUEUE7_MINOR_PTR_UPDATE_DEFAULT                                  0x00000000
439 #define regSDMA0_QUEUE7_RB_PREEMPT_DEFAULT                                        0x00000000
440 #define regSDMA0_QUEUE7_MIDCMD_DATA0_DEFAULT                                      0x00000000
441 #define regSDMA0_QUEUE7_MIDCMD_DATA1_DEFAULT                                      0x00000000
442 #define regSDMA0_QUEUE7_MIDCMD_DATA2_DEFAULT                                      0x00000000
443 #define regSDMA0_QUEUE7_MIDCMD_DATA3_DEFAULT                                      0x00000000
444 #define regSDMA0_QUEUE7_MIDCMD_DATA4_DEFAULT                                      0x00000000
445 #define regSDMA0_QUEUE7_MIDCMD_DATA5_DEFAULT                                      0x00000000
446 #define regSDMA0_QUEUE7_MIDCMD_DATA6_DEFAULT                                      0x00000000
447 #define regSDMA0_QUEUE7_MIDCMD_DATA7_DEFAULT                                      0x00000000
448 #define regSDMA0_QUEUE7_MIDCMD_DATA8_DEFAULT                                      0x00000000
449 #define regSDMA0_QUEUE7_MIDCMD_DATA9_DEFAULT                                      0x00000000
450 #define regSDMA0_QUEUE7_MIDCMD_DATA10_DEFAULT                                     0x00000000
451 #define regSDMA0_QUEUE7_MIDCMD_CNTL_DEFAULT                                       0x00000000
452 
453 
454 // addressBlock: gc_sdma0_sdma1dec
455 #define regSDMA1_DEC_START_DEFAULT                                                0x00000000
456 #define regSDMA1_F32_MISC_CNTL_DEFAULT                                            0x00000000
457 #define regSDMA1_GLOBAL_TIMESTAMP_LO_DEFAULT                                      0x00000000
458 #define regSDMA1_GLOBAL_TIMESTAMP_HI_DEFAULT                                      0x00000000
459 #define regSDMA1_POWER_CNTL_DEFAULT                                               0x00000000
460 #define regSDMA1_CNTL_DEFAULT                                                     0x00002440
461 #define regSDMA1_CHICKEN_BITS_DEFAULT                                             0x0107d186
462 #define regSDMA1_GB_ADDR_CONFIG_DEFAULT                                           0x00000545
463 #define regSDMA1_GB_ADDR_CONFIG_READ_DEFAULT                                      0x00000545
464 #define regSDMA1_RB_RPTR_FETCH_DEFAULT                                            0x00000000
465 #define regSDMA1_RB_RPTR_FETCH_HI_DEFAULT                                         0x00000000
466 #define regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT                                 0x00000000
467 #define regSDMA1_IB_OFFSET_FETCH_DEFAULT                                          0x00000000
468 #define regSDMA1_PROGRAM_DEFAULT                                                  0x00000000
469 #define regSDMA1_STATUS_REG_DEFAULT                                               0x46dee557
470 #define regSDMA1_STATUS1_REG_DEFAULT                                              0x000403ff
471 #define regSDMA1_CNTL1_DEFAULT                                                    0x00000c30
472 #define regSDMA1_HBM_PAGE_CONFIG_DEFAULT                                          0x00000000
473 #define regSDMA1_UCODE_CHECKSUM_DEFAULT                                           0x00000000
474 #define regSDMA1_FREEZE_DEFAULT                                                   0x00000000
475 #define regSDMA1_PROCESS_QUANTUM0_DEFAULT                                         0x00000000
476 #define regSDMA1_PROCESS_QUANTUM1_DEFAULT                                         0x00000000
477 #define regSDMA1_WATCHDOG_CNTL_DEFAULT                                            0x00000000
478 #define regSDMA1_QUEUE_STATUS0_DEFAULT                                            0x22222222
479 #define regSDMA1_EDC_CONFIG_DEFAULT                                               0x00000004
480 #define regSDMA1_BA_THRESHOLD_DEFAULT                                             0x03ff03ff
481 #define regSDMA1_ID_DEFAULT                                                       0x00000001
482 #define regSDMA1_VERSION_DEFAULT                                                  0x00000600
483 #define regSDMA1_EDC_COUNTER_DEFAULT                                              0x00000000
484 #define regSDMA1_EDC_COUNTER_CLEAR_DEFAULT                                        0x00000000
485 #define regSDMA1_STATUS2_REG_DEFAULT                                              0x00000000
486 #define regSDMA1_ATOMIC_CNTL_DEFAULT                                              0x00000200
487 #define regSDMA1_ATOMIC_PREOP_LO_DEFAULT                                          0x00000000
488 #define regSDMA1_ATOMIC_PREOP_HI_DEFAULT                                          0x00000000
489 #define regSDMA1_UTCL1_CNTL_DEFAULT                                               0x2c000288
490 #define regSDMA1_UTCL1_WATERMK_DEFAULT                                            0x00000000
491 #define regSDMA1_UTCL1_TIMEOUT_DEFAULT                                            0x00000000
492 #define regSDMA1_UTCL1_PAGE_DEFAULT                                               0x010cec00
493 #define regSDMA1_UTCL1_RD_STATUS_DEFAULT                                          0xb90700ff
494 #define regSDMA1_UTCL1_WR_STATUS_DEFAULT                                          0xf90780ff
495 #define regSDMA1_UTCL1_INV0_DEFAULT                                               0x00000000
496 #define regSDMA1_UTCL1_INV1_DEFAULT                                               0x00000000
497 #define regSDMA1_UTCL1_INV2_DEFAULT                                               0x00000000
498 #define regSDMA1_UTCL1_RD_XNACK0_DEFAULT                                          0x00000000
499 #define regSDMA1_UTCL1_RD_XNACK1_DEFAULT                                          0x00000000
500 #define regSDMA1_UTCL1_WR_XNACK0_DEFAULT                                          0x00000000
501 #define regSDMA1_UTCL1_WR_XNACK1_DEFAULT                                          0x00000000
502 #define regSDMA1_RELAX_ORDERING_LUT_DEFAULT                                       0xc0000806
503 #define regSDMA1_CHICKEN_BITS_2_DEFAULT                                           0x400007c9
504 #define regSDMA1_STATUS3_REG_DEFAULT                                              0x03f00000
505 #define regSDMA1_PHYSICAL_ADDR_LO_DEFAULT                                         0x00000000
506 #define regSDMA1_PHYSICAL_ADDR_HI_DEFAULT                                         0x00000000
507 #define regSDMA1_GLOBAL_QUANTUM_DEFAULT                                           0x00000000
508 #define regSDMA1_ERROR_LOG_DEFAULT                                                0x0000000f
509 #define regSDMA1_PUB_DUMMY_REG0_DEFAULT                                           0x00000000
510 #define regSDMA1_PUB_DUMMY_REG1_DEFAULT                                           0x00000000
511 #define regSDMA1_PUB_DUMMY_REG2_DEFAULT                                           0x00000000
512 #define regSDMA1_PUB_DUMMY_REG3_DEFAULT                                           0x00000000
513 #define regSDMA1_F32_COUNTER_DEFAULT                                              0x00000000
514 #define regSDMA1_CRD_CNTL_DEFAULT                                                 0x18694840
515 #define regSDMA1_RLC_CGCG_CTRL_DEFAULT                                            0x00400000
516 #define regSDMA1_AQL_STATUS_DEFAULT                                               0x00000003
517 #define regSDMA1_EA_DBIT_ADDR_DATA_DEFAULT                                        0x0000270d
518 #define regSDMA1_EA_DBIT_ADDR_INDEX_DEFAULT                                       0x00000000
519 #define regSDMA1_TLBI_GCR_CNTL_DEFAULT                                            0x40600454
520 #define regSDMA1_TILING_CONFIG_DEFAULT                                            0x00000000
521 #define regSDMA1_INT_STATUS_DEFAULT                                               0x00000000
522 #define regSDMA1_HOLE_ADDR_LO_DEFAULT                                             0x00000000
523 #define regSDMA1_HOLE_ADDR_HI_DEFAULT                                             0x00000000
524 #define regSDMA1_CLOCK_GATING_STATUS_DEFAULT                                      0x00000000
525 #define regSDMA1_STATUS4_REG_DEFAULT                                              0x00000001
526 #define regSDMA1_SCRATCH_RAM_DATA_DEFAULT                                         0x00000000
527 #define regSDMA1_SCRATCH_RAM_ADDR_DEFAULT                                         0x00000000
528 #define regSDMA1_TIMESTAMP_CNTL_DEFAULT                                           0x00000000
529 #define regSDMA1_STATUS5_REG_DEFAULT                                              0x00000000
530 #define regSDMA1_QUEUE_RESET_REQ_DEFAULT                                          0x00000000
531 #define regSDMA1_STATUS6_REG_DEFAULT                                              0x00000000
532 #define regSDMA1_UCODE1_CHECKSUM_DEFAULT                                          0x00000000
533 #define regSDMA1_CE_CTRL_DEFAULT                                                  0x00000000
534 #define regSDMA1_FED_STATUS_DEFAULT                                               0x00000000
535 #define regSDMA1_QUEUE0_RB_CNTL_DEFAULT                                           0x00040800
536 #define regSDMA1_QUEUE0_RB_BASE_DEFAULT                                           0x00000000
537 #define regSDMA1_QUEUE0_RB_BASE_HI_DEFAULT                                        0x00000000
538 #define regSDMA1_QUEUE0_RB_RPTR_DEFAULT                                           0x00000000
539 #define regSDMA1_QUEUE0_RB_RPTR_HI_DEFAULT                                        0x00000000
540 #define regSDMA1_QUEUE0_RB_WPTR_DEFAULT                                           0x00000000
541 #define regSDMA1_QUEUE0_RB_WPTR_HI_DEFAULT                                        0x00000000
542 #define regSDMA1_QUEUE0_RB_RPTR_ADDR_HI_DEFAULT                                   0x00000000
543 #define regSDMA1_QUEUE0_RB_RPTR_ADDR_LO_DEFAULT                                   0x00000000
544 #define regSDMA1_QUEUE0_IB_CNTL_DEFAULT                                           0x00000100
545 #define regSDMA1_QUEUE0_IB_RPTR_DEFAULT                                           0x00000000
546 #define regSDMA1_QUEUE0_IB_OFFSET_DEFAULT                                         0x00000000
547 #define regSDMA1_QUEUE0_IB_BASE_LO_DEFAULT                                        0x00000000
548 #define regSDMA1_QUEUE0_IB_BASE_HI_DEFAULT                                        0x00000000
549 #define regSDMA1_QUEUE0_IB_SIZE_DEFAULT                                           0x00000000
550 #define regSDMA1_QUEUE0_SKIP_CNTL_DEFAULT                                         0x00000000
551 #define regSDMA1_QUEUE0_CONTEXT_STATUS_DEFAULT                                    0x00000804
552 #define regSDMA1_QUEUE0_DOORBELL_DEFAULT                                          0x00000000
553 #define regSDMA1_QUEUE0_DOORBELL_LOG_DEFAULT                                      0x00000000
554 #define regSDMA1_QUEUE0_DOORBELL_OFFSET_DEFAULT                                   0x00000000
555 #define regSDMA1_QUEUE0_CSA_ADDR_LO_DEFAULT                                       0x00000000
556 #define regSDMA1_QUEUE0_CSA_ADDR_HI_DEFAULT                                       0x00000000
557 #define regSDMA1_QUEUE0_SCHEDULE_CNTL_DEFAULT                                     0x00000000
558 #define regSDMA1_QUEUE0_IB_SUB_REMAIN_DEFAULT                                     0x00000000
559 #define regSDMA1_QUEUE0_PREEMPT_DEFAULT                                           0x00000000
560 #define regSDMA1_QUEUE0_DUMMY_REG_DEFAULT                                         0x0000000f
561 #define regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI_DEFAULT                              0x00000000
562 #define regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO_DEFAULT                              0x00000000
563 #define regSDMA1_QUEUE0_RB_AQL_CNTL_DEFAULT                                       0x00004000
564 #define regSDMA1_QUEUE0_MINOR_PTR_UPDATE_DEFAULT                                  0x00000000
565 #define regSDMA1_QUEUE0_RB_PREEMPT_DEFAULT                                        0x00000000
566 #define regSDMA1_QUEUE0_MIDCMD_DATA0_DEFAULT                                      0x00000000
567 #define regSDMA1_QUEUE0_MIDCMD_DATA1_DEFAULT                                      0x00000000
568 #define regSDMA1_QUEUE0_MIDCMD_DATA2_DEFAULT                                      0x00000000
569 #define regSDMA1_QUEUE0_MIDCMD_DATA3_DEFAULT                                      0x00000000
570 #define regSDMA1_QUEUE0_MIDCMD_DATA4_DEFAULT                                      0x00000000
571 #define regSDMA1_QUEUE0_MIDCMD_DATA5_DEFAULT                                      0x00000000
572 #define regSDMA1_QUEUE0_MIDCMD_DATA6_DEFAULT                                      0x00000000
573 #define regSDMA1_QUEUE0_MIDCMD_DATA7_DEFAULT                                      0x00000000
574 #define regSDMA1_QUEUE0_MIDCMD_DATA8_DEFAULT                                      0x00000000
575 #define regSDMA1_QUEUE0_MIDCMD_DATA9_DEFAULT                                      0x00000000
576 #define regSDMA1_QUEUE0_MIDCMD_DATA10_DEFAULT                                     0x00000000
577 #define regSDMA1_QUEUE0_MIDCMD_CNTL_DEFAULT                                       0x00000000
578 #define regSDMA1_QUEUE1_RB_CNTL_DEFAULT                                           0x00040800
579 #define regSDMA1_QUEUE1_RB_BASE_DEFAULT                                           0x00000000
580 #define regSDMA1_QUEUE1_RB_BASE_HI_DEFAULT                                        0x00000000
581 #define regSDMA1_QUEUE1_RB_RPTR_DEFAULT                                           0x00000000
582 #define regSDMA1_QUEUE1_RB_RPTR_HI_DEFAULT                                        0x00000000
583 #define regSDMA1_QUEUE1_RB_WPTR_DEFAULT                                           0x00000000
584 #define regSDMA1_QUEUE1_RB_WPTR_HI_DEFAULT                                        0x00000000
585 #define regSDMA1_QUEUE1_RB_RPTR_ADDR_HI_DEFAULT                                   0x00000000
586 #define regSDMA1_QUEUE1_RB_RPTR_ADDR_LO_DEFAULT                                   0x00000000
587 #define regSDMA1_QUEUE1_IB_CNTL_DEFAULT                                           0x00000100
588 #define regSDMA1_QUEUE1_IB_RPTR_DEFAULT                                           0x00000000
589 #define regSDMA1_QUEUE1_IB_OFFSET_DEFAULT                                         0x00000000
590 #define regSDMA1_QUEUE1_IB_BASE_LO_DEFAULT                                        0x00000000
591 #define regSDMA1_QUEUE1_IB_BASE_HI_DEFAULT                                        0x00000000
592 #define regSDMA1_QUEUE1_IB_SIZE_DEFAULT                                           0x00000000
593 #define regSDMA1_QUEUE1_SKIP_CNTL_DEFAULT                                         0x00000000
594 #define regSDMA1_QUEUE1_CONTEXT_STATUS_DEFAULT                                    0x00000804
595 #define regSDMA1_QUEUE1_DOORBELL_DEFAULT                                          0x00000000
596 #define regSDMA1_QUEUE1_DOORBELL_LOG_DEFAULT                                      0x00000000
597 #define regSDMA1_QUEUE1_DOORBELL_OFFSET_DEFAULT                                   0x00000000
598 #define regSDMA1_QUEUE1_CSA_ADDR_LO_DEFAULT                                       0x00000000
599 #define regSDMA1_QUEUE1_CSA_ADDR_HI_DEFAULT                                       0x00000000
600 #define regSDMA1_QUEUE1_SCHEDULE_CNTL_DEFAULT                                     0x00000000
601 #define regSDMA1_QUEUE1_IB_SUB_REMAIN_DEFAULT                                     0x00000000
602 #define regSDMA1_QUEUE1_PREEMPT_DEFAULT                                           0x00000000
603 #define regSDMA1_QUEUE1_DUMMY_REG_DEFAULT                                         0x0000000f
604 #define regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI_DEFAULT                              0x00000000
605 #define regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO_DEFAULT                              0x00000000
606 #define regSDMA1_QUEUE1_RB_AQL_CNTL_DEFAULT                                       0x00004000
607 #define regSDMA1_QUEUE1_MINOR_PTR_UPDATE_DEFAULT                                  0x00000000
608 #define regSDMA1_QUEUE1_RB_PREEMPT_DEFAULT                                        0x00000000
609 #define regSDMA1_QUEUE1_MIDCMD_DATA0_DEFAULT                                      0x00000000
610 #define regSDMA1_QUEUE1_MIDCMD_DATA1_DEFAULT                                      0x00000000
611 #define regSDMA1_QUEUE1_MIDCMD_DATA2_DEFAULT                                      0x00000000
612 #define regSDMA1_QUEUE1_MIDCMD_DATA3_DEFAULT                                      0x00000000
613 #define regSDMA1_QUEUE1_MIDCMD_DATA4_DEFAULT                                      0x00000000
614 #define regSDMA1_QUEUE1_MIDCMD_DATA5_DEFAULT                                      0x00000000
615 #define regSDMA1_QUEUE1_MIDCMD_DATA6_DEFAULT                                      0x00000000
616 #define regSDMA1_QUEUE1_MIDCMD_DATA7_DEFAULT                                      0x00000000
617 #define regSDMA1_QUEUE1_MIDCMD_DATA8_DEFAULT                                      0x00000000
618 #define regSDMA1_QUEUE1_MIDCMD_DATA9_DEFAULT                                      0x00000000
619 #define regSDMA1_QUEUE1_MIDCMD_DATA10_DEFAULT                                     0x00000000
620 #define regSDMA1_QUEUE1_MIDCMD_CNTL_DEFAULT                                       0x00000000
621 #define regSDMA1_QUEUE2_RB_CNTL_DEFAULT                                           0x00040800
622 #define regSDMA1_QUEUE2_RB_BASE_DEFAULT                                           0x00000000
623 #define regSDMA1_QUEUE2_RB_BASE_HI_DEFAULT                                        0x00000000
624 #define regSDMA1_QUEUE2_RB_RPTR_DEFAULT                                           0x00000000
625 #define regSDMA1_QUEUE2_RB_RPTR_HI_DEFAULT                                        0x00000000
626 #define regSDMA1_QUEUE2_RB_WPTR_DEFAULT                                           0x00000000
627 #define regSDMA1_QUEUE2_RB_WPTR_HI_DEFAULT                                        0x00000000
628 #define regSDMA1_QUEUE2_RB_RPTR_ADDR_HI_DEFAULT                                   0x00000000
629 #define regSDMA1_QUEUE2_RB_RPTR_ADDR_LO_DEFAULT                                   0x00000000
630 #define regSDMA1_QUEUE2_IB_CNTL_DEFAULT                                           0x00000100
631 #define regSDMA1_QUEUE2_IB_RPTR_DEFAULT                                           0x00000000
632 #define regSDMA1_QUEUE2_IB_OFFSET_DEFAULT                                         0x00000000
633 #define regSDMA1_QUEUE2_IB_BASE_LO_DEFAULT                                        0x00000000
634 #define regSDMA1_QUEUE2_IB_BASE_HI_DEFAULT                                        0x00000000
635 #define regSDMA1_QUEUE2_IB_SIZE_DEFAULT                                           0x00000000
636 #define regSDMA1_QUEUE2_SKIP_CNTL_DEFAULT                                         0x00000000
637 #define regSDMA1_QUEUE2_CONTEXT_STATUS_DEFAULT                                    0x00000804
638 #define regSDMA1_QUEUE2_DOORBELL_DEFAULT                                          0x00000000
639 #define regSDMA1_QUEUE2_DOORBELL_LOG_DEFAULT                                      0x00000000
640 #define regSDMA1_QUEUE2_DOORBELL_OFFSET_DEFAULT                                   0x00000000
641 #define regSDMA1_QUEUE2_CSA_ADDR_LO_DEFAULT                                       0x00000000
642 #define regSDMA1_QUEUE2_CSA_ADDR_HI_DEFAULT                                       0x00000000
643 #define regSDMA1_QUEUE2_SCHEDULE_CNTL_DEFAULT                                     0x00000000
644 #define regSDMA1_QUEUE2_IB_SUB_REMAIN_DEFAULT                                     0x00000000
645 #define regSDMA1_QUEUE2_PREEMPT_DEFAULT                                           0x00000000
646 #define regSDMA1_QUEUE2_DUMMY_REG_DEFAULT                                         0x0000000f
647 #define regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI_DEFAULT                              0x00000000
648 #define regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO_DEFAULT                              0x00000000
649 #define regSDMA1_QUEUE2_RB_AQL_CNTL_DEFAULT                                       0x00004000
650 #define regSDMA1_QUEUE2_MINOR_PTR_UPDATE_DEFAULT                                  0x00000000
651 #define regSDMA1_QUEUE2_RB_PREEMPT_DEFAULT                                        0x00000000
652 #define regSDMA1_QUEUE2_MIDCMD_DATA0_DEFAULT                                      0x00000000
653 #define regSDMA1_QUEUE2_MIDCMD_DATA1_DEFAULT                                      0x00000000
654 #define regSDMA1_QUEUE2_MIDCMD_DATA2_DEFAULT                                      0x00000000
655 #define regSDMA1_QUEUE2_MIDCMD_DATA3_DEFAULT                                      0x00000000
656 #define regSDMA1_QUEUE2_MIDCMD_DATA4_DEFAULT                                      0x00000000
657 #define regSDMA1_QUEUE2_MIDCMD_DATA5_DEFAULT                                      0x00000000
658 #define regSDMA1_QUEUE2_MIDCMD_DATA6_DEFAULT                                      0x00000000
659 #define regSDMA1_QUEUE2_MIDCMD_DATA7_DEFAULT                                      0x00000000
660 #define regSDMA1_QUEUE2_MIDCMD_DATA8_DEFAULT                                      0x00000000
661 #define regSDMA1_QUEUE2_MIDCMD_DATA9_DEFAULT                                      0x00000000
662 #define regSDMA1_QUEUE2_MIDCMD_DATA10_DEFAULT                                     0x00000000
663 #define regSDMA1_QUEUE2_MIDCMD_CNTL_DEFAULT                                       0x00000000
664 #define regSDMA1_QUEUE3_RB_CNTL_DEFAULT                                           0x00040800
665 #define regSDMA1_QUEUE3_RB_BASE_DEFAULT                                           0x00000000
666 #define regSDMA1_QUEUE3_RB_BASE_HI_DEFAULT                                        0x00000000
667 #define regSDMA1_QUEUE3_RB_RPTR_DEFAULT                                           0x00000000
668 #define regSDMA1_QUEUE3_RB_RPTR_HI_DEFAULT                                        0x00000000
669 #define regSDMA1_QUEUE3_RB_WPTR_DEFAULT                                           0x00000000
670 #define regSDMA1_QUEUE3_RB_WPTR_HI_DEFAULT                                        0x00000000
671 #define regSDMA1_QUEUE3_RB_RPTR_ADDR_HI_DEFAULT                                   0x00000000
672 #define regSDMA1_QUEUE3_RB_RPTR_ADDR_LO_DEFAULT                                   0x00000000
673 #define regSDMA1_QUEUE3_IB_CNTL_DEFAULT                                           0x00000100
674 #define regSDMA1_QUEUE3_IB_RPTR_DEFAULT                                           0x00000000
675 #define regSDMA1_QUEUE3_IB_OFFSET_DEFAULT                                         0x00000000
676 #define regSDMA1_QUEUE3_IB_BASE_LO_DEFAULT                                        0x00000000
677 #define regSDMA1_QUEUE3_IB_BASE_HI_DEFAULT                                        0x00000000
678 #define regSDMA1_QUEUE3_IB_SIZE_DEFAULT                                           0x00000000
679 #define regSDMA1_QUEUE3_SKIP_CNTL_DEFAULT                                         0x00000000
680 #define regSDMA1_QUEUE3_CONTEXT_STATUS_DEFAULT                                    0x00000804
681 #define regSDMA1_QUEUE3_DOORBELL_DEFAULT                                          0x00000000
682 #define regSDMA1_QUEUE3_DOORBELL_LOG_DEFAULT                                      0x00000000
683 #define regSDMA1_QUEUE3_DOORBELL_OFFSET_DEFAULT                                   0x00000000
684 #define regSDMA1_QUEUE3_CSA_ADDR_LO_DEFAULT                                       0x00000000
685 #define regSDMA1_QUEUE3_CSA_ADDR_HI_DEFAULT                                       0x00000000
686 #define regSDMA1_QUEUE3_SCHEDULE_CNTL_DEFAULT                                     0x00000000
687 #define regSDMA1_QUEUE3_IB_SUB_REMAIN_DEFAULT                                     0x00000000
688 #define regSDMA1_QUEUE3_PREEMPT_DEFAULT                                           0x00000000
689 #define regSDMA1_QUEUE3_DUMMY_REG_DEFAULT                                         0x0000000f
690 #define regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI_DEFAULT                              0x00000000
691 #define regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO_DEFAULT                              0x00000000
692 #define regSDMA1_QUEUE3_RB_AQL_CNTL_DEFAULT                                       0x00004000
693 #define regSDMA1_QUEUE3_MINOR_PTR_UPDATE_DEFAULT                                  0x00000000
694 #define regSDMA1_QUEUE3_RB_PREEMPT_DEFAULT                                        0x00000000
695 #define regSDMA1_QUEUE3_MIDCMD_DATA0_DEFAULT                                      0x00000000
696 #define regSDMA1_QUEUE3_MIDCMD_DATA1_DEFAULT                                      0x00000000
697 #define regSDMA1_QUEUE3_MIDCMD_DATA2_DEFAULT                                      0x00000000
698 #define regSDMA1_QUEUE3_MIDCMD_DATA3_DEFAULT                                      0x00000000
699 #define regSDMA1_QUEUE3_MIDCMD_DATA4_DEFAULT                                      0x00000000
700 #define regSDMA1_QUEUE3_MIDCMD_DATA5_DEFAULT                                      0x00000000
701 #define regSDMA1_QUEUE3_MIDCMD_DATA6_DEFAULT                                      0x00000000
702 #define regSDMA1_QUEUE3_MIDCMD_DATA7_DEFAULT                                      0x00000000
703 #define regSDMA1_QUEUE3_MIDCMD_DATA8_DEFAULT                                      0x00000000
704 #define regSDMA1_QUEUE3_MIDCMD_DATA9_DEFAULT                                      0x00000000
705 #define regSDMA1_QUEUE3_MIDCMD_DATA10_DEFAULT                                     0x00000000
706 #define regSDMA1_QUEUE3_MIDCMD_CNTL_DEFAULT                                       0x00000000
707 #define regSDMA1_QUEUE4_RB_CNTL_DEFAULT                                           0x00040800
708 #define regSDMA1_QUEUE4_RB_BASE_DEFAULT                                           0x00000000
709 #define regSDMA1_QUEUE4_RB_BASE_HI_DEFAULT                                        0x00000000
710 #define regSDMA1_QUEUE4_RB_RPTR_DEFAULT                                           0x00000000
711 #define regSDMA1_QUEUE4_RB_RPTR_HI_DEFAULT                                        0x00000000
712 #define regSDMA1_QUEUE4_RB_WPTR_DEFAULT                                           0x00000000
713 #define regSDMA1_QUEUE4_RB_WPTR_HI_DEFAULT                                        0x00000000
714 #define regSDMA1_QUEUE4_RB_RPTR_ADDR_HI_DEFAULT                                   0x00000000
715 #define regSDMA1_QUEUE4_RB_RPTR_ADDR_LO_DEFAULT                                   0x00000000
716 #define regSDMA1_QUEUE4_IB_CNTL_DEFAULT                                           0x00000100
717 #define regSDMA1_QUEUE4_IB_RPTR_DEFAULT                                           0x00000000
718 #define regSDMA1_QUEUE4_IB_OFFSET_DEFAULT                                         0x00000000
719 #define regSDMA1_QUEUE4_IB_BASE_LO_DEFAULT                                        0x00000000
720 #define regSDMA1_QUEUE4_IB_BASE_HI_DEFAULT                                        0x00000000
721 #define regSDMA1_QUEUE4_IB_SIZE_DEFAULT                                           0x00000000
722 #define regSDMA1_QUEUE4_SKIP_CNTL_DEFAULT                                         0x00000000
723 #define regSDMA1_QUEUE4_CONTEXT_STATUS_DEFAULT                                    0x00000804
724 #define regSDMA1_QUEUE4_DOORBELL_DEFAULT                                          0x00000000
725 #define regSDMA1_QUEUE4_DOORBELL_LOG_DEFAULT                                      0x00000000
726 #define regSDMA1_QUEUE4_DOORBELL_OFFSET_DEFAULT                                   0x00000000
727 #define regSDMA1_QUEUE4_CSA_ADDR_LO_DEFAULT                                       0x00000000
728 #define regSDMA1_QUEUE4_CSA_ADDR_HI_DEFAULT                                       0x00000000
729 #define regSDMA1_QUEUE4_SCHEDULE_CNTL_DEFAULT                                     0x00000000
730 #define regSDMA1_QUEUE4_IB_SUB_REMAIN_DEFAULT                                     0x00000000
731 #define regSDMA1_QUEUE4_PREEMPT_DEFAULT                                           0x00000000
732 #define regSDMA1_QUEUE4_DUMMY_REG_DEFAULT                                         0x0000000f
733 #define regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI_DEFAULT                              0x00000000
734 #define regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO_DEFAULT                              0x00000000
735 #define regSDMA1_QUEUE4_RB_AQL_CNTL_DEFAULT                                       0x00004000
736 #define regSDMA1_QUEUE4_MINOR_PTR_UPDATE_DEFAULT                                  0x00000000
737 #define regSDMA1_QUEUE4_RB_PREEMPT_DEFAULT                                        0x00000000
738 #define regSDMA1_QUEUE4_MIDCMD_DATA0_DEFAULT                                      0x00000000
739 #define regSDMA1_QUEUE4_MIDCMD_DATA1_DEFAULT                                      0x00000000
740 #define regSDMA1_QUEUE4_MIDCMD_DATA2_DEFAULT                                      0x00000000
741 #define regSDMA1_QUEUE4_MIDCMD_DATA3_DEFAULT                                      0x00000000
742 #define regSDMA1_QUEUE4_MIDCMD_DATA4_DEFAULT                                      0x00000000
743 #define regSDMA1_QUEUE4_MIDCMD_DATA5_DEFAULT                                      0x00000000
744 #define regSDMA1_QUEUE4_MIDCMD_DATA6_DEFAULT                                      0x00000000
745 #define regSDMA1_QUEUE4_MIDCMD_DATA7_DEFAULT                                      0x00000000
746 #define regSDMA1_QUEUE4_MIDCMD_DATA8_DEFAULT                                      0x00000000
747 #define regSDMA1_QUEUE4_MIDCMD_DATA9_DEFAULT                                      0x00000000
748 #define regSDMA1_QUEUE4_MIDCMD_DATA10_DEFAULT                                     0x00000000
749 #define regSDMA1_QUEUE4_MIDCMD_CNTL_DEFAULT                                       0x00000000
750 #define regSDMA1_QUEUE5_RB_CNTL_DEFAULT                                           0x00040800
751 #define regSDMA1_QUEUE5_RB_BASE_DEFAULT                                           0x00000000
752 #define regSDMA1_QUEUE5_RB_BASE_HI_DEFAULT                                        0x00000000
753 #define regSDMA1_QUEUE5_RB_RPTR_DEFAULT                                           0x00000000
754 #define regSDMA1_QUEUE5_RB_RPTR_HI_DEFAULT                                        0x00000000
755 #define regSDMA1_QUEUE5_RB_WPTR_DEFAULT                                           0x00000000
756 #define regSDMA1_QUEUE5_RB_WPTR_HI_DEFAULT                                        0x00000000
757 #define regSDMA1_QUEUE5_RB_RPTR_ADDR_HI_DEFAULT                                   0x00000000
758 #define regSDMA1_QUEUE5_RB_RPTR_ADDR_LO_DEFAULT                                   0x00000000
759 #define regSDMA1_QUEUE5_IB_CNTL_DEFAULT                                           0x00000100
760 #define regSDMA1_QUEUE5_IB_RPTR_DEFAULT                                           0x00000000
761 #define regSDMA1_QUEUE5_IB_OFFSET_DEFAULT                                         0x00000000
762 #define regSDMA1_QUEUE5_IB_BASE_LO_DEFAULT                                        0x00000000
763 #define regSDMA1_QUEUE5_IB_BASE_HI_DEFAULT                                        0x00000000
764 #define regSDMA1_QUEUE5_IB_SIZE_DEFAULT                                           0x00000000
765 #define regSDMA1_QUEUE5_SKIP_CNTL_DEFAULT                                         0x00000000
766 #define regSDMA1_QUEUE5_CONTEXT_STATUS_DEFAULT                                    0x00000804
767 #define regSDMA1_QUEUE5_DOORBELL_DEFAULT                                          0x00000000
768 #define regSDMA1_QUEUE5_DOORBELL_LOG_DEFAULT                                      0x00000000
769 #define regSDMA1_QUEUE5_DOORBELL_OFFSET_DEFAULT                                   0x00000000
770 #define regSDMA1_QUEUE5_CSA_ADDR_LO_DEFAULT                                       0x00000000
771 #define regSDMA1_QUEUE5_CSA_ADDR_HI_DEFAULT                                       0x00000000
772 #define regSDMA1_QUEUE5_SCHEDULE_CNTL_DEFAULT                                     0x00000000
773 #define regSDMA1_QUEUE5_IB_SUB_REMAIN_DEFAULT                                     0x00000000
774 #define regSDMA1_QUEUE5_PREEMPT_DEFAULT                                           0x00000000
775 #define regSDMA1_QUEUE5_DUMMY_REG_DEFAULT                                         0x0000000f
776 #define regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI_DEFAULT                              0x00000000
777 #define regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO_DEFAULT                              0x00000000
778 #define regSDMA1_QUEUE5_RB_AQL_CNTL_DEFAULT                                       0x00004000
779 #define regSDMA1_QUEUE5_MINOR_PTR_UPDATE_DEFAULT                                  0x00000000
780 #define regSDMA1_QUEUE5_RB_PREEMPT_DEFAULT                                        0x00000000
781 #define regSDMA1_QUEUE5_MIDCMD_DATA0_DEFAULT                                      0x00000000
782 #define regSDMA1_QUEUE5_MIDCMD_DATA1_DEFAULT                                      0x00000000
783 #define regSDMA1_QUEUE5_MIDCMD_DATA2_DEFAULT                                      0x00000000
784 #define regSDMA1_QUEUE5_MIDCMD_DATA3_DEFAULT                                      0x00000000
785 #define regSDMA1_QUEUE5_MIDCMD_DATA4_DEFAULT                                      0x00000000
786 #define regSDMA1_QUEUE5_MIDCMD_DATA5_DEFAULT                                      0x00000000
787 #define regSDMA1_QUEUE5_MIDCMD_DATA6_DEFAULT                                      0x00000000
788 #define regSDMA1_QUEUE5_MIDCMD_DATA7_DEFAULT                                      0x00000000
789 #define regSDMA1_QUEUE5_MIDCMD_DATA8_DEFAULT                                      0x00000000
790 #define regSDMA1_QUEUE5_MIDCMD_DATA9_DEFAULT                                      0x00000000
791 #define regSDMA1_QUEUE5_MIDCMD_DATA10_DEFAULT                                     0x00000000
792 #define regSDMA1_QUEUE5_MIDCMD_CNTL_DEFAULT                                       0x00000000
793 #define regSDMA1_QUEUE6_RB_CNTL_DEFAULT                                           0x00040800
794 #define regSDMA1_QUEUE6_RB_BASE_DEFAULT                                           0x00000000
795 #define regSDMA1_QUEUE6_RB_BASE_HI_DEFAULT                                        0x00000000
796 #define regSDMA1_QUEUE6_RB_RPTR_DEFAULT                                           0x00000000
797 #define regSDMA1_QUEUE6_RB_RPTR_HI_DEFAULT                                        0x00000000
798 #define regSDMA1_QUEUE6_RB_WPTR_DEFAULT                                           0x00000000
799 #define regSDMA1_QUEUE6_RB_WPTR_HI_DEFAULT                                        0x00000000
800 #define regSDMA1_QUEUE6_RB_RPTR_ADDR_HI_DEFAULT                                   0x00000000
801 #define regSDMA1_QUEUE6_RB_RPTR_ADDR_LO_DEFAULT                                   0x00000000
802 #define regSDMA1_QUEUE6_IB_CNTL_DEFAULT                                           0x00000100
803 #define regSDMA1_QUEUE6_IB_RPTR_DEFAULT                                           0x00000000
804 #define regSDMA1_QUEUE6_IB_OFFSET_DEFAULT                                         0x00000000
805 #define regSDMA1_QUEUE6_IB_BASE_LO_DEFAULT                                        0x00000000
806 #define regSDMA1_QUEUE6_IB_BASE_HI_DEFAULT                                        0x00000000
807 #define regSDMA1_QUEUE6_IB_SIZE_DEFAULT                                           0x00000000
808 #define regSDMA1_QUEUE6_SKIP_CNTL_DEFAULT                                         0x00000000
809 #define regSDMA1_QUEUE6_CONTEXT_STATUS_DEFAULT                                    0x00000804
810 #define regSDMA1_QUEUE6_DOORBELL_DEFAULT                                          0x00000000
811 #define regSDMA1_QUEUE6_DOORBELL_LOG_DEFAULT                                      0x00000000
812 #define regSDMA1_QUEUE6_DOORBELL_OFFSET_DEFAULT                                   0x00000000
813 #define regSDMA1_QUEUE6_CSA_ADDR_LO_DEFAULT                                       0x00000000
814 #define regSDMA1_QUEUE6_CSA_ADDR_HI_DEFAULT                                       0x00000000
815 #define regSDMA1_QUEUE6_SCHEDULE_CNTL_DEFAULT                                     0x00000000
816 #define regSDMA1_QUEUE6_IB_SUB_REMAIN_DEFAULT                                     0x00000000
817 #define regSDMA1_QUEUE6_PREEMPT_DEFAULT                                           0x00000000
818 #define regSDMA1_QUEUE6_DUMMY_REG_DEFAULT                                         0x0000000f
819 #define regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI_DEFAULT                              0x00000000
820 #define regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO_DEFAULT                              0x00000000
821 #define regSDMA1_QUEUE6_RB_AQL_CNTL_DEFAULT                                       0x00004000
822 #define regSDMA1_QUEUE6_MINOR_PTR_UPDATE_DEFAULT                                  0x00000000
823 #define regSDMA1_QUEUE6_RB_PREEMPT_DEFAULT                                        0x00000000
824 #define regSDMA1_QUEUE6_MIDCMD_DATA0_DEFAULT                                      0x00000000
825 #define regSDMA1_QUEUE6_MIDCMD_DATA1_DEFAULT                                      0x00000000
826 #define regSDMA1_QUEUE6_MIDCMD_DATA2_DEFAULT                                      0x00000000
827 #define regSDMA1_QUEUE6_MIDCMD_DATA3_DEFAULT                                      0x00000000
828 #define regSDMA1_QUEUE6_MIDCMD_DATA4_DEFAULT                                      0x00000000
829 #define regSDMA1_QUEUE6_MIDCMD_DATA5_DEFAULT                                      0x00000000
830 #define regSDMA1_QUEUE6_MIDCMD_DATA6_DEFAULT                                      0x00000000
831 #define regSDMA1_QUEUE6_MIDCMD_DATA7_DEFAULT                                      0x00000000
832 #define regSDMA1_QUEUE6_MIDCMD_DATA8_DEFAULT                                      0x00000000
833 #define regSDMA1_QUEUE6_MIDCMD_DATA9_DEFAULT                                      0x00000000
834 #define regSDMA1_QUEUE6_MIDCMD_DATA10_DEFAULT                                     0x00000000
835 #define regSDMA1_QUEUE6_MIDCMD_CNTL_DEFAULT                                       0x00000000
836 #define regSDMA1_QUEUE7_RB_CNTL_DEFAULT                                           0x00040800
837 #define regSDMA1_QUEUE7_RB_BASE_DEFAULT                                           0x00000000
838 #define regSDMA1_QUEUE7_RB_BASE_HI_DEFAULT                                        0x00000000
839 #define regSDMA1_QUEUE7_RB_RPTR_DEFAULT                                           0x00000000
840 #define regSDMA1_QUEUE7_RB_RPTR_HI_DEFAULT                                        0x00000000
841 #define regSDMA1_QUEUE7_RB_WPTR_DEFAULT                                           0x00000000
842 #define regSDMA1_QUEUE7_RB_WPTR_HI_DEFAULT                                        0x00000000
843 #define regSDMA1_QUEUE7_RB_RPTR_ADDR_HI_DEFAULT                                   0x00000000
844 #define regSDMA1_QUEUE7_RB_RPTR_ADDR_LO_DEFAULT                                   0x00000000
845 #define regSDMA1_QUEUE7_IB_CNTL_DEFAULT                                           0x00000100
846 #define regSDMA1_QUEUE7_IB_RPTR_DEFAULT                                           0x00000000
847 #define regSDMA1_QUEUE7_IB_OFFSET_DEFAULT                                         0x00000000
848 #define regSDMA1_QUEUE7_IB_BASE_LO_DEFAULT                                        0x00000000
849 #define regSDMA1_QUEUE7_IB_BASE_HI_DEFAULT                                        0x00000000
850 #define regSDMA1_QUEUE7_IB_SIZE_DEFAULT                                           0x00000000
851 #define regSDMA1_QUEUE7_SKIP_CNTL_DEFAULT                                         0x00000000
852 #define regSDMA1_QUEUE7_CONTEXT_STATUS_DEFAULT                                    0x00000804
853 #define regSDMA1_QUEUE7_DOORBELL_DEFAULT                                          0x00000000
854 #define regSDMA1_QUEUE7_DOORBELL_LOG_DEFAULT                                      0x00000000
855 #define regSDMA1_QUEUE7_DOORBELL_OFFSET_DEFAULT                                   0x00000000
856 #define regSDMA1_QUEUE7_CSA_ADDR_LO_DEFAULT                                       0x00000000
857 #define regSDMA1_QUEUE7_CSA_ADDR_HI_DEFAULT                                       0x00000000
858 #define regSDMA1_QUEUE7_SCHEDULE_CNTL_DEFAULT                                     0x00000000
859 #define regSDMA1_QUEUE7_IB_SUB_REMAIN_DEFAULT                                     0x00000000
860 #define regSDMA1_QUEUE7_PREEMPT_DEFAULT                                           0x00000000
861 #define regSDMA1_QUEUE7_DUMMY_REG_DEFAULT                                         0x0000000f
862 #define regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI_DEFAULT                              0x00000000
863 #define regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO_DEFAULT                              0x00000000
864 #define regSDMA1_QUEUE7_RB_AQL_CNTL_DEFAULT                                       0x00004000
865 #define regSDMA1_QUEUE7_MINOR_PTR_UPDATE_DEFAULT                                  0x00000000
866 #define regSDMA1_QUEUE7_RB_PREEMPT_DEFAULT                                        0x00000000
867 #define regSDMA1_QUEUE7_MIDCMD_DATA0_DEFAULT                                      0x00000000
868 #define regSDMA1_QUEUE7_MIDCMD_DATA1_DEFAULT                                      0x00000000
869 #define regSDMA1_QUEUE7_MIDCMD_DATA2_DEFAULT                                      0x00000000
870 #define regSDMA1_QUEUE7_MIDCMD_DATA3_DEFAULT                                      0x00000000
871 #define regSDMA1_QUEUE7_MIDCMD_DATA4_DEFAULT                                      0x00000000
872 #define regSDMA1_QUEUE7_MIDCMD_DATA5_DEFAULT                                      0x00000000
873 #define regSDMA1_QUEUE7_MIDCMD_DATA6_DEFAULT                                      0x00000000
874 #define regSDMA1_QUEUE7_MIDCMD_DATA7_DEFAULT                                      0x00000000
875 #define regSDMA1_QUEUE7_MIDCMD_DATA8_DEFAULT                                      0x00000000
876 #define regSDMA1_QUEUE7_MIDCMD_DATA9_DEFAULT                                      0x00000000
877 #define regSDMA1_QUEUE7_MIDCMD_DATA10_DEFAULT                                     0x00000000
878 #define regSDMA1_QUEUE7_MIDCMD_CNTL_DEFAULT                                       0x00000000
879 
880 
881 // addressBlock: gc_grbmdec
882 #define regGRBM_CNTL_DEFAULT                                                      0x00000018
883 #define regGRBM_SKEW_CNTL_DEFAULT                                                 0x00000020
884 #define regGRBM_STATUS2_DEFAULT                                                   0x00000000
885 #define regGRBM_PWR_CNTL_DEFAULT                                                  0x00000000
886 #define regGRBM_STATUS_DEFAULT                                                    0x00000000
887 #define regGRBM_STATUS_SE0_DEFAULT                                                0x00000000
888 #define regGRBM_STATUS_SE1_DEFAULT                                                0x00000000
889 #define regGRBM_STATUS3_DEFAULT                                                   0x00000000
890 #define regGRBM_SOFT_RESET_DEFAULT                                                0x00000000
891 #define regGRBM_GFX_CLKEN_CNTL_DEFAULT                                            0x00000402
892 #define regGRBM_WAIT_IDLE_CLOCKS_DEFAULT                                          0x00000030
893 #define regGRBM_STATUS_SE2_DEFAULT                                                0x00000000
894 #define regGRBM_STATUS_SE3_DEFAULT                                                0x00000000
895 #define regGRBM_STATUS_SE4_DEFAULT                                                0x00000000
896 #define regGRBM_STATUS_SE5_DEFAULT                                                0x00000000
897 #define regGRBM_READ_ERROR_DEFAULT                                                0x00000000
898 #define regGRBM_READ_ERROR2_DEFAULT                                               0x00000000
899 #define regGRBM_INT_CNTL_DEFAULT                                                  0x00000000
900 #define regGRBM_TRAP_OP_DEFAULT                                                   0x00000000
901 #define regGRBM_TRAP_ADDR_DEFAULT                                                 0x00000000
902 #define regGRBM_TRAP_ADDR_MSK_DEFAULT                                             0x0003ffff
903 #define regGRBM_TRAP_WD_DEFAULT                                                   0x00000000
904 #define regGRBM_TRAP_WD_MSK_DEFAULT                                               0xffffffff
905 #define regGRBM_DSM_BYPASS_DEFAULT                                                0x00000000
906 #define regGRBM_WRITE_ERROR_DEFAULT                                               0x00000000
907 #define regGRBM_CHIP_REVISION_DEFAULT                                             0x00000000
908 #define regGRBM_IH_CREDIT_DEFAULT                                                 0x00010000
909 #define regGRBM_PWR_CNTL2_DEFAULT                                                 0x00010000
910 #define regGRBM_UTCL2_INVAL_RANGE_START_DEFAULT                                   0x0000286d
911 #define regGRBM_UTCL2_INVAL_RANGE_END_DEFAULT                                     0x000028c6
912 #define regGRBM_INVALID_PIPE_DEFAULT                                              0x00000000
913 #define regGRBM_FENCE_RANGE0_DEFAULT                                              0x00000000
914 #define regGRBM_FENCE_RANGE1_DEFAULT                                              0x00000000
915 #define regGRBM_SCRATCH_REG0_DEFAULT                                              0x00000000
916 #define regGRBM_SCRATCH_REG1_DEFAULT                                              0x00000000
917 #define regGRBM_SCRATCH_REG2_DEFAULT                                              0x00000000
918 #define regGRBM_SCRATCH_REG3_DEFAULT                                              0x00000000
919 #define regGRBM_SCRATCH_REG4_DEFAULT                                              0x00000000
920 #define regGRBM_SCRATCH_REG5_DEFAULT                                              0x00000000
921 #define regGRBM_SCRATCH_REG6_DEFAULT                                              0x00000000
922 #define regGRBM_SCRATCH_REG7_DEFAULT                                              0x00000000
923 #define regVIOLATION_DATA_ASYNC_VF_PROG_DEFAULT                                   0x00000000
924 
925 
926 // addressBlock: gc_cpdec
927 #define regCP_CPC_DEBUG_CNTL_DEFAULT                                              0x00000000
928 #define regCP_CPC_DEBUG_DATA_DEFAULT                                              0x00000000
929 #define regCP_CPC_STATUS_DEFAULT                                                  0x00000000
930 #define regCP_CPC_BUSY_STAT_DEFAULT                                               0x00000000
931 #define regCP_CPC_STALLED_STAT1_DEFAULT                                           0x00000000
932 #define regCP_CPF_STATUS_DEFAULT                                                  0x00000000
933 #define regCP_CPF_BUSY_STAT_DEFAULT                                               0x00000000
934 #define regCP_CPF_STALLED_STAT1_DEFAULT                                           0x00000000
935 #define regCP_CPC_BUSY_STAT2_DEFAULT                                              0x00000000
936 #define regCP_CPC_GRBM_FREE_COUNT_DEFAULT                                         0x00000008
937 #define regCP_CPC_PRIV_VIOLATION_ADDR_DEFAULT                                     0x00000000
938 #define regCP_MEC_ME1_HEADER_DUMP_DEFAULT                                         0xdef0def0
939 #define regCP_MEC_ME2_HEADER_DUMP_DEFAULT                                         0xdef0def0
940 #define regCP_CPC_SCRATCH_INDEX_DEFAULT                                           0x00000000
941 #define regCP_CPC_SCRATCH_DATA_DEFAULT                                            0x00000000
942 #define regCP_CPF_GRBM_FREE_COUNT_DEFAULT                                         0x00000002
943 #define regCP_CPF_BUSY_STAT2_DEFAULT                                              0x00000000
944 #define regCP_CPC_HALT_HYST_COUNT_DEFAULT                                         0x00000002
945 #define regCP_STALLED_STAT3_DEFAULT                                               0x00000000
946 #define regCP_STALLED_STAT1_DEFAULT                                               0x00000000
947 #define regCP_STALLED_STAT2_DEFAULT                                               0x00000000
948 #define regCP_BUSY_STAT_DEFAULT                                                   0x00000000
949 #define regCP_STAT_DEFAULT                                                        0x00000000
950 #define regCP_ME_HEADER_DUMP_DEFAULT                                              0xdef0def0
951 #define regCP_PFP_HEADER_DUMP_DEFAULT                                             0xdef0def0
952 #define regCP_GRBM_FREE_COUNT_DEFAULT                                             0x000c0c0c
953 #define regCP_PFP_INSTR_PNTR_DEFAULT                                              0x00000000
954 #define regCP_ME_INSTR_PNTR_DEFAULT                                               0x00000000
955 #define regCP_MEC1_INSTR_PNTR_DEFAULT                                             0x00000000
956 #define regCP_MEC2_INSTR_PNTR_DEFAULT                                             0x00000000
957 #define regCP_CSF_STAT_DEFAULT                                                    0x00000000
958 #define regCP_CNTX_STAT_DEFAULT                                                   0x00000000
959 #define regCP_ME_PREEMPTION_DEFAULT                                               0x00000000
960 #define regCP_RB1_RPTR_DEFAULT                                                    0x00000000
961 #define regCP_RB0_RPTR_DEFAULT                                                    0x00000000
962 #define regCP_RB_RPTR_DEFAULT                                                     0x00000000
963 #define regCP_RB_WPTR_DELAY_DEFAULT                                               0x00000000
964 #define regCP_RB_WPTR_POLL_CNTL_DEFAULT                                           0x00400000
965 #define regCP_ROQ1_THRESHOLDS_DEFAULT                                             0x06008010
966 #define regCP_ROQ2_THRESHOLDS_DEFAULT                                             0x000380a0
967 #define regCP_STQ_THRESHOLDS_DEFAULT                                              0x00804000
968 #define regCP_MEQ_THRESHOLDS_DEFAULT                                              0x00008040
969 #define regCP_ROQ_AVAIL_DEFAULT                                                   0x02000080
970 #define regCP_STQ_AVAIL_DEFAULT                                                   0x00000000
971 #define regCP_ROQ2_AVAIL_DEFAULT                                                  0x00800200
972 #define regCP_MEQ_AVAIL_DEFAULT                                                   0x00000200
973 #define regCP_CMD_INDEX_DEFAULT                                                   0x00000000
974 #define regCP_CMD_DATA_DEFAULT                                                    0x00000000
975 #define regCP_ROQ_RB_STAT_DEFAULT                                                 0x00000000
976 #define regCP_ROQ_IB1_STAT_DEFAULT                                                0x01600160
977 #define regCP_ROQ_IB2_STAT_DEFAULT                                                0x05000500
978 #define regCP_STQ_STAT_DEFAULT                                                    0x00000000
979 #define regCP_STQ_WR_STAT_DEFAULT                                                 0x00000000
980 #define regCP_MEQ_STAT_DEFAULT                                                    0x00000000
981 #define regCP_ROQ3_THRESHOLDS_DEFAULT                                             0x00050120
982 #define regCP_ROQ_DB_STAT_DEFAULT                                                 0x09000900
983 #define regCP_DEBUG_CNTL_DEFAULT                                                  0x00000000
984 #define regCP_DEBUG_DATA_DEFAULT                                                  0x00000000
985 #define regCP_PRIV_VIOLATION_ADDR_DEFAULT                                         0x00000000
986 
987 
988 // addressBlock: gc_padec
989 #define regVGT_DMA_DATA_FIFO_DEPTH_DEFAULT                                        0x00000200
990 #define regVGT_DMA_REQ_FIFO_DEPTH_DEFAULT                                         0x00000020
991 #define regVGT_DRAW_INIT_FIFO_DEPTH_DEFAULT                                       0x00000020
992 #define regVGT_MC_LAT_CNTL_DEFAULT                                                0x00000002
993 #define regIA_UTCL1_STATUS_2_DEFAULT                                              0x00000000
994 #define regWD_CNTL_STATUS_DEFAULT                                                 0x00000000
995 #define regCC_GC_PRIM_CONFIG_DEFAULT                                              0x000faaa0
996 #define regWD_QOS_DEFAULT                                                         0x00000000
997 #define regWD_UTCL1_CNTL_DEFAULT                                                  0x00000080
998 #define regWD_UTCL1_STATUS_DEFAULT                                                0x00000000
999 #define regIA_UTCL1_CNTL_DEFAULT                                                  0x00000080
1000 #define regIA_UTCL1_STATUS_DEFAULT                                                0x00000000
1001 #define regCC_GC_SA_UNIT_DISABLE_DEFAULT                                          0x00f00000
1002 #define regGE_RATE_CNTL_1_DEFAULT                                                 0x10101010
1003 #define regGE_RATE_CNTL_2_DEFAULT                                                 0x00001010
1004 #define regVGT_SYS_CONFIG_DEFAULT                                                 0x00000011
1005 #define regGE_PRIV_CONTROL_DEFAULT                                                0x000001fe
1006 #define regGE_STATUS_DEFAULT                                                      0x00000000
1007 #define regVGT_GS_MAX_WAVE_ID_DEFAULT                                             0x00000bff
1008 #define regGFX_PIPE_CONTROL_DEFAULT                                               0x00000000
1009 #define regCC_GC_SHADER_ARRAY_CONFIG_DEFAULT                                      0xfff00000
1010 #define regGE2_SE_CNTL_STATUS_DEFAULT                                             0x00000000
1011 #define regGE_SPI_IF_SAFE_REG_DEFAULT                                             0x00020db6
1012 #define regGE_PA_IF_SAFE_REG_DEFAULT                                              0x0000dc37
1013 #define regPA_CL_CNTL_STATUS_DEFAULT                                              0x00000000
1014 #define regPA_CL_ENHANCE_DEFAULT                                                  0x00080007
1015 #define regPA_SU_CNTL_STATUS_DEFAULT                                              0x00000000
1016 #define regPA_SC_FIFO_DEPTH_CNTL_DEFAULT                                          0x00000034
1017 
1018 
1019 // addressBlock: gc_sqdec
1020 #define regSQ_CONFIG_DEFAULT                                                      0x00180000
1021 #define regSQC_CONFIG_DEFAULT                                                     0x00028800
1022 #define regLDS_CONFIG_DEFAULT                                                     0x00000000
1023 #define regSQ_RANDOM_WAVE_PRI_DEFAULT                                             0x0000007f
1024 #define regSQG_STATUS_DEFAULT                                                     0x00000000
1025 #define regSQ_FIFO_SIZES_DEFAULT                                                  0x0000d001
1026 #define regSQ_DSM_CNTL_DEFAULT                                                    0x00000000
1027 #define regSQ_DSM_CNTL2_DEFAULT                                                   0x00000000
1028 #define regSP_CONFIG_DEFAULT                                                      0x00000010
1029 #define regSQ_ARB_CONFIG_DEFAULT                                                  0x00000030
1030 #define regSQ_DEBUG_HOST_TRAP_STATUS_DEFAULT                                      0x00000000
1031 #define regSQG_GL1H_STATUS_DEFAULT                                                0x00000000
1032 #define regSQG_CONFIG_DEFAULT                                                     0x00002000
1033 #define regSQ_PERF_SNAPSHOT_CTRL_DEFAULT                                          0x0001fffe
1034 #define regCC_GC_SHADER_RATE_CONFIG_DEFAULT                                       0x00000000
1035 #define regSQ_INTERRUPT_AUTO_MASK_DEFAULT                                         0x00ffffff
1036 #define regSQ_INTERRUPT_MSG_CTRL_DEFAULT                                          0x00000000
1037 #define regSQ_WATCH0_ADDR_H_DEFAULT                                               0x00000000
1038 #define regSQ_WATCH0_ADDR_L_DEFAULT                                               0x00000000
1039 #define regSQ_WATCH0_CNTL_DEFAULT                                                 0x00000000
1040 #define regSQ_WATCH1_ADDR_H_DEFAULT                                               0x00000000
1041 #define regSQ_WATCH1_ADDR_L_DEFAULT                                               0x00000000
1042 #define regSQ_WATCH1_CNTL_DEFAULT                                                 0x00000000
1043 #define regSQ_WATCH2_ADDR_H_DEFAULT                                               0x00000000
1044 #define regSQ_WATCH2_ADDR_L_DEFAULT                                               0x00000000
1045 #define regSQ_WATCH2_CNTL_DEFAULT                                                 0x00000000
1046 #define regSQ_WATCH3_ADDR_H_DEFAULT                                               0x00000000
1047 #define regSQ_WATCH3_ADDR_L_DEFAULT                                               0x00000000
1048 #define regSQ_WATCH3_CNTL_DEFAULT                                                 0x00000000
1049 #define regSQ_IND_INDEX_DEFAULT                                                   0x00000000
1050 #define regSQ_IND_DATA_DEFAULT                                                    0x00000000
1051 #define regSQ_CMD_DEFAULT                                                         0x00000000
1052 
1053 
1054 // addressBlock: gc_shsdec
1055 #define regSX_DEBUG_1_DEFAULT                                                     0x00000020
1056 #define regSPI_PS_MAX_WAVE_ID_DEFAULT                                             0x020000ff
1057 #define regSPI_GFX_CNTL_DEFAULT                                                   0x00000000
1058 #define regSPI_DSM_CNTL_DEFAULT                                                   0x00000000
1059 #define regSPI_DSM_CNTL2_DEFAULT                                                  0x00000000
1060 #define regSPI_EDC_CNT_DEFAULT                                                    0x00000000
1061 #define regSPI_CONFIG_PS_CU_EN_DEFAULT                                            0x00000000
1062 #define regSPI_WF_LIFETIME_CNTL_DEFAULT                                           0x00000000
1063 #define regSPI_WF_LIFETIME_LIMIT_0_DEFAULT                                        0x00000100
1064 #define regSPI_WF_LIFETIME_LIMIT_1_DEFAULT                                        0x00000100
1065 #define regSPI_WF_LIFETIME_LIMIT_2_DEFAULT                                        0x00000100
1066 #define regSPI_WF_LIFETIME_LIMIT_3_DEFAULT                                        0x00000100
1067 #define regSPI_WF_LIFETIME_LIMIT_4_DEFAULT                                        0x00000100
1068 #define regSPI_WF_LIFETIME_LIMIT_5_DEFAULT                                        0x00000100
1069 #define regSPI_WF_LIFETIME_STATUS_0_DEFAULT                                       0x00000000
1070 #define regSPI_WF_LIFETIME_STATUS_2_DEFAULT                                       0x00000000
1071 #define regSPI_WF_LIFETIME_STATUS_4_DEFAULT                                       0x00000000
1072 #define regSPI_WF_LIFETIME_STATUS_6_DEFAULT                                       0x00000000
1073 #define regSPI_WF_LIFETIME_STATUS_7_DEFAULT                                       0x00000000
1074 #define regSPI_WF_LIFETIME_STATUS_9_DEFAULT                                       0x00000000
1075 #define regSPI_WF_LIFETIME_STATUS_11_DEFAULT                                      0x00000000
1076 #define regSPI_WF_LIFETIME_STATUS_13_DEFAULT                                      0x00000000
1077 #define regSPI_WF_LIFETIME_STATUS_14_DEFAULT                                      0x00000000
1078 #define regSPI_WF_LIFETIME_STATUS_15_DEFAULT                                      0x00000000
1079 #define regSPI_WF_LIFETIME_STATUS_16_DEFAULT                                      0x00000000
1080 #define regSPI_WF_LIFETIME_STATUS_17_DEFAULT                                      0x00000000
1081 #define regSPI_WF_LIFETIME_STATUS_18_DEFAULT                                      0x00000000
1082 #define regSPI_WF_LIFETIME_STATUS_19_DEFAULT                                      0x00000000
1083 #define regSPI_WF_LIFETIME_STATUS_20_DEFAULT                                      0x00000000
1084 #define regSPI_WF_LIFETIME_STATUS_21_DEFAULT                                      0x00000000
1085 #define regSPI_LB_CTR_CTRL_DEFAULT                                                0x00000000
1086 #define regSPI_LB_WGP_MASK_DEFAULT                                                0x0000ffff
1087 #define regSPI_LB_DATA_REG_DEFAULT                                                0x00000000
1088 #define regSPI_PG_ENABLE_STATIC_WGP_MASK_DEFAULT                                  0x0000ffff
1089 #define regSPI_GDS_CREDITS_DEFAULT                                                0x00004040
1090 #define regSPI_SX_EXPORT_BUFFER_SIZES_DEFAULT                                     0x10000160
1091 #define regSPI_SX_SCOREBOARD_BUFFER_SIZES_DEFAULT                                 0x00800040
1092 #define regSPI_CSQ_WF_ACTIVE_STATUS_DEFAULT                                       0x00000000
1093 #define regSPI_CSQ_WF_ACTIVE_COUNT_0_DEFAULT                                      0x00000000
1094 #define regSPI_CSQ_WF_ACTIVE_COUNT_1_DEFAULT                                      0x00000000
1095 #define regSPI_CSQ_WF_ACTIVE_COUNT_2_DEFAULT                                      0x00000000
1096 #define regSPI_CSQ_WF_ACTIVE_COUNT_3_DEFAULT                                      0x00000000
1097 #define regSPI_LB_DATA_WAVES_DEFAULT                                              0x00000000
1098 #define regSPI_P0_TRAP_SCREEN_PSBA_LO_DEFAULT                                     0x00000000
1099 #define regSPI_P0_TRAP_SCREEN_PSBA_HI_DEFAULT                                     0x00000000
1100 #define regSPI_P0_TRAP_SCREEN_PSMA_LO_DEFAULT                                     0x00000000
1101 #define regSPI_P0_TRAP_SCREEN_PSMA_HI_DEFAULT                                     0x00000000
1102 #define regSPI_P0_TRAP_SCREEN_GPR_MIN_DEFAULT                                     0x00000000
1103 #define regSPI_P1_TRAP_SCREEN_PSBA_LO_DEFAULT                                     0x00000000
1104 #define regSPI_P1_TRAP_SCREEN_PSBA_HI_DEFAULT                                     0x00000000
1105 #define regSPI_P1_TRAP_SCREEN_PSMA_LO_DEFAULT                                     0x00000000
1106 #define regSPI_P1_TRAP_SCREEN_PSMA_HI_DEFAULT                                     0x00000000
1107 #define regSPI_P1_TRAP_SCREEN_GPR_MIN_DEFAULT                                     0x00000000
1108 
1109 
1110 // addressBlock: gc_tpdec
1111 #define regTD_STATUS_DEFAULT                                                      0x00000000
1112 #define regTD_DSM_CNTL_DEFAULT                                                    0x00000000
1113 #define regTD_DSM_CNTL2_DEFAULT                                                   0x00000000
1114 #define regTD_SCRATCH_DEFAULT                                                     0x00000000
1115 #define regTA_CNTL_DEFAULT                                                        0xc0040000
1116 #define regTA_CNTL_AUX_DEFAULT                                                    0x01030000
1117 #define regTA_CNTL2_DEFAULT                                                       0x00000000
1118 #define regTA_STATUS_DEFAULT                                                      0x00000000
1119 #define regTA_SCRATCH_DEFAULT                                                     0x00000000
1120 
1121 
1122 // addressBlock: gc_gdsdec
1123 #define regGDS_CONFIG_DEFAULT                                                     0x00000000
1124 #define regGDS_CNTL_STATUS_DEFAULT                                                0x00000000
1125 #define regGDS_ENHANCE_DEFAULT                                                    0x00000000
1126 #define regGDS_PROTECTION_FAULT_DEFAULT                                           0x00000000
1127 #define regGDS_VM_PROTECTION_FAULT_DEFAULT                                        0x00000000
1128 #define regGDS_EDC_CNT_DEFAULT                                                    0x00000000
1129 #define regGDS_EDC_GRBM_CNT_DEFAULT                                               0x00000000
1130 #define regGDS_EDC_OA_DED_DEFAULT                                                 0x00000000
1131 #define regGDS_DSM_CNTL_DEFAULT                                                   0x00000000
1132 #define regGDS_EDC_OA_PHY_CNT_DEFAULT                                             0x00000000
1133 #define regGDS_EDC_OA_PIPE_CNT_DEFAULT                                            0x00000000
1134 #define regGDS_DSM_CNTL2_DEFAULT                                                  0x00000000
1135 
1136 
1137 // addressBlock: gc_rbdec
1138 #define regDB_DEBUG_DEFAULT                                                       0x00000000
1139 #define regDB_DEBUG2_DEFAULT                                                      0x00000420
1140 #define regDB_DEBUG3_DEFAULT                                                      0x00000000
1141 #define regDB_DEBUG4_DEFAULT                                                      0x04000000
1142 #define regDB_ETILE_STUTTER_CONTROL_DEFAULT                                       0x00000000
1143 #define regDB_LTILE_STUTTER_CONTROL_DEFAULT                                       0x00000000
1144 #define regDB_EQUAD_STUTTER_CONTROL_DEFAULT                                       0x00000000
1145 #define regDB_LQUAD_STUTTER_CONTROL_DEFAULT                                       0x00000000
1146 #define regDB_CREDIT_LIMIT_DEFAULT                                                0x00000000
1147 #define regDB_WATERMARKS_DEFAULT                                                  0x0a040a05
1148 #define regDB_SUBTILE_CONTROL_DEFAULT                                             0x00000000
1149 #define regDB_FREE_CACHELINES_DEFAULT                                             0x00000000
1150 #define regDB_FIFO_DEPTH1_DEFAULT                                                 0x00000000
1151 #define regDB_FIFO_DEPTH2_DEFAULT                                                 0x00000000
1152 #define regDB_LAST_OF_BURST_CONFIG_DEFAULT                                        0x00c28210
1153 #define regDB_RING_CONTROL_DEFAULT                                                0x00000001
1154 #define regDB_MEM_ARB_WATERMARKS_DEFAULT                                          0x04040404
1155 #define regDB_FIFO_DEPTH3_DEFAULT                                                 0x00000000
1156 #define regDB_DEBUG6_DEFAULT                                                      0x00100000
1157 #define regDB_EXCEPTION_CONTROL_DEFAULT                                           0x00000000
1158 #define regDB_DEBUG7_DEFAULT                                                      0x00000000
1159 #define regDB_DEBUG5_DEFAULT                                                      0x00000000
1160 #define regDB_FGCG_SRAMS_CLK_CTRL_DEFAULT                                         0x00000000
1161 #define regDB_FGCG_INTERFACES_CLK_CTRL_DEFAULT                                    0x00000000
1162 #define regDB_FIFO_DEPTH4_DEFAULT                                                 0x00000000
1163 #define regCC_RB_REDUNDANCY_DEFAULT                                               0x00000000
1164 #define regCC_RB_BACKEND_DISABLE_DEFAULT                                          0x00000000
1165 #define regGB_ADDR_CONFIG_DEFAULT                                                 0x00000545
1166 #define regGB_BACKEND_MAP_DEFAULT                                                 0x00000000
1167 #define regGB_GPU_ID_DEFAULT                                                      0x00000000
1168 #define regCC_RB_DAISY_CHAIN_DEFAULT                                              0x76543210
1169 #define regGB_ADDR_CONFIG_READ_DEFAULT                                            0x00000545
1170 #define regCB_HW_CONTROL_4_DEFAULT                                                0x00001814
1171 #define regCB_HW_CONTROL_3_DEFAULT                                                0x00000000
1172 #define regCB_HW_CONTROL_DEFAULT                                                  0x00000140
1173 #define regCB_HW_CONTROL_1_DEFAULT                                                0x00000000
1174 #define regCB_HW_CONTROL_2_DEFAULT                                                0x00003700
1175 #define regCB_DCC_CONFIG_DEFAULT                                                  0x00000000
1176 #define regCB_HW_MEM_ARBITER_RD_DEFAULT                                           0x00002000
1177 #define regCB_HW_MEM_ARBITER_WR_DEFAULT                                           0x00002000
1178 #define regCB_FGCG_SRAM_OVERRIDE_DEFAULT                                          0x00000000
1179 #define regCB_DCC_CONFIG2_DEFAULT                                                 0x00000000
1180 #define regCHICKEN_BITS_DEFAULT                                                   0x00000000
1181 #define regCB_CACHE_EVICT_POINTS_DEFAULT                                          0x0410051a
1182 
1183 
1184 // addressBlock: gc_gceadec2
1185 #define regGCEA_MISC_DEFAULT                                                      0x0de8bff0
1186 #define regGCEA_LATENCY_SAMPLING_DEFAULT                                          0x00000000
1187 #define regGCEA_MAM_CTRL2_DEFAULT                                                 0x0002ba00
1188 #define regGCEA_MAM_CTRL_DEFAULT                                                  0x0000d000
1189 #define regGCEA_EDC_CNT_DEFAULT                                                   0x00000000
1190 #define regGCEA_EDC_CNT2_DEFAULT                                                  0x00000000
1191 #define regGCEA_DSM_CNTL_DEFAULT                                                  0x00000000
1192 #define regGCEA_DSM_CNTLA_DEFAULT                                                 0x00000000
1193 #define regGCEA_DSM_CNTLB_DEFAULT                                                 0x00000000
1194 #define regGCEA_DSM_CNTL2_DEFAULT                                                 0x00000000
1195 #define regGCEA_DSM_CNTL2A_DEFAULT                                                0x00000000
1196 #define regGCEA_DSM_CNTL2B_DEFAULT                                                0x00000000
1197 #define regGCEA_GL2C_XBR_CREDITS_DEFAULT                                          0x637f637f
1198 #define regGCEA_GL2C_XBR_MAXBURST_DEFAULT                                         0x00333333
1199 #define regGCEA_PROBE_CNTL_DEFAULT                                                0x00000000
1200 #define regGCEA_PROBE_MAP_DEFAULT                                                 0x0000aaaa
1201 #define regGCEA_ERR_STATUS_DEFAULT                                                0x00000300
1202 #define regGCEA_MISC2_DEFAULT                                                     0x00000000
1203 
1204 
1205 // addressBlock: gc_spipdec2
1206 #define regSPI_PQEV_CTRL_DEFAULT                                                  0x00ff1008
1207 #define regSPI_EXP_THROTTLE_CTRL_DEFAULT                                          0x08782e2e
1208 
1209 
1210 // addressBlock: gc_gceadec3
1211 #define regGCEA_RRET_MEM_RESERVE_DEFAULT                                          0x00000000
1212 #define regGCEA_EDC_CNT3_DEFAULT                                                  0x00000000
1213 #define regGCEA_SDP_ENABLE_DEFAULT                                                0x00000000
1214 
1215 
1216 // addressBlock: gc_pmmdec
1217 #define regGCR_PIO_CNTL_DEFAULT                                                   0x80000000
1218 #define regGCR_PIO_DATA_DEFAULT                                                   0x00000000
1219 #define regPMM_CNTL_DEFAULT                                                       0x00000040
1220 #define regPMM_STATUS_DEFAULT                                                     0x00000000
1221 
1222 
1223 // addressBlock: gc_utcl1dec
1224 #define regUTCL1_CTRL_1_DEFAULT                                                   0x00000000
1225 #define regUTCL1_ALOG_DEFAULT                                                     0x00186482
1226 #define regUTCL1_STATUS_DEFAULT                                                   0x00000000
1227 
1228 
1229 // addressBlock: gc_gcvmsharedpfdec
1230 #define regGCMC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT                                   0x00000000
1231 #define regGCMC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT                                  0x00000000
1232 #define regGCMC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT                                  0x00000000
1233 #define regGCMC_VM_FB_OFFSET_DEFAULT                                              0x00000000
1234 #define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT                       0x00000000
1235 #define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT                       0x00000000
1236 #define regGCMC_VM_STEERING_DEFAULT                                               0x00000001
1237 #define regGCMC_MEM_POWER_LS_DEFAULT                                              0x00000208
1238 #define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT                           0x00000000
1239 #define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT                             0x000fffff
1240 #define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START_DEFAULT                             0x00000000
1241 #define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END_DEFAULT                               0x000fffff
1242 #define regGCMC_VM_APT_CNTL_DEFAULT                                               0x0000000c
1243 #define regGCMC_VM_LOCAL_FB_ADDRESS_START_DEFAULT                                 0x00000000
1244 #define regGCMC_VM_LOCAL_FB_ADDRESS_END_DEFAULT                                   0x000fffff
1245 #define regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_DEFAULT                             0x00000000
1246 #define regGCUTCL2_ICG_CTRL_DEFAULT                                               0x00000000
1247 #define regGCUTCL2_CGTT_BUSY_CTRL_DEFAULT                                         0x00000001
1248 #define regGCMC_VM_FB_NOALLOC_CNTL_DEFAULT                                        0x00000010
1249 #define regGCUTCL2_HARVEST_BYPASS_GROUPS_DEFAULT                                  0x00000000
1250 #define regGCUTCL2_GROUP_RET_FAULT_STATUS_DEFAULT                                 0x00000000
1251 
1252 
1253 // addressBlock: gc_gcvml2pfdec
1254 #define regGCVM_L2_CNTL_DEFAULT                                                   0x00080602
1255 #define regGCVM_L2_CNTL2_DEFAULT                                                  0x00000000
1256 #define regGCVM_L2_CNTL3_DEFAULT                                                  0x80120007
1257 #define regGCVM_L2_STATUS_DEFAULT                                                 0x00000000
1258 #define regGCVM_DUMMY_PAGE_FAULT_CNTL_DEFAULT                                     0x00000090
1259 #define regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT                                0x00000000
1260 #define regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT                                0x00000000
1261 #define regGCVM_INVALIDATE_CNTL_DEFAULT                                           0x0000010f
1262 #define regGCVM_L2_PROTECTION_FAULT_CNTL_DEFAULT                                  0x3ffffffc
1263 #define regGCVM_L2_PROTECTION_FAULT_CNTL2_DEFAULT                                 0x000a0000
1264 #define regGCVM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT                              0xffffffff
1265 #define regGCVM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT                              0xffffffff
1266 #define regGCVM_L2_PROTECTION_FAULT_STATUS_DEFAULT                                0x00000000
1267 #define regGCVM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT                             0x00000000
1268 #define regGCVM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT                             0x00000000
1269 #define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT                     0x00000000
1270 #define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT                     0x00000000
1271 #define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT               0x00000000
1272 #define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT               0x00000000
1273 #define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT              0x00000000
1274 #define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT              0x00000000
1275 #define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT                  0x00000000
1276 #define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT                  0x00000000
1277 #define regGCVM_L2_CNTL4_DEFAULT                                                  0x000000c1
1278 #define regGCVM_L2_MM_GROUP_RT_CLASSES_DEFAULT                                    0x00000000
1279 #define regGCVM_L2_BANK_SELECT_RESERVED_CID_DEFAULT                               0x00000000
1280 #define regGCVM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT                              0x00000000
1281 #define regGCVM_L2_CACHE_PARITY_CNTL_DEFAULT                                      0x00000000
1282 #define regGCVM_L2_ICG_CTRL_DEFAULT                                               0x00000000
1283 #define regGCVM_L2_CNTL5_DEFAULT                                                  0x00003fe0
1284 #define regGCVM_L2_GCR_CNTL_DEFAULT                                               0x00000000
1285 #define regGCVML2_WALKER_MACRO_THROTTLE_TIME_DEFAULT                              0x00000000
1286 #define regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_DEFAULT                       0x00000000
1287 #define regGCVML2_WALKER_MICRO_THROTTLE_TIME_DEFAULT                              0x00000000
1288 #define regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_DEFAULT                       0x00000000
1289 #define regGCVM_L2_CGTT_BUSY_CTRL_DEFAULT                                         0x00000001
1290 #define regGCVM_L2_PTE_CACHE_DUMP_CNTL_DEFAULT                                    0x00000000
1291 #define regGCVM_L2_PTE_CACHE_DUMP_READ_DEFAULT                                    0x00000000
1292 #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_DEFAULT                 0x00000000
1293 #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_DEFAULT                 0x00000000
1294 #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_DEFAULT                0x00000000
1295 #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_DEFAULT                0x00000000
1296 #define regGCVM_L2_BANK_SELECT_MASKS_DEFAULT                                      0x00000000
1297 #define regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_DEFAULT                            0x00000000
1298 #define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_DEFAULT                 0x00000000
1299 #define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_DEFAULT               0x00000000
1300 #define regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_DEFAULT                        0x00000000
1301 #define regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_DEFAULT                        0x00000000
1302 
1303 
1304 // addressBlock: gc_gcvmsharedvcdec
1305 #define regGCMC_VM_FB_LOCATION_BASE_DEFAULT                                       0x00000000
1306 #define regGCMC_VM_FB_LOCATION_TOP_DEFAULT                                        0x00000000
1307 #define regGCMC_VM_AGP_TOP_DEFAULT                                                0x00000000
1308 #define regGCMC_VM_AGP_BOT_DEFAULT                                                0x00000000
1309 #define regGCMC_VM_AGP_BASE_DEFAULT                                               0x00000000
1310 #define regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT                               0x00000000
1311 #define regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT                              0x00000000
1312 #define regGCMC_VM_MX_L1_TLB_CNTL_DEFAULT                                         0x00000501
1313 
1314 
1315 // addressBlock: gc_gcvml2vcdec
1316 #define regGCVM_CONTEXT0_CNTL_DEFAULT                                             0x01fffe00
1317 #define regGCVM_CONTEXT1_CNTL_DEFAULT                                             0x01fffe00
1318 #define regGCVM_CONTEXT2_CNTL_DEFAULT                                             0x01fffe00
1319 #define regGCVM_CONTEXT3_CNTL_DEFAULT                                             0x01fffe00
1320 #define regGCVM_CONTEXT4_CNTL_DEFAULT                                             0x01fffe00
1321 #define regGCVM_CONTEXT5_CNTL_DEFAULT                                             0x01fffe00
1322 #define regGCVM_CONTEXT6_CNTL_DEFAULT                                             0x01fffe00
1323 #define regGCVM_CONTEXT7_CNTL_DEFAULT                                             0x01fffe00
1324 #define regGCVM_CONTEXT8_CNTL_DEFAULT                                             0x01fffe00
1325 #define regGCVM_CONTEXT9_CNTL_DEFAULT                                             0x01fffe00
1326 #define regGCVM_CONTEXT10_CNTL_DEFAULT                                            0x01fffe00
1327 #define regGCVM_CONTEXT11_CNTL_DEFAULT                                            0x01fffe00
1328 #define regGCVM_CONTEXT12_CNTL_DEFAULT                                            0x01fffe00
1329 #define regGCVM_CONTEXT13_CNTL_DEFAULT                                            0x01fffe00
1330 #define regGCVM_CONTEXT14_CNTL_DEFAULT                                            0x01fffe00
1331 #define regGCVM_CONTEXT15_CNTL_DEFAULT                                            0x01fffe00
1332 #define regGCVM_CONTEXTS_DISABLE_DEFAULT                                          0x00000000
1333 #define regGCVM_INVALIDATE_ENG0_SEM_DEFAULT                                       0x00000000
1334 #define regGCVM_INVALIDATE_ENG1_SEM_DEFAULT                                       0x00000000
1335 #define regGCVM_INVALIDATE_ENG2_SEM_DEFAULT                                       0x00000000
1336 #define regGCVM_INVALIDATE_ENG3_SEM_DEFAULT                                       0x00000000
1337 #define regGCVM_INVALIDATE_ENG4_SEM_DEFAULT                                       0x00000000
1338 #define regGCVM_INVALIDATE_ENG5_SEM_DEFAULT                                       0x00000000
1339 #define regGCVM_INVALIDATE_ENG6_SEM_DEFAULT                                       0x00000000
1340 #define regGCVM_INVALIDATE_ENG7_SEM_DEFAULT                                       0x00000000
1341 #define regGCVM_INVALIDATE_ENG8_SEM_DEFAULT                                       0x00000000
1342 #define regGCVM_INVALIDATE_ENG9_SEM_DEFAULT                                       0x00000000
1343 #define regGCVM_INVALIDATE_ENG10_SEM_DEFAULT                                      0x00000000
1344 #define regGCVM_INVALIDATE_ENG11_SEM_DEFAULT                                      0x00000000
1345 #define regGCVM_INVALIDATE_ENG12_SEM_DEFAULT                                      0x00000000
1346 #define regGCVM_INVALIDATE_ENG13_SEM_DEFAULT                                      0x00000000
1347 #define regGCVM_INVALIDATE_ENG14_SEM_DEFAULT                                      0x00000000
1348 #define regGCVM_INVALIDATE_ENG15_SEM_DEFAULT                                      0x00000000
1349 #define regGCVM_INVALIDATE_ENG16_SEM_DEFAULT                                      0x00000000
1350 #define regGCVM_INVALIDATE_ENG17_SEM_DEFAULT                                      0x00000000
1351 #define regGCVM_INVALIDATE_ENG0_REQ_DEFAULT                                       0x02f80000
1352 #define regGCVM_INVALIDATE_ENG1_REQ_DEFAULT                                       0x02f80000
1353 #define regGCVM_INVALIDATE_ENG2_REQ_DEFAULT                                       0x02f80000
1354 #define regGCVM_INVALIDATE_ENG3_REQ_DEFAULT                                       0x02f80000
1355 #define regGCVM_INVALIDATE_ENG4_REQ_DEFAULT                                       0x02f80000
1356 #define regGCVM_INVALIDATE_ENG5_REQ_DEFAULT                                       0x02f80000
1357 #define regGCVM_INVALIDATE_ENG6_REQ_DEFAULT                                       0x02f80000
1358 #define regGCVM_INVALIDATE_ENG7_REQ_DEFAULT                                       0x02f80000
1359 #define regGCVM_INVALIDATE_ENG8_REQ_DEFAULT                                       0x02f80000
1360 #define regGCVM_INVALIDATE_ENG9_REQ_DEFAULT                                       0x02f80000
1361 #define regGCVM_INVALIDATE_ENG10_REQ_DEFAULT                                      0x02f80000
1362 #define regGCVM_INVALIDATE_ENG11_REQ_DEFAULT                                      0x02f80000
1363 #define regGCVM_INVALIDATE_ENG12_REQ_DEFAULT                                      0x02f80000
1364 #define regGCVM_INVALIDATE_ENG13_REQ_DEFAULT                                      0x02f80000
1365 #define regGCVM_INVALIDATE_ENG14_REQ_DEFAULT                                      0x02f80000
1366 #define regGCVM_INVALIDATE_ENG15_REQ_DEFAULT                                      0x02f80000
1367 #define regGCVM_INVALIDATE_ENG16_REQ_DEFAULT                                      0x02f80000
1368 #define regGCVM_INVALIDATE_ENG17_REQ_DEFAULT                                      0x02f80000
1369 #define regGCVM_INVALIDATE_ENG0_ACK_DEFAULT                                       0x00000000
1370 #define regGCVM_INVALIDATE_ENG1_ACK_DEFAULT                                       0x00000000
1371 #define regGCVM_INVALIDATE_ENG2_ACK_DEFAULT                                       0x00000000
1372 #define regGCVM_INVALIDATE_ENG3_ACK_DEFAULT                                       0x00000000
1373 #define regGCVM_INVALIDATE_ENG4_ACK_DEFAULT                                       0x00000000
1374 #define regGCVM_INVALIDATE_ENG5_ACK_DEFAULT                                       0x00000000
1375 #define regGCVM_INVALIDATE_ENG6_ACK_DEFAULT                                       0x00000000
1376 #define regGCVM_INVALIDATE_ENG7_ACK_DEFAULT                                       0x00000000
1377 #define regGCVM_INVALIDATE_ENG8_ACK_DEFAULT                                       0x00000000
1378 #define regGCVM_INVALIDATE_ENG9_ACK_DEFAULT                                       0x00000000
1379 #define regGCVM_INVALIDATE_ENG10_ACK_DEFAULT                                      0x00000000
1380 #define regGCVM_INVALIDATE_ENG11_ACK_DEFAULT                                      0x00000000
1381 #define regGCVM_INVALIDATE_ENG12_ACK_DEFAULT                                      0x00000000
1382 #define regGCVM_INVALIDATE_ENG13_ACK_DEFAULT                                      0x00000000
1383 #define regGCVM_INVALIDATE_ENG14_ACK_DEFAULT                                      0x00000000
1384 #define regGCVM_INVALIDATE_ENG15_ACK_DEFAULT                                      0x00000000
1385 #define regGCVM_INVALIDATE_ENG16_ACK_DEFAULT                                      0x00000000
1386 #define regGCVM_INVALIDATE_ENG17_ACK_DEFAULT                                      0x00000000
1387 #define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT                           0x00000000
1388 #define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT                           0x00000000
1389 #define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT                           0x00000000
1390 #define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT                           0x00000000
1391 #define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT                           0x00000000
1392 #define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT                           0x00000000
1393 #define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT                           0x00000000
1394 #define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT                           0x00000000
1395 #define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT                           0x00000000
1396 #define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT                           0x00000000
1397 #define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT                           0x00000000
1398 #define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT                           0x00000000
1399 #define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT                           0x00000000
1400 #define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT                           0x00000000
1401 #define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT                           0x00000000
1402 #define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT                           0x00000000
1403 #define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT                           0x00000000
1404 #define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT                           0x00000000
1405 #define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT                           0x00000000
1406 #define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT                           0x00000000
1407 #define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT                          0x00000000
1408 #define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT                          0x00000000
1409 #define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT                          0x00000000
1410 #define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT                          0x00000000
1411 #define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT                          0x00000000
1412 #define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT                          0x00000000
1413 #define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT                          0x00000000
1414 #define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT                          0x00000000
1415 #define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT                          0x00000000
1416 #define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT                          0x00000000
1417 #define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT                          0x00000000
1418 #define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT                          0x00000000
1419 #define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT                          0x00000000
1420 #define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT                          0x00000000
1421 #define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT                          0x00000000
1422 #define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT                          0x00000000
1423 #define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                        0x00000000
1424 #define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                        0x00000000
1425 #define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                        0x00000000
1426 #define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                        0x00000000
1427 #define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                        0x00000000
1428 #define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                        0x00000000
1429 #define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                        0x00000000
1430 #define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                        0x00000000
1431 #define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                        0x00000000
1432 #define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                        0x00000000
1433 #define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                        0x00000000
1434 #define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                        0x00000000
1435 #define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                        0x00000000
1436 #define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                        0x00000000
1437 #define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                        0x00000000
1438 #define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                        0x00000000
1439 #define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                        0x00000000
1440 #define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                        0x00000000
1441 #define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                        0x00000000
1442 #define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                        0x00000000
1443 #define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                       0x00000000
1444 #define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                       0x00000000
1445 #define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                       0x00000000
1446 #define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                       0x00000000
1447 #define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                       0x00000000
1448 #define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                       0x00000000
1449 #define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                       0x00000000
1450 #define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                       0x00000000
1451 #define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                       0x00000000
1452 #define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                       0x00000000
1453 #define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                       0x00000000
1454 #define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                       0x00000000
1455 #define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT                       0x00000000
1456 #define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT                       0x00000000
1457 #define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT                       0x00000000
1458 #define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT                       0x00000000
1459 #define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT                       0x00000000
1460 #define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT                       0x00000000
1461 #define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT                       0x00000000
1462 #define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT                       0x00000000
1463 #define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT                       0x00000000
1464 #define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT                       0x00000000
1465 #define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT                       0x00000000
1466 #define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT                       0x00000000
1467 #define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT                       0x00000000
1468 #define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT                       0x00000000
1469 #define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT                       0x00000000
1470 #define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT                       0x00000000
1471 #define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT                       0x00000000
1472 #define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT                       0x00000000
1473 #define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT                       0x00000000
1474 #define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT                       0x00000000
1475 #define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT                      0x00000000
1476 #define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT                      0x00000000
1477 #define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT                      0x00000000
1478 #define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT                      0x00000000
1479 #define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT                      0x00000000
1480 #define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT                      0x00000000
1481 #define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT                      0x00000000
1482 #define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT                      0x00000000
1483 #define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT                      0x00000000
1484 #define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT                      0x00000000
1485 #define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT                      0x00000000
1486 #define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT                      0x00000000
1487 #define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT                         0x00000000
1488 #define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT                         0x00000000
1489 #define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT                         0x00000000
1490 #define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT                         0x00000000
1491 #define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT                         0x00000000
1492 #define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT                         0x00000000
1493 #define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT                         0x00000000
1494 #define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT                         0x00000000
1495 #define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT                         0x00000000
1496 #define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT                         0x00000000
1497 #define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT                         0x00000000
1498 #define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT                         0x00000000
1499 #define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT                         0x00000000
1500 #define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT                         0x00000000
1501 #define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT                         0x00000000
1502 #define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT                         0x00000000
1503 #define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT                         0x00000000
1504 #define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT                         0x00000000
1505 #define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT                         0x00000000
1506 #define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT                         0x00000000
1507 #define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT                        0x00000000
1508 #define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT                        0x00000000
1509 #define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT                        0x00000000
1510 #define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT                        0x00000000
1511 #define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT                        0x00000000
1512 #define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT                        0x00000000
1513 #define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT                        0x00000000
1514 #define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT                        0x00000000
1515 #define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT                        0x00000000
1516 #define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT                        0x00000000
1517 #define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT                        0x00000000
1518 #define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT                        0x00000000
1519 #define regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT                      0x00001c80
1520 #define regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT             0x00001c80
1521 #define regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT             0x00001c80
1522 #define regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT             0x00001c80
1523 #define regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT             0x00001c80
1524 #define regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT             0x00001c80
1525 #define regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT             0x00001c80
1526 #define regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT             0x00001c80
1527 #define regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT             0x00001c80
1528 #define regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT             0x00001c80
1529 #define regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT             0x00001c80
1530 #define regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT            0x00001c80
1531 #define regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT            0x00001c80
1532 #define regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT            0x00001c80
1533 #define regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT            0x00001c80
1534 #define regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT            0x00001c80
1535 #define regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT            0x00001c80
1536 
1537 
1538 // addressBlock: gc_gceadec
1539 #define regGCEA_DRAM_RD_CLI2GRP_MAP0_DEFAULT                                      0xa9503aaa
1540 #define regGCEA_DRAM_RD_CLI2GRP_MAP1_DEFAULT                                      0xa9503aaa
1541 #define regGCEA_DRAM_WR_CLI2GRP_MAP0_DEFAULT                                      0xa9503aaa
1542 #define regGCEA_DRAM_WR_CLI2GRP_MAP1_DEFAULT                                      0xa9503aaa
1543 #define regGCEA_DRAM_RD_GRP2VC_MAP_DEFAULT                                        0x00000924
1544 #define regGCEA_DRAM_WR_GRP2VC_MAP_DEFAULT                                        0x00000324
1545 #define regGCEA_DRAM_RD_LAZY_DEFAULT                                              0x78000924
1546 #define regGCEA_DRAM_WR_LAZY_DEFAULT                                              0x78000924
1547 #define regGCEA_DRAM_RD_CAM_CNTL_DEFAULT                                          0x16db4444
1548 #define regGCEA_DRAM_WR_CAM_CNTL_DEFAULT                                          0x16db4444
1549 #define regGCEA_DRAM_PAGE_BURST_DEFAULT                                           0x20082008
1550 #define regGCEA_DRAM_RD_PRI_AGE_DEFAULT                                           0x00db6249
1551 #define regGCEA_DRAM_WR_PRI_AGE_DEFAULT                                           0x00db6249
1552 #define regGCEA_DRAM_RD_PRI_QUEUING_DEFAULT                                       0x00000db6
1553 #define regGCEA_DRAM_WR_PRI_QUEUING_DEFAULT                                       0x00000db6
1554 #define regGCEA_DRAM_RD_PRI_FIXED_DEFAULT                                         0x00000924
1555 #define regGCEA_DRAM_WR_PRI_FIXED_DEFAULT                                         0x00000924
1556 #define regGCEA_DRAM_RD_PRI_URGENCY_DEFAULT                                       0x0000fdb6
1557 #define regGCEA_DRAM_WR_PRI_URGENCY_DEFAULT                                       0x0000fdb6
1558 #define regGCEA_DRAM_RD_PRI_QUANT_PRI1_DEFAULT                                    0x3f3f3f3f
1559 #define regGCEA_DRAM_RD_PRI_QUANT_PRI2_DEFAULT                                    0x7f7f7f7f
1560 #define regGCEA_DRAM_RD_PRI_QUANT_PRI3_DEFAULT                                    0xffffffff
1561 #define regGCEA_DRAM_WR_PRI_QUANT_PRI1_DEFAULT                                    0x3f3f3f3f
1562 #define regGCEA_DRAM_WR_PRI_QUANT_PRI2_DEFAULT                                    0x7f7f7f7f
1563 #define regGCEA_DRAM_WR_PRI_QUANT_PRI3_DEFAULT                                    0xffffffff
1564 #define regGCEA_IO_RD_CLI2GRP_MAP0_DEFAULT                                        0xa9503aaa
1565 #define regGCEA_IO_RD_CLI2GRP_MAP1_DEFAULT                                        0xa9503aaa
1566 #define regGCEA_IO_WR_CLI2GRP_MAP0_DEFAULT                                        0xa9503aaa
1567 #define regGCEA_IO_WR_CLI2GRP_MAP1_DEFAULT                                        0xa9503aaa
1568 #define regGCEA_IO_RD_COMBINE_FLUSH_DEFAULT                                       0x00007777
1569 #define regGCEA_IO_WR_COMBINE_FLUSH_DEFAULT                                       0x00017777
1570 #define regGCEA_IO_GROUP_BURST_DEFAULT                                            0x1f031f03
1571 #define regGCEA_IO_RD_PRI_AGE_DEFAULT                                             0x00db6249
1572 #define regGCEA_IO_WR_PRI_AGE_DEFAULT                                             0x00db6249
1573 #define regGCEA_IO_RD_PRI_QUEUING_DEFAULT                                         0x00000db6
1574 #define regGCEA_IO_WR_PRI_QUEUING_DEFAULT                                         0x00000db6
1575 #define regGCEA_IO_RD_PRI_FIXED_DEFAULT                                           0x00000924
1576 #define regGCEA_IO_WR_PRI_FIXED_DEFAULT                                           0x00000924
1577 #define regGCEA_IO_RD_PRI_URGENCY_DEFAULT                                         0x00000492
1578 #define regGCEA_IO_WR_PRI_URGENCY_DEFAULT                                         0x00000492
1579 #define regGCEA_IO_RD_PRI_URGENCY_MASKING_DEFAULT                                 0xffffffff
1580 #define regGCEA_IO_WR_PRI_URGENCY_MASKING_DEFAULT                                 0xffffffff
1581 #define regGCEA_IO_RD_PRI_QUANT_PRI1_DEFAULT                                      0x3f3f3f3f
1582 #define regGCEA_IO_RD_PRI_QUANT_PRI2_DEFAULT                                      0x7f7f7f7f
1583 #define regGCEA_IO_RD_PRI_QUANT_PRI3_DEFAULT                                      0xffffffff
1584 #define regGCEA_IO_WR_PRI_QUANT_PRI1_DEFAULT                                      0x3f3f3f3f
1585 #define regGCEA_IO_WR_PRI_QUANT_PRI2_DEFAULT                                      0x7f7f7f7f
1586 #define regGCEA_IO_WR_PRI_QUANT_PRI3_DEFAULT                                      0xffffffff
1587 #define regGCEA_SDP_ARB_FINAL_DEFAULT                                             0x00007fff
1588 #define regGCEA_SDP_IO_PRIORITY_DEFAULT                                           0x00000000
1589 #define regGCEA_SDP_CREDITS_DEFAULT                                               0x000101bf
1590 #define regGCEA_SDP_TAG_RESERVE0_DEFAULT                                          0x00000000
1591 #define regGCEA_SDP_TAG_RESERVE1_DEFAULT                                          0x00000000
1592 #define regGCEA_SDP_VCC_RESERVE0_DEFAULT                                          0x00000000
1593 #define regGCEA_SDP_VCC_RESERVE1_DEFAULT                                          0x00000000
1594 
1595 
1596 // addressBlock: gc_shdec
1597 #define regSPI_SHADER_PGM_RSRC4_PS_DEFAULT                                        0x00000000
1598 #define regSPI_SHADER_PGM_CHKSUM_PS_DEFAULT                                       0x00000000
1599 #define regSPI_SHADER_PGM_RSRC3_PS_DEFAULT                                        0x00000000
1600 #define regSPI_SHADER_PGM_LO_PS_DEFAULT                                           0x00000000
1601 #define regSPI_SHADER_PGM_HI_PS_DEFAULT                                           0x00000000
1602 #define regSPI_SHADER_PGM_RSRC1_PS_DEFAULT                                        0x00000000
1603 #define regSPI_SHADER_PGM_RSRC2_PS_DEFAULT                                        0x00000000
1604 #define regSPI_SHADER_USER_DATA_PS_0_DEFAULT                                      0x00000000
1605 #define regSPI_SHADER_USER_DATA_PS_1_DEFAULT                                      0x00000000
1606 #define regSPI_SHADER_USER_DATA_PS_2_DEFAULT                                      0x00000000
1607 #define regSPI_SHADER_USER_DATA_PS_3_DEFAULT                                      0x00000000
1608 #define regSPI_SHADER_USER_DATA_PS_4_DEFAULT                                      0x00000000
1609 #define regSPI_SHADER_USER_DATA_PS_5_DEFAULT                                      0x00000000
1610 #define regSPI_SHADER_USER_DATA_PS_6_DEFAULT                                      0x00000000
1611 #define regSPI_SHADER_USER_DATA_PS_7_DEFAULT                                      0x00000000
1612 #define regSPI_SHADER_USER_DATA_PS_8_DEFAULT                                      0x00000000
1613 #define regSPI_SHADER_USER_DATA_PS_9_DEFAULT                                      0x00000000
1614 #define regSPI_SHADER_USER_DATA_PS_10_DEFAULT                                     0x00000000
1615 #define regSPI_SHADER_USER_DATA_PS_11_DEFAULT                                     0x00000000
1616 #define regSPI_SHADER_USER_DATA_PS_12_DEFAULT                                     0x00000000
1617 #define regSPI_SHADER_USER_DATA_PS_13_DEFAULT                                     0x00000000
1618 #define regSPI_SHADER_USER_DATA_PS_14_DEFAULT                                     0x00000000
1619 #define regSPI_SHADER_USER_DATA_PS_15_DEFAULT                                     0x00000000
1620 #define regSPI_SHADER_USER_DATA_PS_16_DEFAULT                                     0x00000000
1621 #define regSPI_SHADER_USER_DATA_PS_17_DEFAULT                                     0x00000000
1622 #define regSPI_SHADER_USER_DATA_PS_18_DEFAULT                                     0x00000000
1623 #define regSPI_SHADER_USER_DATA_PS_19_DEFAULT                                     0x00000000
1624 #define regSPI_SHADER_USER_DATA_PS_20_DEFAULT                                     0x00000000
1625 #define regSPI_SHADER_USER_DATA_PS_21_DEFAULT                                     0x00000000
1626 #define regSPI_SHADER_USER_DATA_PS_22_DEFAULT                                     0x00000000
1627 #define regSPI_SHADER_USER_DATA_PS_23_DEFAULT                                     0x00000000
1628 #define regSPI_SHADER_USER_DATA_PS_24_DEFAULT                                     0x00000000
1629 #define regSPI_SHADER_USER_DATA_PS_25_DEFAULT                                     0x00000000
1630 #define regSPI_SHADER_USER_DATA_PS_26_DEFAULT                                     0x00000000
1631 #define regSPI_SHADER_USER_DATA_PS_27_DEFAULT                                     0x00000000
1632 #define regSPI_SHADER_USER_DATA_PS_28_DEFAULT                                     0x00000000
1633 #define regSPI_SHADER_USER_DATA_PS_29_DEFAULT                                     0x00000000
1634 #define regSPI_SHADER_USER_DATA_PS_30_DEFAULT                                     0x00000000
1635 #define regSPI_SHADER_USER_DATA_PS_31_DEFAULT                                     0x00000000
1636 #define regSPI_SHADER_REQ_CTRL_PS_DEFAULT                                         0x00000000
1637 #define regSPI_SHADER_USER_ACCUM_PS_0_DEFAULT                                     0x00000000
1638 #define regSPI_SHADER_USER_ACCUM_PS_1_DEFAULT                                     0x00000000
1639 #define regSPI_SHADER_USER_ACCUM_PS_2_DEFAULT                                     0x00000000
1640 #define regSPI_SHADER_USER_ACCUM_PS_3_DEFAULT                                     0x00000000
1641 #define regSPI_SHADER_PGM_CHKSUM_GS_DEFAULT                                       0x00000000
1642 #define regSPI_SHADER_PGM_RSRC4_GS_DEFAULT                                        0x00000000
1643 #define regSPI_SHADER_USER_DATA_ADDR_LO_GS_DEFAULT                                0x00000000
1644 #define regSPI_SHADER_USER_DATA_ADDR_HI_GS_DEFAULT                                0x00000000
1645 #define regSPI_SHADER_PGM_LO_ES_GS_DEFAULT                                        0x00000000
1646 #define regSPI_SHADER_PGM_HI_ES_GS_DEFAULT                                        0x00000000
1647 #define regSPI_SHADER_PGM_RSRC3_GS_DEFAULT                                        0x00000000
1648 #define regSPI_SHADER_PGM_LO_GS_DEFAULT                                           0x00000000
1649 #define regSPI_SHADER_PGM_HI_GS_DEFAULT                                           0x00000000
1650 #define regSPI_SHADER_PGM_RSRC1_GS_DEFAULT                                        0x00000000
1651 #define regSPI_SHADER_PGM_RSRC2_GS_DEFAULT                                        0x00000000
1652 #define regSPI_SHADER_USER_DATA_GS_0_DEFAULT                                      0x00000000
1653 #define regSPI_SHADER_USER_DATA_GS_1_DEFAULT                                      0x00000000
1654 #define regSPI_SHADER_USER_DATA_GS_2_DEFAULT                                      0x00000000
1655 #define regSPI_SHADER_USER_DATA_GS_3_DEFAULT                                      0x00000000
1656 #define regSPI_SHADER_USER_DATA_GS_4_DEFAULT                                      0x00000000
1657 #define regSPI_SHADER_USER_DATA_GS_5_DEFAULT                                      0x00000000
1658 #define regSPI_SHADER_USER_DATA_GS_6_DEFAULT                                      0x00000000
1659 #define regSPI_SHADER_USER_DATA_GS_7_DEFAULT                                      0x00000000
1660 #define regSPI_SHADER_USER_DATA_GS_8_DEFAULT                                      0x00000000
1661 #define regSPI_SHADER_USER_DATA_GS_9_DEFAULT                                      0x00000000
1662 #define regSPI_SHADER_USER_DATA_GS_10_DEFAULT                                     0x00000000
1663 #define regSPI_SHADER_USER_DATA_GS_11_DEFAULT                                     0x00000000
1664 #define regSPI_SHADER_USER_DATA_GS_12_DEFAULT                                     0x00000000
1665 #define regSPI_SHADER_USER_DATA_GS_13_DEFAULT                                     0x00000000
1666 #define regSPI_SHADER_USER_DATA_GS_14_DEFAULT                                     0x00000000
1667 #define regSPI_SHADER_USER_DATA_GS_15_DEFAULT                                     0x00000000
1668 #define regSPI_SHADER_USER_DATA_GS_16_DEFAULT                                     0x00000000
1669 #define regSPI_SHADER_USER_DATA_GS_17_DEFAULT                                     0x00000000
1670 #define regSPI_SHADER_USER_DATA_GS_18_DEFAULT                                     0x00000000
1671 #define regSPI_SHADER_USER_DATA_GS_19_DEFAULT                                     0x00000000
1672 #define regSPI_SHADER_USER_DATA_GS_20_DEFAULT                                     0x00000000
1673 #define regSPI_SHADER_USER_DATA_GS_21_DEFAULT                                     0x00000000
1674 #define regSPI_SHADER_USER_DATA_GS_22_DEFAULT                                     0x00000000
1675 #define regSPI_SHADER_USER_DATA_GS_23_DEFAULT                                     0x00000000
1676 #define regSPI_SHADER_USER_DATA_GS_24_DEFAULT                                     0x00000000
1677 #define regSPI_SHADER_USER_DATA_GS_25_DEFAULT                                     0x00000000
1678 #define regSPI_SHADER_USER_DATA_GS_26_DEFAULT                                     0x00000000
1679 #define regSPI_SHADER_USER_DATA_GS_27_DEFAULT                                     0x00000000
1680 #define regSPI_SHADER_USER_DATA_GS_28_DEFAULT                                     0x00000000
1681 #define regSPI_SHADER_USER_DATA_GS_29_DEFAULT                                     0x00000000
1682 #define regSPI_SHADER_USER_DATA_GS_30_DEFAULT                                     0x00000000
1683 #define regSPI_SHADER_USER_DATA_GS_31_DEFAULT                                     0x00000000
1684 #define regSPI_SHADER_GS_MESHLET_DIM_DEFAULT                                      0x00000000
1685 #define regSPI_SHADER_GS_MESHLET_EXP_ALLOC_DEFAULT                                0x00000000
1686 #define regSPI_SHADER_REQ_CTRL_ESGS_DEFAULT                                       0x00000000
1687 #define regSPI_SHADER_USER_ACCUM_ESGS_0_DEFAULT                                   0x00000000
1688 #define regSPI_SHADER_USER_ACCUM_ESGS_1_DEFAULT                                   0x00000000
1689 #define regSPI_SHADER_USER_ACCUM_ESGS_2_DEFAULT                                   0x00000000
1690 #define regSPI_SHADER_USER_ACCUM_ESGS_3_DEFAULT                                   0x00000000
1691 #define regSPI_SHADER_PGM_LO_ES_DEFAULT                                           0x00000000
1692 #define regSPI_SHADER_PGM_HI_ES_DEFAULT                                           0x00000000
1693 #define regSPI_SHADER_PGM_CHKSUM_HS_DEFAULT                                       0x00000000
1694 #define regSPI_SHADER_PGM_RSRC4_HS_DEFAULT                                        0x00000000
1695 #define regSPI_SHADER_USER_DATA_ADDR_LO_HS_DEFAULT                                0x00000000
1696 #define regSPI_SHADER_USER_DATA_ADDR_HI_HS_DEFAULT                                0x00000000
1697 #define regSPI_SHADER_PGM_LO_LS_HS_DEFAULT                                        0x00000000
1698 #define regSPI_SHADER_PGM_HI_LS_HS_DEFAULT                                        0x00000000
1699 #define regSPI_SHADER_PGM_RSRC3_HS_DEFAULT                                        0x00000000
1700 #define regSPI_SHADER_PGM_LO_HS_DEFAULT                                           0x00000000
1701 #define regSPI_SHADER_PGM_HI_HS_DEFAULT                                           0x00000000
1702 #define regSPI_SHADER_PGM_RSRC1_HS_DEFAULT                                        0x00000000
1703 #define regSPI_SHADER_PGM_RSRC2_HS_DEFAULT                                        0x00000000
1704 #define regSPI_SHADER_USER_DATA_HS_0_DEFAULT                                      0x00000000
1705 #define regSPI_SHADER_USER_DATA_HS_1_DEFAULT                                      0x00000000
1706 #define regSPI_SHADER_USER_DATA_HS_2_DEFAULT                                      0x00000000
1707 #define regSPI_SHADER_USER_DATA_HS_3_DEFAULT                                      0x00000000
1708 #define regSPI_SHADER_USER_DATA_HS_4_DEFAULT                                      0x00000000
1709 #define regSPI_SHADER_USER_DATA_HS_5_DEFAULT                                      0x00000000
1710 #define regSPI_SHADER_USER_DATA_HS_6_DEFAULT                                      0x00000000
1711 #define regSPI_SHADER_USER_DATA_HS_7_DEFAULT                                      0x00000000
1712 #define regSPI_SHADER_USER_DATA_HS_8_DEFAULT                                      0x00000000
1713 #define regSPI_SHADER_USER_DATA_HS_9_DEFAULT                                      0x00000000
1714 #define regSPI_SHADER_USER_DATA_HS_10_DEFAULT                                     0x00000000
1715 #define regSPI_SHADER_USER_DATA_HS_11_DEFAULT                                     0x00000000
1716 #define regSPI_SHADER_USER_DATA_HS_12_DEFAULT                                     0x00000000
1717 #define regSPI_SHADER_USER_DATA_HS_13_DEFAULT                                     0x00000000
1718 #define regSPI_SHADER_USER_DATA_HS_14_DEFAULT                                     0x00000000
1719 #define regSPI_SHADER_USER_DATA_HS_15_DEFAULT                                     0x00000000
1720 #define regSPI_SHADER_USER_DATA_HS_16_DEFAULT                                     0x00000000
1721 #define regSPI_SHADER_USER_DATA_HS_17_DEFAULT                                     0x00000000
1722 #define regSPI_SHADER_USER_DATA_HS_18_DEFAULT                                     0x00000000
1723 #define regSPI_SHADER_USER_DATA_HS_19_DEFAULT                                     0x00000000
1724 #define regSPI_SHADER_USER_DATA_HS_20_DEFAULT                                     0x00000000
1725 #define regSPI_SHADER_USER_DATA_HS_21_DEFAULT                                     0x00000000
1726 #define regSPI_SHADER_USER_DATA_HS_22_DEFAULT                                     0x00000000
1727 #define regSPI_SHADER_USER_DATA_HS_23_DEFAULT                                     0x00000000
1728 #define regSPI_SHADER_USER_DATA_HS_24_DEFAULT                                     0x00000000
1729 #define regSPI_SHADER_USER_DATA_HS_25_DEFAULT                                     0x00000000
1730 #define regSPI_SHADER_USER_DATA_HS_26_DEFAULT                                     0x00000000
1731 #define regSPI_SHADER_USER_DATA_HS_27_DEFAULT                                     0x00000000
1732 #define regSPI_SHADER_USER_DATA_HS_28_DEFAULT                                     0x00000000
1733 #define regSPI_SHADER_USER_DATA_HS_29_DEFAULT                                     0x00000000
1734 #define regSPI_SHADER_USER_DATA_HS_30_DEFAULT                                     0x00000000
1735 #define regSPI_SHADER_USER_DATA_HS_31_DEFAULT                                     0x00000000
1736 #define regSPI_SHADER_REQ_CTRL_LSHS_DEFAULT                                       0x00000000
1737 #define regSPI_SHADER_USER_ACCUM_LSHS_0_DEFAULT                                   0x00000000
1738 #define regSPI_SHADER_USER_ACCUM_LSHS_1_DEFAULT                                   0x00000000
1739 #define regSPI_SHADER_USER_ACCUM_LSHS_2_DEFAULT                                   0x00000000
1740 #define regSPI_SHADER_USER_ACCUM_LSHS_3_DEFAULT                                   0x00000000
1741 #define regSPI_SHADER_PGM_LO_LS_DEFAULT                                           0x00000000
1742 #define regSPI_SHADER_PGM_HI_LS_DEFAULT                                           0x00000000
1743 #define regCOMPUTE_DISPATCH_INITIATOR_DEFAULT                                     0x00000000
1744 #define regCOMPUTE_DIM_X_DEFAULT                                                  0x00000000
1745 #define regCOMPUTE_DIM_Y_DEFAULT                                                  0x00000000
1746 #define regCOMPUTE_DIM_Z_DEFAULT                                                  0x00000000
1747 #define regCOMPUTE_START_X_DEFAULT                                                0x00000000
1748 #define regCOMPUTE_START_Y_DEFAULT                                                0x00000000
1749 #define regCOMPUTE_START_Z_DEFAULT                                                0x00000000
1750 #define regCOMPUTE_NUM_THREAD_X_DEFAULT                                           0x00000000
1751 #define regCOMPUTE_NUM_THREAD_Y_DEFAULT                                           0x00000000
1752 #define regCOMPUTE_NUM_THREAD_Z_DEFAULT                                           0x00000000
1753 #define regCOMPUTE_PIPELINESTAT_ENABLE_DEFAULT                                    0x00000001
1754 #define regCOMPUTE_PERFCOUNT_ENABLE_DEFAULT                                       0x00000000
1755 #define regCOMPUTE_PGM_LO_DEFAULT                                                 0x00000000
1756 #define regCOMPUTE_PGM_HI_DEFAULT                                                 0x00000000
1757 #define regCOMPUTE_DISPATCH_PKT_ADDR_LO_DEFAULT                                   0x00000000
1758 #define regCOMPUTE_DISPATCH_PKT_ADDR_HI_DEFAULT                                   0x00000000
1759 #define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_DEFAULT                               0x00000000
1760 #define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_DEFAULT                               0x00000000
1761 #define regCOMPUTE_PGM_RSRC1_DEFAULT                                              0x00000000
1762 #define regCOMPUTE_PGM_RSRC2_DEFAULT                                              0x00000000
1763 #define regCOMPUTE_VMID_DEFAULT                                                   0x00000000
1764 #define regCOMPUTE_RESOURCE_LIMITS_DEFAULT                                        0x00000000
1765 #define regCOMPUTE_DESTINATION_EN_SE0_DEFAULT                                     0x00000000
1766 #define regCOMPUTE_STATIC_THREAD_MGMT_SE0_DEFAULT                                 0xffffffff
1767 #define regCOMPUTE_DESTINATION_EN_SE1_DEFAULT                                     0x00000000
1768 #define regCOMPUTE_STATIC_THREAD_MGMT_SE1_DEFAULT                                 0xffffffff
1769 #define regCOMPUTE_TMPRING_SIZE_DEFAULT                                           0x00000000
1770 #define regCOMPUTE_DESTINATION_EN_SE2_DEFAULT                                     0x00000000
1771 #define regCOMPUTE_STATIC_THREAD_MGMT_SE2_DEFAULT                                 0xffffffff
1772 #define regCOMPUTE_DESTINATION_EN_SE3_DEFAULT                                     0x00000000
1773 #define regCOMPUTE_STATIC_THREAD_MGMT_SE3_DEFAULT                                 0xffffffff
1774 #define regCOMPUTE_RESTART_X_DEFAULT                                              0x00000000
1775 #define regCOMPUTE_RESTART_Y_DEFAULT                                              0x00000000
1776 #define regCOMPUTE_RESTART_Z_DEFAULT                                              0x00000000
1777 #define regCOMPUTE_THREAD_TRACE_ENABLE_DEFAULT                                    0x00000000
1778 #define regCOMPUTE_MISC_RESERVED_DEFAULT                                          0x00000007
1779 #define regCOMPUTE_DISPATCH_ID_DEFAULT                                            0x00000000
1780 #define regCOMPUTE_THREADGROUP_ID_DEFAULT                                         0x00000000
1781 #define regCOMPUTE_REQ_CTRL_DEFAULT                                               0x00000000
1782 #define regCOMPUTE_USER_ACCUM_0_DEFAULT                                           0x00000000
1783 #define regCOMPUTE_USER_ACCUM_1_DEFAULT                                           0x00000000
1784 #define regCOMPUTE_USER_ACCUM_2_DEFAULT                                           0x00000000
1785 #define regCOMPUTE_USER_ACCUM_3_DEFAULT                                           0x00000000
1786 #define regCOMPUTE_PGM_RSRC3_DEFAULT                                              0x00000000
1787 #define regCOMPUTE_DDID_INDEX_DEFAULT                                             0x00000000
1788 #define regCOMPUTE_SHADER_CHKSUM_DEFAULT                                          0x00000000
1789 #define regCOMPUTE_STATIC_THREAD_MGMT_SE4_DEFAULT                                 0xffffffff
1790 #define regCOMPUTE_STATIC_THREAD_MGMT_SE5_DEFAULT                                 0xffffffff
1791 #define regCOMPUTE_STATIC_THREAD_MGMT_SE6_DEFAULT                                 0xffffffff
1792 #define regCOMPUTE_STATIC_THREAD_MGMT_SE7_DEFAULT                                 0xffffffff
1793 #define regCOMPUTE_DISPATCH_INTERLEAVE_DEFAULT                                    0x00000040
1794 #define regCOMPUTE_RELAUNCH_DEFAULT                                               0x00000000
1795 #define regCOMPUTE_WAVE_RESTORE_ADDR_LO_DEFAULT                                   0x00000000
1796 #define regCOMPUTE_WAVE_RESTORE_ADDR_HI_DEFAULT                                   0x00000000
1797 #define regCOMPUTE_RELAUNCH2_DEFAULT                                              0x00000000
1798 #define regCOMPUTE_USER_DATA_0_DEFAULT                                            0x00000000
1799 #define regCOMPUTE_USER_DATA_1_DEFAULT                                            0x00000000
1800 #define regCOMPUTE_USER_DATA_2_DEFAULT                                            0x00000000
1801 #define regCOMPUTE_USER_DATA_3_DEFAULT                                            0x00000000
1802 #define regCOMPUTE_USER_DATA_4_DEFAULT                                            0x00000000
1803 #define regCOMPUTE_USER_DATA_5_DEFAULT                                            0x00000000
1804 #define regCOMPUTE_USER_DATA_6_DEFAULT                                            0x00000000
1805 #define regCOMPUTE_USER_DATA_7_DEFAULT                                            0x00000000
1806 #define regCOMPUTE_USER_DATA_8_DEFAULT                                            0x00000000
1807 #define regCOMPUTE_USER_DATA_9_DEFAULT                                            0x00000000
1808 #define regCOMPUTE_USER_DATA_10_DEFAULT                                           0x00000000
1809 #define regCOMPUTE_USER_DATA_11_DEFAULT                                           0x00000000
1810 #define regCOMPUTE_USER_DATA_12_DEFAULT                                           0x00000000
1811 #define regCOMPUTE_USER_DATA_13_DEFAULT                                           0x00000000
1812 #define regCOMPUTE_USER_DATA_14_DEFAULT                                           0x00000000
1813 #define regCOMPUTE_USER_DATA_15_DEFAULT                                           0x00000000
1814 #define regCOMPUTE_DISPATCH_TUNNEL_DEFAULT                                        0x00000000
1815 #define regCOMPUTE_DISPATCH_END_DEFAULT                                           0x00000000
1816 #define regCOMPUTE_NOWHERE_DEFAULT                                                0x00000000
1817 #define regSH_RESERVED_REG0_DEFAULT                                               0x00000000
1818 #define regSH_RESERVED_REG1_DEFAULT                                               0x00000000
1819 
1820 
1821 // addressBlock: gc_cppdec
1822 #define regCP_CU_MASK_ADDR_LO_DEFAULT                                             0x00000000
1823 #define regCP_CU_MASK_ADDR_HI_DEFAULT                                             0x00000000
1824 #define regCP_CU_MASK_CNTL_DEFAULT                                                0x00000000
1825 #define regCP_EOPQ_WAIT_TIME_DEFAULT                                              0x0000052c
1826 #define regCP_CPC_MGCG_SYNC_CNTL_DEFAULT                                          0x00001020
1827 #define regCPC_INT_INFO_DEFAULT                                                   0x00000000
1828 #define regCP_VIRT_STATUS_DEFAULT                                                 0x00000000
1829 #define regCPC_INT_ADDR_DEFAULT                                                   0x00000000
1830 #define regCPC_INT_PASID_DEFAULT                                                  0x00000000
1831 #define regCP_GFX_ERROR_DEFAULT                                                   0x00000000
1832 #define regCPG_UTCL1_CNTL_DEFAULT                                                 0x00000080
1833 #define regCPC_UTCL1_CNTL_DEFAULT                                                 0x00000080
1834 #define regCPF_UTCL1_CNTL_DEFAULT                                                 0x00000080
1835 #define regCP_AQL_SMM_STATUS_DEFAULT                                              0x00000000
1836 #define regCP_RB0_BASE_DEFAULT                                                    0xfedcbaef
1837 #define regCP_RB_BASE_DEFAULT                                                     0xfedcbaef
1838 #define regCP_RB0_CNTL_DEFAULT                                                    0x00a00000
1839 #define regCP_RB_CNTL_DEFAULT                                                     0x00a00000
1840 #define regCP_RB_RPTR_WR_DEFAULT                                                  0x00000000
1841 #define regCP_RB0_RPTR_ADDR_DEFAULT                                               0x00000000
1842 #define regCP_RB_RPTR_ADDR_DEFAULT                                                0x00000000
1843 #define regCP_RB0_RPTR_ADDR_HI_DEFAULT                                            0x00000000
1844 #define regCP_RB_RPTR_ADDR_HI_DEFAULT                                             0x00000000
1845 #define regCP_RB0_BUFSZ_MASK_DEFAULT                                              0x00000000
1846 #define regCP_RB_BUFSZ_MASK_DEFAULT                                               0x00000000
1847 #define regCP_INT_CNTL_DEFAULT                                                    0x00000000
1848 #define regCP_INT_STATUS_DEFAULT                                                  0x00000000
1849 #define regCP_DEVICE_ID_DEFAULT                                                   0x00000000
1850 #define regCP_ME0_PIPE_PRIORITY_CNTS_DEFAULT                                      0x08081020
1851 #define regCP_RING_PRIORITY_CNTS_DEFAULT                                          0x08081020
1852 #define regCP_ME0_PIPE0_PRIORITY_DEFAULT                                          0x00000002
1853 #define regCP_RING0_PRIORITY_DEFAULT                                              0x00000002
1854 #define regCP_ME0_PIPE1_PRIORITY_DEFAULT                                          0x00000002
1855 #define regCP_RING1_PRIORITY_DEFAULT                                              0x00000002
1856 #define regCP_FATAL_ERROR_DEFAULT                                                 0x00000000
1857 #define regCP_RB_VMID_DEFAULT                                                     0x00000000
1858 #define regCP_ME0_PIPE0_VMID_DEFAULT                                              0x00000000
1859 #define regCP_ME0_PIPE1_VMID_DEFAULT                                              0x00000000
1860 #define regCP_RB0_WPTR_DEFAULT                                                    0x00000000
1861 #define regCP_RB_WPTR_DEFAULT                                                     0x00000000
1862 #define regCP_RB0_WPTR_HI_DEFAULT                                                 0x00000000
1863 #define regCP_RB_WPTR_HI_DEFAULT                                                  0x00000000
1864 #define regCP_RB1_WPTR_DEFAULT                                                    0x00000000
1865 #define regCP_RB1_WPTR_HI_DEFAULT                                                 0x00000000
1866 #define regCP_PROCESS_QUANTUM_DEFAULT                                             0x00000008
1867 #define regCP_RB_DOORBELL_RANGE_LOWER_DEFAULT                                     0x00000000
1868 #define regCP_RB_DOORBELL_RANGE_UPPER_DEFAULT                                     0x00000108
1869 #define regCP_MEC_DOORBELL_RANGE_LOWER_DEFAULT                                    0x00000110
1870 #define regCP_MEC_DOORBELL_RANGE_UPPER_DEFAULT                                    0x00000ffc
1871 #define regCPG_UTCL1_ERROR_DEFAULT                                                0x00000000
1872 #define regCPC_UTCL1_ERROR_DEFAULT                                                0x00000000
1873 #define regCP_RB1_BASE_DEFAULT                                                    0xfedcbadf
1874 #define regCP_RB1_CNTL_DEFAULT                                                    0x00a00000
1875 #define regCP_RB1_RPTR_ADDR_DEFAULT                                               0x00000000
1876 #define regCP_RB1_RPTR_ADDR_HI_DEFAULT                                            0x00000000
1877 #define regCP_RB1_BUFSZ_MASK_DEFAULT                                              0x00000000
1878 #define regCP_INT_CNTL_RING0_DEFAULT                                              0x00000000
1879 #define regCP_INT_CNTL_RING1_DEFAULT                                              0x00000000
1880 #define regCP_INT_STATUS_RING0_DEFAULT                                            0x00000000
1881 #define regCP_INT_STATUS_RING1_DEFAULT                                            0x00000000
1882 #define regCP_ME_F32_INTERRUPT_DEFAULT                                            0x00000000
1883 #define regCP_PFP_F32_INTERRUPT_DEFAULT                                           0x00000000
1884 #define regCP_MEC1_F32_INTERRUPT_DEFAULT                                          0x00000000
1885 #define regCP_MEC2_F32_INTERRUPT_DEFAULT                                          0x00000000
1886 #define regCP_PWR_CNTL_DEFAULT                                                    0x00000000
1887 #define regCP_ECC_FIRSTOCCURRENCE_DEFAULT                                         0x00000000
1888 #define regCP_ECC_FIRSTOCCURRENCE_RING0_DEFAULT                                   0x00000000
1889 #define regCP_ECC_FIRSTOCCURRENCE_RING1_DEFAULT                                   0x00000000
1890 #define regGB_EDC_MODE_DEFAULT                                                    0x00000000
1891 #define regCP_DEBUG_DEFAULT                                                       0x00400000
1892 #define regCP_CPC_DEBUG_DEFAULT                                                   0x00500000
1893 #define regCP_PQ_WPTR_POLL_CNTL_DEFAULT                                           0x00000001
1894 #define regCP_PQ_WPTR_POLL_CNTL1_DEFAULT                                          0x00000000
1895 #define regCP_ME1_PIPE0_INT_CNTL_DEFAULT                                          0x00000000
1896 #define regCP_ME1_PIPE1_INT_CNTL_DEFAULT                                          0x00000000
1897 #define regCP_ME1_PIPE2_INT_CNTL_DEFAULT                                          0x00000000
1898 #define regCP_ME1_PIPE3_INT_CNTL_DEFAULT                                          0x00000000
1899 #define regCP_ME2_PIPE0_INT_CNTL_DEFAULT                                          0x00000000
1900 #define regCP_ME2_PIPE1_INT_CNTL_DEFAULT                                          0x00000000
1901 #define regCP_ME2_PIPE2_INT_CNTL_DEFAULT                                          0x00000000
1902 #define regCP_ME2_PIPE3_INT_CNTL_DEFAULT                                          0x00000000
1903 #define regCP_ME1_PIPE0_INT_STATUS_DEFAULT                                        0x00000000
1904 #define regCP_ME1_PIPE1_INT_STATUS_DEFAULT                                        0x00000000
1905 #define regCP_ME1_PIPE2_INT_STATUS_DEFAULT                                        0x00000000
1906 #define regCP_ME1_PIPE3_INT_STATUS_DEFAULT                                        0x00000000
1907 #define regCP_ME2_PIPE0_INT_STATUS_DEFAULT                                        0x00000000
1908 #define regCP_ME2_PIPE1_INT_STATUS_DEFAULT                                        0x00000000
1909 #define regCP_ME2_PIPE2_INT_STATUS_DEFAULT                                        0x00000000
1910 #define regCP_ME2_PIPE3_INT_STATUS_DEFAULT                                        0x00000000
1911 #define regCP_GFX_QUEUE_INDEX_DEFAULT                                             0x00000000
1912 #define regCC_GC_EDC_CONFIG_DEFAULT                                               0x00000000
1913 #define regCP_ME1_PIPE_PRIORITY_CNTS_DEFAULT                                      0x08081020
1914 #define regCP_ME1_PIPE0_PRIORITY_DEFAULT                                          0x00000002
1915 #define regCP_ME1_PIPE1_PRIORITY_DEFAULT                                          0x00000002
1916 #define regCP_ME1_PIPE2_PRIORITY_DEFAULT                                          0x00000002
1917 #define regCP_ME1_PIPE3_PRIORITY_DEFAULT                                          0x00000002
1918 #define regCP_ME2_PIPE_PRIORITY_CNTS_DEFAULT                                      0x08081020
1919 #define regCP_ME2_PIPE0_PRIORITY_DEFAULT                                          0x00000002
1920 #define regCP_ME2_PIPE1_PRIORITY_DEFAULT                                          0x00000002
1921 #define regCP_ME2_PIPE2_PRIORITY_DEFAULT                                          0x00000002
1922 #define regCP_ME2_PIPE3_PRIORITY_DEFAULT                                          0x00000002
1923 #define regCP_PFP_PRGRM_CNTR_START_DEFAULT                                        0x00000000
1924 #define regCP_ME_PRGRM_CNTR_START_DEFAULT                                         0x00000000
1925 #define regCP_MEC1_PRGRM_CNTR_START_DEFAULT                                       0x00000000
1926 #define regCP_MEC2_PRGRM_CNTR_START_DEFAULT                                       0x00000000
1927 #define regCP_PFP_INTR_ROUTINE_START_DEFAULT                                      0x00000002
1928 #define regCP_ME_INTR_ROUTINE_START_DEFAULT                                       0x00000002
1929 #define regCP_MEC1_INTR_ROUTINE_START_DEFAULT                                     0x00000002
1930 #define regCP_MEC2_INTR_ROUTINE_START_DEFAULT                                     0x00000002
1931 #define regCP_CONTEXT_CNTL_DEFAULT                                                0x00750075
1932 #define regCP_MAX_CONTEXT_DEFAULT                                                 0x00000007
1933 #define regCP_IQ_WAIT_TIME1_DEFAULT                                               0x40404040
1934 #define regCP_IQ_WAIT_TIME2_DEFAULT                                               0x40404040
1935 #define regCP_RB0_BASE_HI_DEFAULT                                                 0x00000000
1936 #define regCP_RB1_BASE_HI_DEFAULT                                                 0x00000000
1937 #define regCP_VMID_RESET_DEFAULT                                                  0x00000000
1938 #define regCPC_INT_CNTL_DEFAULT                                                   0x00000000
1939 #define regCPC_INT_STATUS_DEFAULT                                                 0x00000000
1940 #define regCP_VMID_PREEMPT_DEFAULT                                                0x00000000
1941 #define regCPC_INT_CNTX_ID_DEFAULT                                                0x00000000
1942 #define regCP_PQ_STATUS_DEFAULT                                                   0x00000000
1943 #define regCP_PFP_PRGRM_CNTR_START_HI_DEFAULT                                     0x00000000
1944 #define regCP_MAX_DRAW_COUNT_DEFAULT                                              0x00000000
1945 #define regCP_MEC1_F32_INT_DIS_DEFAULT                                            0x00000000
1946 #define regCP_MEC2_F32_INT_DIS_DEFAULT                                            0x00000000
1947 #define regCP_VMID_STATUS_DEFAULT                                                 0x00000000
1948 #define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_DEFAULT                              0x00000000
1949 #define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_DEFAULT                              0x00000000
1950 #define regCPC_SUSPEND_CTX_SAVE_CONTROL_DEFAULT                                   0x00000000
1951 #define regCPC_SUSPEND_CNTL_STACK_OFFSET_DEFAULT                                  0x00000000
1952 #define regCPC_SUSPEND_CNTL_STACK_SIZE_DEFAULT                                    0x00000000
1953 #define regCPC_SUSPEND_WG_STATE_OFFSET_DEFAULT                                    0x00000000
1954 #define regCPC_SUSPEND_CTX_SAVE_SIZE_DEFAULT                                      0x00000000
1955 #define regCPC_OS_PIPES_DEFAULT                                                   0x00000000
1956 #define regCP_SUSPEND_RESUME_REQ_DEFAULT                                          0x00000000
1957 #define regCP_SUSPEND_CNTL_DEFAULT                                                0x00000002
1958 #define regCP_IQ_WAIT_TIME3_DEFAULT                                               0x00000040
1959 #define regCPC_DDID_BASE_ADDR_LO_DEFAULT                                          0x00000000
1960 #define regCP_DDID_BASE_ADDR_LO_DEFAULT                                           0x00000000
1961 #define regCPC_DDID_BASE_ADDR_HI_DEFAULT                                          0x00000000
1962 #define regCP_DDID_BASE_ADDR_HI_DEFAULT                                           0x00000000
1963 #define regCPC_DDID_CNTL_DEFAULT                                                  0x00000080
1964 #define regCP_DDID_CNTL_DEFAULT                                                   0x00000080
1965 #define regCP_GFX_DDID_INFLIGHT_COUNT_DEFAULT                                     0x00000000
1966 #define regCP_GFX_DDID_WPTR_DEFAULT                                               0x00000000
1967 #define regCP_GFX_DDID_RPTR_DEFAULT                                               0x00000000
1968 #define regCP_GFX_DDID_DELTA_RPT_COUNT_DEFAULT                                    0x00000000
1969 #define regCP_GFX_HPD_STATUS0_DEFAULT                                             0x01000000
1970 #define regCP_GFX_HPD_CONTROL0_DEFAULT                                            0x00000001
1971 #define regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_DEFAULT                                 0x00000000
1972 #define regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_DEFAULT                                 0x00000000
1973 #define regCP_GFX_HPD_OSPRE_FENCE_DATA_LO_DEFAULT                                 0x00000000
1974 #define regCP_GFX_HPD_OSPRE_FENCE_DATA_HI_DEFAULT                                 0x00000000
1975 #define regCP_GFX_INDEX_MUTEX_DEFAULT                                             0x00000000
1976 #define regCP_ME_PRGRM_CNTR_START_HI_DEFAULT                                      0x00000000
1977 #define regCP_PFP_INTR_ROUTINE_START_HI_DEFAULT                                   0x00000002
1978 #define regCP_ME_INTR_ROUTINE_START_HI_DEFAULT                                    0x00000002
1979 #define regCP_GFX_MQD_BASE_ADDR_DEFAULT                                           0x00000000
1980 #define regCP_GFX_MQD_BASE_ADDR_HI_DEFAULT                                        0x00000000
1981 #define regCP_GFX_HQD_ACTIVE_DEFAULT                                              0x00000000
1982 #define regCP_GFX_HQD_VMID_DEFAULT                                                0x00000000
1983 #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT                                      0x00000000
1984 #define regCP_GFX_HQD_QUANTUM_DEFAULT                                             0x00000a01
1985 #define regCP_GFX_HQD_BASE_DEFAULT                                                0xfedcbaef
1986 #define regCP_GFX_HQD_BASE_HI_DEFAULT                                             0x00000000
1987 #define regCP_GFX_HQD_RPTR_DEFAULT                                                0x00000000
1988 #define regCP_GFX_HQD_RPTR_ADDR_DEFAULT                                           0x00000000
1989 #define regCP_GFX_HQD_RPTR_ADDR_HI_DEFAULT                                        0x00000000
1990 #define regCP_RB_WPTR_POLL_ADDR_LO_DEFAULT                                        0x00000000
1991 #define regCP_RB_WPTR_POLL_ADDR_HI_DEFAULT                                        0x00000000
1992 #define regCP_RB_DOORBELL_CONTROL_DEFAULT                                         0x00000000
1993 #define regCP_GFX_HQD_OFFSET_DEFAULT                                              0x00000000
1994 #define regCP_GFX_HQD_CNTL_DEFAULT                                                0x00a00000
1995 #define regCP_GFX_HQD_CSMD_RPTR_DEFAULT                                           0x00000000
1996 #define regCP_GFX_HQD_WPTR_DEFAULT                                                0x00000000
1997 #define regCP_GFX_HQD_WPTR_HI_DEFAULT                                             0x00000000
1998 #define regCP_GFX_HQD_DEQUEUE_REQUEST_DEFAULT                                     0x00000000
1999 #define regCP_GFX_HQD_MAPPED_DEFAULT                                              0x00000000
2000 #define regCP_GFX_HQD_QUE_MGR_CONTROL_DEFAULT                                     0x00000000
2001 #define regCP_GFX_HQD_IQ_TIMER_DEFAULT                                            0x00000000
2002 #define regCP_GFX_HQD_HQ_STATUS0_DEFAULT                                          0x40000000
2003 #define regCP_GFX_HQD_HQ_CONTROL0_DEFAULT                                         0x00000000
2004 #define regCP_GFX_MQD_CONTROL_DEFAULT                                             0x00000100
2005 #define regCP_HQD_GFX_CONTROL_DEFAULT                                             0x00000000
2006 #define regCP_HQD_GFX_STATUS_DEFAULT                                              0x00000000
2007 #define regCP_DMA_WATCH0_ADDR_LO_DEFAULT                                          0x00000000
2008 #define regCP_DMA_WATCH0_ADDR_HI_DEFAULT                                          0x00000000
2009 #define regCP_DMA_WATCH0_MASK_DEFAULT                                             0x00000000
2010 #define regCP_DMA_WATCH0_CNTL_DEFAULT                                             0x00000000
2011 #define regCP_DMA_WATCH1_ADDR_LO_DEFAULT                                          0x00000000
2012 #define regCP_DMA_WATCH1_ADDR_HI_DEFAULT                                          0x00000000
2013 #define regCP_DMA_WATCH1_MASK_DEFAULT                                             0x00000000
2014 #define regCP_DMA_WATCH1_CNTL_DEFAULT                                             0x00000000
2015 #define regCP_DMA_WATCH2_ADDR_LO_DEFAULT                                          0x00000000
2016 #define regCP_DMA_WATCH2_ADDR_HI_DEFAULT                                          0x00000000
2017 #define regCP_DMA_WATCH2_MASK_DEFAULT                                             0x00000000
2018 #define regCP_DMA_WATCH2_CNTL_DEFAULT                                             0x00000000
2019 #define regCP_DMA_WATCH3_ADDR_LO_DEFAULT                                          0x00000000
2020 #define regCP_DMA_WATCH3_ADDR_HI_DEFAULT                                          0x00000000
2021 #define regCP_DMA_WATCH3_MASK_DEFAULT                                             0x00000000
2022 #define regCP_DMA_WATCH3_CNTL_DEFAULT                                             0x00000000
2023 #define regCP_DMA_WATCH_STAT_ADDR_LO_DEFAULT                                      0x00000000
2024 #define regCP_DMA_WATCH_STAT_ADDR_HI_DEFAULT                                      0x00000000
2025 #define regCP_DMA_WATCH_STAT_DEFAULT                                              0x00000000
2026 #define regCP_PFP_JT_STAT_DEFAULT                                                 0x00000000
2027 #define regCP_MEC_JT_STAT_DEFAULT                                                 0x00000000
2028 #define regCP_CPC_BUSY_HYSTERESIS_DEFAULT                                         0x00002020
2029 #define regCP_CPF_BUSY_HYSTERESIS1_DEFAULT                                        0x20202020
2030 #define regCP_CPF_BUSY_HYSTERESIS2_DEFAULT                                        0x00000020
2031 #define regCP_CPG_BUSY_HYSTERESIS1_DEFAULT                                        0x20202020
2032 #define regCP_CPG_BUSY_HYSTERESIS2_DEFAULT                                        0x00101020
2033 #define regCP_RB_DOORBELL_CLEAR_DEFAULT                                           0x00000000
2034 #define regCP_RB0_ACTIVE_DEFAULT                                                  0x00000000
2035 #define regCP_RB_ACTIVE_DEFAULT                                                   0x00000000
2036 #define regCP_RB1_ACTIVE_DEFAULT                                                  0x00000000
2037 #define regCP_RB_STATUS_DEFAULT                                                   0x00000000
2038 #define regCPG_RCIU_CAM_INDEX_DEFAULT                                             0x00000000
2039 #define regCPG_RCIU_CAM_DATA_DEFAULT                                              0x00000000
2040 #define regCPG_RCIU_CAM_DATA_PHASE0_DEFAULT                                       0x00000000
2041 #define regCPG_RCIU_CAM_DATA_PHASE1_DEFAULT                                       0x00000000
2042 #define regCPG_RCIU_CAM_DATA_PHASE2_DEFAULT                                       0x00000000
2043 #define regCP_GPU_TIMESTAMP_OFFSET_LO_DEFAULT                                     0x00000000
2044 #define regCP_GPU_TIMESTAMP_OFFSET_HI_DEFAULT                                     0x00000000
2045 #define regCP_SDMA_DMA_DONE_DEFAULT                                               0x00000000
2046 #define regCP_PFP_SDMA_CS_DEFAULT                                                 0x00000000
2047 #define regCP_ME_SDMA_CS_DEFAULT                                                  0x00000000
2048 #define regCPF_GCR_CNTL_DEFAULT                                                   0x0000c000
2049 #define regCPG_UTCL1_STATUS_DEFAULT                                               0x00000000
2050 #define regCPC_UTCL1_STATUS_DEFAULT                                               0x00000000
2051 #define regCPF_UTCL1_STATUS_DEFAULT                                               0x00000000
2052 #define regCP_SD_CNTL_DEFAULT                                                     0x0000046f
2053 #define regCP_SOFT_RESET_CNTL_DEFAULT                                             0x00000000
2054 #define regCP_CPC_GFX_CNTL_DEFAULT                                                0x00000000
2055 
2056 
2057 // addressBlock: gc_spipdec
2058 #define regSPI_ARB_PRIORITY_DEFAULT                                               0x00000000
2059 #define regSPI_ARB_CYCLES_0_DEFAULT                                               0x00000000
2060 #define regSPI_ARB_CYCLES_1_DEFAULT                                               0x00000000
2061 #define regSPI_WCL_PIPE_PERCENT_GFX_DEFAULT                                       0x07c1f07f
2062 #define regSPI_WCL_PIPE_PERCENT_HP3D_DEFAULT                                      0x07c1f07f
2063 #define regSPI_WCL_PIPE_PERCENT_CS0_DEFAULT                                       0x0000007f
2064 #define regSPI_WCL_PIPE_PERCENT_CS1_DEFAULT                                       0x0000007f
2065 #define regSPI_WCL_PIPE_PERCENT_CS2_DEFAULT                                       0x0000007f
2066 #define regSPI_WCL_PIPE_PERCENT_CS3_DEFAULT                                       0x0000007f
2067 #define regSPI_WCL_PIPE_PERCENT_CS4_DEFAULT                                       0x0000007f
2068 #define regSPI_WCL_PIPE_PERCENT_CS5_DEFAULT                                       0x0000007f
2069 #define regSPI_WCL_PIPE_PERCENT_CS6_DEFAULT                                       0x0000007f
2070 #define regSPI_WCL_PIPE_PERCENT_CS7_DEFAULT                                       0x0000007f
2071 #define regSPI_USER_ACCUM_VMID_CNTL_DEFAULT                                       0x00000000
2072 #define regSPI_GDBG_PER_VMID_CNTL_DEFAULT                                         0x00000000
2073 #define regSPI_COMPUTE_QUEUE_RESET_DEFAULT                                        0x00000000
2074 #define regSPI_COMPUTE_WF_CTX_SAVE_DEFAULT                                        0x00000000
2075 
2076 
2077 // addressBlock: gc_cpphqddec
2078 #define regCP_HPD_UTCL1_CNTL_DEFAULT                                              0x00000000
2079 #define regCP_HPD_UTCL1_ERROR_DEFAULT                                             0x00000000
2080 #define regCP_HPD_UTCL1_ERROR_ADDR_DEFAULT                                        0x00000000
2081 #define regCP_MQD_BASE_ADDR_DEFAULT                                               0x00000000
2082 #define regCP_MQD_BASE_ADDR_HI_DEFAULT                                            0x00000000
2083 #define regCP_HQD_ACTIVE_DEFAULT                                                  0x00000000
2084 #define regCP_HQD_VMID_DEFAULT                                                    0x00000000
2085 #define regCP_HQD_PERSISTENT_STATE_DEFAULT                                        0x0be05501
2086 #define regCP_HQD_PIPE_PRIORITY_DEFAULT                                           0x00000000
2087 #define regCP_HQD_QUEUE_PRIORITY_DEFAULT                                          0x00000000
2088 #define regCP_HQD_QUANTUM_DEFAULT                                                 0x00000000
2089 #define regCP_HQD_PQ_BASE_DEFAULT                                                 0x00000000
2090 #define regCP_HQD_PQ_BASE_HI_DEFAULT                                              0x00000000
2091 #define regCP_HQD_PQ_RPTR_DEFAULT                                                 0x00000000
2092 #define regCP_HQD_PQ_RPTR_REPORT_ADDR_DEFAULT                                     0x00000000
2093 #define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_DEFAULT                                  0x00000000
2094 #define regCP_HQD_PQ_WPTR_POLL_ADDR_DEFAULT                                       0x00000000
2095 #define regCP_HQD_PQ_WPTR_POLL_ADDR_HI_DEFAULT                                    0x00000000
2096 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT                                     0x00000000
2097 #define regCP_HQD_PQ_CONTROL_DEFAULT                                              0x00308509
2098 #define regCP_HQD_IB_BASE_ADDR_DEFAULT                                            0x00000000
2099 #define regCP_HQD_IB_BASE_ADDR_HI_DEFAULT                                         0x00000000
2100 #define regCP_HQD_IB_RPTR_DEFAULT                                                 0x00000000
2101 #define regCP_HQD_IB_CONTROL_DEFAULT                                              0x00300000
2102 #define regCP_HQD_IQ_TIMER_DEFAULT                                                0x00000000
2103 #define regCP_HQD_IQ_RPTR_DEFAULT                                                 0x00000000
2104 #define regCP_HQD_DEQUEUE_REQUEST_DEFAULT                                         0x00000000
2105 #define regCP_HQD_DMA_OFFLOAD_DEFAULT                                             0x00000000
2106 #define regCP_HQD_OFFLOAD_DEFAULT                                                 0x00000000
2107 #define regCP_HQD_SEMA_CMD_DEFAULT                                                0x00000000
2108 #define regCP_HQD_MSG_TYPE_DEFAULT                                                0x00000000
2109 #define regCP_HQD_ATOMIC0_PREOP_LO_DEFAULT                                        0x00000000
2110 #define regCP_HQD_ATOMIC0_PREOP_HI_DEFAULT                                        0x00000000
2111 #define regCP_HQD_ATOMIC1_PREOP_LO_DEFAULT                                        0x00000000
2112 #define regCP_HQD_ATOMIC1_PREOP_HI_DEFAULT                                        0x00000000
2113 #define regCP_HQD_HQ_SCHEDULER0_DEFAULT                                           0x40000000
2114 #define regCP_HQD_HQ_STATUS0_DEFAULT                                              0x40000000
2115 #define regCP_HQD_HQ_CONTROL0_DEFAULT                                             0x00000000
2116 #define regCP_HQD_HQ_SCHEDULER1_DEFAULT                                           0x00000000
2117 #define regCP_MQD_CONTROL_DEFAULT                                                 0x00000100
2118 #define regCP_HQD_HQ_STATUS1_DEFAULT                                              0x00000000
2119 #define regCP_HQD_HQ_CONTROL1_DEFAULT                                             0x00000000
2120 #define regCP_HQD_EOP_BASE_ADDR_DEFAULT                                           0x00000000
2121 #define regCP_HQD_EOP_BASE_ADDR_HI_DEFAULT                                        0x00000000
2122 #define regCP_HQD_EOP_CONTROL_DEFAULT                                             0x00000006
2123 #define regCP_HQD_EOP_RPTR_DEFAULT                                                0x40000000
2124 #define regCP_HQD_EOP_WPTR_DEFAULT                                                0x00008000
2125 #define regCP_HQD_EOP_EVENTS_DEFAULT                                              0x00000000
2126 #define regCP_HQD_CTX_SAVE_BASE_ADDR_LO_DEFAULT                                   0x00000000
2127 #define regCP_HQD_CTX_SAVE_BASE_ADDR_HI_DEFAULT                                   0x00000000
2128 #define regCP_HQD_CTX_SAVE_CONTROL_DEFAULT                                        0x00000000
2129 #define regCP_HQD_CNTL_STACK_OFFSET_DEFAULT                                       0x00000000
2130 #define regCP_HQD_CNTL_STACK_SIZE_DEFAULT                                         0x00000000
2131 #define regCP_HQD_WG_STATE_OFFSET_DEFAULT                                         0x00000000
2132 #define regCP_HQD_CTX_SAVE_SIZE_DEFAULT                                           0x00000000
2133 #define regCP_HQD_GDS_RESOURCE_STATE_DEFAULT                                      0x00000000
2134 #define regCP_HQD_ERROR_DEFAULT                                                   0x00000000
2135 #define regCP_HQD_EOP_WPTR_MEM_DEFAULT                                            0x00000000
2136 #define regCP_HQD_AQL_CONTROL_DEFAULT                                             0x00000000
2137 #define regCP_HQD_PQ_WPTR_LO_DEFAULT                                              0x00000000
2138 #define regCP_HQD_PQ_WPTR_HI_DEFAULT                                              0x00000000
2139 #define regCP_HQD_SUSPEND_CNTL_STACK_OFFSET_DEFAULT                               0x00000000
2140 #define regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_DEFAULT                               0x00000000
2141 #define regCP_HQD_SUSPEND_WG_STATE_OFFSET_DEFAULT                                 0x00000000
2142 #define regCP_HQD_DDID_RPTR_DEFAULT                                               0x00000000
2143 #define regCP_HQD_DDID_WPTR_DEFAULT                                               0x00000000
2144 #define regCP_HQD_DDID_INFLIGHT_COUNT_DEFAULT                                     0x00000000
2145 #define regCP_HQD_DDID_DELTA_RPT_COUNT_DEFAULT                                    0x00000000
2146 #define regCP_HQD_DEQUEUE_STATUS_DEFAULT                                          0x00000000
2147 
2148 
2149 // addressBlock: gc_tcpdec
2150 #define regTCP_WATCH0_ADDR_H_DEFAULT                                              0x00000000
2151 #define regTCP_WATCH0_ADDR_L_DEFAULT                                              0x00000000
2152 #define regTCP_WATCH0_CNTL_DEFAULT                                                0x00000000
2153 #define regTCP_WATCH1_ADDR_H_DEFAULT                                              0x00000000
2154 #define regTCP_WATCH1_ADDR_L_DEFAULT                                              0x00000000
2155 #define regTCP_WATCH1_CNTL_DEFAULT                                                0x00000000
2156 #define regTCP_WATCH2_ADDR_H_DEFAULT                                              0x00000000
2157 #define regTCP_WATCH2_ADDR_L_DEFAULT                                              0x00000000
2158 #define regTCP_WATCH2_CNTL_DEFAULT                                                0x00000000
2159 #define regTCP_WATCH3_ADDR_H_DEFAULT                                              0x00000000
2160 #define regTCP_WATCH3_ADDR_L_DEFAULT                                              0x00000000
2161 #define regTCP_WATCH3_CNTL_DEFAULT                                                0x00000000
2162 
2163 
2164 // addressBlock: gc_gdspdec
2165 #define regGDS_VMID0_BASE_DEFAULT                                                 0x00000000
2166 #define regGDS_VMID0_SIZE_DEFAULT                                                 0x00001000
2167 #define regGDS_VMID1_BASE_DEFAULT                                                 0x00000000
2168 #define regGDS_VMID1_SIZE_DEFAULT                                                 0x00001000
2169 #define regGDS_VMID2_BASE_DEFAULT                                                 0x00000000
2170 #define regGDS_VMID2_SIZE_DEFAULT                                                 0x00001000
2171 #define regGDS_VMID3_BASE_DEFAULT                                                 0x00000000
2172 #define regGDS_VMID3_SIZE_DEFAULT                                                 0x00001000
2173 #define regGDS_VMID4_BASE_DEFAULT                                                 0x00000000
2174 #define regGDS_VMID4_SIZE_DEFAULT                                                 0x00001000
2175 #define regGDS_VMID5_BASE_DEFAULT                                                 0x00000000
2176 #define regGDS_VMID5_SIZE_DEFAULT                                                 0x00001000
2177 #define regGDS_VMID6_BASE_DEFAULT                                                 0x00000000
2178 #define regGDS_VMID6_SIZE_DEFAULT                                                 0x00001000
2179 #define regGDS_VMID7_BASE_DEFAULT                                                 0x00000000
2180 #define regGDS_VMID7_SIZE_DEFAULT                                                 0x00001000
2181 #define regGDS_VMID8_BASE_DEFAULT                                                 0x00000000
2182 #define regGDS_VMID8_SIZE_DEFAULT                                                 0x00001000
2183 #define regGDS_VMID9_BASE_DEFAULT                                                 0x00000000
2184 #define regGDS_VMID9_SIZE_DEFAULT                                                 0x00001000
2185 #define regGDS_VMID10_BASE_DEFAULT                                                0x00000000
2186 #define regGDS_VMID10_SIZE_DEFAULT                                                0x00001000
2187 #define regGDS_VMID11_BASE_DEFAULT                                                0x00000000
2188 #define regGDS_VMID11_SIZE_DEFAULT                                                0x00001000
2189 #define regGDS_VMID12_BASE_DEFAULT                                                0x00000000
2190 #define regGDS_VMID12_SIZE_DEFAULT                                                0x00001000
2191 #define regGDS_VMID13_BASE_DEFAULT                                                0x00000000
2192 #define regGDS_VMID13_SIZE_DEFAULT                                                0x00001000
2193 #define regGDS_VMID14_BASE_DEFAULT                                                0x00000000
2194 #define regGDS_VMID14_SIZE_DEFAULT                                                0x00001000
2195 #define regGDS_VMID15_BASE_DEFAULT                                                0x00000000
2196 #define regGDS_VMID15_SIZE_DEFAULT                                                0x00001000
2197 #define regGDS_GWS_VMID0_DEFAULT                                                  0x00400000
2198 #define regGDS_GWS_VMID1_DEFAULT                                                  0x00400000
2199 #define regGDS_GWS_VMID2_DEFAULT                                                  0x00400000
2200 #define regGDS_GWS_VMID3_DEFAULT                                                  0x00400000
2201 #define regGDS_GWS_VMID4_DEFAULT                                                  0x00400000
2202 #define regGDS_GWS_VMID5_DEFAULT                                                  0x00400000
2203 #define regGDS_GWS_VMID6_DEFAULT                                                  0x00400000
2204 #define regGDS_GWS_VMID7_DEFAULT                                                  0x00400000
2205 #define regGDS_GWS_VMID8_DEFAULT                                                  0x00400000
2206 #define regGDS_GWS_VMID9_DEFAULT                                                  0x00400000
2207 #define regGDS_GWS_VMID10_DEFAULT                                                 0x00400000
2208 #define regGDS_GWS_VMID11_DEFAULT                                                 0x00400000
2209 #define regGDS_GWS_VMID12_DEFAULT                                                 0x00400000
2210 #define regGDS_GWS_VMID13_DEFAULT                                                 0x00400000
2211 #define regGDS_GWS_VMID14_DEFAULT                                                 0x00400000
2212 #define regGDS_GWS_VMID15_DEFAULT                                                 0x00400000
2213 #define regGDS_OA_VMID0_DEFAULT                                                   0x00000000
2214 #define regGDS_OA_VMID1_DEFAULT                                                   0x00000000
2215 #define regGDS_OA_VMID2_DEFAULT                                                   0x00000000
2216 #define regGDS_OA_VMID3_DEFAULT                                                   0x00000000
2217 #define regGDS_OA_VMID4_DEFAULT                                                   0x00000000
2218 #define regGDS_OA_VMID5_DEFAULT                                                   0x00000000
2219 #define regGDS_OA_VMID6_DEFAULT                                                   0x00000000
2220 #define regGDS_OA_VMID7_DEFAULT                                                   0x00000000
2221 #define regGDS_OA_VMID8_DEFAULT                                                   0x00000000
2222 #define regGDS_OA_VMID9_DEFAULT                                                   0x00000000
2223 #define regGDS_OA_VMID10_DEFAULT                                                  0x00000000
2224 #define regGDS_OA_VMID11_DEFAULT                                                  0x00000000
2225 #define regGDS_OA_VMID12_DEFAULT                                                  0x00000000
2226 #define regGDS_OA_VMID13_DEFAULT                                                  0x00000000
2227 #define regGDS_OA_VMID14_DEFAULT                                                  0x00000000
2228 #define regGDS_OA_VMID15_DEFAULT                                                  0x00000000
2229 #define regGDS_GWS_RESET0_DEFAULT                                                 0x00000000
2230 #define regGDS_GWS_RESET1_DEFAULT                                                 0x00000000
2231 #define regGDS_GWS_RESOURCE_RESET_DEFAULT                                         0x00000000
2232 #define regGDS_COMPUTE_MAX_WAVE_ID_DEFAULT                                        0x00000bff
2233 #define regGDS_OA_RESET_MASK_DEFAULT                                              0x00000000
2234 #define regGDS_OA_RESET_DEFAULT                                                   0x00000000
2235 #define regGDS_CS_CTXSW_STATUS_DEFAULT                                            0x00000000
2236 #define regGDS_CS_CTXSW_CNT0_DEFAULT                                              0x00000000
2237 #define regGDS_CS_CTXSW_CNT1_DEFAULT                                              0x00000000
2238 #define regGDS_CS_CTXSW_CNT2_DEFAULT                                              0x00000000
2239 #define regGDS_CS_CTXSW_CNT3_DEFAULT                                              0x00000000
2240 #define regGDS_GFX_CTXSW_STATUS_DEFAULT                                           0x00000000
2241 #define regGDS_PS_CTXSW_CNT0_DEFAULT                                              0x00000000
2242 #define regGDS_PS_CTXSW_CNT1_DEFAULT                                              0x00000000
2243 #define regGDS_PS_CTXSW_CNT2_DEFAULT                                              0x00000000
2244 #define regGDS_PS_CTXSW_CNT3_DEFAULT                                              0x00000000
2245 #define regGDS_PS_CTXSW_IDX_DEFAULT                                               0x00000000
2246 #define regGDS_GS_CTXSW_CNT0_DEFAULT                                              0x00000000
2247 #define regGDS_GS_CTXSW_CNT1_DEFAULT                                              0x00000000
2248 #define regGDS_GS_CTXSW_CNT2_DEFAULT                                              0x00000000
2249 #define regGDS_GS_CTXSW_CNT3_DEFAULT                                              0x00000000
2250 #define regGDS_MEMORY_CLEAN_DEFAULT                                               0x00000000
2251 
2252 
2253 // addressBlock: gc_gfxdec0
2254 #define regDB_RENDER_CONTROL_DEFAULT                                              0x00000000
2255 #define regDB_COUNT_CONTROL_DEFAULT                                               0x00000000
2256 #define regDB_DEPTH_VIEW_DEFAULT                                                  0x00000000
2257 #define regDB_RENDER_OVERRIDE_DEFAULT                                             0x00000000
2258 #define regDB_RENDER_OVERRIDE2_DEFAULT                                            0x00000000
2259 #define regDB_HTILE_DATA_BASE_DEFAULT                                             0x00000000
2260 #define regDB_DEPTH_SIZE_XY_DEFAULT                                               0x00000000
2261 #define regDB_DEPTH_BOUNDS_MIN_DEFAULT                                            0x00000000
2262 #define regDB_DEPTH_BOUNDS_MAX_DEFAULT                                            0x00000000
2263 #define regDB_STENCIL_CLEAR_DEFAULT                                               0x00000000
2264 #define regDB_DEPTH_CLEAR_DEFAULT                                                 0x00000000
2265 #define regPA_SC_SCREEN_SCISSOR_TL_DEFAULT                                        0x00000000
2266 #define regPA_SC_SCREEN_SCISSOR_BR_DEFAULT                                        0x00000000
2267 #define regDB_RESERVED_REG_2_DEFAULT                                              0x00000000
2268 #define regDB_Z_INFO_DEFAULT                                                      0x00000000
2269 #define regDB_STENCIL_INFO_DEFAULT                                                0x00000000
2270 #define regDB_Z_READ_BASE_DEFAULT                                                 0x00000000
2271 #define regDB_STENCIL_READ_BASE_DEFAULT                                           0x00000000
2272 #define regDB_Z_WRITE_BASE_DEFAULT                                                0x00000000
2273 #define regDB_STENCIL_WRITE_BASE_DEFAULT                                          0x00000000
2274 #define regDB_RESERVED_REG_1_DEFAULT                                              0x00000000
2275 #define regDB_RESERVED_REG_3_DEFAULT                                              0x00000000
2276 #define regDB_Z_READ_BASE_HI_DEFAULT                                              0x00000000
2277 #define regDB_STENCIL_READ_BASE_HI_DEFAULT                                        0x00000000
2278 #define regDB_Z_WRITE_BASE_HI_DEFAULT                                             0x00000000
2279 #define regDB_STENCIL_WRITE_BASE_HI_DEFAULT                                       0x00000000
2280 #define regDB_HTILE_DATA_BASE_HI_DEFAULT                                          0x00000000
2281 #define regDB_RMI_L2_CACHE_CONTROL_DEFAULT                                        0x00000000
2282 #define regTA_BC_BASE_ADDR_DEFAULT                                                0x00000000
2283 #define regTA_BC_BASE_ADDR_HI_DEFAULT                                             0x00000000
2284 #define regCOHER_DEST_BASE_HI_0_DEFAULT                                           0x00000000
2285 #define regCOHER_DEST_BASE_HI_1_DEFAULT                                           0x00000000
2286 #define regCOHER_DEST_BASE_HI_2_DEFAULT                                           0x00000000
2287 #define regCOHER_DEST_BASE_HI_3_DEFAULT                                           0x00000000
2288 #define regCOHER_DEST_BASE_2_DEFAULT                                              0x00000000
2289 #define regCOHER_DEST_BASE_3_DEFAULT                                              0x00000000
2290 #define regPA_SC_WINDOW_OFFSET_DEFAULT                                            0x00000000
2291 #define regPA_SC_WINDOW_SCISSOR_TL_DEFAULT                                        0x00000000
2292 #define regPA_SC_WINDOW_SCISSOR_BR_DEFAULT                                        0x00000000
2293 #define regPA_SC_CLIPRECT_RULE_DEFAULT                                            0x00000000
2294 #define regPA_SC_CLIPRECT_0_TL_DEFAULT                                            0x00000000
2295 #define regPA_SC_CLIPRECT_0_BR_DEFAULT                                            0x00000000
2296 #define regPA_SC_CLIPRECT_1_TL_DEFAULT                                            0x00000000
2297 #define regPA_SC_CLIPRECT_1_BR_DEFAULT                                            0x00000000
2298 #define regPA_SC_CLIPRECT_2_TL_DEFAULT                                            0x00000000
2299 #define regPA_SC_CLIPRECT_2_BR_DEFAULT                                            0x00000000
2300 #define regPA_SC_CLIPRECT_3_TL_DEFAULT                                            0x00000000
2301 #define regPA_SC_CLIPRECT_3_BR_DEFAULT                                            0x00000000
2302 #define regPA_SC_EDGERULE_DEFAULT                                                 0x00000000
2303 #define regPA_SU_HARDWARE_SCREEN_OFFSET_DEFAULT                                   0x00000000
2304 #define regCB_TARGET_MASK_DEFAULT                                                 0x00000000
2305 #define regCB_SHADER_MASK_DEFAULT                                                 0x00000000
2306 #define regPA_SC_GENERIC_SCISSOR_TL_DEFAULT                                       0x00000000
2307 #define regPA_SC_GENERIC_SCISSOR_BR_DEFAULT                                       0x00000000
2308 #define regCOHER_DEST_BASE_0_DEFAULT                                              0x00000000
2309 #define regCOHER_DEST_BASE_1_DEFAULT                                              0x00000000
2310 #define regPA_SC_VPORT_SCISSOR_0_TL_DEFAULT                                       0x00000000
2311 #define regPA_SC_VPORT_SCISSOR_0_BR_DEFAULT                                       0x00000000
2312 #define regPA_SC_VPORT_SCISSOR_1_TL_DEFAULT                                       0x00000000
2313 #define regPA_SC_VPORT_SCISSOR_1_BR_DEFAULT                                       0x00000000
2314 #define regPA_SC_VPORT_SCISSOR_2_TL_DEFAULT                                       0x00000000
2315 #define regPA_SC_VPORT_SCISSOR_2_BR_DEFAULT                                       0x00000000
2316 #define regPA_SC_VPORT_SCISSOR_3_TL_DEFAULT                                       0x00000000
2317 #define regPA_SC_VPORT_SCISSOR_3_BR_DEFAULT                                       0x00000000
2318 #define regPA_SC_VPORT_SCISSOR_4_TL_DEFAULT                                       0x00000000
2319 #define regPA_SC_VPORT_SCISSOR_4_BR_DEFAULT                                       0x00000000
2320 #define regPA_SC_VPORT_SCISSOR_5_TL_DEFAULT                                       0x00000000
2321 #define regPA_SC_VPORT_SCISSOR_5_BR_DEFAULT                                       0x00000000
2322 #define regPA_SC_VPORT_SCISSOR_6_TL_DEFAULT                                       0x00000000
2323 #define regPA_SC_VPORT_SCISSOR_6_BR_DEFAULT                                       0x00000000
2324 #define regPA_SC_VPORT_SCISSOR_7_TL_DEFAULT                                       0x00000000
2325 #define regPA_SC_VPORT_SCISSOR_7_BR_DEFAULT                                       0x00000000
2326 #define regPA_SC_VPORT_SCISSOR_8_TL_DEFAULT                                       0x00000000
2327 #define regPA_SC_VPORT_SCISSOR_8_BR_DEFAULT                                       0x00000000
2328 #define regPA_SC_VPORT_SCISSOR_9_TL_DEFAULT                                       0x00000000
2329 #define regPA_SC_VPORT_SCISSOR_9_BR_DEFAULT                                       0x00000000
2330 #define regPA_SC_VPORT_SCISSOR_10_TL_DEFAULT                                      0x00000000
2331 #define regPA_SC_VPORT_SCISSOR_10_BR_DEFAULT                                      0x00000000
2332 #define regPA_SC_VPORT_SCISSOR_11_TL_DEFAULT                                      0x00000000
2333 #define regPA_SC_VPORT_SCISSOR_11_BR_DEFAULT                                      0x00000000
2334 #define regPA_SC_VPORT_SCISSOR_12_TL_DEFAULT                                      0x00000000
2335 #define regPA_SC_VPORT_SCISSOR_12_BR_DEFAULT                                      0x00000000
2336 #define regPA_SC_VPORT_SCISSOR_13_TL_DEFAULT                                      0x00000000
2337 #define regPA_SC_VPORT_SCISSOR_13_BR_DEFAULT                                      0x00000000
2338 #define regPA_SC_VPORT_SCISSOR_14_TL_DEFAULT                                      0x00000000
2339 #define regPA_SC_VPORT_SCISSOR_14_BR_DEFAULT                                      0x00000000
2340 #define regPA_SC_VPORT_SCISSOR_15_TL_DEFAULT                                      0x00000000
2341 #define regPA_SC_VPORT_SCISSOR_15_BR_DEFAULT                                      0x00000000
2342 #define regPA_SC_VPORT_ZMIN_0_DEFAULT                                             0x00000000
2343 #define regPA_SC_VPORT_ZMAX_0_DEFAULT                                             0x00000000
2344 #define regPA_SC_VPORT_ZMIN_1_DEFAULT                                             0x00000000
2345 #define regPA_SC_VPORT_ZMAX_1_DEFAULT                                             0x00000000
2346 #define regPA_SC_VPORT_ZMIN_2_DEFAULT                                             0x00000000
2347 #define regPA_SC_VPORT_ZMAX_2_DEFAULT                                             0x00000000
2348 #define regPA_SC_VPORT_ZMIN_3_DEFAULT                                             0x00000000
2349 #define regPA_SC_VPORT_ZMAX_3_DEFAULT                                             0x00000000
2350 #define regPA_SC_VPORT_ZMIN_4_DEFAULT                                             0x00000000
2351 #define regPA_SC_VPORT_ZMAX_4_DEFAULT                                             0x00000000
2352 #define regPA_SC_VPORT_ZMIN_5_DEFAULT                                             0x00000000
2353 #define regPA_SC_VPORT_ZMAX_5_DEFAULT                                             0x00000000
2354 #define regPA_SC_VPORT_ZMIN_6_DEFAULT                                             0x00000000
2355 #define regPA_SC_VPORT_ZMAX_6_DEFAULT                                             0x00000000
2356 #define regPA_SC_VPORT_ZMIN_7_DEFAULT                                             0x00000000
2357 #define regPA_SC_VPORT_ZMAX_7_DEFAULT                                             0x00000000
2358 #define regPA_SC_VPORT_ZMIN_8_DEFAULT                                             0x00000000
2359 #define regPA_SC_VPORT_ZMAX_8_DEFAULT                                             0x00000000
2360 #define regPA_SC_VPORT_ZMIN_9_DEFAULT                                             0x00000000
2361 #define regPA_SC_VPORT_ZMAX_9_DEFAULT                                             0x00000000
2362 #define regPA_SC_VPORT_ZMIN_10_DEFAULT                                            0x00000000
2363 #define regPA_SC_VPORT_ZMAX_10_DEFAULT                                            0x00000000
2364 #define regPA_SC_VPORT_ZMIN_11_DEFAULT                                            0x00000000
2365 #define regPA_SC_VPORT_ZMAX_11_DEFAULT                                            0x00000000
2366 #define regPA_SC_VPORT_ZMIN_12_DEFAULT                                            0x00000000
2367 #define regPA_SC_VPORT_ZMAX_12_DEFAULT                                            0x00000000
2368 #define regPA_SC_VPORT_ZMIN_13_DEFAULT                                            0x00000000
2369 #define regPA_SC_VPORT_ZMAX_13_DEFAULT                                            0x00000000
2370 #define regPA_SC_VPORT_ZMIN_14_DEFAULT                                            0x00000000
2371 #define regPA_SC_VPORT_ZMAX_14_DEFAULT                                            0x00000000
2372 #define regPA_SC_VPORT_ZMIN_15_DEFAULT                                            0x00000000
2373 #define regPA_SC_VPORT_ZMAX_15_DEFAULT                                            0x00000000
2374 #define regPA_SC_RASTER_CONFIG_DEFAULT                                            0x2a00126a
2375 #define regPA_SC_RASTER_CONFIG_1_DEFAULT                                          0x00000000
2376 #define regPA_SC_SCREEN_EXTENT_CONTROL_DEFAULT                                    0x00000000
2377 #define regPA_SC_TILE_STEERING_OVERRIDE_DEFAULT                                   0x00000000
2378 #define regCP_PERFMON_CNTX_CNTL_DEFAULT                                           0x00000000
2379 #define regCP_PIPEID_DEFAULT                                                      0x00000000
2380 #define regCP_RINGID_DEFAULT                                                      0x00000000
2381 #define regCP_VMID_DEFAULT                                                        0x00000000
2382 #define regCONTEXT_RESERVED_REG0_DEFAULT                                          0x00000000
2383 #define regCONTEXT_RESERVED_REG1_DEFAULT                                          0x00000000
2384 #define regPA_SC_VRS_OVERRIDE_CNTL_DEFAULT                                        0x00000000
2385 #define regPA_SC_VRS_RATE_FEEDBACK_BASE_DEFAULT                                   0x00000000
2386 #define regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT_DEFAULT                               0x00000000
2387 #define regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY_DEFAULT                                0x00000000
2388 #define regPA_SC_VRS_RATE_CACHE_CNTL_DEFAULT                                      0x00000000
2389 #define regPA_SC_VRS_RATE_BASE_DEFAULT                                            0x00000000
2390 #define regPA_SC_VRS_RATE_BASE_EXT_DEFAULT                                        0x00000000
2391 #define regPA_SC_VRS_RATE_SIZE_XY_DEFAULT                                         0x00000000
2392 #define regVGT_MULTI_PRIM_IB_RESET_INDX_DEFAULT                                   0x00000000
2393 #define regCB_RMI_GL2_CACHE_CONTROL_DEFAULT                                       0x00000000
2394 #define regCB_BLEND_RED_DEFAULT                                                   0x00000000
2395 #define regCB_BLEND_GREEN_DEFAULT                                                 0x00000000
2396 #define regCB_BLEND_BLUE_DEFAULT                                                  0x00000000
2397 #define regCB_BLEND_ALPHA_DEFAULT                                                 0x00000000
2398 #define regCB_FDCC_CONTROL_DEFAULT                                                0x00000000
2399 #define regCB_COVERAGE_OUT_CONTROL_DEFAULT                                        0x00000000
2400 #define regDB_STENCIL_CONTROL_DEFAULT                                             0x00000000
2401 #define regDB_STENCILREFMASK_DEFAULT                                              0x00000000
2402 #define regDB_STENCILREFMASK_BF_DEFAULT                                           0x00000000
2403 #define regPA_CL_VPORT_XSCALE_DEFAULT                                             0x00000000
2404 #define regPA_CL_VPORT_XOFFSET_DEFAULT                                            0x00000000
2405 #define regPA_CL_VPORT_YSCALE_DEFAULT                                             0x00000000
2406 #define regPA_CL_VPORT_YOFFSET_DEFAULT                                            0x00000000
2407 #define regPA_CL_VPORT_ZSCALE_DEFAULT                                             0x00000000
2408 #define regPA_CL_VPORT_ZOFFSET_DEFAULT                                            0x00000000
2409 #define regPA_CL_VPORT_XSCALE_1_DEFAULT                                           0x00000000
2410 #define regPA_CL_VPORT_XOFFSET_1_DEFAULT                                          0x00000000
2411 #define regPA_CL_VPORT_YSCALE_1_DEFAULT                                           0x00000000
2412 #define regPA_CL_VPORT_YOFFSET_1_DEFAULT                                          0x00000000
2413 #define regPA_CL_VPORT_ZSCALE_1_DEFAULT                                           0x00000000
2414 #define regPA_CL_VPORT_ZOFFSET_1_DEFAULT                                          0x00000000
2415 #define regPA_CL_VPORT_XSCALE_2_DEFAULT                                           0x00000000
2416 #define regPA_CL_VPORT_XOFFSET_2_DEFAULT                                          0x00000000
2417 #define regPA_CL_VPORT_YSCALE_2_DEFAULT                                           0x00000000
2418 #define regPA_CL_VPORT_YOFFSET_2_DEFAULT                                          0x00000000
2419 #define regPA_CL_VPORT_ZSCALE_2_DEFAULT                                           0x00000000
2420 #define regPA_CL_VPORT_ZOFFSET_2_DEFAULT                                          0x00000000
2421 #define regPA_CL_VPORT_XSCALE_3_DEFAULT                                           0x00000000
2422 #define regPA_CL_VPORT_XOFFSET_3_DEFAULT                                          0x00000000
2423 #define regPA_CL_VPORT_YSCALE_3_DEFAULT                                           0x00000000
2424 #define regPA_CL_VPORT_YOFFSET_3_DEFAULT                                          0x00000000
2425 #define regPA_CL_VPORT_ZSCALE_3_DEFAULT                                           0x00000000
2426 #define regPA_CL_VPORT_ZOFFSET_3_DEFAULT                                          0x00000000
2427 #define regPA_CL_VPORT_XSCALE_4_DEFAULT                                           0x00000000
2428 #define regPA_CL_VPORT_XOFFSET_4_DEFAULT                                          0x00000000
2429 #define regPA_CL_VPORT_YSCALE_4_DEFAULT                                           0x00000000
2430 #define regPA_CL_VPORT_YOFFSET_4_DEFAULT                                          0x00000000
2431 #define regPA_CL_VPORT_ZSCALE_4_DEFAULT                                           0x00000000
2432 #define regPA_CL_VPORT_ZOFFSET_4_DEFAULT                                          0x00000000
2433 #define regPA_CL_VPORT_XSCALE_5_DEFAULT                                           0x00000000
2434 #define regPA_CL_VPORT_XOFFSET_5_DEFAULT                                          0x00000000
2435 #define regPA_CL_VPORT_YSCALE_5_DEFAULT                                           0x00000000
2436 #define regPA_CL_VPORT_YOFFSET_5_DEFAULT                                          0x00000000
2437 #define regPA_CL_VPORT_ZSCALE_5_DEFAULT                                           0x00000000
2438 #define regPA_CL_VPORT_ZOFFSET_5_DEFAULT                                          0x00000000
2439 #define regPA_CL_VPORT_XSCALE_6_DEFAULT                                           0x00000000
2440 #define regPA_CL_VPORT_XOFFSET_6_DEFAULT                                          0x00000000
2441 #define regPA_CL_VPORT_YSCALE_6_DEFAULT                                           0x00000000
2442 #define regPA_CL_VPORT_YOFFSET_6_DEFAULT                                          0x00000000
2443 #define regPA_CL_VPORT_ZSCALE_6_DEFAULT                                           0x00000000
2444 #define regPA_CL_VPORT_ZOFFSET_6_DEFAULT                                          0x00000000
2445 #define regPA_CL_VPORT_XSCALE_7_DEFAULT                                           0x00000000
2446 #define regPA_CL_VPORT_XOFFSET_7_DEFAULT                                          0x00000000
2447 #define regPA_CL_VPORT_YSCALE_7_DEFAULT                                           0x00000000
2448 #define regPA_CL_VPORT_YOFFSET_7_DEFAULT                                          0x00000000
2449 #define regPA_CL_VPORT_ZSCALE_7_DEFAULT                                           0x00000000
2450 #define regPA_CL_VPORT_ZOFFSET_7_DEFAULT                                          0x00000000
2451 #define regPA_CL_VPORT_XSCALE_8_DEFAULT                                           0x00000000
2452 #define regPA_CL_VPORT_XOFFSET_8_DEFAULT                                          0x00000000
2453 #define regPA_CL_VPORT_YSCALE_8_DEFAULT                                           0x00000000
2454 #define regPA_CL_VPORT_YOFFSET_8_DEFAULT                                          0x00000000
2455 #define regPA_CL_VPORT_ZSCALE_8_DEFAULT                                           0x00000000
2456 #define regPA_CL_VPORT_ZOFFSET_8_DEFAULT                                          0x00000000
2457 #define regPA_CL_VPORT_XSCALE_9_DEFAULT                                           0x00000000
2458 #define regPA_CL_VPORT_XOFFSET_9_DEFAULT                                          0x00000000
2459 #define regPA_CL_VPORT_YSCALE_9_DEFAULT                                           0x00000000
2460 #define regPA_CL_VPORT_YOFFSET_9_DEFAULT                                          0x00000000
2461 #define regPA_CL_VPORT_ZSCALE_9_DEFAULT                                           0x00000000
2462 #define regPA_CL_VPORT_ZOFFSET_9_DEFAULT                                          0x00000000
2463 #define regPA_CL_VPORT_XSCALE_10_DEFAULT                                          0x00000000
2464 #define regPA_CL_VPORT_XOFFSET_10_DEFAULT                                         0x00000000
2465 #define regPA_CL_VPORT_YSCALE_10_DEFAULT                                          0x00000000
2466 #define regPA_CL_VPORT_YOFFSET_10_DEFAULT                                         0x00000000
2467 #define regPA_CL_VPORT_ZSCALE_10_DEFAULT                                          0x00000000
2468 #define regPA_CL_VPORT_ZOFFSET_10_DEFAULT                                         0x00000000
2469 #define regPA_CL_VPORT_XSCALE_11_DEFAULT                                          0x00000000
2470 #define regPA_CL_VPORT_XOFFSET_11_DEFAULT                                         0x00000000
2471 #define regPA_CL_VPORT_YSCALE_11_DEFAULT                                          0x00000000
2472 #define regPA_CL_VPORT_YOFFSET_11_DEFAULT                                         0x00000000
2473 #define regPA_CL_VPORT_ZSCALE_11_DEFAULT                                          0x00000000
2474 #define regPA_CL_VPORT_ZOFFSET_11_DEFAULT                                         0x00000000
2475 #define regPA_CL_VPORT_XSCALE_12_DEFAULT                                          0x00000000
2476 #define regPA_CL_VPORT_XOFFSET_12_DEFAULT                                         0x00000000
2477 #define regPA_CL_VPORT_YSCALE_12_DEFAULT                                          0x00000000
2478 #define regPA_CL_VPORT_YOFFSET_12_DEFAULT                                         0x00000000
2479 #define regPA_CL_VPORT_ZSCALE_12_DEFAULT                                          0x00000000
2480 #define regPA_CL_VPORT_ZOFFSET_12_DEFAULT                                         0x00000000
2481 #define regPA_CL_VPORT_XSCALE_13_DEFAULT                                          0x00000000
2482 #define regPA_CL_VPORT_XOFFSET_13_DEFAULT                                         0x00000000
2483 #define regPA_CL_VPORT_YSCALE_13_DEFAULT                                          0x00000000
2484 #define regPA_CL_VPORT_YOFFSET_13_DEFAULT                                         0x00000000
2485 #define regPA_CL_VPORT_ZSCALE_13_DEFAULT                                          0x00000000
2486 #define regPA_CL_VPORT_ZOFFSET_13_DEFAULT                                         0x00000000
2487 #define regPA_CL_VPORT_XSCALE_14_DEFAULT                                          0x00000000
2488 #define regPA_CL_VPORT_XOFFSET_14_DEFAULT                                         0x00000000
2489 #define regPA_CL_VPORT_YSCALE_14_DEFAULT                                          0x00000000
2490 #define regPA_CL_VPORT_YOFFSET_14_DEFAULT                                         0x00000000
2491 #define regPA_CL_VPORT_ZSCALE_14_DEFAULT                                          0x00000000
2492 #define regPA_CL_VPORT_ZOFFSET_14_DEFAULT                                         0x00000000
2493 #define regPA_CL_VPORT_XSCALE_15_DEFAULT                                          0x00000000
2494 #define regPA_CL_VPORT_XOFFSET_15_DEFAULT                                         0x00000000
2495 #define regPA_CL_VPORT_YSCALE_15_DEFAULT                                          0x00000000
2496 #define regPA_CL_VPORT_YOFFSET_15_DEFAULT                                         0x00000000
2497 #define regPA_CL_VPORT_ZSCALE_15_DEFAULT                                          0x00000000
2498 #define regPA_CL_VPORT_ZOFFSET_15_DEFAULT                                         0x00000000
2499 #define regPA_CL_UCP_0_X_DEFAULT                                                  0x00000000
2500 #define regPA_CL_UCP_0_Y_DEFAULT                                                  0x00000000
2501 #define regPA_CL_UCP_0_Z_DEFAULT                                                  0x00000000
2502 #define regPA_CL_UCP_0_W_DEFAULT                                                  0x00000000
2503 #define regPA_CL_UCP_1_X_DEFAULT                                                  0x00000000
2504 #define regPA_CL_UCP_1_Y_DEFAULT                                                  0x00000000
2505 #define regPA_CL_UCP_1_Z_DEFAULT                                                  0x00000000
2506 #define regPA_CL_UCP_1_W_DEFAULT                                                  0x00000000
2507 #define regPA_CL_UCP_2_X_DEFAULT                                                  0x00000000
2508 #define regPA_CL_UCP_2_Y_DEFAULT                                                  0x00000000
2509 #define regPA_CL_UCP_2_Z_DEFAULT                                                  0x00000000
2510 #define regPA_CL_UCP_2_W_DEFAULT                                                  0x00000000
2511 #define regPA_CL_UCP_3_X_DEFAULT                                                  0x00000000
2512 #define regPA_CL_UCP_3_Y_DEFAULT                                                  0x00000000
2513 #define regPA_CL_UCP_3_Z_DEFAULT                                                  0x00000000
2514 #define regPA_CL_UCP_3_W_DEFAULT                                                  0x00000000
2515 #define regPA_CL_UCP_4_X_DEFAULT                                                  0x00000000
2516 #define regPA_CL_UCP_4_Y_DEFAULT                                                  0x00000000
2517 #define regPA_CL_UCP_4_Z_DEFAULT                                                  0x00000000
2518 #define regPA_CL_UCP_4_W_DEFAULT                                                  0x00000000
2519 #define regPA_CL_UCP_5_X_DEFAULT                                                  0x00000000
2520 #define regPA_CL_UCP_5_Y_DEFAULT                                                  0x00000000
2521 #define regPA_CL_UCP_5_Z_DEFAULT                                                  0x00000000
2522 #define regPA_CL_UCP_5_W_DEFAULT                                                  0x00000000
2523 #define regPA_CL_PROG_NEAR_CLIP_Z_DEFAULT                                         0x00000000
2524 #define regPA_RATE_CNTL_DEFAULT                                                   0x00000000
2525 #define regSPI_PS_INPUT_CNTL_0_DEFAULT                                            0x00000000
2526 #define regSPI_PS_INPUT_CNTL_1_DEFAULT                                            0x00000000
2527 #define regSPI_PS_INPUT_CNTL_2_DEFAULT                                            0x00000000
2528 #define regSPI_PS_INPUT_CNTL_3_DEFAULT                                            0x00000000
2529 #define regSPI_PS_INPUT_CNTL_4_DEFAULT                                            0x00000000
2530 #define regSPI_PS_INPUT_CNTL_5_DEFAULT                                            0x00000000
2531 #define regSPI_PS_INPUT_CNTL_6_DEFAULT                                            0x00000000
2532 #define regSPI_PS_INPUT_CNTL_7_DEFAULT                                            0x00000000
2533 #define regSPI_PS_INPUT_CNTL_8_DEFAULT                                            0x00000000
2534 #define regSPI_PS_INPUT_CNTL_9_DEFAULT                                            0x00000000
2535 #define regSPI_PS_INPUT_CNTL_10_DEFAULT                                           0x00000000
2536 #define regSPI_PS_INPUT_CNTL_11_DEFAULT                                           0x00000000
2537 #define regSPI_PS_INPUT_CNTL_12_DEFAULT                                           0x00000000
2538 #define regSPI_PS_INPUT_CNTL_13_DEFAULT                                           0x00000000
2539 #define regSPI_PS_INPUT_CNTL_14_DEFAULT                                           0x00000000
2540 #define regSPI_PS_INPUT_CNTL_15_DEFAULT                                           0x00000000
2541 #define regSPI_PS_INPUT_CNTL_16_DEFAULT                                           0x00000000
2542 #define regSPI_PS_INPUT_CNTL_17_DEFAULT                                           0x00000000
2543 #define regSPI_PS_INPUT_CNTL_18_DEFAULT                                           0x00000000
2544 #define regSPI_PS_INPUT_CNTL_19_DEFAULT                                           0x00000000
2545 #define regSPI_PS_INPUT_CNTL_20_DEFAULT                                           0x00000000
2546 #define regSPI_PS_INPUT_CNTL_21_DEFAULT                                           0x00000000
2547 #define regSPI_PS_INPUT_CNTL_22_DEFAULT                                           0x00000000
2548 #define regSPI_PS_INPUT_CNTL_23_DEFAULT                                           0x00000000
2549 #define regSPI_PS_INPUT_CNTL_24_DEFAULT                                           0x00000000
2550 #define regSPI_PS_INPUT_CNTL_25_DEFAULT                                           0x00000000
2551 #define regSPI_PS_INPUT_CNTL_26_DEFAULT                                           0x00000000
2552 #define regSPI_PS_INPUT_CNTL_27_DEFAULT                                           0x00000000
2553 #define regSPI_PS_INPUT_CNTL_28_DEFAULT                                           0x00000000
2554 #define regSPI_PS_INPUT_CNTL_29_DEFAULT                                           0x00000000
2555 #define regSPI_PS_INPUT_CNTL_30_DEFAULT                                           0x00000000
2556 #define regSPI_PS_INPUT_CNTL_31_DEFAULT                                           0x00000000
2557 #define regSPI_VS_OUT_CONFIG_DEFAULT                                              0x00000000
2558 #define regSPI_PS_INPUT_ENA_DEFAULT                                               0x00000000
2559 #define regSPI_PS_INPUT_ADDR_DEFAULT                                              0x00000000
2560 #define regSPI_INTERP_CONTROL_0_DEFAULT                                           0x00000000
2561 #define regSPI_PS_IN_CONTROL_DEFAULT                                              0x00000000
2562 #define regSPI_BARYC_CNTL_DEFAULT                                                 0x00000000
2563 #define regSPI_TMPRING_SIZE_DEFAULT                                               0x00000000
2564 #define regSPI_GFX_SCRATCH_BASE_LO_DEFAULT                                        0x00000000
2565 #define regSPI_GFX_SCRATCH_BASE_HI_DEFAULT                                        0x00000000
2566 #define regSPI_SHADER_IDX_FORMAT_DEFAULT                                          0x00000000
2567 #define regSPI_SHADER_POS_FORMAT_DEFAULT                                          0x00000000
2568 #define regSPI_SHADER_Z_FORMAT_DEFAULT                                            0x00000000
2569 #define regSPI_SHADER_COL_FORMAT_DEFAULT                                          0x00000000
2570 #define regSX_PS_DOWNCONVERT_CONTROL_DEFAULT                                      0x00000000
2571 #define regSX_PS_DOWNCONVERT_DEFAULT                                              0x00000000
2572 #define regSX_BLEND_OPT_EPSILON_DEFAULT                                           0x00000000
2573 #define regSX_BLEND_OPT_CONTROL_DEFAULT                                           0x00000000
2574 #define regSX_MRT0_BLEND_OPT_DEFAULT                                              0x00000000
2575 #define regSX_MRT1_BLEND_OPT_DEFAULT                                              0x00000000
2576 #define regSX_MRT2_BLEND_OPT_DEFAULT                                              0x00000000
2577 #define regSX_MRT3_BLEND_OPT_DEFAULT                                              0x00000000
2578 #define regSX_MRT4_BLEND_OPT_DEFAULT                                              0x00000000
2579 #define regSX_MRT5_BLEND_OPT_DEFAULT                                              0x00000000
2580 #define regSX_MRT6_BLEND_OPT_DEFAULT                                              0x00000000
2581 #define regSX_MRT7_BLEND_OPT_DEFAULT                                              0x00000000
2582 #define regCB_BLEND0_CONTROL_DEFAULT                                              0x00000000
2583 #define regCB_BLEND1_CONTROL_DEFAULT                                              0x00000000
2584 #define regCB_BLEND2_CONTROL_DEFAULT                                              0x00000000
2585 #define regCB_BLEND3_CONTROL_DEFAULT                                              0x00000000
2586 #define regCB_BLEND4_CONTROL_DEFAULT                                              0x00000000
2587 #define regCB_BLEND5_CONTROL_DEFAULT                                              0x00000000
2588 #define regCB_BLEND6_CONTROL_DEFAULT                                              0x00000000
2589 #define regCB_BLEND7_CONTROL_DEFAULT                                              0x00000000
2590 #define regGFX_COPY_STATE_DEFAULT                                                 0x00000000
2591 #define regPA_CL_POINT_X_RAD_DEFAULT                                              0x00000000
2592 #define regPA_CL_POINT_Y_RAD_DEFAULT                                              0x00000000
2593 #define regPA_CL_POINT_SIZE_DEFAULT                                               0x00000000
2594 #define regPA_CL_POINT_CULL_RAD_DEFAULT                                           0x00000000
2595 #define regVGT_DMA_BASE_HI_DEFAULT                                                0x00000000
2596 #define regVGT_DMA_BASE_DEFAULT                                                   0x00000000
2597 #define regVGT_DRAW_INITIATOR_DEFAULT                                             0x00000000
2598 #define regVGT_EVENT_ADDRESS_REG_DEFAULT                                          0x00000000
2599 #define regGE_MAX_OUTPUT_PER_SUBGROUP_DEFAULT                                     0x00000000
2600 #define regDB_DEPTH_CONTROL_DEFAULT                                               0x00000000
2601 #define regDB_EQAA_DEFAULT                                                        0x00000000
2602 #define regCB_COLOR_CONTROL_DEFAULT                                               0x00000000
2603 #define regDB_SHADER_CONTROL_DEFAULT                                              0x00000000
2604 #define regPA_CL_CLIP_CNTL_DEFAULT                                                0x00000000
2605 #define regPA_SU_SC_MODE_CNTL_DEFAULT                                             0x00000000
2606 #define regPA_CL_VTE_CNTL_DEFAULT                                                 0x00000000
2607 #define regPA_CL_VS_OUT_CNTL_DEFAULT                                              0x00000000
2608 #define regPA_CL_NANINF_CNTL_DEFAULT                                              0x00000000
2609 #define regPA_SU_LINE_STIPPLE_CNTL_DEFAULT                                        0x00000000
2610 #define regPA_SU_LINE_STIPPLE_SCALE_DEFAULT                                       0x00000000
2611 #define regPA_SU_PRIM_FILTER_CNTL_DEFAULT                                         0x00000000
2612 #define regPA_SU_SMALL_PRIM_FILTER_CNTL_DEFAULT                                   0x00000000
2613 #define regPA_CL_NGG_CNTL_DEFAULT                                                 0x00000000
2614 #define regPA_SU_OVER_RASTERIZATION_CNTL_DEFAULT                                  0x00000000
2615 #define regPA_STEREO_CNTL_DEFAULT                                                 0x00000000
2616 #define regPA_STATE_STEREO_X_DEFAULT                                              0x00000000
2617 #define regPA_CL_VRS_CNTL_DEFAULT                                                 0x00000000
2618 #define regPA_SU_POINT_SIZE_DEFAULT                                               0x00000000
2619 #define regPA_SU_POINT_MINMAX_DEFAULT                                             0x00000000
2620 #define regPA_SU_LINE_CNTL_DEFAULT                                                0x00000000
2621 #define regPA_SC_LINE_STIPPLE_DEFAULT                                             0x00000000
2622 #define regVGT_HOS_MAX_TESS_LEVEL_DEFAULT                                         0x00000000
2623 #define regVGT_HOS_MIN_TESS_LEVEL_DEFAULT                                         0x00000000
2624 #define regPA_SC_MODE_CNTL_0_DEFAULT                                              0x00000000
2625 #define regPA_SC_MODE_CNTL_1_DEFAULT                                              0x06000000
2626 #define regVGT_ENHANCE_DEFAULT                                                    0x00000000
2627 #define regIA_ENHANCE_DEFAULT                                                     0x00000000
2628 #define regVGT_DMA_SIZE_DEFAULT                                                   0x00000000
2629 #define regVGT_DMA_MAX_SIZE_DEFAULT                                               0x00000000
2630 #define regVGT_DMA_INDEX_TYPE_DEFAULT                                             0x00000000
2631 #define regWD_ENHANCE_DEFAULT                                                     0x00000000
2632 #define regVGT_PRIMITIVEID_EN_DEFAULT                                             0x00000000
2633 #define regVGT_DMA_NUM_INSTANCES_DEFAULT                                          0x00000000
2634 #define regVGT_PRIMITIVEID_RESET_DEFAULT                                          0x00000000
2635 #define regVGT_EVENT_INITIATOR_DEFAULT                                            0x00000000
2636 #define regVGT_DRAW_PAYLOAD_CNTL_DEFAULT                                          0x00000000
2637 #define regVGT_ESGS_RING_ITEMSIZE_DEFAULT                                         0x00000000
2638 #define regVGT_REUSE_OFF_DEFAULT                                                  0x00000000
2639 #define regDB_HTILE_SURFACE_DEFAULT                                               0x00000000
2640 #define regDB_SRESULTS_COMPARE_STATE0_DEFAULT                                     0x00000000
2641 #define regDB_SRESULTS_COMPARE_STATE1_DEFAULT                                     0x00000000
2642 #define regDB_PRELOAD_CONTROL_DEFAULT                                             0x00000000
2643 #define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_DEFAULT                                 0x00000000
2644 #define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_DEFAULT                     0x00000000
2645 #define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_DEFAULT                          0x00000000
2646 #define regVGT_GS_MAX_VERT_OUT_DEFAULT                                            0x00000000
2647 #define regGE_NGG_SUBGRP_CNTL_DEFAULT                                             0x00000000
2648 #define regVGT_TESS_DISTRIBUTION_DEFAULT                                          0x00000000
2649 #define regVGT_SHADER_STAGES_EN_DEFAULT                                           0x00000000
2650 #define regVGT_LS_HS_CONFIG_DEFAULT                                               0x00000000
2651 #define regVGT_TF_PARAM_DEFAULT                                                   0x00000000
2652 #define regDB_ALPHA_TO_MASK_DEFAULT                                               0x00000000
2653 #define regPA_SU_POLY_OFFSET_DB_FMT_CNTL_DEFAULT                                  0x00000000
2654 #define regPA_SU_POLY_OFFSET_CLAMP_DEFAULT                                        0x00000000
2655 #define regPA_SU_POLY_OFFSET_FRONT_SCALE_DEFAULT                                  0x00000000
2656 #define regPA_SU_POLY_OFFSET_FRONT_OFFSET_DEFAULT                                 0x00000000
2657 #define regPA_SU_POLY_OFFSET_BACK_SCALE_DEFAULT                                   0x00000000
2658 #define regPA_SU_POLY_OFFSET_BACK_OFFSET_DEFAULT                                  0x00000000
2659 #define regVGT_GS_INSTANCE_CNT_DEFAULT                                            0x00000000
2660 #define regPA_SC_CENTROID_PRIORITY_0_DEFAULT                                      0x00000000
2661 #define regPA_SC_CENTROID_PRIORITY_1_DEFAULT                                      0x00000000
2662 #define regPA_SC_LINE_CNTL_DEFAULT                                                0x00000000
2663 #define regPA_SC_AA_CONFIG_DEFAULT                                                0x00000000
2664 #define regPA_SU_VTX_CNTL_DEFAULT                                                 0x00000000
2665 #define regPA_CL_GB_VERT_CLIP_ADJ_DEFAULT                                         0x00000000
2666 #define regPA_CL_GB_VERT_DISC_ADJ_DEFAULT                                         0x00000000
2667 #define regPA_CL_GB_HORZ_CLIP_ADJ_DEFAULT                                         0x00000000
2668 #define regPA_CL_GB_HORZ_DISC_ADJ_DEFAULT                                         0x00000000
2669 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_DEFAULT                              0x00000000
2670 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_DEFAULT                              0x00000000
2671 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_DEFAULT                              0x00000000
2672 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_DEFAULT                              0x00000000
2673 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_DEFAULT                              0x00000000
2674 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_DEFAULT                              0x00000000
2675 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_DEFAULT                              0x00000000
2676 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_DEFAULT                              0x00000000
2677 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_DEFAULT                              0x00000000
2678 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_DEFAULT                              0x00000000
2679 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_DEFAULT                              0x00000000
2680 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_DEFAULT                              0x00000000
2681 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_DEFAULT                              0x00000000
2682 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_DEFAULT                              0x00000000
2683 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_DEFAULT                              0x00000000
2684 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_DEFAULT                              0x00000000
2685 #define regPA_SC_AA_MASK_X0Y0_X1Y0_DEFAULT                                        0x00000000
2686 #define regPA_SC_AA_MASK_X0Y1_X1Y1_DEFAULT                                        0x00000000
2687 #define regPA_SC_SHADER_CONTROL_DEFAULT                                           0x00000000
2688 #define regPA_SC_BINNER_CNTL_0_DEFAULT                                            0x00000000
2689 #define regPA_SC_BINNER_CNTL_1_DEFAULT                                            0x00000000
2690 #define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_DEFAULT                          0x00000000
2691 #define regPA_SC_NGG_MODE_CNTL_DEFAULT                                            0x00000000
2692 #define regPA_SC_BINNER_CNTL_2_DEFAULT                                            0x00000000
2693 #define regCB_COLOR0_BASE_DEFAULT                                                 0x00000000
2694 #define regCB_COLOR0_VIEW_DEFAULT                                                 0x00000000
2695 #define regCB_COLOR0_INFO_DEFAULT                                                 0x00000000
2696 #define regCB_COLOR0_ATTRIB_DEFAULT                                               0x00000000
2697 #define regCB_COLOR0_FDCC_CONTROL_DEFAULT                                         0x00000000
2698 #define regCB_COLOR0_DCC_BASE_DEFAULT                                             0x00000000
2699 #define regCB_COLOR1_BASE_DEFAULT                                                 0x00000000
2700 #define regCB_COLOR1_VIEW_DEFAULT                                                 0x00000000
2701 #define regCB_COLOR1_INFO_DEFAULT                                                 0x00000000
2702 #define regCB_COLOR1_ATTRIB_DEFAULT                                               0x00000000
2703 #define regCB_COLOR1_FDCC_CONTROL_DEFAULT                                         0x00000000
2704 #define regCB_COLOR1_DCC_BASE_DEFAULT                                             0x00000000
2705 #define regCB_COLOR2_BASE_DEFAULT                                                 0x00000000
2706 #define regCB_COLOR2_VIEW_DEFAULT                                                 0x00000000
2707 #define regCB_COLOR2_INFO_DEFAULT                                                 0x00000000
2708 #define regCB_COLOR2_ATTRIB_DEFAULT                                               0x00000000
2709 #define regCB_COLOR2_FDCC_CONTROL_DEFAULT                                         0x00000000
2710 #define regCB_COLOR2_DCC_BASE_DEFAULT                                             0x00000000
2711 #define regCB_COLOR3_BASE_DEFAULT                                                 0x00000000
2712 #define regCB_COLOR3_VIEW_DEFAULT                                                 0x00000000
2713 #define regCB_COLOR3_INFO_DEFAULT                                                 0x00000000
2714 #define regCB_COLOR3_ATTRIB_DEFAULT                                               0x00000000
2715 #define regCB_COLOR3_FDCC_CONTROL_DEFAULT                                         0x00000000
2716 #define regCB_COLOR3_DCC_BASE_DEFAULT                                             0x00000000
2717 #define regCB_COLOR4_BASE_DEFAULT                                                 0x00000000
2718 #define regCB_COLOR4_VIEW_DEFAULT                                                 0x00000000
2719 #define regCB_COLOR4_INFO_DEFAULT                                                 0x00000000
2720 #define regCB_COLOR4_ATTRIB_DEFAULT                                               0x00000000
2721 #define regCB_COLOR4_FDCC_CONTROL_DEFAULT                                         0x00000000
2722 #define regCB_COLOR4_DCC_BASE_DEFAULT                                             0x00000000
2723 #define regCB_COLOR5_BASE_DEFAULT                                                 0x00000000
2724 #define regCB_COLOR5_VIEW_DEFAULT                                                 0x00000000
2725 #define regCB_COLOR5_INFO_DEFAULT                                                 0x00000000
2726 #define regCB_COLOR5_ATTRIB_DEFAULT                                               0x00000000
2727 #define regCB_COLOR5_FDCC_CONTROL_DEFAULT                                         0x00000000
2728 #define regCB_COLOR5_DCC_BASE_DEFAULT                                             0x00000000
2729 #define regCB_COLOR6_BASE_DEFAULT                                                 0x00000000
2730 #define regCB_COLOR6_VIEW_DEFAULT                                                 0x00000000
2731 #define regCB_COLOR6_INFO_DEFAULT                                                 0x00000000
2732 #define regCB_COLOR6_ATTRIB_DEFAULT                                               0x00000000
2733 #define regCB_COLOR6_FDCC_CONTROL_DEFAULT                                         0x00000000
2734 #define regCB_COLOR6_DCC_BASE_DEFAULT                                             0x00000000
2735 #define regCB_COLOR7_BASE_DEFAULT                                                 0x00000000
2736 #define regCB_COLOR7_VIEW_DEFAULT                                                 0x00000000
2737 #define regCB_COLOR7_INFO_DEFAULT                                                 0x00000000
2738 #define regCB_COLOR7_ATTRIB_DEFAULT                                               0x00000000
2739 #define regCB_COLOR7_FDCC_CONTROL_DEFAULT                                         0x00000000
2740 #define regCB_COLOR7_DCC_BASE_DEFAULT                                             0x00000000
2741 #define regCB_COLOR0_BASE_EXT_DEFAULT                                             0x00000000
2742 #define regCB_COLOR1_BASE_EXT_DEFAULT                                             0x00000000
2743 #define regCB_COLOR2_BASE_EXT_DEFAULT                                             0x00000000
2744 #define regCB_COLOR3_BASE_EXT_DEFAULT                                             0x00000000
2745 #define regCB_COLOR4_BASE_EXT_DEFAULT                                             0x00000000
2746 #define regCB_COLOR5_BASE_EXT_DEFAULT                                             0x00000000
2747 #define regCB_COLOR6_BASE_EXT_DEFAULT                                             0x00000000
2748 #define regCB_COLOR7_BASE_EXT_DEFAULT                                             0x00000000
2749 #define regCB_COLOR0_DCC_BASE_EXT_DEFAULT                                         0x00000000
2750 #define regCB_COLOR1_DCC_BASE_EXT_DEFAULT                                         0x00000000
2751 #define regCB_COLOR2_DCC_BASE_EXT_DEFAULT                                         0x00000000
2752 #define regCB_COLOR3_DCC_BASE_EXT_DEFAULT                                         0x00000000
2753 #define regCB_COLOR4_DCC_BASE_EXT_DEFAULT                                         0x00000000
2754 #define regCB_COLOR5_DCC_BASE_EXT_DEFAULT                                         0x00000000
2755 #define regCB_COLOR6_DCC_BASE_EXT_DEFAULT                                         0x00000000
2756 #define regCB_COLOR7_DCC_BASE_EXT_DEFAULT                                         0x00000000
2757 #define regCB_COLOR0_ATTRIB2_DEFAULT                                              0x00000000
2758 #define regCB_COLOR1_ATTRIB2_DEFAULT                                              0x00000000
2759 #define regCB_COLOR2_ATTRIB2_DEFAULT                                              0x00000000
2760 #define regCB_COLOR3_ATTRIB2_DEFAULT                                              0x00000000
2761 #define regCB_COLOR4_ATTRIB2_DEFAULT                                              0x00000000
2762 #define regCB_COLOR5_ATTRIB2_DEFAULT                                              0x00000000
2763 #define regCB_COLOR6_ATTRIB2_DEFAULT                                              0x00000000
2764 #define regCB_COLOR7_ATTRIB2_DEFAULT                                              0x00000000
2765 #define regCB_COLOR0_ATTRIB3_DEFAULT                                              0x00000000
2766 #define regCB_COLOR1_ATTRIB3_DEFAULT                                              0x00000000
2767 #define regCB_COLOR2_ATTRIB3_DEFAULT                                              0x00000000
2768 #define regCB_COLOR3_ATTRIB3_DEFAULT                                              0x00000000
2769 #define regCB_COLOR4_ATTRIB3_DEFAULT                                              0x00000000
2770 #define regCB_COLOR5_ATTRIB3_DEFAULT                                              0x00000000
2771 #define regCB_COLOR6_ATTRIB3_DEFAULT                                              0x00000000
2772 #define regCB_COLOR7_ATTRIB3_DEFAULT                                              0x00000000
2773 
2774 
2775 // addressBlock: gc_pfvf_cpdec
2776 #define regCONFIG_RESERVED_REG0_DEFAULT                                           0x00000000
2777 #define regCONFIG_RESERVED_REG1_DEFAULT                                           0x00000000
2778 #define regCP_MEC_CNTL_DEFAULT                                                    0x50000000
2779 #define regCP_ME_CNTL_DEFAULT                                                     0x15000000
2780 
2781 
2782 // addressBlock: gc_pfvf_grbmdec
2783 #define regGRBM_GFX_CNTL_DEFAULT                                                  0x00000000
2784 #define regGRBM_NOWHERE_DEFAULT                                                   0x00000000
2785 
2786 
2787 // addressBlock: gc_pfvf_padec
2788 #define regPA_SC_VRS_SURFACE_CNTL_DEFAULT                                         0x42000000
2789 #define regPA_SC_ENHANCE_DEFAULT                                                  0x08000009
2790 #define regPA_SC_ENHANCE_1_DEFAULT                                                0x040c2000
2791 #define regPA_SC_ENHANCE_2_DEFAULT                                                0x00000820
2792 #define regPA_SC_ENHANCE_3_DEFAULT                                                0x00000180
2793 #define regPA_SC_BINNER_CNTL_OVERRIDE_DEFAULT                                     0x08000000
2794 #define regPA_SC_PBB_OVERRIDE_FLAG_DEFAULT                                        0x00000000
2795 #define regPA_SC_DSM_CNTL_DEFAULT                                                 0x00000000
2796 #define regPA_SC_TILE_STEERING_CREST_OVERRIDE_DEFAULT                             0x00000000
2797 #define regPA_SC_FIFO_SIZE_DEFAULT                                                0x00000000
2798 #define regPA_SC_IF_FIFO_SIZE_DEFAULT                                             0x00000000
2799 #define regPA_SC_PACKER_WAVE_ID_CNTL_DEFAULT                                      0x00000000
2800 #define regPA_SC_ATM_CNTL_DEFAULT                                                 0x00000000
2801 #define regPA_SC_PKR_WAVE_TABLE_CNTL_DEFAULT                                      0x00000000
2802 #define regPA_SC_FORCE_EOV_MAX_CNTS_DEFAULT                                       0x00ffffff
2803 #define regPA_SC_BINNER_EVENT_CNTL_0_DEFAULT                                      0x842a4c02
2804 #define regPA_SC_BINNER_EVENT_CNTL_1_DEFAULT                                      0x82000008
2805 #define regPA_SC_BINNER_EVENT_CNTL_2_DEFAULT                                      0x1118aab8
2806 #define regPA_SC_BINNER_EVENT_CNTL_3_DEFAULT                                      0xc2400024
2807 #define regPA_SC_BINNER_TIMEOUT_COUNTER_DEFAULT                                   0x00000800
2808 #define regPA_SC_BINNER_PERF_CNTL_0_DEFAULT                                       0x00000000
2809 #define regPA_SC_BINNER_PERF_CNTL_1_DEFAULT                                       0x00000000
2810 #define regPA_SC_BINNER_PERF_CNTL_2_DEFAULT                                       0x00000000
2811 #define regPA_SC_BINNER_PERF_CNTL_3_DEFAULT                                       0x00000000
2812 #define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_DEFAULT                                  0x00000000
2813 #define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_DEFAULT                                 0x00000000
2814 #define regPA_SC_TRAP_SCREEN_HV_LOCK_DEFAULT                                      0x00000000
2815 #define regPA_PH_INTERFACE_FIFO_SIZE_DEFAULT                                      0x00000034
2816 #define regPA_PH_ENHANCE_DEFAULT                                                  0x00001000
2817 #define regPA_SC_VRS_SURFACE_CNTL_1_DEFAULT                                       0x55488100
2818 
2819 
2820 // addressBlock: gc_pfvfdec_rlc
2821 #define regRLC_SAFE_MODE_DEFAULT                                                  0x00000000
2822 #define regRLC_SPM_SAMPLE_CNT_DEFAULT                                             0x00000000
2823 #define regRLC_SPM_MC_CNTL_DEFAULT                                                0x00000000
2824 #define regRLC_SPM_INT_CNTL_DEFAULT                                               0x00000000
2825 #define regRLC_SPM_INT_STATUS_DEFAULT                                             0x00000000
2826 #define regRLC_SPM_INT_INFO_1_DEFAULT                                             0x00000000
2827 #define regRLC_SPM_INT_INFO_2_DEFAULT                                             0x00ca0000
2828 #define regRLC_CSIB_ADDR_LO_DEFAULT                                               0x00000000
2829 #define regRLC_CSIB_ADDR_HI_DEFAULT                                               0x00000000
2830 #define regRLC_CSIB_LENGTH_DEFAULT                                                0x00000000
2831 #define regRLC_CP_SCHEDULERS_DEFAULT                                              0x00003038
2832 #define regRLC_CP_EOF_INT_DEFAULT                                                 0x00000000
2833 #define regRLC_CP_EOF_INT_CNT_DEFAULT                                             0x00000000
2834 #define regRLC_SPARE_INT_0_DEFAULT                                                0x00000000
2835 #define regRLC_SPARE_INT_1_DEFAULT                                                0x00000000
2836 #define regRLC_SPARE_INT_2_DEFAULT                                                0x00000000
2837 #define regRLC_PACE_SPARE_INT_DEFAULT                                             0x00000000
2838 #define regRLC_PACE_SPARE_INT_1_DEFAULT                                           0x00000000
2839 #define regRLC_RLCV_SPARE_INT_1_DEFAULT                                           0x00000000
2840 
2841 
2842 // addressBlock: gc_pfvf_sqdec
2843 #define regSQ_RUNTIME_CONFIG_DEFAULT                                              0x00000000
2844 #define regSQ_DEBUG_STS_GLOBAL_DEFAULT                                            0x00000000
2845 #define regSQ_DEBUG_STS_GLOBAL2_DEFAULT                                           0x00000000
2846 #define regSH_MEM_BASES_DEFAULT                                                   0x00000000
2847 #define regSH_MEM_CONFIG_DEFAULT                                                  0x0000c000
2848 #define regSQ_DEBUG_DEFAULT                                                       0x00000000
2849 #define regSQ_SHADER_TBA_LO_DEFAULT                                               0x00000000
2850 #define regSQ_SHADER_TBA_HI_DEFAULT                                               0x00000000
2851 #define regSQ_SHADER_TMA_LO_DEFAULT                                               0x00000000
2852 #define regSQ_SHADER_TMA_HI_DEFAULT                                               0x00000000
2853 
2854 
2855 // addressBlock: gc_pfonly_cpdec
2856 #define regCP_DEBUG_2_DEFAULT                                                     0x00000000
2857 #define regCP_FETCHER_SOURCE_DEFAULT                                              0x00000000
2858 
2859 
2860 // addressBlock: gc_pfonly_cpphqddec
2861 #define regCP_HPD_MES_ROQ_OFFSETS_DEFAULT                                         0x00400000
2862 #define regCP_HPD_ROQ_OFFSETS_DEFAULT                                             0x00200604
2863 #define regCP_HPD_STATUS0_DEFAULT                                                 0x01000000
2864 
2865 
2866 // addressBlock: gc_rmi_rmidec
2867 #define regRMI_GENERAL_CNTL_DEFAULT                                               0x01e00000
2868 #define regRMI_GENERAL_CNTL1_DEFAULT                                              0x00000201
2869 #define regRMI_GENERAL_STATUS_DEFAULT                                             0x00000000
2870 #define regRMI_SUBBLOCK_STATUS0_DEFAULT                                           0x00000000
2871 #define regRMI_SUBBLOCK_STATUS1_DEFAULT                                           0x00000000
2872 #define regRMI_SUBBLOCK_STATUS2_DEFAULT                                           0x00000000
2873 #define regRMI_SUBBLOCK_STATUS3_DEFAULT                                           0x00000000
2874 #define regRMI_XBAR_CONFIG_DEFAULT                                                0x00000000
2875 #define regRMI_PROBE_POP_LOGIC_CNTL_DEFAULT                                       0x000300c0
2876 #define regRMI_UTC_XNACK_N_MISC_CNTL_DEFAULT                                      0x00000564
2877 #define regRMI_DEMUX_CNTL_DEFAULT                                                 0x02000200
2878 #define regRMI_UTCL1_CNTL1_DEFAULT                                                0x00020000
2879 #define regRMI_UTCL1_CNTL2_DEFAULT                                                0x00010000
2880 #define regRMI_UTC_UNIT_CONFIG_DEFAULT                                            0x00000000
2881 #define regRMI_TCIW_FORMATTER0_CNTL_DEFAULT                                       0x00040000
2882 #define regRMI_TCIW_FORMATTER1_CNTL_DEFAULT                                       0x4004001e
2883 #define regRMI_SCOREBOARD_CNTL_DEFAULT                                            0x001ffe00
2884 #define regRMI_SCOREBOARD_STATUS0_DEFAULT                                         0x00000000
2885 #define regRMI_SCOREBOARD_STATUS1_DEFAULT                                         0x00000000
2886 #define regRMI_SCOREBOARD_STATUS2_DEFAULT                                         0x00000000
2887 #define regRMI_XBAR_ARBITER_CONFIG_DEFAULT                                        0x08000000
2888 #define regRMI_XBAR_ARBITER_CONFIG_1_DEFAULT                                      0x0000ffff
2889 #define regRMI_CLOCK_CNTRL_DEFAULT                                                0x00008822
2890 #define regRMI_UTCL1_STATUS_DEFAULT                                               0x00000000
2891 #define regRMI_RB_GLX_CID_MAP_DEFAULT                                             0xbcaa9987
2892 #define regRMI_SPARE_DEFAULT                                                      0xffff3100
2893 #define regRMI_SPARE_1_DEFAULT                                                    0x00000a00
2894 #define regRMI_SPARE_2_DEFAULT                                                    0x00000000
2895 #define regCC_RMI_REDUNDANCY_DEFAULT                                              0x00000010
2896 
2897 
2898 // addressBlock: gc_pfonly_didtdec
2899 #define regDIDT_INDEX_AUTO_INCR_EN_DEFAULT                                        0x00000001
2900 #define regDIDT_EDC_CTRL_DEFAULT                                                  0x00003800
2901 #define regDIDT_EDC_THROTTLE_CTRL_DEFAULT                                         0x00000010
2902 #define regDIDT_EDC_THRESHOLD_DEFAULT                                             0x00000000
2903 #define regDIDT_EDC_STALL_PATTERN_1_2_DEFAULT                                     0x01010001
2904 #define regDIDT_EDC_STALL_PATTERN_3_4_DEFAULT                                     0x11110421
2905 #define regDIDT_EDC_STALL_PATTERN_5_6_DEFAULT                                     0x25291249
2906 #define regDIDT_EDC_STALL_PATTERN_7_DEFAULT                                       0x00002aaa
2907 #define regDIDT_EDC_STATUS_DEFAULT                                                0x00000000
2908 #define regDIDT_EDC_DYNAMIC_THRESHOLD_RO_DEFAULT                                  0x00000000
2909 #define regDIDT_EDC_OVERFLOW_DEFAULT                                              0x00000000
2910 #define regDIDT_EDC_ROLLING_POWER_DELTA_DEFAULT                                   0x00000000
2911 #define regDIDT_IND_INDEX_DEFAULT                                                 0x00000000
2912 #define regDIDT_IND_DATA_DEFAULT                                                  0x00000000
2913 
2914 
2915 // addressBlock: gc_pfonly_spidec
2916 #define regSPI_GDBG_WAVE_CNTL_DEFAULT                                             0x00000000
2917 #define regSPI_GDBG_TRAP_CONFIG_DEFAULT                                           0x00000000
2918 #define regSPI_GDBG_WAVE_CNTL3_DEFAULT                                            0x00000000
2919 #define regSPI_ARB_CNTL_0_DEFAULT                                                 0x00000000
2920 #define regSPI_FEATURE_CTRL_DEFAULT                                               0x000013e0
2921 #define regSPI_SHADER_RSRC_LIMIT_CTRL_DEFAULT                                     0x00000000
2922 #define regSPI_COMPUTE_WF_CTX_SAVE_STATUS_DEFAULT                                 0x00000000
2923 
2924 
2925 // addressBlock: gc_pfonly_utcl1dec
2926 #define regUTCL1_CTRL_0_DEFAULT                                                   0x00001168
2927 #define regUTCL1_UTCL0_INVREQ_DISABLE_DEFAULT                                     0x00000000
2928 #define regUTCL1_CTRL_2_DEFAULT                                                   0x0000060f
2929 #define regUTCL1_FIFO_SIZING_DEFAULT                                              0x00000003
2930 #define regGCRD_SA0_TARGETS_DISABLE_DEFAULT                                       0x00000000
2931 #define regGCRD_SA1_TARGETS_DISABLE_DEFAULT                                       0x00000000
2932 #define regGCRD_CREDIT_SAFE_DEFAULT                                               0x00000044
2933 
2934 
2935 // addressBlock: gc_pfonly_pmmdec
2936 #define regGCR_GENERAL_CNTL_DEFAULT                                               0x00f00400
2937 #define regGCR_CMD_STATUS_DEFAULT                                                 0x00000000
2938 #define regGCR_SPARE_DEFAULT                                                      0x00482d00
2939 #define regPMM_CNTL2_DEFAULT                                                      0x60000000
2940 
2941 
2942 // addressBlock: gc_pfonly_tcpdec
2943 #define regTCP_INVALIDATE_DEFAULT                                                 0x00000000
2944 #define regTCP_STATUS_DEFAULT                                                     0x00000000
2945 #define regTCP_CNTL2_DEFAULT                                                      0x0000200a
2946 #define regTCP_DEBUG_INDEX_DEFAULT                                                0x00000000
2947 #define regTCP_DEBUG_DATA_DEFAULT                                                 0x00000000
2948 
2949 
2950 // addressBlock: gc_pfonly_gdsdec
2951 #define regGDS_ENHANCE2_DEFAULT                                                   0x00000000
2952 #define regGDS_OA_CGPG_RESTORE_DEFAULT                                            0x00000000
2953 
2954 
2955 // addressBlock: gc_sedcdec
2956 #define regSEDC_GL1_GL2_OVERRIDES_DEFAULT                                         0x00002828
2957 
2958 
2959 // addressBlock: gc_pfonly_gccacdec
2960 #define regGC_CAC_CTRL_1_DEFAULT                                                  0x00000108
2961 #define regGC_CAC_CTRL_2_DEFAULT                                                  0x00007fc4
2962 #define regGC_CAC_AGGR_LOWER_DEFAULT                                              0x00000000
2963 #define regGC_CAC_AGGR_UPPER_DEFAULT                                              0x00000000
2964 #define regSE0_CAC_AGGR_LOWER_DEFAULT                                             0x00000000
2965 #define regSE0_CAC_AGGR_UPPER_DEFAULT                                             0x00000000
2966 #define regSE1_CAC_AGGR_LOWER_DEFAULT                                             0x00000000
2967 #define regSE1_CAC_AGGR_UPPER_DEFAULT                                             0x00000000
2968 #define regSE2_CAC_AGGR_LOWER_DEFAULT                                             0x00000000
2969 #define regSE2_CAC_AGGR_UPPER_DEFAULT                                             0x00000000
2970 #define regSE3_CAC_AGGR_LOWER_DEFAULT                                             0x00000000
2971 #define regSE3_CAC_AGGR_UPPER_DEFAULT                                             0x00000000
2972 #define regSE4_CAC_AGGR_LOWER_DEFAULT                                             0x00000000
2973 #define regSE4_CAC_AGGR_UPPER_DEFAULT                                             0x00000000
2974 #define regSE5_CAC_AGGR_LOWER_DEFAULT                                             0x00000000
2975 #define regSE5_CAC_AGGR_UPPER_DEFAULT                                             0x00000000
2976 #define regGC_CAC_AGGR_GFXCLK_CYCLE_DEFAULT                                       0x00000000
2977 #define regSE0_CAC_AGGR_GFXCLK_CYCLE_DEFAULT                                      0x00000000
2978 #define regSE1_CAC_AGGR_GFXCLK_CYCLE_DEFAULT                                      0x00000000
2979 #define regSE2_CAC_AGGR_GFXCLK_CYCLE_DEFAULT                                      0x00000000
2980 #define regSE3_CAC_AGGR_GFXCLK_CYCLE_DEFAULT                                      0x00000000
2981 #define regSE4_CAC_AGGR_GFXCLK_CYCLE_DEFAULT                                      0x00000000
2982 #define regSE5_CAC_AGGR_GFXCLK_CYCLE_DEFAULT                                      0x00000000
2983 #define regGC_EDC_CTRL_DEFAULT                                                    0x00007800
2984 #define regGC_EDC_THRESHOLD_DEFAULT                                               0x00000000
2985 #define regGC_EDC_STRETCH_CTRL_DEFAULT                                            0x00000000
2986 #define regGC_EDC_STRETCH_THRESHOLD_DEFAULT                                       0x00000000
2987 #define regEDC_HYSTERESIS_CNTL_DEFAULT                                            0x00018001
2988 #define regGC_THROTTLE_CTRL_DEFAULT                                               0x00002040
2989 #define regGC_THROTTLE_CTRL1_DEFAULT                                              0x00cc0660
2990 #define regPCC_STALL_PATTERN_CTRL_DEFAULT                                         0x07fa0401
2991 #define regPWRBRK_STALL_PATTERN_CTRL_DEFAULT                                      0x00fa0401
2992 #define regPCC_STALL_PATTERN_1_2_DEFAULT                                          0x00000000
2993 #define regPCC_STALL_PATTERN_3_4_DEFAULT                                          0x00000000
2994 #define regPCC_STALL_PATTERN_5_6_DEFAULT                                          0x00000000
2995 #define regPCC_STALL_PATTERN_7_DEFAULT                                            0x00000000
2996 #define regPWRBRK_STALL_PATTERN_1_2_DEFAULT                                       0x00000000
2997 #define regPWRBRK_STALL_PATTERN_3_4_DEFAULT                                       0x00000000
2998 #define regPWRBRK_STALL_PATTERN_5_6_DEFAULT                                       0x00000000
2999 #define regPWRBRK_STALL_PATTERN_7_DEFAULT                                         0x00000000
3000 #define regDIDT_STALL_PATTERN_CTRL_DEFAULT                                        0x000000f8
3001 #define regDIDT_STALL_PATTERN_1_2_DEFAULT                                         0x00000000
3002 #define regDIDT_STALL_PATTERN_3_4_DEFAULT                                         0x00000000
3003 #define regDIDT_STALL_PATTERN_5_6_DEFAULT                                         0x00000000
3004 #define regDIDT_STALL_PATTERN_7_DEFAULT                                           0x00000000
3005 #define regPCC_PWRBRK_HYSTERESIS_CTRL_DEFAULT                                     0x00000000
3006 #define regEDC_STRETCH_PERF_COUNTER_DEFAULT                                       0x00000000
3007 #define regEDC_UNSTRETCH_PERF_COUNTER_DEFAULT                                     0x00000000
3008 #define regEDC_STRETCH_NUM_PERF_COUNTER_DEFAULT                                   0x00000000
3009 #define regGC_EDC_STATUS_DEFAULT                                                  0x00000000
3010 #define regGC_EDC_OVERFLOW_DEFAULT                                                0x00000000
3011 #define regGC_EDC_ROLLING_POWER_DELTA_DEFAULT                                     0x00000000
3012 #define regGC_THROTTLE_STATUS_DEFAULT                                             0x00000000
3013 #define regEDC_PERF_COUNTER_DEFAULT                                               0x00000000
3014 #define regPCC_PERF_COUNTER_DEFAULT                                               0x00000000
3015 #define regPWRBRK_PERF_COUNTER_DEFAULT                                            0x00000000
3016 #define regEDC_HYSTERESIS_STAT_DEFAULT                                            0x00000000
3017 #define regGC_CAC_WEIGHT_CP_0_DEFAULT                                             0x00000000
3018 #define regGC_CAC_WEIGHT_CP_1_DEFAULT                                             0x00000000
3019 #define regGC_CAC_WEIGHT_EA_0_DEFAULT                                             0x00000000
3020 #define regGC_CAC_WEIGHT_EA_1_DEFAULT                                             0x00000000
3021 #define regGC_CAC_WEIGHT_EA_2_DEFAULT                                             0x00000000
3022 #define regGC_CAC_WEIGHT_UTCL2_ROUTER_0_DEFAULT                                   0x00000000
3023 #define regGC_CAC_WEIGHT_UTCL2_ROUTER_1_DEFAULT                                   0x00000000
3024 #define regGC_CAC_WEIGHT_UTCL2_ROUTER_2_DEFAULT                                   0x00000000
3025 #define regGC_CAC_WEIGHT_UTCL2_ROUTER_3_DEFAULT                                   0x00000000
3026 #define regGC_CAC_WEIGHT_UTCL2_ROUTER_4_DEFAULT                                   0x00000000
3027 #define regGC_CAC_WEIGHT_UTCL2_VML2_0_DEFAULT                                     0x00000000
3028 #define regGC_CAC_WEIGHT_UTCL2_VML2_1_DEFAULT                                     0x00000000
3029 #define regGC_CAC_WEIGHT_UTCL2_VML2_2_DEFAULT                                     0x00000000
3030 #define regGC_CAC_WEIGHT_UTCL2_WALKER_0_DEFAULT                                   0x00000000
3031 #define regGC_CAC_WEIGHT_UTCL2_WALKER_1_DEFAULT                                   0x00000000
3032 #define regGC_CAC_WEIGHT_UTCL2_WALKER_2_DEFAULT                                   0x00000000
3033 #define regGC_CAC_WEIGHT_GDS_0_DEFAULT                                            0x00000000
3034 #define regGC_CAC_WEIGHT_GDS_1_DEFAULT                                            0x00000000
3035 #define regGC_CAC_WEIGHT_GDS_2_DEFAULT                                            0x00000000
3036 #define regGC_CAC_WEIGHT_GE_0_DEFAULT                                             0x00000000
3037 #define regGC_CAC_WEIGHT_GE_1_DEFAULT                                             0x00000000
3038 #define regGC_CAC_WEIGHT_GE_2_DEFAULT                                             0x00000000
3039 #define regGC_CAC_WEIGHT_GE_3_DEFAULT                                             0x00000000
3040 #define regGC_CAC_WEIGHT_GE_4_DEFAULT                                             0x00000000
3041 #define regGC_CAC_WEIGHT_GE_5_DEFAULT                                             0x00000000
3042 #define regGC_CAC_WEIGHT_GE_6_DEFAULT                                             0x00000000
3043 #define regGC_CAC_WEIGHT_PMM_0_DEFAULT                                            0x00000000
3044 #define regGC_CAC_WEIGHT_GL2C_0_DEFAULT                                           0x00000000
3045 #define regGC_CAC_WEIGHT_GL2C_1_DEFAULT                                           0x00000000
3046 #define regGC_CAC_WEIGHT_GL2C_2_DEFAULT                                           0x00000000
3047 #define regGC_CAC_WEIGHT_PH_0_DEFAULT                                             0x00000000
3048 #define regGC_CAC_WEIGHT_PH_1_DEFAULT                                             0x00000000
3049 #define regGC_CAC_WEIGHT_PH_2_DEFAULT                                             0x00000000
3050 #define regGC_CAC_WEIGHT_PH_3_DEFAULT                                             0x00000000
3051 #define regGC_CAC_WEIGHT_SDMA_0_DEFAULT                                           0x00000000
3052 #define regGC_CAC_WEIGHT_SDMA_1_DEFAULT                                           0x00000000
3053 #define regGC_CAC_WEIGHT_SDMA_2_DEFAULT                                           0x00000000
3054 #define regGC_CAC_WEIGHT_SDMA_3_DEFAULT                                           0x00000000
3055 #define regGC_CAC_WEIGHT_SDMA_4_DEFAULT                                           0x00000000
3056 #define regGC_CAC_WEIGHT_SDMA_5_DEFAULT                                           0x00000000
3057 #define regGC_CAC_WEIGHT_CHC_0_DEFAULT                                            0x00000000
3058 #define regGC_CAC_WEIGHT_CHC_1_DEFAULT                                            0x00000000
3059 #define regGC_CAC_WEIGHT_GUS_0_DEFAULT                                            0x00000000
3060 #define regGC_CAC_WEIGHT_GUS_1_DEFAULT                                            0x00000000
3061 #define regGC_CAC_WEIGHT_RLC_0_DEFAULT                                            0x00000000
3062 #define regGC_CAC_WEIGHT_GRBM_0_DEFAULT                                           0x00000000
3063 #define regGC_EDC_CLK_MONITOR_CTRL_DEFAULT                                        0x00000000
3064 #define regGC_CAC_IND_INDEX_DEFAULT                                               0x00000000
3065 #define regGC_CAC_IND_DATA_DEFAULT                                                0x00000000
3066 #define regSE_CAC_CTRL_1_DEFAULT                                                  0x00000108
3067 #define regSE_CAC_CTRL_2_DEFAULT                                                  0x00000008
3068 #define regSE_CAC_WEIGHT_TA_0_DEFAULT                                             0x00000000
3069 #define regSE_CAC_WEIGHT_TD_0_DEFAULT                                             0x00000000
3070 #define regSE_CAC_WEIGHT_TD_1_DEFAULT                                             0x00000000
3071 #define regSE_CAC_WEIGHT_TD_2_DEFAULT                                             0x00000000
3072 #define regSE_CAC_WEIGHT_TD_3_DEFAULT                                             0x00000000
3073 #define regSE_CAC_WEIGHT_TD_4_DEFAULT                                             0x00000000
3074 #define regSE_CAC_WEIGHT_TD_5_DEFAULT                                             0x00000000
3075 #define regSE_CAC_WEIGHT_TCP_0_DEFAULT                                            0x00000000
3076 #define regSE_CAC_WEIGHT_TCP_1_DEFAULT                                            0x00000000
3077 #define regSE_CAC_WEIGHT_TCP_2_DEFAULT                                            0x00000000
3078 #define regSE_CAC_WEIGHT_TCP_3_DEFAULT                                            0x00000000
3079 #define regSE_CAC_WEIGHT_SQ_0_DEFAULT                                             0x00000000
3080 #define regSE_CAC_WEIGHT_SQ_1_DEFAULT                                             0x00000000
3081 #define regSE_CAC_WEIGHT_SQ_2_DEFAULT                                             0x00000000
3082 #define regSE_CAC_WEIGHT_SP_0_DEFAULT                                             0x00000000
3083 #define regSE_CAC_WEIGHT_SP_1_DEFAULT                                             0x00000000
3084 #define regSE_CAC_WEIGHT_LDS_0_DEFAULT                                            0x00000000
3085 #define regSE_CAC_WEIGHT_LDS_1_DEFAULT                                            0x00000000
3086 #define regSE_CAC_WEIGHT_LDS_2_DEFAULT                                            0x00000000
3087 #define regSE_CAC_WEIGHT_LDS_3_DEFAULT                                            0x00000000
3088 #define regSE_CAC_WEIGHT_SQC_0_DEFAULT                                            0x00000000
3089 #define regSE_CAC_WEIGHT_SQC_1_DEFAULT                                            0x00000000
3090 #define regSE_CAC_WEIGHT_CU_0_DEFAULT                                             0x00000000
3091 #define regSE_CAC_WEIGHT_BCI_0_DEFAULT                                            0x00000000
3092 #define regSE_CAC_WEIGHT_CB_0_DEFAULT                                             0x00000000
3093 #define regSE_CAC_WEIGHT_CB_1_DEFAULT                                             0x00000000
3094 #define regSE_CAC_WEIGHT_CB_2_DEFAULT                                             0x00000000
3095 #define regSE_CAC_WEIGHT_CB_3_DEFAULT                                             0x00000000
3096 #define regSE_CAC_WEIGHT_CB_4_DEFAULT                                             0x00000000
3097 #define regSE_CAC_WEIGHT_CB_5_DEFAULT                                             0x00000000
3098 #define regSE_CAC_WEIGHT_CB_6_DEFAULT                                             0x00000000
3099 #define regSE_CAC_WEIGHT_CB_7_DEFAULT                                             0x00000000
3100 #define regSE_CAC_WEIGHT_CB_8_DEFAULT                                             0x00000000
3101 #define regSE_CAC_WEIGHT_CB_9_DEFAULT                                             0x00000000
3102 #define regSE_CAC_WEIGHT_CB_10_DEFAULT                                            0x00000000
3103 #define regSE_CAC_WEIGHT_CB_11_DEFAULT                                            0x00000000
3104 #define regSE_CAC_WEIGHT_DB_0_DEFAULT                                             0x00000000
3105 #define regSE_CAC_WEIGHT_DB_1_DEFAULT                                             0x00000000
3106 #define regSE_CAC_WEIGHT_DB_2_DEFAULT                                             0x00000000
3107 #define regSE_CAC_WEIGHT_DB_3_DEFAULT                                             0x00000000
3108 #define regSE_CAC_WEIGHT_DB_4_DEFAULT                                             0x00000000
3109 #define regSE_CAC_WEIGHT_RMI_0_DEFAULT                                            0x00000000
3110 #define regSE_CAC_WEIGHT_RMI_1_DEFAULT                                            0x00000000
3111 #define regSE_CAC_WEIGHT_SX_0_DEFAULT                                             0x00000000
3112 #define regSE_CAC_WEIGHT_SXRB_0_DEFAULT                                           0x00000000
3113 #define regSE_CAC_WEIGHT_UTCL1_0_DEFAULT                                          0x00000000
3114 #define regSE_CAC_WEIGHT_GL1C_0_DEFAULT                                           0x00000000
3115 #define regSE_CAC_WEIGHT_GL1C_1_DEFAULT                                           0x00000000
3116 #define regSE_CAC_WEIGHT_GL1C_2_DEFAULT                                           0x00000000
3117 #define regSE_CAC_WEIGHT_SPI_0_DEFAULT                                            0x00000000
3118 #define regSE_CAC_WEIGHT_SPI_1_DEFAULT                                            0x00000000
3119 #define regSE_CAC_WEIGHT_SPI_2_DEFAULT                                            0x00000000
3120 #define regSE_CAC_WEIGHT_PC_0_DEFAULT                                             0x00000000
3121 #define regSE_CAC_WEIGHT_PA_0_DEFAULT                                             0x00000000
3122 #define regSE_CAC_WEIGHT_PA_1_DEFAULT                                             0x00000000
3123 #define regSE_CAC_WEIGHT_PA_2_DEFAULT                                             0x00000000
3124 #define regSE_CAC_WEIGHT_PA_3_DEFAULT                                             0x00000000
3125 #define regSE_CAC_WEIGHT_SC_0_DEFAULT                                             0x00000000
3126 #define regSE_CAC_WEIGHT_SC_1_DEFAULT                                             0x00000000
3127 #define regSE_CAC_WEIGHT_SC_2_DEFAULT                                             0x00000000
3128 #define regSE_CAC_WEIGHT_SC_3_DEFAULT                                             0x00000000
3129 #define regSE_CAC_WINDOW_AGGR_VALUE_DEFAULT                                       0x00000000
3130 #define regSE_CAC_WINDOW_GFXCLK_CYCLE_DEFAULT                                     0x00000000
3131 #define regSE_CAC_IND_INDEX_DEFAULT                                               0x00000000
3132 #define regSE_CAC_IND_DATA_DEFAULT                                                0x00000000
3133 
3134 
3135 // addressBlock: gc_pfonly2_spidec
3136 #define regSPI_RESOURCE_RESERVE_CU_0_DEFAULT                                      0x00000000
3137 #define regSPI_RESOURCE_RESERVE_CU_1_DEFAULT                                      0x00000000
3138 #define regSPI_RESOURCE_RESERVE_CU_2_DEFAULT                                      0x00000000
3139 #define regSPI_RESOURCE_RESERVE_CU_3_DEFAULT                                      0x00000000
3140 #define regSPI_RESOURCE_RESERVE_CU_4_DEFAULT                                      0x00000000
3141 #define regSPI_RESOURCE_RESERVE_CU_5_DEFAULT                                      0x00000000
3142 #define regSPI_RESOURCE_RESERVE_CU_6_DEFAULT                                      0x00000000
3143 #define regSPI_RESOURCE_RESERVE_CU_7_DEFAULT                                      0x00000000
3144 #define regSPI_RESOURCE_RESERVE_CU_8_DEFAULT                                      0x00000000
3145 #define regSPI_RESOURCE_RESERVE_CU_9_DEFAULT                                      0x00000000
3146 #define regSPI_RESOURCE_RESERVE_CU_10_DEFAULT                                     0x00000000
3147 #define regSPI_RESOURCE_RESERVE_CU_11_DEFAULT                                     0x00000000
3148 #define regSPI_RESOURCE_RESERVE_CU_12_DEFAULT                                     0x00000000
3149 #define regSPI_RESOURCE_RESERVE_CU_13_DEFAULT                                     0x00000000
3150 #define regSPI_RESOURCE_RESERVE_CU_14_DEFAULT                                     0x00000000
3151 #define regSPI_RESOURCE_RESERVE_CU_15_DEFAULT                                     0x00000000
3152 #define regSPI_RESOURCE_RESERVE_EN_CU_0_DEFAULT                                   0x00000000
3153 #define regSPI_RESOURCE_RESERVE_EN_CU_1_DEFAULT                                   0x00000000
3154 #define regSPI_RESOURCE_RESERVE_EN_CU_2_DEFAULT                                   0x00000000
3155 #define regSPI_RESOURCE_RESERVE_EN_CU_3_DEFAULT                                   0x00000000
3156 #define regSPI_RESOURCE_RESERVE_EN_CU_4_DEFAULT                                   0x00000000
3157 #define regSPI_RESOURCE_RESERVE_EN_CU_5_DEFAULT                                   0x00000000
3158 #define regSPI_RESOURCE_RESERVE_EN_CU_6_DEFAULT                                   0x00000000
3159 #define regSPI_RESOURCE_RESERVE_EN_CU_7_DEFAULT                                   0x00000000
3160 #define regSPI_RESOURCE_RESERVE_EN_CU_8_DEFAULT                                   0x00000000
3161 #define regSPI_RESOURCE_RESERVE_EN_CU_9_DEFAULT                                   0x00000000
3162 #define regSPI_RESOURCE_RESERVE_EN_CU_10_DEFAULT                                  0x00000000
3163 #define regSPI_RESOURCE_RESERVE_EN_CU_11_DEFAULT                                  0x00000000
3164 #define regSPI_RESOURCE_RESERVE_EN_CU_12_DEFAULT                                  0x00000000
3165 #define regSPI_RESOURCE_RESERVE_EN_CU_13_DEFAULT                                  0x00000000
3166 #define regSPI_RESOURCE_RESERVE_EN_CU_14_DEFAULT                                  0x00000000
3167 #define regSPI_RESOURCE_RESERVE_EN_CU_15_DEFAULT                                  0x00000000
3168 
3169 
3170 // addressBlock: gc_gfxudec
3171 #define regCP_EOP_DONE_ADDR_LO_DEFAULT                                            0x00000000
3172 #define regCP_EOP_DONE_ADDR_HI_DEFAULT                                            0x00000000
3173 #define regCP_EOP_DONE_DATA_LO_DEFAULT                                            0x00000000
3174 #define regCP_EOP_DONE_DATA_HI_DEFAULT                                            0x00000000
3175 #define regCP_EOP_LAST_FENCE_LO_DEFAULT                                           0x00000000
3176 #define regCP_EOP_LAST_FENCE_HI_DEFAULT                                           0x00000000
3177 #define regCP_PIPE_STATS_ADDR_LO_DEFAULT                                          0x00000000
3178 #define regCP_PIPE_STATS_ADDR_HI_DEFAULT                                          0x00000000
3179 #define regCP_VGT_IAVERT_COUNT_LO_DEFAULT                                         0x00000000
3180 #define regCP_VGT_IAVERT_COUNT_HI_DEFAULT                                         0x00000000
3181 #define regCP_VGT_IAPRIM_COUNT_LO_DEFAULT                                         0x00000000
3182 #define regCP_VGT_IAPRIM_COUNT_HI_DEFAULT                                         0x00000000
3183 #define regCP_VGT_GSPRIM_COUNT_LO_DEFAULT                                         0x00000000
3184 #define regCP_VGT_GSPRIM_COUNT_HI_DEFAULT                                         0x00000000
3185 #define regCP_VGT_VSINVOC_COUNT_LO_DEFAULT                                        0x00000000
3186 #define regCP_VGT_VSINVOC_COUNT_HI_DEFAULT                                        0x00000000
3187 #define regCP_VGT_GSINVOC_COUNT_LO_DEFAULT                                        0x00000000
3188 #define regCP_VGT_GSINVOC_COUNT_HI_DEFAULT                                        0x00000000
3189 #define regCP_VGT_HSINVOC_COUNT_LO_DEFAULT                                        0x00000000
3190 #define regCP_VGT_HSINVOC_COUNT_HI_DEFAULT                                        0x00000000
3191 #define regCP_VGT_DSINVOC_COUNT_LO_DEFAULT                                        0x00000000
3192 #define regCP_VGT_DSINVOC_COUNT_HI_DEFAULT                                        0x00000000
3193 #define regCP_PA_CINVOC_COUNT_LO_DEFAULT                                          0x00000000
3194 #define regCP_PA_CINVOC_COUNT_HI_DEFAULT                                          0x00000000
3195 #define regCP_PA_CPRIM_COUNT_LO_DEFAULT                                           0x00000000
3196 #define regCP_PA_CPRIM_COUNT_HI_DEFAULT                                           0x00000000
3197 #define regCP_SC_PSINVOC_COUNT0_LO_DEFAULT                                        0x00000000
3198 #define regCP_SC_PSINVOC_COUNT0_HI_DEFAULT                                        0x00000000
3199 #define regCP_SC_PSINVOC_COUNT1_LO_DEFAULT                                        0x00000000
3200 #define regCP_SC_PSINVOC_COUNT1_HI_DEFAULT                                        0x00000000
3201 #define regCP_VGT_CSINVOC_COUNT_LO_DEFAULT                                        0x00000000
3202 #define regCP_VGT_CSINVOC_COUNT_HI_DEFAULT                                        0x00000000
3203 #define regCP_VGT_ASINVOC_COUNT_LO_DEFAULT                                        0x00000000
3204 #define regCP_VGT_ASINVOC_COUNT_HI_DEFAULT                                        0x00000000
3205 #define regCP_PIPE_STATS_CONTROL_DEFAULT                                          0x00000000
3206 #define regSCRATCH_REG0_DEFAULT                                                   0x00000000
3207 #define regSCRATCH_REG1_DEFAULT                                                   0x00000000
3208 #define regSCRATCH_REG2_DEFAULT                                                   0x00000000
3209 #define regSCRATCH_REG3_DEFAULT                                                   0x00000000
3210 #define regSCRATCH_REG4_DEFAULT                                                   0x00000000
3211 #define regSCRATCH_REG5_DEFAULT                                                   0x00000000
3212 #define regSCRATCH_REG6_DEFAULT                                                   0x00000000
3213 #define regSCRATCH_REG7_DEFAULT                                                   0x00000000
3214 #define regSCRATCH_REG_ATOMIC_DEFAULT                                             0x00000000
3215 #define regSCRATCH_REG_CMPSWAP_ATOMIC_DEFAULT                                     0x00000000
3216 #define regCP_APPEND_DDID_CNT_DEFAULT                                             0x00000000
3217 #define regCP_APPEND_DATA_HI_DEFAULT                                              0x00000000
3218 #define regCP_APPEND_LAST_CS_FENCE_HI_DEFAULT                                     0x00000000
3219 #define regCP_APPEND_LAST_PS_FENCE_HI_DEFAULT                                     0x00000000
3220 #define regCP_PFP_ATOMIC_PREOP_LO_DEFAULT                                         0x00000000
3221 #define regCP_PFP_ATOMIC_PREOP_HI_DEFAULT                                         0x00000000
3222 #define regCP_PFP_GDS_ATOMIC0_PREOP_LO_DEFAULT                                    0x00000000
3223 #define regCP_PFP_GDS_ATOMIC0_PREOP_HI_DEFAULT                                    0x00000000
3224 #define regCP_PFP_GDS_ATOMIC1_PREOP_LO_DEFAULT                                    0x00000000
3225 #define regCP_PFP_GDS_ATOMIC1_PREOP_HI_DEFAULT                                    0x00000000
3226 #define regCP_APPEND_ADDR_LO_DEFAULT                                              0x00000000
3227 #define regCP_APPEND_ADDR_HI_DEFAULT                                              0x00000000
3228 #define regCP_APPEND_DATA_DEFAULT                                                 0x00000000
3229 #define regCP_APPEND_DATA_LO_DEFAULT                                              0x00000000
3230 #define regCP_APPEND_LAST_CS_FENCE_DEFAULT                                        0x00000000
3231 #define regCP_APPEND_LAST_CS_FENCE_LO_DEFAULT                                     0x00000000
3232 #define regCP_APPEND_LAST_PS_FENCE_DEFAULT                                        0x00000000
3233 #define regCP_APPEND_LAST_PS_FENCE_LO_DEFAULT                                     0x00000000
3234 #define regCP_ATOMIC_PREOP_LO_DEFAULT                                             0x00000000
3235 #define regCP_ME_ATOMIC_PREOP_LO_DEFAULT                                          0x00000000
3236 #define regCP_ATOMIC_PREOP_HI_DEFAULT                                             0x00000000
3237 #define regCP_ME_ATOMIC_PREOP_HI_DEFAULT                                          0x00000000
3238 #define regCP_GDS_ATOMIC0_PREOP_LO_DEFAULT                                        0x00000000
3239 #define regCP_ME_GDS_ATOMIC0_PREOP_LO_DEFAULT                                     0x00000000
3240 #define regCP_GDS_ATOMIC0_PREOP_HI_DEFAULT                                        0x00000000
3241 #define regCP_ME_GDS_ATOMIC0_PREOP_HI_DEFAULT                                     0x00000000
3242 #define regCP_GDS_ATOMIC1_PREOP_LO_DEFAULT                                        0x00000000
3243 #define regCP_ME_GDS_ATOMIC1_PREOP_LO_DEFAULT                                     0x00000000
3244 #define regCP_GDS_ATOMIC1_PREOP_HI_DEFAULT                                        0x00000000
3245 #define regCP_ME_GDS_ATOMIC1_PREOP_HI_DEFAULT                                     0x00000000
3246 #define regCP_ME_MC_WADDR_LO_DEFAULT                                              0x00000000
3247 #define regCP_ME_MC_WADDR_HI_DEFAULT                                              0x00000000
3248 #define regCP_ME_MC_WDATA_LO_DEFAULT                                              0x00000000
3249 #define regCP_ME_MC_WDATA_HI_DEFAULT                                              0x00000000
3250 #define regCP_ME_MC_RADDR_LO_DEFAULT                                              0x00000000
3251 #define regCP_ME_MC_RADDR_HI_DEFAULT                                              0x80000000
3252 #define regCP_SEM_WAIT_TIMER_DEFAULT                                              0x00000000
3253 #define regCP_SIG_SEM_ADDR_LO_DEFAULT                                             0x00000000
3254 #define regCP_SIG_SEM_ADDR_HI_DEFAULT                                             0x00000000
3255 #define regCP_WAIT_REG_MEM_TIMEOUT_DEFAULT                                        0x00000000
3256 #define regCP_WAIT_SEM_ADDR_LO_DEFAULT                                            0x00000000
3257 #define regCP_WAIT_SEM_ADDR_HI_DEFAULT                                            0x00000000
3258 #define regCP_DMA_PFP_CONTROL_DEFAULT                                             0x00000000
3259 #define regCP_DMA_ME_CONTROL_DEFAULT                                              0x00000000
3260 #define regCP_DMA_ME_SRC_ADDR_DEFAULT                                             0x00000000
3261 #define regCP_DMA_ME_SRC_ADDR_HI_DEFAULT                                          0x00000000
3262 #define regCP_DMA_ME_DST_ADDR_DEFAULT                                             0x00000000
3263 #define regCP_DMA_ME_DST_ADDR_HI_DEFAULT                                          0x00000000
3264 #define regCP_DMA_ME_COMMAND_DEFAULT                                              0x00000000
3265 #define regCP_DMA_PFP_SRC_ADDR_DEFAULT                                            0x00000000
3266 #define regCP_DMA_PFP_SRC_ADDR_HI_DEFAULT                                         0x00000000
3267 #define regCP_DMA_PFP_DST_ADDR_DEFAULT                                            0x00000000
3268 #define regCP_DMA_PFP_DST_ADDR_HI_DEFAULT                                         0x00000000
3269 #define regCP_DMA_PFP_COMMAND_DEFAULT                                             0x00000000
3270 #define regCP_DMA_CNTL_DEFAULT                                                    0x10100020
3271 #define regCP_DMA_READ_TAGS_DEFAULT                                               0x00000000
3272 #define regCP_PFP_IB_CONTROL_DEFAULT                                              0x00000000
3273 #define regCP_PFP_LOAD_CONTROL_DEFAULT                                            0x00000000
3274 #define regCP_SCRATCH_INDEX_DEFAULT                                               0x00000000
3275 #define regCP_SCRATCH_DATA_DEFAULT                                                0x00000000
3276 #define regCP_RB_OFFSET_DEFAULT                                                   0x00000000
3277 #define regCP_IB2_OFFSET_DEFAULT                                                  0x00000000
3278 #define regCP_IB2_PREAMBLE_BEGIN_DEFAULT                                          0x00000000
3279 #define regCP_IB2_PREAMBLE_END_DEFAULT                                            0x00000000
3280 #define regCP_DMA_ME_CMD_ADDR_LO_DEFAULT                                          0x00000000
3281 #define regCP_DMA_ME_CMD_ADDR_HI_DEFAULT                                          0x00000000
3282 #define regCP_DMA_PFP_CMD_ADDR_LO_DEFAULT                                         0x00000000
3283 #define regCP_DMA_PFP_CMD_ADDR_HI_DEFAULT                                         0x00000000
3284 #define regCP_APPEND_CMD_ADDR_LO_DEFAULT                                          0x00000000
3285 #define regCP_APPEND_CMD_ADDR_HI_DEFAULT                                          0x00000000
3286 #define regUCONFIG_RESERVED_REG0_DEFAULT                                          0x00000000
3287 #define regUCONFIG_RESERVED_REG1_DEFAULT                                          0x00000000
3288 #define regCP_PA_MSPRIM_COUNT_LO_DEFAULT                                          0x00000000
3289 #define regCP_PA_MSPRIM_COUNT_HI_DEFAULT                                          0x00000000
3290 #define regCP_GE_MSINVOC_COUNT_LO_DEFAULT                                         0x00000000
3291 #define regCP_GE_MSINVOC_COUNT_HI_DEFAULT                                         0x00000000
3292 #define regCP_IB2_CMD_BUFSZ_DEFAULT                                               0x00000000
3293 #define regCP_ST_CMD_BUFSZ_DEFAULT                                                0x00000000
3294 #define regCP_IB2_BASE_LO_DEFAULT                                                 0x00000000
3295 #define regCP_IB2_BASE_HI_DEFAULT                                                 0x00000000
3296 #define regCP_IB2_BUFSZ_DEFAULT                                                   0x00000000
3297 #define regCP_ST_BASE_LO_DEFAULT                                                  0x00000000
3298 #define regCP_ST_BASE_HI_DEFAULT                                                  0x00000000
3299 #define regCP_ST_BUFSZ_DEFAULT                                                    0x00000000
3300 #define regCP_EOP_DONE_EVENT_CNTL_DEFAULT                                         0x00000000
3301 #define regCP_EOP_DONE_DATA_CNTL_DEFAULT                                          0x00000000
3302 #define regCP_EOP_DONE_CNTX_ID_DEFAULT                                            0x00000000
3303 #define regCP_DB_BASE_LO_DEFAULT                                                  0x00000000
3304 #define regCP_DB_BASE_HI_DEFAULT                                                  0x00000000
3305 #define regCP_DB_BUFSZ_DEFAULT                                                    0x00000000
3306 #define regCP_DB_CMD_BUFSZ_DEFAULT                                                0x00000000
3307 #define regCP_PFP_COMPLETION_STATUS_DEFAULT                                       0x00000000
3308 #define regCP_PRED_NOT_VISIBLE_DEFAULT                                            0x00000000
3309 #define regCP_PFP_METADATA_BASE_ADDR_DEFAULT                                      0x00000000
3310 #define regCP_PFP_METADATA_BASE_ADDR_HI_DEFAULT                                   0x00000000
3311 #define regCP_DRAW_INDX_INDR_ADDR_DEFAULT                                         0x00000000
3312 #define regCP_DRAW_INDX_INDR_ADDR_HI_DEFAULT                                      0x00000000
3313 #define regCP_DISPATCH_INDR_ADDR_DEFAULT                                          0x00000000
3314 #define regCP_DISPATCH_INDR_ADDR_HI_DEFAULT                                       0x00000000
3315 #define regCP_INDEX_BASE_ADDR_DEFAULT                                             0x00000000
3316 #define regCP_INDEX_BASE_ADDR_HI_DEFAULT                                          0x00000000
3317 #define regCP_INDEX_TYPE_DEFAULT                                                  0x00000000
3318 #define regCP_GDS_BKUP_ADDR_DEFAULT                                               0x00000000
3319 #define regCP_GDS_BKUP_ADDR_HI_DEFAULT                                            0x00000000
3320 #define regCP_SAMPLE_STATUS_DEFAULT                                               0x00000000
3321 #define regCP_ME_COHER_CNTL_DEFAULT                                               0x00000000
3322 #define regCP_ME_COHER_SIZE_DEFAULT                                               0x00000000
3323 #define regCP_ME_COHER_SIZE_HI_DEFAULT                                            0x00000000
3324 #define regCP_ME_COHER_BASE_DEFAULT                                               0x00000000
3325 #define regCP_ME_COHER_BASE_HI_DEFAULT                                            0x00000000
3326 #define regCP_ME_COHER_STATUS_DEFAULT                                             0x00000000
3327 #define regRLC_GPM_PERF_COUNT_0_DEFAULT                                           0x00000000
3328 #define regRLC_GPM_PERF_COUNT_1_DEFAULT                                           0x00000000
3329 #define regGRBM_GFX_INDEX_DEFAULT                                                 0xe0000000
3330 #define regVGT_PRIMITIVE_TYPE_DEFAULT                                             0x00000000
3331 #define regVGT_INDEX_TYPE_DEFAULT                                                 0x00000000
3332 #define regGE_MIN_VTX_INDX_DEFAULT                                                0x00000000
3333 #define regGE_INDX_OFFSET_DEFAULT                                                 0x00000000
3334 #define regGE_MULTI_PRIM_IB_RESET_EN_DEFAULT                                      0x00000000
3335 #define regVGT_NUM_INDICES_DEFAULT                                                0x00000000
3336 #define regVGT_NUM_INSTANCES_DEFAULT                                              0x00000000
3337 #define regVGT_TF_RING_SIZE_DEFAULT                                               0x00003000
3338 #define regVGT_HS_OFFCHIP_PARAM_DEFAULT                                           0x00000000
3339 #define regVGT_TF_MEMORY_BASE_DEFAULT                                             0x00000000
3340 #define regGE_MAX_VTX_INDX_DEFAULT                                                0x00000000
3341 #define regVGT_INSTANCE_BASE_ID_DEFAULT                                           0x00000000
3342 #define regGE_CNTL_DEFAULT                                                        0x00000000
3343 #define regGE_USER_VGPR1_DEFAULT                                                  0x00000000
3344 #define regGE_USER_VGPR2_DEFAULT                                                  0x00000000
3345 #define regGE_USER_VGPR3_DEFAULT                                                  0x00000000
3346 #define regGE_STEREO_CNTL_DEFAULT                                                 0x00000000
3347 #define regGE_PC_ALLOC_DEFAULT                                                    0x00000000
3348 #define regVGT_TF_MEMORY_BASE_HI_DEFAULT                                          0x00000000
3349 #define regGE_USER_VGPR_EN_DEFAULT                                                0x00000000
3350 #define regGE_GS_FAST_LAUNCH_WG_DIM_DEFAULT                                       0x00000000
3351 #define regGE_GS_FAST_LAUNCH_WG_DIM_1_DEFAULT                                     0x00000000
3352 #define regVGT_GS_OUT_PRIM_TYPE_DEFAULT                                           0x00000000
3353 #define regPA_SU_LINE_STIPPLE_VALUE_DEFAULT                                       0x00000000
3354 #define regPA_SC_LINE_STIPPLE_STATE_DEFAULT                                       0x00000000
3355 #define regPA_SC_SCREEN_EXTENT_MIN_0_DEFAULT                                      0x7fff7fff
3356 #define regPA_SC_SCREEN_EXTENT_MAX_0_DEFAULT                                      0x80008000
3357 #define regPA_SC_SCREEN_EXTENT_MIN_1_DEFAULT                                      0x7fff7fff
3358 #define regPA_SC_SCREEN_EXTENT_MAX_1_DEFAULT                                      0x80008000
3359 #define regPA_SC_P3D_TRAP_SCREEN_HV_EN_DEFAULT                                    0x00000000
3360 #define regPA_SC_P3D_TRAP_SCREEN_H_DEFAULT                                        0x00000000
3361 #define regPA_SC_P3D_TRAP_SCREEN_V_DEFAULT                                        0x00000000
3362 #define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_DEFAULT                               0x00000000
3363 #define regPA_SC_P3D_TRAP_SCREEN_COUNT_DEFAULT                                    0x00000000
3364 #define regPA_SC_HP3D_TRAP_SCREEN_HV_EN_DEFAULT                                   0x00000000
3365 #define regPA_SC_HP3D_TRAP_SCREEN_H_DEFAULT                                       0x00000000
3366 #define regPA_SC_HP3D_TRAP_SCREEN_V_DEFAULT                                       0x00000000
3367 #define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_DEFAULT                              0x00000000
3368 #define regPA_SC_HP3D_TRAP_SCREEN_COUNT_DEFAULT                                   0x00000000
3369 #define regPA_SC_TRAP_SCREEN_HV_EN_DEFAULT                                        0x00000000
3370 #define regPA_SC_TRAP_SCREEN_H_DEFAULT                                            0x00000000
3371 #define regPA_SC_TRAP_SCREEN_V_DEFAULT                                            0x00000000
3372 #define regPA_SC_TRAP_SCREEN_OCCURRENCE_DEFAULT                                   0x00000000
3373 #define regPA_SC_TRAP_SCREEN_COUNT_DEFAULT                                        0x00000000
3374 #define regSQ_THREAD_TRACE_USERDATA_0_DEFAULT                                     0x00000000
3375 #define regSQ_THREAD_TRACE_USERDATA_1_DEFAULT                                     0x00000000
3376 #define regSQ_THREAD_TRACE_USERDATA_2_DEFAULT                                     0x00000000
3377 #define regSQ_THREAD_TRACE_USERDATA_3_DEFAULT                                     0x00000000
3378 #define regSQ_THREAD_TRACE_USERDATA_4_DEFAULT                                     0x00000000
3379 #define regSQ_THREAD_TRACE_USERDATA_5_DEFAULT                                     0x00000000
3380 #define regSQ_THREAD_TRACE_USERDATA_6_DEFAULT                                     0x00000000
3381 #define regSQ_THREAD_TRACE_USERDATA_7_DEFAULT                                     0x00000000
3382 #define regSQC_CACHES_DEFAULT                                                     0x00000000
3383 #define regTA_CS_BC_BASE_ADDR_DEFAULT                                             0x00000000
3384 #define regTA_CS_BC_BASE_ADDR_HI_DEFAULT                                          0x00000000
3385 #define regDB_OCCLUSION_COUNT0_LOW_DEFAULT                                        0x00000000
3386 #define regDB_OCCLUSION_COUNT0_HI_DEFAULT                                         0x00000000
3387 #define regDB_OCCLUSION_COUNT1_LOW_DEFAULT                                        0x00000000
3388 #define regDB_OCCLUSION_COUNT1_HI_DEFAULT                                         0x00000000
3389 #define regDB_OCCLUSION_COUNT2_LOW_DEFAULT                                        0x00000000
3390 #define regDB_OCCLUSION_COUNT2_HI_DEFAULT                                         0x00000000
3391 #define regDB_OCCLUSION_COUNT3_LOW_DEFAULT                                        0x00000000
3392 #define regDB_OCCLUSION_COUNT3_HI_DEFAULT                                         0x00000000
3393 #define regGDS_RD_ADDR_DEFAULT                                                    0x00000000
3394 #define regGDS_RD_DATA_DEFAULT                                                    0x00000000
3395 #define regGDS_RD_BURST_ADDR_DEFAULT                                              0x00000000
3396 #define regGDS_RD_BURST_COUNT_DEFAULT                                             0x00000000
3397 #define regGDS_RD_BURST_DATA_DEFAULT                                              0x00000000
3398 #define regGDS_WR_ADDR_DEFAULT                                                    0x00000000
3399 #define regGDS_WR_DATA_DEFAULT                                                    0x00000000
3400 #define regGDS_WR_BURST_ADDR_DEFAULT                                              0x00000000
3401 #define regGDS_WR_BURST_DATA_DEFAULT                                              0x00000000
3402 #define regGDS_WRITE_COMPLETE_DEFAULT                                             0x00000000
3403 #define regGDS_ATOM_CNTL_DEFAULT                                                  0x00000000
3404 #define regGDS_ATOM_COMPLETE_DEFAULT                                              0x00000001
3405 #define regGDS_ATOM_BASE_DEFAULT                                                  0x00000000
3406 #define regGDS_ATOM_SIZE_DEFAULT                                                  0x00000000
3407 #define regGDS_ATOM_OFFSET0_DEFAULT                                               0x00000000
3408 #define regGDS_ATOM_OFFSET1_DEFAULT                                               0x00000000
3409 #define regGDS_ATOM_DST_DEFAULT                                                   0x00000000
3410 #define regGDS_ATOM_OP_DEFAULT                                                    0x00000000
3411 #define regGDS_ATOM_SRC0_DEFAULT                                                  0x00000000
3412 #define regGDS_ATOM_SRC0_U_DEFAULT                                                0x00000000
3413 #define regGDS_ATOM_SRC1_DEFAULT                                                  0x00000000
3414 #define regGDS_ATOM_SRC1_U_DEFAULT                                                0x00000000
3415 #define regGDS_ATOM_READ0_DEFAULT                                                 0x00000000
3416 #define regGDS_ATOM_READ0_U_DEFAULT                                               0x00000000
3417 #define regGDS_ATOM_READ1_DEFAULT                                                 0x00000000
3418 #define regGDS_ATOM_READ1_U_DEFAULT                                               0x00000000
3419 #define regGDS_GWS_RESOURCE_CNTL_DEFAULT                                          0x00000000
3420 #define regGDS_GWS_RESOURCE_DEFAULT                                               0x00000000
3421 #define regGDS_GWS_RESOURCE_CNT_DEFAULT                                           0x00000000
3422 #define regGDS_OA_CNTL_DEFAULT                                                    0x00000000
3423 #define regGDS_OA_COUNTER_DEFAULT                                                 0x00000000
3424 #define regGDS_OA_ADDRESS_DEFAULT                                                 0x00000000
3425 #define regGDS_OA_INCDEC_DEFAULT                                                  0x00000000
3426 #define regGDS_OA_RING_SIZE_DEFAULT                                               0x00000000
3427 #define regGDS_STRMOUT_DWORDS_WRITTEN_0_DEFAULT                                   0x00000000
3428 #define regGDS_STRMOUT_DWORDS_WRITTEN_1_DEFAULT                                   0x00000000
3429 #define regGDS_STRMOUT_DWORDS_WRITTEN_2_DEFAULT                                   0x00000000
3430 #define regGDS_STRMOUT_DWORDS_WRITTEN_3_DEFAULT                                   0x00000000
3431 #define regGDS_GS_0_DEFAULT                                                       0x00000000
3432 #define regGDS_GS_1_DEFAULT                                                       0x00000000
3433 #define regGDS_GS_2_DEFAULT                                                       0x00000000
3434 #define regGDS_GS_3_DEFAULT                                                       0x00000000
3435 #define regGDS_STRMOUT_PRIMS_NEEDED_0_LO_DEFAULT                                  0x00000000
3436 #define regGDS_STRMOUT_PRIMS_NEEDED_0_HI_DEFAULT                                  0x00000000
3437 #define regGDS_STRMOUT_PRIMS_WRITTEN_0_LO_DEFAULT                                 0x00000000
3438 #define regGDS_STRMOUT_PRIMS_WRITTEN_0_HI_DEFAULT                                 0x00000000
3439 #define regGDS_STRMOUT_PRIMS_NEEDED_1_LO_DEFAULT                                  0x00000000
3440 #define regGDS_STRMOUT_PRIMS_NEEDED_1_HI_DEFAULT                                  0x00000000
3441 #define regGDS_STRMOUT_PRIMS_WRITTEN_1_LO_DEFAULT                                 0x00000000
3442 #define regGDS_STRMOUT_PRIMS_WRITTEN_1_HI_DEFAULT                                 0x00000000
3443 #define regGDS_STRMOUT_PRIMS_NEEDED_2_LO_DEFAULT                                  0x00000000
3444 #define regGDS_STRMOUT_PRIMS_NEEDED_2_HI_DEFAULT                                  0x00000000
3445 #define regGDS_STRMOUT_PRIMS_WRITTEN_2_LO_DEFAULT                                 0x00000000
3446 #define regGDS_STRMOUT_PRIMS_WRITTEN_2_HI_DEFAULT                                 0x00000000
3447 #define regGDS_STRMOUT_PRIMS_NEEDED_3_LO_DEFAULT                                  0x00000000
3448 #define regGDS_STRMOUT_PRIMS_NEEDED_3_HI_DEFAULT                                  0x00000000
3449 #define regGDS_STRMOUT_PRIMS_WRITTEN_3_LO_DEFAULT                                 0x00000000
3450 #define regGDS_STRMOUT_PRIMS_WRITTEN_3_HI_DEFAULT                                 0x00000000
3451 #define regSPI_CONFIG_CNTL_DEFAULT                                                0xc062c688
3452 #define regSPI_CONFIG_CNTL_1_DEFAULT                                              0x80070000
3453 #define regSPI_CONFIG_CNTL_2_DEFAULT                                              0x00010011
3454 #define regSPI_WAVE_LIMIT_CNTL_DEFAULT                                            0x00000000
3455 #define regSPI_GS_THROTTLE_CNTL1_DEFAULT                                          0x12355123
3456 #define regSPI_GS_THROTTLE_CNTL2_DEFAULT                                          0x0001544d
3457 #define regSPI_ATTRIBUTE_RING_BASE_DEFAULT                                        0x00000000
3458 #define regSPI_ATTRIBUTE_RING_SIZE_DEFAULT                                        0x00020000
3459 
3460 
3461 // addressBlock: gc_cprs64dec
3462 #define regCP_MES_PRGRM_CNTR_START_DEFAULT                                        0x00000800
3463 #define regCP_MES_INTR_ROUTINE_START_DEFAULT                                      0x00000000
3464 #define regCP_MES_MTVEC_LO_DEFAULT                                                0x00000000
3465 #define regCP_MES_INTR_ROUTINE_START_HI_DEFAULT                                   0x00000000
3466 #define regCP_MES_MTVEC_HI_DEFAULT                                                0x00000000
3467 #define regCP_MES_CNTL_DEFAULT                                                    0x40000000
3468 #define regCP_MES_PIPE_PRIORITY_CNTS_DEFAULT                                      0x08081020
3469 #define regCP_MES_PIPE0_PRIORITY_DEFAULT                                          0x00000002
3470 #define regCP_MES_PIPE1_PRIORITY_DEFAULT                                          0x00000002
3471 #define regCP_MES_PIPE2_PRIORITY_DEFAULT                                          0x00000002
3472 #define regCP_MES_PIPE3_PRIORITY_DEFAULT                                          0x00000002
3473 #define regCP_MES_HEADER_DUMP_DEFAULT                                             0xdef0def0
3474 #define regCP_MES_MIE_LO_DEFAULT                                                  0x00000000
3475 #define regCP_MES_MIE_HI_DEFAULT                                                  0x00000000
3476 #define regCP_MES_INTERRUPT_DEFAULT                                               0x00000000
3477 #define regCP_MES_SCRATCH_INDEX_DEFAULT                                           0x00000000
3478 #define regCP_MES_SCRATCH_DATA_DEFAULT                                            0x00000000
3479 #define regCP_MES_INSTR_PNTR_DEFAULT                                              0x00000000
3480 #define regCP_MES_MSCRATCH_HI_DEFAULT                                             0x00000000
3481 #define regCP_MES_MSCRATCH_LO_DEFAULT                                             0x00000000
3482 #define regCP_MES_MSTATUS_LO_DEFAULT                                              0x00000000
3483 #define regCP_MES_MSTATUS_HI_DEFAULT                                              0x00000000
3484 #define regCP_MES_MEPC_LO_DEFAULT                                                 0x00000000
3485 #define regCP_MES_MEPC_HI_DEFAULT                                                 0x00000000
3486 #define regCP_MES_MCAUSE_LO_DEFAULT                                               0x00000000
3487 #define regCP_MES_MCAUSE_HI_DEFAULT                                               0x00000000
3488 #define regCP_MES_MBADADDR_LO_DEFAULT                                             0x00000000
3489 #define regCP_MES_MBADADDR_HI_DEFAULT                                             0x00000000
3490 #define regCP_MES_MIP_LO_DEFAULT                                                  0x00000000
3491 #define regCP_MES_MIP_HI_DEFAULT                                                  0x00000000
3492 #define regCP_MES_IC_OP_CNTL_DEFAULT                                              0x00000000
3493 #define regCP_MES_MCYCLE_LO_DEFAULT                                               0x00000000
3494 #define regCP_MES_MCYCLE_HI_DEFAULT                                               0x00000000
3495 #define regCP_MES_MTIME_LO_DEFAULT                                                0x00000000
3496 #define regCP_MES_MTIME_HI_DEFAULT                                                0x00000000
3497 #define regCP_MES_MINSTRET_LO_DEFAULT                                             0x00000000
3498 #define regCP_MES_MINSTRET_HI_DEFAULT                                             0x00000000
3499 #define regCP_MES_MISA_LO_DEFAULT                                                 0x00000000
3500 #define regCP_MES_MISA_HI_DEFAULT                                                 0x00000000
3501 #define regCP_MES_MVENDORID_LO_DEFAULT                                            0x00000000
3502 #define regCP_MES_MVENDORID_HI_DEFAULT                                            0x00000000
3503 #define regCP_MES_MARCHID_LO_DEFAULT                                              0x00000000
3504 #define regCP_MES_MARCHID_HI_DEFAULT                                              0x00000000
3505 #define regCP_MES_MIMPID_LO_DEFAULT                                               0x00000000
3506 #define regCP_MES_MIMPID_HI_DEFAULT                                               0x00000000
3507 #define regCP_MES_MHARTID_LO_DEFAULT                                              0x00000000
3508 #define regCP_MES_MHARTID_HI_DEFAULT                                              0x00000000
3509 #define regCP_MES_DC_BASE_CNTL_DEFAULT                                            0x00000000
3510 #define regCP_MES_DC_OP_CNTL_DEFAULT                                              0x00000000
3511 #define regCP_MES_MTIMECMP_LO_DEFAULT                                             0x00000000
3512 #define regCP_MES_MTIMECMP_HI_DEFAULT                                             0x00000000
3513 #define regCP_MES_PROCESS_QUANTUM_PIPE0_DEFAULT                                   0x00000008
3514 #define regCP_MES_PROCESS_QUANTUM_PIPE1_DEFAULT                                   0x00000008
3515 #define regCP_MES_DOORBELL_CONTROL1_DEFAULT                                       0x00000000
3516 #define regCP_MES_DOORBELL_CONTROL2_DEFAULT                                       0x00000000
3517 #define regCP_MES_DOORBELL_CONTROL3_DEFAULT                                       0x00000000
3518 #define regCP_MES_DOORBELL_CONTROL4_DEFAULT                                       0x00000000
3519 #define regCP_MES_DOORBELL_CONTROL5_DEFAULT                                       0x00000000
3520 #define regCP_MES_DOORBELL_CONTROL6_DEFAULT                                       0x00000000
3521 #define regCP_MES_GP0_LO_DEFAULT                                                  0x00000000
3522 #define regCP_MES_GP0_HI_DEFAULT                                                  0x00000000
3523 #define regCP_MES_GP1_LO_DEFAULT                                                  0x00002001
3524 #define regCP_MES_GP1_HI_DEFAULT                                                  0x00000000
3525 #define regCP_MES_GP2_LO_DEFAULT                                                  0x00000000
3526 #define regCP_MES_GP2_HI_DEFAULT                                                  0x00000000
3527 #define regCP_MES_GP3_LO_DEFAULT                                                  0x00000000
3528 #define regCP_MES_GP3_HI_DEFAULT                                                  0x00000000
3529 #define regCP_MES_GP4_LO_DEFAULT                                                  0x00000000
3530 #define regCP_MES_GP4_HI_DEFAULT                                                  0x00000000
3531 #define regCP_MES_GP5_LO_DEFAULT                                                  0x00000000
3532 #define regCP_MES_GP5_HI_DEFAULT                                                  0x00000000
3533 #define regCP_MES_GP6_LO_DEFAULT                                                  0x00000000
3534 #define regCP_MES_GP6_HI_DEFAULT                                                  0x00000000
3535 #define regCP_MES_GP7_LO_DEFAULT                                                  0x00000000
3536 #define regCP_MES_GP7_HI_DEFAULT                                                  0x00000000
3537 #define regCP_MES_GP8_LO_DEFAULT                                                  0x00000000
3538 #define regCP_MES_GP8_HI_DEFAULT                                                  0x00000000
3539 #define regCP_MES_GP9_LO_DEFAULT                                                  0x40000000
3540 #define regCP_MES_GP9_HI_DEFAULT                                                  0x40000000
3541 #define regCP_MES_LOCAL_BASE0_LO_DEFAULT                                          0x00000000
3542 #define regCP_MES_LOCAL_BASE0_HI_DEFAULT                                          0x00000000
3543 #define regCP_MES_LOCAL_MASK0_LO_DEFAULT                                          0xffff0000
3544 #define regCP_MES_LOCAL_MASK0_HI_DEFAULT                                          0x0000ffff
3545 #define regCP_MES_LOCAL_APERTURE_DEFAULT                                          0x00000007
3546 #define regCP_MES_LOCAL_INSTR_BASE_LO_DEFAULT                                     0x00000000
3547 #define regCP_MES_LOCAL_INSTR_BASE_HI_DEFAULT                                     0x00000000
3548 #define regCP_MES_LOCAL_INSTR_MASK_LO_DEFAULT                                     0x000f0000
3549 #define regCP_MES_LOCAL_INSTR_MASK_HI_DEFAULT                                     0x00000000
3550 #define regCP_MES_LOCAL_INSTR_APERTURE_DEFAULT                                    0x00000007
3551 #define regCP_MES_LOCAL_SCRATCH_APERTURE_DEFAULT                                  0x00000003
3552 #define regCP_MES_LOCAL_SCRATCH_BASE_LO_DEFAULT                                   0x00000000
3553 #define regCP_MES_LOCAL_SCRATCH_BASE_HI_DEFAULT                                   0x00000000
3554 #define regCP_MES_PERFCOUNT_CNTL_DEFAULT                                          0x00000000
3555 #define regCP_MES_PENDING_INTERRUPT_DEFAULT                                       0x00000000
3556 #define regCP_MES_PRGRM_CNTR_START_HI_DEFAULT                                     0x00000000
3557 #define regCP_MES_INTERRUPT_DATA_16_DEFAULT                                       0x00000000
3558 #define regCP_MES_INTERRUPT_DATA_17_DEFAULT                                       0x00000000
3559 #define regCP_MES_INTERRUPT_DATA_18_DEFAULT                                       0x00000000
3560 #define regCP_MES_INTERRUPT_DATA_19_DEFAULT                                       0x00000000
3561 #define regCP_MES_INTERRUPT_DATA_20_DEFAULT                                       0x00000000
3562 #define regCP_MES_INTERRUPT_DATA_21_DEFAULT                                       0x00000000
3563 #define regCP_MES_INTERRUPT_DATA_22_DEFAULT                                       0x00000000
3564 #define regCP_MES_INTERRUPT_DATA_23_DEFAULT                                       0x00000000
3565 #define regCP_MES_INTERRUPT_DATA_24_DEFAULT                                       0x00000000
3566 #define regCP_MES_INTERRUPT_DATA_25_DEFAULT                                       0x00000000
3567 #define regCP_MES_INTERRUPT_DATA_26_DEFAULT                                       0x00000000
3568 #define regCP_MES_INTERRUPT_DATA_27_DEFAULT                                       0x00000000
3569 #define regCP_MES_INTERRUPT_DATA_28_DEFAULT                                       0x00000000
3570 #define regCP_MES_INTERRUPT_DATA_29_DEFAULT                                       0x00000000
3571 #define regCP_MES_INTERRUPT_DATA_30_DEFAULT                                       0x00000000
3572 #define regCP_MES_INTERRUPT_DATA_31_DEFAULT                                       0x00000000
3573 #define regCP_MES_DC_APERTURE0_BASE_DEFAULT                                       0x00000000
3574 #define regCP_MES_DC_APERTURE0_MASK_DEFAULT                                       0x00000000
3575 #define regCP_MES_DC_APERTURE0_CNTL_DEFAULT                                       0x00000010
3576 #define regCP_MES_DC_APERTURE1_BASE_DEFAULT                                       0x00000000
3577 #define regCP_MES_DC_APERTURE1_MASK_DEFAULT                                       0x00000000
3578 #define regCP_MES_DC_APERTURE1_CNTL_DEFAULT                                       0x00000011
3579 #define regCP_MES_DC_APERTURE2_BASE_DEFAULT                                       0x00000000
3580 #define regCP_MES_DC_APERTURE2_MASK_DEFAULT                                       0x00000000
3581 #define regCP_MES_DC_APERTURE2_CNTL_DEFAULT                                       0x00000012
3582 #define regCP_MES_DC_APERTURE3_BASE_DEFAULT                                       0x00000000
3583 #define regCP_MES_DC_APERTURE3_MASK_DEFAULT                                       0x00000000
3584 #define regCP_MES_DC_APERTURE3_CNTL_DEFAULT                                       0x00000013
3585 #define regCP_MES_DC_APERTURE4_BASE_DEFAULT                                       0x00000000
3586 #define regCP_MES_DC_APERTURE4_MASK_DEFAULT                                       0x00000000
3587 #define regCP_MES_DC_APERTURE4_CNTL_DEFAULT                                       0x00000014
3588 #define regCP_MES_DC_APERTURE5_BASE_DEFAULT                                       0x00000000
3589 #define regCP_MES_DC_APERTURE5_MASK_DEFAULT                                       0x00000000
3590 #define regCP_MES_DC_APERTURE5_CNTL_DEFAULT                                       0x00000015
3591 #define regCP_MES_DC_APERTURE6_BASE_DEFAULT                                       0x00000000
3592 #define regCP_MES_DC_APERTURE6_MASK_DEFAULT                                       0x00000000
3593 #define regCP_MES_DC_APERTURE6_CNTL_DEFAULT                                       0x00000016
3594 #define regCP_MES_DC_APERTURE7_BASE_DEFAULT                                       0x00000000
3595 #define regCP_MES_DC_APERTURE7_MASK_DEFAULT                                       0x00000000
3596 #define regCP_MES_DC_APERTURE7_CNTL_DEFAULT                                       0x00000017
3597 #define regCP_MES_DC_APERTURE8_BASE_DEFAULT                                       0x00000000
3598 #define regCP_MES_DC_APERTURE8_MASK_DEFAULT                                       0x00000000
3599 #define regCP_MES_DC_APERTURE8_CNTL_DEFAULT                                       0x00000018
3600 #define regCP_MES_DC_APERTURE9_BASE_DEFAULT                                       0x00000000
3601 #define regCP_MES_DC_APERTURE9_MASK_DEFAULT                                       0x00000000
3602 #define regCP_MES_DC_APERTURE9_CNTL_DEFAULT                                       0x00000019
3603 #define regCP_MES_DC_APERTURE10_BASE_DEFAULT                                      0x00000000
3604 #define regCP_MES_DC_APERTURE10_MASK_DEFAULT                                      0x00000000
3605 #define regCP_MES_DC_APERTURE10_CNTL_DEFAULT                                      0x0000001a
3606 #define regCP_MES_DC_APERTURE11_BASE_DEFAULT                                      0x00000000
3607 #define regCP_MES_DC_APERTURE11_MASK_DEFAULT                                      0x00000000
3608 #define regCP_MES_DC_APERTURE11_CNTL_DEFAULT                                      0x0000001b
3609 #define regCP_MES_DC_APERTURE12_BASE_DEFAULT                                      0x00000000
3610 #define regCP_MES_DC_APERTURE12_MASK_DEFAULT                                      0x00000000
3611 #define regCP_MES_DC_APERTURE12_CNTL_DEFAULT                                      0x0000001c
3612 #define regCP_MES_DC_APERTURE13_BASE_DEFAULT                                      0x00000000
3613 #define regCP_MES_DC_APERTURE13_MASK_DEFAULT                                      0x00000000
3614 #define regCP_MES_DC_APERTURE13_CNTL_DEFAULT                                      0x0000001d
3615 #define regCP_MES_DC_APERTURE14_BASE_DEFAULT                                      0x00000000
3616 #define regCP_MES_DC_APERTURE14_MASK_DEFAULT                                      0x00000000
3617 #define regCP_MES_DC_APERTURE14_CNTL_DEFAULT                                      0x0000001e
3618 #define regCP_MES_DC_APERTURE15_BASE_DEFAULT                                      0x00000000
3619 #define regCP_MES_DC_APERTURE15_MASK_DEFAULT                                      0x00000000
3620 #define regCP_MES_DC_APERTURE15_CNTL_DEFAULT                                      0x0000001f
3621 #define regCP_MEC_RS64_PRGRM_CNTR_START_DEFAULT                                   0x00000800
3622 #define regCP_MEC_MTVEC_LO_DEFAULT                                                0x00000000
3623 #define regCP_MEC_MTVEC_HI_DEFAULT                                                0x00000000
3624 #define regCP_MEC_ISA_CNTL_DEFAULT                                                0x00000000
3625 #define regCP_MEC_RS64_CNTL_DEFAULT                                               0x40000000
3626 #define regCP_MEC_MIE_LO_DEFAULT                                                  0x00000000
3627 #define regCP_MEC_MIE_HI_DEFAULT                                                  0x00000000
3628 #define regCP_MEC_RS64_INTERRUPT_DEFAULT                                          0x00000000
3629 #define regCP_MEC_RS64_INSTR_PNTR_DEFAULT                                         0x00000000
3630 #define regCP_MEC_MIP_LO_DEFAULT                                                  0x00000000
3631 #define regCP_MEC_MIP_HI_DEFAULT                                                  0x00000000
3632 #define regCP_MEC_DC_BASE_CNTL_DEFAULT                                            0x00000000
3633 #define regCP_MEC_DC_OP_CNTL_DEFAULT                                              0x00000000
3634 #define regCP_MEC_MTIMECMP_LO_DEFAULT                                             0x00000000
3635 #define regCP_MEC_MTIMECMP_HI_DEFAULT                                             0x00000000
3636 #define regCP_MEC_GP0_LO_DEFAULT                                                  0x00000000
3637 #define regCP_MEC_GP0_HI_DEFAULT                                                  0x00000000
3638 #define regCP_MEC_GP1_LO_DEFAULT                                                  0x00002001
3639 #define regCP_MEC_GP1_HI_DEFAULT                                                  0x00000000
3640 #define regCP_MEC_GP2_LO_DEFAULT                                                  0x00000000
3641 #define regCP_MEC_GP2_HI_DEFAULT                                                  0x00000000
3642 #define regCP_MEC_GP3_LO_DEFAULT                                                  0x00000000
3643 #define regCP_MEC_GP3_HI_DEFAULT                                                  0x00000000
3644 #define regCP_MEC_GP4_LO_DEFAULT                                                  0x00000000
3645 #define regCP_MEC_GP4_HI_DEFAULT                                                  0x00000000
3646 #define regCP_MEC_GP5_LO_DEFAULT                                                  0x00000000
3647 #define regCP_MEC_GP5_HI_DEFAULT                                                  0x00000000
3648 #define regCP_MEC_GP6_LO_DEFAULT                                                  0x00000000
3649 #define regCP_MEC_GP6_HI_DEFAULT                                                  0x00000000
3650 #define regCP_MEC_GP7_LO_DEFAULT                                                  0x00000000
3651 #define regCP_MEC_GP7_HI_DEFAULT                                                  0x00000000
3652 #define regCP_MEC_GP8_LO_DEFAULT                                                  0x00000000
3653 #define regCP_MEC_GP8_HI_DEFAULT                                                  0x00000000
3654 #define regCP_MEC_GP9_LO_DEFAULT                                                  0x40000000
3655 #define regCP_MEC_GP9_HI_DEFAULT                                                  0x40000000
3656 #define regCP_MEC_LOCAL_BASE0_LO_DEFAULT                                          0x00000000
3657 #define regCP_MEC_LOCAL_BASE0_HI_DEFAULT                                          0x00000000
3658 #define regCP_MEC_LOCAL_MASK0_LO_DEFAULT                                          0xffff0000
3659 #define regCP_MEC_LOCAL_MASK0_HI_DEFAULT                                          0x0000ffff
3660 #define regCP_MEC_LOCAL_APERTURE_DEFAULT                                          0x00000007
3661 #define regCP_MEC_LOCAL_INSTR_BASE_LO_DEFAULT                                     0x00000000
3662 #define regCP_MEC_LOCAL_INSTR_BASE_HI_DEFAULT                                     0x00000000
3663 #define regCP_MEC_LOCAL_INSTR_MASK_LO_DEFAULT                                     0x000f0000
3664 #define regCP_MEC_LOCAL_INSTR_MASK_HI_DEFAULT                                     0x00000000
3665 #define regCP_MEC_LOCAL_INSTR_APERTURE_DEFAULT                                    0x00000007
3666 #define regCP_MEC_LOCAL_SCRATCH_APERTURE_DEFAULT                                  0x00000003
3667 #define regCP_MEC_LOCAL_SCRATCH_BASE_LO_DEFAULT                                   0x00000000
3668 #define regCP_MEC_LOCAL_SCRATCH_BASE_HI_DEFAULT                                   0x00000000
3669 #define regCP_MEC_RS64_PERFCOUNT_CNTL_DEFAULT                                     0x00000000
3670 #define regCP_MEC_RS64_PENDING_INTERRUPT_DEFAULT                                  0x00000000
3671 #define regCP_MEC_RS64_PRGRM_CNTR_START_HI_DEFAULT                                0x00000000
3672 #define regCP_MEC_RS64_INTERRUPT_DATA_16_DEFAULT                                  0x00000000
3673 #define regCP_MEC_RS64_INTERRUPT_DATA_17_DEFAULT                                  0x00000000
3674 #define regCP_MEC_RS64_INTERRUPT_DATA_18_DEFAULT                                  0x00000000
3675 #define regCP_MEC_RS64_INTERRUPT_DATA_19_DEFAULT                                  0x00000000
3676 #define regCP_MEC_RS64_INTERRUPT_DATA_20_DEFAULT                                  0x00000000
3677 #define regCP_MEC_RS64_INTERRUPT_DATA_21_DEFAULT                                  0x00000000
3678 #define regCP_MEC_RS64_INTERRUPT_DATA_22_DEFAULT                                  0x00000000
3679 #define regCP_MEC_RS64_INTERRUPT_DATA_23_DEFAULT                                  0x00000000
3680 #define regCP_MEC_RS64_INTERRUPT_DATA_24_DEFAULT                                  0x00000000
3681 #define regCP_MEC_RS64_INTERRUPT_DATA_25_DEFAULT                                  0x00000000
3682 #define regCP_MEC_RS64_INTERRUPT_DATA_26_DEFAULT                                  0x00000000
3683 #define regCP_MEC_RS64_INTERRUPT_DATA_27_DEFAULT                                  0x00000000
3684 #define regCP_MEC_RS64_INTERRUPT_DATA_28_DEFAULT                                  0x00000000
3685 #define regCP_MEC_RS64_INTERRUPT_DATA_29_DEFAULT                                  0x00000000
3686 #define regCP_MEC_RS64_INTERRUPT_DATA_30_DEFAULT                                  0x00000000
3687 #define regCP_MEC_RS64_INTERRUPT_DATA_31_DEFAULT                                  0x00000000
3688 #define regCP_MEC_DC_APERTURE0_BASE_DEFAULT                                       0x00000000
3689 #define regCP_MEC_DC_APERTURE0_MASK_DEFAULT                                       0x00000000
3690 #define regCP_MEC_DC_APERTURE0_CNTL_DEFAULT                                       0x00000000
3691 #define regCP_MEC_DC_APERTURE1_BASE_DEFAULT                                       0x00000000
3692 #define regCP_MEC_DC_APERTURE1_MASK_DEFAULT                                       0x00000000
3693 #define regCP_MEC_DC_APERTURE1_CNTL_DEFAULT                                       0x00000001
3694 #define regCP_MEC_DC_APERTURE2_BASE_DEFAULT                                       0x00000000
3695 #define regCP_MEC_DC_APERTURE2_MASK_DEFAULT                                       0x00000000
3696 #define regCP_MEC_DC_APERTURE2_CNTL_DEFAULT                                       0x00000002
3697 #define regCP_MEC_DC_APERTURE3_BASE_DEFAULT                                       0x00000000
3698 #define regCP_MEC_DC_APERTURE3_MASK_DEFAULT                                       0x00000000
3699 #define regCP_MEC_DC_APERTURE3_CNTL_DEFAULT                                       0x00000003
3700 #define regCP_MEC_DC_APERTURE4_BASE_DEFAULT                                       0x00000000
3701 #define regCP_MEC_DC_APERTURE4_MASK_DEFAULT                                       0x00000000
3702 #define regCP_MEC_DC_APERTURE4_CNTL_DEFAULT                                       0x00000004
3703 #define regCP_MEC_DC_APERTURE5_BASE_DEFAULT                                       0x00000000
3704 #define regCP_MEC_DC_APERTURE5_MASK_DEFAULT                                       0x00000000
3705 #define regCP_MEC_DC_APERTURE5_CNTL_DEFAULT                                       0x00000005
3706 #define regCP_MEC_DC_APERTURE6_BASE_DEFAULT                                       0x00000000
3707 #define regCP_MEC_DC_APERTURE6_MASK_DEFAULT                                       0x00000000
3708 #define regCP_MEC_DC_APERTURE6_CNTL_DEFAULT                                       0x00000006
3709 #define regCP_MEC_DC_APERTURE7_BASE_DEFAULT                                       0x00000000
3710 #define regCP_MEC_DC_APERTURE7_MASK_DEFAULT                                       0x00000000
3711 #define regCP_MEC_DC_APERTURE7_CNTL_DEFAULT                                       0x00000007
3712 #define regCP_MEC_DC_APERTURE8_BASE_DEFAULT                                       0x00000000
3713 #define regCP_MEC_DC_APERTURE8_MASK_DEFAULT                                       0x00000000
3714 #define regCP_MEC_DC_APERTURE8_CNTL_DEFAULT                                       0x00000008
3715 #define regCP_MEC_DC_APERTURE9_BASE_DEFAULT                                       0x00000000
3716 #define regCP_MEC_DC_APERTURE9_MASK_DEFAULT                                       0x00000000
3717 #define regCP_MEC_DC_APERTURE9_CNTL_DEFAULT                                       0x00000009
3718 #define regCP_MEC_DC_APERTURE10_BASE_DEFAULT                                      0x00000000
3719 #define regCP_MEC_DC_APERTURE10_MASK_DEFAULT                                      0x00000000
3720 #define regCP_MEC_DC_APERTURE10_CNTL_DEFAULT                                      0x0000000a
3721 #define regCP_MEC_DC_APERTURE11_BASE_DEFAULT                                      0x00000000
3722 #define regCP_MEC_DC_APERTURE11_MASK_DEFAULT                                      0x00000000
3723 #define regCP_MEC_DC_APERTURE11_CNTL_DEFAULT                                      0x0000000b
3724 #define regCP_MEC_DC_APERTURE12_BASE_DEFAULT                                      0x00000000
3725 #define regCP_MEC_DC_APERTURE12_MASK_DEFAULT                                      0x00000000
3726 #define regCP_MEC_DC_APERTURE12_CNTL_DEFAULT                                      0x0000000c
3727 #define regCP_MEC_DC_APERTURE13_BASE_DEFAULT                                      0x00000000
3728 #define regCP_MEC_DC_APERTURE13_MASK_DEFAULT                                      0x00000000
3729 #define regCP_MEC_DC_APERTURE13_CNTL_DEFAULT                                      0x0000000d
3730 #define regCP_MEC_DC_APERTURE14_BASE_DEFAULT                                      0x00000000
3731 #define regCP_MEC_DC_APERTURE14_MASK_DEFAULT                                      0x00000000
3732 #define regCP_MEC_DC_APERTURE14_CNTL_DEFAULT                                      0x0000000e
3733 #define regCP_MEC_DC_APERTURE15_BASE_DEFAULT                                      0x00000000
3734 #define regCP_MEC_DC_APERTURE15_MASK_DEFAULT                                      0x00000000
3735 #define regCP_MEC_DC_APERTURE15_CNTL_DEFAULT                                      0x0000000f
3736 #define regCP_CPC_IC_OP_CNTL_DEFAULT                                              0x00000000
3737 #define regCP_GFX_CNTL_DEFAULT                                                    0x00000000
3738 #define regCP_GFX_RS64_INTERRUPT0_DEFAULT                                         0x00000000
3739 #define regCP_GFX_RS64_INTR_EN0_DEFAULT                                           0x00000000
3740 #define regCP_GFX_RS64_INTR_EN1_DEFAULT                                           0x00000000
3741 #define regCP_GFX_RS64_DC_BASE_CNTL_DEFAULT                                       0x00000000
3742 #define regCP_GFX_RS64_DC_OP_CNTL_DEFAULT                                         0x00000000
3743 #define regCP_GFX_RS64_LOCAL_BASE0_LO_DEFAULT                                     0x00000000
3744 #define regCP_GFX_RS64_LOCAL_BASE0_HI_DEFAULT                                     0x00000000
3745 #define regCP_GFX_RS64_LOCAL_MASK0_LO_DEFAULT                                     0xffff0000
3746 #define regCP_GFX_RS64_LOCAL_MASK0_HI_DEFAULT                                     0x0000ffff
3747 #define regCP_GFX_RS64_LOCAL_APERTURE_DEFAULT                                     0x00000007
3748 #define regCP_GFX_RS64_LOCAL_INSTR_BASE_LO_DEFAULT                                0x00000000
3749 #define regCP_GFX_RS64_LOCAL_INSTR_BASE_HI_DEFAULT                                0x00000000
3750 #define regCP_GFX_RS64_LOCAL_INSTR_MASK_LO_DEFAULT                                0x000f0000
3751 #define regCP_GFX_RS64_LOCAL_INSTR_MASK_HI_DEFAULT                                0x00000000
3752 #define regCP_GFX_RS64_LOCAL_INSTR_APERTURE_DEFAULT                               0x00000007
3753 #define regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE_DEFAULT                             0x00000003
3754 #define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO_DEFAULT                              0x00000000
3755 #define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI_DEFAULT                              0x00000000
3756 #define regCP_GFX_RS64_PERFCOUNT_CNTL0_DEFAULT                                    0x00000000
3757 #define regCP_GFX_RS64_PERFCOUNT_CNTL1_DEFAULT                                    0x00000000
3758 #define regCP_GFX_RS64_MIP_LO0_DEFAULT                                            0x00000000
3759 #define regCP_GFX_RS64_MIP_LO1_DEFAULT                                            0x00000000
3760 #define regCP_GFX_RS64_MIP_HI0_DEFAULT                                            0x00000000
3761 #define regCP_GFX_RS64_MIP_HI1_DEFAULT                                            0x00000000
3762 #define regCP_GFX_RS64_MTIMECMP_LO0_DEFAULT                                       0x00000000
3763 #define regCP_GFX_RS64_MTIMECMP_LO1_DEFAULT                                       0x00000000
3764 #define regCP_GFX_RS64_MTIMECMP_HI0_DEFAULT                                       0x00000000
3765 #define regCP_GFX_RS64_MTIMECMP_HI1_DEFAULT                                       0x00000000
3766 #define regCP_GFX_RS64_GP0_LO0_DEFAULT                                            0x00000000
3767 #define regCP_GFX_RS64_GP0_LO1_DEFAULT                                            0x00000000
3768 #define regCP_GFX_RS64_GP0_HI0_DEFAULT                                            0x00000000
3769 #define regCP_GFX_RS64_GP0_HI1_DEFAULT                                            0x00000000
3770 #define regCP_GFX_RS64_GP1_LO0_DEFAULT                                            0x00002001
3771 #define regCP_GFX_RS64_GP1_LO1_DEFAULT                                            0x00002001
3772 #define regCP_GFX_RS64_GP1_HI0_DEFAULT                                            0x00000000
3773 #define regCP_GFX_RS64_GP1_HI1_DEFAULT                                            0x00000000
3774 #define regCP_GFX_RS64_GP2_LO0_DEFAULT                                            0x00000000
3775 #define regCP_GFX_RS64_GP2_LO1_DEFAULT                                            0x00000000
3776 #define regCP_GFX_RS64_GP2_HI0_DEFAULT                                            0x00000000
3777 #define regCP_GFX_RS64_GP2_HI1_DEFAULT                                            0x00000000
3778 #define regCP_GFX_RS64_GP3_LO0_DEFAULT                                            0x00000000
3779 #define regCP_GFX_RS64_GP3_LO1_DEFAULT                                            0x00000000
3780 #define regCP_GFX_RS64_GP3_HI0_DEFAULT                                            0x00000000
3781 #define regCP_GFX_RS64_GP3_HI1_DEFAULT                                            0x00000000
3782 #define regCP_GFX_RS64_GP4_LO0_DEFAULT                                            0x00000000
3783 #define regCP_GFX_RS64_GP4_LO1_DEFAULT                                            0x00000000
3784 #define regCP_GFX_RS64_GP4_HI0_DEFAULT                                            0x00000000
3785 #define regCP_GFX_RS64_GP4_HI1_DEFAULT                                            0x00000000
3786 #define regCP_GFX_RS64_GP5_LO0_DEFAULT                                            0x00000000
3787 #define regCP_GFX_RS64_GP5_LO1_DEFAULT                                            0x00000000
3788 #define regCP_GFX_RS64_GP5_HI0_DEFAULT                                            0x00000000
3789 #define regCP_GFX_RS64_GP5_HI1_DEFAULT                                            0x00000000
3790 #define regCP_GFX_RS64_GP6_LO_DEFAULT                                             0x00000000
3791 #define regCP_GFX_RS64_GP6_HI_DEFAULT                                             0x00000000
3792 #define regCP_GFX_RS64_GP7_LO_DEFAULT                                             0x00000000
3793 #define regCP_GFX_RS64_GP7_HI_DEFAULT                                             0x00000000
3794 #define regCP_GFX_RS64_GP8_LO_DEFAULT                                             0x00000000
3795 #define regCP_GFX_RS64_GP8_HI_DEFAULT                                             0x00000000
3796 #define regCP_GFX_RS64_GP9_LO_DEFAULT                                             0x40000000
3797 #define regCP_GFX_RS64_GP9_HI_DEFAULT                                             0x40000000
3798 #define regCP_GFX_RS64_INSTR_PNTR0_DEFAULT                                        0x00000000
3799 #define regCP_GFX_RS64_INSTR_PNTR1_DEFAULT                                        0x00000000
3800 #define regCP_GFX_RS64_PENDING_INTERRUPT0_DEFAULT                                 0x00000000
3801 #define regCP_GFX_RS64_PENDING_INTERRUPT1_DEFAULT                                 0x00000000
3802 #define regCP_GFX_RS64_DC_APERTURE0_BASE0_DEFAULT                                 0x00000000
3803 #define regCP_GFX_RS64_DC_APERTURE0_MASK0_DEFAULT                                 0x00000000
3804 #define regCP_GFX_RS64_DC_APERTURE0_CNTL0_DEFAULT                                 0x00000010
3805 #define regCP_GFX_RS64_DC_APERTURE1_BASE0_DEFAULT                                 0x00000000
3806 #define regCP_GFX_RS64_DC_APERTURE1_MASK0_DEFAULT                                 0x00000000
3807 #define regCP_GFX_RS64_DC_APERTURE1_CNTL0_DEFAULT                                 0x00000011
3808 #define regCP_GFX_RS64_DC_APERTURE2_BASE0_DEFAULT                                 0x00000000
3809 #define regCP_GFX_RS64_DC_APERTURE2_MASK0_DEFAULT                                 0x00000000
3810 #define regCP_GFX_RS64_DC_APERTURE2_CNTL0_DEFAULT                                 0x00000012
3811 #define regCP_GFX_RS64_DC_APERTURE3_BASE0_DEFAULT                                 0x00000000
3812 #define regCP_GFX_RS64_DC_APERTURE3_MASK0_DEFAULT                                 0x00000000
3813 #define regCP_GFX_RS64_DC_APERTURE3_CNTL0_DEFAULT                                 0x00000013
3814 #define regCP_GFX_RS64_DC_APERTURE4_BASE0_DEFAULT                                 0x00000000
3815 #define regCP_GFX_RS64_DC_APERTURE4_MASK0_DEFAULT                                 0x00000000
3816 #define regCP_GFX_RS64_DC_APERTURE4_CNTL0_DEFAULT                                 0x00000014
3817 #define regCP_GFX_RS64_DC_APERTURE5_BASE0_DEFAULT                                 0x00000000
3818 #define regCP_GFX_RS64_DC_APERTURE5_MASK0_DEFAULT                                 0x00000000
3819 #define regCP_GFX_RS64_DC_APERTURE5_CNTL0_DEFAULT                                 0x00000015
3820 #define regCP_GFX_RS64_DC_APERTURE6_BASE0_DEFAULT                                 0x00000000
3821 #define regCP_GFX_RS64_DC_APERTURE6_MASK0_DEFAULT                                 0x00000000
3822 #define regCP_GFX_RS64_DC_APERTURE6_CNTL0_DEFAULT                                 0x00000016
3823 #define regCP_GFX_RS64_DC_APERTURE7_BASE0_DEFAULT                                 0x00000000
3824 #define regCP_GFX_RS64_DC_APERTURE7_MASK0_DEFAULT                                 0x00000000
3825 #define regCP_GFX_RS64_DC_APERTURE7_CNTL0_DEFAULT                                 0x00000017
3826 #define regCP_GFX_RS64_DC_APERTURE8_BASE0_DEFAULT                                 0x00000000
3827 #define regCP_GFX_RS64_DC_APERTURE8_MASK0_DEFAULT                                 0x00000000
3828 #define regCP_GFX_RS64_DC_APERTURE8_CNTL0_DEFAULT                                 0x00000018
3829 #define regCP_GFX_RS64_DC_APERTURE9_BASE0_DEFAULT                                 0x00000000
3830 #define regCP_GFX_RS64_DC_APERTURE9_MASK0_DEFAULT                                 0x00000000
3831 #define regCP_GFX_RS64_DC_APERTURE9_CNTL0_DEFAULT                                 0x00000019
3832 #define regCP_GFX_RS64_DC_APERTURE10_BASE0_DEFAULT                                0x00000000
3833 #define regCP_GFX_RS64_DC_APERTURE10_MASK0_DEFAULT                                0x00000000
3834 #define regCP_GFX_RS64_DC_APERTURE10_CNTL0_DEFAULT                                0x0000001a
3835 #define regCP_GFX_RS64_DC_APERTURE11_BASE0_DEFAULT                                0x00000000
3836 #define regCP_GFX_RS64_DC_APERTURE11_MASK0_DEFAULT                                0x00000000
3837 #define regCP_GFX_RS64_DC_APERTURE11_CNTL0_DEFAULT                                0x0000001b
3838 #define regCP_GFX_RS64_DC_APERTURE12_BASE0_DEFAULT                                0x00000000
3839 #define regCP_GFX_RS64_DC_APERTURE12_MASK0_DEFAULT                                0x00000000
3840 #define regCP_GFX_RS64_DC_APERTURE12_CNTL0_DEFAULT                                0x0000001c
3841 #define regCP_GFX_RS64_DC_APERTURE13_BASE0_DEFAULT                                0x00000000
3842 #define regCP_GFX_RS64_DC_APERTURE13_MASK0_DEFAULT                                0x00000000
3843 #define regCP_GFX_RS64_DC_APERTURE13_CNTL0_DEFAULT                                0x0000001d
3844 #define regCP_GFX_RS64_DC_APERTURE14_BASE0_DEFAULT                                0x00000000
3845 #define regCP_GFX_RS64_DC_APERTURE14_MASK0_DEFAULT                                0x00000000
3846 #define regCP_GFX_RS64_DC_APERTURE14_CNTL0_DEFAULT                                0x0000001e
3847 #define regCP_GFX_RS64_DC_APERTURE15_BASE0_DEFAULT                                0x00000000
3848 #define regCP_GFX_RS64_DC_APERTURE15_MASK0_DEFAULT                                0x00000000
3849 #define regCP_GFX_RS64_DC_APERTURE15_CNTL0_DEFAULT                                0x0000001f
3850 #define regCP_GFX_RS64_DC_APERTURE0_BASE1_DEFAULT                                 0x00000000
3851 #define regCP_GFX_RS64_DC_APERTURE0_MASK1_DEFAULT                                 0x00000000
3852 #define regCP_GFX_RS64_DC_APERTURE0_CNTL1_DEFAULT                                 0x00000010
3853 #define regCP_GFX_RS64_DC_APERTURE1_BASE1_DEFAULT                                 0x00000000
3854 #define regCP_GFX_RS64_DC_APERTURE1_MASK1_DEFAULT                                 0x00000000
3855 #define regCP_GFX_RS64_DC_APERTURE1_CNTL1_DEFAULT                                 0x00000011
3856 #define regCP_GFX_RS64_DC_APERTURE2_BASE1_DEFAULT                                 0x00000000
3857 #define regCP_GFX_RS64_DC_APERTURE2_MASK1_DEFAULT                                 0x00000000
3858 #define regCP_GFX_RS64_DC_APERTURE2_CNTL1_DEFAULT                                 0x00000012
3859 #define regCP_GFX_RS64_DC_APERTURE3_BASE1_DEFAULT                                 0x00000000
3860 #define regCP_GFX_RS64_DC_APERTURE3_MASK1_DEFAULT                                 0x00000000
3861 #define regCP_GFX_RS64_DC_APERTURE3_CNTL1_DEFAULT                                 0x00000013
3862 #define regCP_GFX_RS64_DC_APERTURE4_BASE1_DEFAULT                                 0x00000000
3863 #define regCP_GFX_RS64_DC_APERTURE4_MASK1_DEFAULT                                 0x00000000
3864 #define regCP_GFX_RS64_DC_APERTURE4_CNTL1_DEFAULT                                 0x00000014
3865 #define regCP_GFX_RS64_DC_APERTURE5_BASE1_DEFAULT                                 0x00000000
3866 #define regCP_GFX_RS64_DC_APERTURE5_MASK1_DEFAULT                                 0x00000000
3867 #define regCP_GFX_RS64_DC_APERTURE5_CNTL1_DEFAULT                                 0x00000015
3868 #define regCP_GFX_RS64_DC_APERTURE6_BASE1_DEFAULT                                 0x00000000
3869 #define regCP_GFX_RS64_DC_APERTURE6_MASK1_DEFAULT                                 0x00000000
3870 #define regCP_GFX_RS64_DC_APERTURE6_CNTL1_DEFAULT                                 0x00000016
3871 #define regCP_GFX_RS64_DC_APERTURE7_BASE1_DEFAULT                                 0x00000000
3872 #define regCP_GFX_RS64_DC_APERTURE7_MASK1_DEFAULT                                 0x00000000
3873 #define regCP_GFX_RS64_DC_APERTURE7_CNTL1_DEFAULT                                 0x00000017
3874 #define regCP_GFX_RS64_DC_APERTURE8_BASE1_DEFAULT                                 0x00000000
3875 #define regCP_GFX_RS64_DC_APERTURE8_MASK1_DEFAULT                                 0x00000000
3876 #define regCP_GFX_RS64_DC_APERTURE8_CNTL1_DEFAULT                                 0x00000018
3877 #define regCP_GFX_RS64_DC_APERTURE9_BASE1_DEFAULT                                 0x00000000
3878 #define regCP_GFX_RS64_DC_APERTURE9_MASK1_DEFAULT                                 0x00000000
3879 #define regCP_GFX_RS64_DC_APERTURE9_CNTL1_DEFAULT                                 0x00000019
3880 #define regCP_GFX_RS64_DC_APERTURE10_BASE1_DEFAULT                                0x00000000
3881 #define regCP_GFX_RS64_DC_APERTURE10_MASK1_DEFAULT                                0x00000000
3882 #define regCP_GFX_RS64_DC_APERTURE10_CNTL1_DEFAULT                                0x0000001a
3883 #define regCP_GFX_RS64_DC_APERTURE11_BASE1_DEFAULT                                0x00000000
3884 #define regCP_GFX_RS64_DC_APERTURE11_MASK1_DEFAULT                                0x00000000
3885 #define regCP_GFX_RS64_DC_APERTURE11_CNTL1_DEFAULT                                0x0000001b
3886 #define regCP_GFX_RS64_DC_APERTURE12_BASE1_DEFAULT                                0x00000000
3887 #define regCP_GFX_RS64_DC_APERTURE12_MASK1_DEFAULT                                0x00000000
3888 #define regCP_GFX_RS64_DC_APERTURE12_CNTL1_DEFAULT                                0x0000001c
3889 #define regCP_GFX_RS64_DC_APERTURE13_BASE1_DEFAULT                                0x00000000
3890 #define regCP_GFX_RS64_DC_APERTURE13_MASK1_DEFAULT                                0x00000000
3891 #define regCP_GFX_RS64_DC_APERTURE13_CNTL1_DEFAULT                                0x0000001d
3892 #define regCP_GFX_RS64_DC_APERTURE14_BASE1_DEFAULT                                0x00000000
3893 #define regCP_GFX_RS64_DC_APERTURE14_MASK1_DEFAULT                                0x00000000
3894 #define regCP_GFX_RS64_DC_APERTURE14_CNTL1_DEFAULT                                0x0000001e
3895 #define regCP_GFX_RS64_DC_APERTURE15_BASE1_DEFAULT                                0x00000000
3896 #define regCP_GFX_RS64_DC_APERTURE15_MASK1_DEFAULT                                0x00000000
3897 #define regCP_GFX_RS64_DC_APERTURE15_CNTL1_DEFAULT                                0x0000001f
3898 #define regCP_GFX_RS64_INTERRUPT1_DEFAULT                                         0x00000000
3899 
3900 
3901 // addressBlock: gc_gusdec
3902 #define regGUS_IO_RD_COMBINE_FLUSH_DEFAULT                                        0x00000000
3903 #define regGUS_IO_WR_COMBINE_FLUSH_DEFAULT                                        0x01000000
3904 #define regGUS_IO_RD_PRI_AGE_RATE_DEFAULT                                         0x00000000
3905 #define regGUS_IO_WR_PRI_AGE_RATE_DEFAULT                                         0x00000000
3906 #define regGUS_IO_RD_PRI_AGE_COEFF_DEFAULT                                        0x0003ffff
3907 #define regGUS_IO_WR_PRI_AGE_COEFF_DEFAULT                                        0x0003ffff
3908 #define regGUS_IO_RD_PRI_QUEUING_DEFAULT                                          0x0003ffff
3909 #define regGUS_IO_WR_PRI_QUEUING_DEFAULT                                          0x0003ffff
3910 #define regGUS_IO_RD_PRI_FIXED_DEFAULT                                            0x00000000
3911 #define regGUS_IO_WR_PRI_FIXED_DEFAULT                                            0x00000000
3912 #define regGUS_IO_RD_PRI_URGENCY_COEFF_DEFAULT                                    0x00000000
3913 #define regGUS_IO_WR_PRI_URGENCY_COEFF_DEFAULT                                    0x00000000
3914 #define regGUS_IO_RD_PRI_URGENCY_MODE_DEFAULT                                     0x00000000
3915 #define regGUS_IO_WR_PRI_URGENCY_MODE_DEFAULT                                     0x00000000
3916 #define regGUS_IO_RD_PRI_QUANT_PRI1_DEFAULT                                       0x1f1f1f1f
3917 #define regGUS_IO_RD_PRI_QUANT_PRI2_DEFAULT                                       0x3f3f3f3f
3918 #define regGUS_IO_RD_PRI_QUANT_PRI3_DEFAULT                                       0x7f7f7f7f
3919 #define regGUS_IO_RD_PRI_QUANT_PRI4_DEFAULT                                       0xffffffff
3920 #define regGUS_IO_WR_PRI_QUANT_PRI1_DEFAULT                                       0x1f1f1f1f
3921 #define regGUS_IO_WR_PRI_QUANT_PRI2_DEFAULT                                       0x3f3f3f3f
3922 #define regGUS_IO_WR_PRI_QUANT_PRI3_DEFAULT                                       0x7f7f7f7f
3923 #define regGUS_IO_WR_PRI_QUANT_PRI4_DEFAULT                                       0xffffffff
3924 #define regGUS_IO_RD_PRI_QUANT1_PRI1_DEFAULT                                      0x00001f1f
3925 #define regGUS_IO_RD_PRI_QUANT1_PRI2_DEFAULT                                      0x00003f3f
3926 #define regGUS_IO_RD_PRI_QUANT1_PRI3_DEFAULT                                      0x00007f7f
3927 #define regGUS_IO_RD_PRI_QUANT1_PRI4_DEFAULT                                      0x0000ffff
3928 #define regGUS_IO_WR_PRI_QUANT1_PRI1_DEFAULT                                      0x00001f1f
3929 #define regGUS_IO_WR_PRI_QUANT1_PRI2_DEFAULT                                      0x00003f3f
3930 #define regGUS_IO_WR_PRI_QUANT1_PRI3_DEFAULT                                      0x00007f7f
3931 #define regGUS_IO_WR_PRI_QUANT1_PRI4_DEFAULT                                      0x0000ffff
3932 #define regGUS_DRAM_COMBINE_FLUSH_DEFAULT                                         0x00000000
3933 #define regGUS_DRAM_COMBINE_RD_WR_EN_DEFAULT                                      0x00000fff
3934 #define regGUS_DRAM_PRI_AGE_RATE_DEFAULT                                          0x00001249
3935 #define regGUS_DRAM_PRI_AGE_COEFF_DEFAULT                                         0x0003ffff
3936 #define regGUS_DRAM_PRI_QUEUING_DEFAULT                                           0x0003edb6
3937 #define regGUS_DRAM_PRI_FIXED_DEFAULT                                             0x00000000
3938 #define regGUS_DRAM_PRI_URGENCY_COEFF_DEFAULT                                     0x00000000
3939 #define regGUS_DRAM_PRI_URGENCY_MODE_DEFAULT                                      0x00000000
3940 #define regGUS_DRAM_PRI_QUANT_PRI1_DEFAULT                                        0x0f0f0f0f
3941 #define regGUS_DRAM_PRI_QUANT_PRI2_DEFAULT                                        0x1f1f1f1f
3942 #define regGUS_DRAM_PRI_QUANT_PRI3_DEFAULT                                        0x3f3f3f3f
3943 #define regGUS_DRAM_PRI_QUANT_PRI4_DEFAULT                                        0x7f7f7f7f
3944 #define regGUS_DRAM_PRI_QUANT_PRI5_DEFAULT                                        0xffffffff
3945 #define regGUS_DRAM_PRI_QUANT1_PRI1_DEFAULT                                       0x00000f0f
3946 #define regGUS_DRAM_PRI_QUANT1_PRI2_DEFAULT                                       0x00001f1f
3947 #define regGUS_DRAM_PRI_QUANT1_PRI3_DEFAULT                                       0x00003f3f
3948 #define regGUS_DRAM_PRI_QUANT1_PRI4_DEFAULT                                       0x00007f7f
3949 #define regGUS_DRAM_PRI_QUANT1_PRI5_DEFAULT                                       0x0000ffff
3950 #define regGUS_IO_GROUP_BURST_DEFAULT                                             0x05040504
3951 #define regGUS_DRAM_GROUP_BURST_DEFAULT                                           0x00000504
3952 #define regGUS_SDP_ARB_FINAL_DEFAULT                                              0x00007fff
3953 #define regGUS_SDP_QOS_VC_PRIORITY_DEFAULT                                        0x0000a000
3954 #define regGUS_SDP_CREDITS_DEFAULT                                                0x000100ff
3955 #define regGUS_SDP_TAG_RESERVE0_DEFAULT                                           0x07070000
3956 #define regGUS_SDP_TAG_RESERVE1_DEFAULT                                           0x00000707
3957 #define regGUS_SDP_VCC_RESERVE0_DEFAULT                                           0x02041000
3958 #define regGUS_SDP_VCC_RESERVE1_DEFAULT                                           0x00000002
3959 #define regGUS_SDP_VCD_RESERVE0_DEFAULT                                           0x02040000
3960 #define regGUS_SDP_VCD_RESERVE1_DEFAULT                                           0x00000002
3961 #define regGUS_SDP_REQ_CNTL_DEFAULT                                               0x0000001f
3962 #define regGUS_MISC_DEFAULT                                                       0x00003c07
3963 #define regGUS_LATENCY_SAMPLING_DEFAULT                                           0x00000000
3964 #define regGUS_ERR_STATUS_DEFAULT                                                 0x00000300
3965 #define regGUS_MISC2_DEFAULT                                                      0x0000103e
3966 #define regGUS_SDP_ENABLE_DEFAULT                                                 0x00000000
3967 #define regGUS_L1_CH0_CMD_IN_DEFAULT                                              0x00000000
3968 #define regGUS_L1_CH0_CMD_OUT_DEFAULT                                             0x00000000
3969 #define regGUS_L1_CH0_DATA_IN_DEFAULT                                             0x00000000
3970 #define regGUS_L1_CH0_DATA_OUT_DEFAULT                                            0x00000000
3971 #define regGUS_L1_CH0_DATA_U_IN_DEFAULT                                           0x00000000
3972 #define regGUS_L1_CH0_DATA_U_OUT_DEFAULT                                          0x00000000
3973 #define regGUS_L1_CH1_CMD_IN_DEFAULT                                              0x00000000
3974 #define regGUS_L1_CH1_CMD_OUT_DEFAULT                                             0x00000000
3975 #define regGUS_L1_CH1_DATA_IN_DEFAULT                                             0x00000000
3976 #define regGUS_L1_CH1_DATA_OUT_DEFAULT                                            0x00000000
3977 #define regGUS_L1_CH1_DATA_U_IN_DEFAULT                                           0x00000000
3978 #define regGUS_L1_CH1_DATA_U_OUT_DEFAULT                                          0x00000000
3979 #define regGUS_L1_SA0_CMD_IN_DEFAULT                                              0x00000000
3980 #define regGUS_L1_SA0_CMD_OUT_DEFAULT                                             0x00000000
3981 #define regGUS_L1_SA0_DATA_IN_DEFAULT                                             0x00000000
3982 #define regGUS_L1_SA0_DATA_OUT_DEFAULT                                            0x00000000
3983 #define regGUS_L1_SA0_DATA_U_IN_DEFAULT                                           0x00000000
3984 #define regGUS_L1_SA0_DATA_U_OUT_DEFAULT                                          0x00000000
3985 #define regGUS_L1_SA1_CMD_IN_DEFAULT                                              0x00000000
3986 #define regGUS_L1_SA1_CMD_OUT_DEFAULT                                             0x00000000
3987 #define regGUS_L1_SA1_DATA_IN_DEFAULT                                             0x00000000
3988 #define regGUS_L1_SA1_DATA_OUT_DEFAULT                                            0x00000000
3989 #define regGUS_L1_SA1_DATA_U_IN_DEFAULT                                           0x00000000
3990 #define regGUS_L1_SA1_DATA_U_OUT_DEFAULT                                          0x00000000
3991 #define regGUS_L1_SA2_CMD_IN_DEFAULT                                              0x00000000
3992 #define regGUS_L1_SA2_CMD_OUT_DEFAULT                                             0x00000000
3993 #define regGUS_L1_SA2_DATA_IN_DEFAULT                                             0x00000000
3994 #define regGUS_L1_SA2_DATA_OUT_DEFAULT                                            0x00000000
3995 #define regGUS_L1_SA2_DATA_U_IN_DEFAULT                                           0x00000000
3996 #define regGUS_L1_SA2_DATA_U_OUT_DEFAULT                                          0x00000000
3997 #define regGUS_L1_SA3_CMD_IN_DEFAULT                                              0x00000000
3998 #define regGUS_L1_SA3_CMD_OUT_DEFAULT                                             0x00000000
3999 #define regGUS_L1_SA3_DATA_IN_DEFAULT                                             0x00000000
4000 #define regGUS_L1_SA3_DATA_OUT_DEFAULT                                            0x00000000
4001 #define regGUS_L1_SA3_DATA_U_IN_DEFAULT                                           0x00000000
4002 #define regGUS_L1_SA3_DATA_U_OUT_DEFAULT                                          0x00000000
4003 #define regGUS_MISC3_DEFAULT                                                      0x00000000
4004 #define regGUS_WRRSP_FIFO_CNTL_DEFAULT                                            0x0000000a
4005 
4006 
4007 // addressBlock: gc_gl1dec
4008 #define regGL1_DRAM_BURST_MASK_DEFAULT                                            0x000000cf
4009 #define regGL1_ARB_STATUS_DEFAULT                                                 0x00000000
4010 #define regGL1I_GL1R_REP_FGCG_OVERRIDE_DEFAULT                                    0x00000000
4011 #define regGL1C_STATUS_DEFAULT                                                    0x80000000
4012 #define regGL1C_UTCL0_CNTL2_DEFAULT                                               0x00000010
4013 #define regGL1C_UTCL0_STATUS_DEFAULT                                              0x00000000
4014 #define regGL1C_UTCL0_RETRY_DEFAULT                                               0x00000040
4015 
4016 
4017 // addressBlock: gc_chdec
4018 #define regCH_ARB_CTRL_DEFAULT                                                    0x00001e02
4019 #define regCH_DRAM_BURST_MASK_DEFAULT                                             0x000000cf
4020 #define regCH_ARB_STATUS_DEFAULT                                                  0x00000000
4021 #define regCH_DRAM_BURST_CTRL_DEFAULT                                             0x000001f7
4022 #define regCHA_CHC_CREDITS_DEFAULT                                                0x00000000
4023 #define regCHA_CLIENT_FREE_DELAY_DEFAULT                                          0x00000000
4024 #define regCHI_CHR_REP_FGCG_OVERRIDE_DEFAULT                                      0x00000000
4025 #define regCH_VC5_ENABLE_DEFAULT                                                  0x00000000
4026 #define regCHC_CTRL_DEFAULT                                                       0x0000b16f
4027 #define regCHC_STATUS_DEFAULT                                                     0x00000000
4028 #define regCHCG_CTRL_DEFAULT                                                      0x001830ff
4029 #define regCHCG_STATUS_DEFAULT                                                    0x00000000
4030 
4031 
4032 // addressBlock: gc_gl2dec
4033 #define regGL2C_CTRL_DEFAULT                                                      0xf37fff7f
4034 #define regGL2C_CTRL2_DEFAULT                                                     0x0402002f
4035 #define regGL2C_ADDR_MATCH_MASK_DEFAULT                                           0xffffffff
4036 #define regGL2C_ADDR_MATCH_SIZE_DEFAULT                                           0x00000007
4037 #define regGL2C_WBINVL2_DEFAULT                                                   0x00000010
4038 #define regGL2C_SOFT_RESET_DEFAULT                                                0x00000000
4039 #define regGL2C_CM_CTRL0_DEFAULT                                                  0x42108421
4040 #define regGL2C_CM_CTRL1_DEFAULT                                                  0x190f1008
4041 #define regGL2C_CM_STALL_DEFAULT                                                  0x00000000
4042 #define regGL2C_CTRL3_DEFAULT                                                     0xc0d41988
4043 #define regGL2C_LB_CTR_CTRL_DEFAULT                                               0x00000000
4044 #define regGL2C_LB_DATA0_DEFAULT                                                  0x00000000
4045 #define regGL2C_LB_DATA1_DEFAULT                                                  0x00000000
4046 #define regGL2C_LB_DATA2_DEFAULT                                                  0x00000000
4047 #define regGL2C_LB_DATA3_DEFAULT                                                  0x00000000
4048 #define regGL2C_LB_CTR_SEL0_DEFAULT                                               0x00000000
4049 #define regGL2C_LB_CTR_SEL1_DEFAULT                                               0x00000000
4050 #define regGL2C_CTRL4_DEFAULT                                                     0x04000007
4051 #define regGL2C_DISCARD_STALL_CTRL_DEFAULT                                        0x00c800c8
4052 #define regGL2A_ADDR_MATCH_CTRL_DEFAULT                                           0x00000000
4053 #define regGL2A_ADDR_MATCH_MASK_DEFAULT                                           0xffffffff
4054 #define regGL2A_ADDR_MATCH_SIZE_DEFAULT                                           0x00000007
4055 #define regGL2A_PRIORITY_CTRL_DEFAULT                                             0x00000000
4056 #define regGL2A_RESP_THROTTLE_CTRL_DEFAULT                                        0x00000000
4057 
4058 
4059 // addressBlock: gc_gl1hdec
4060 #define regGL1H_ARB_CTRL_DEFAULT                                                  0x00000000
4061 #define regGL1H_GL1_CREDITS_DEFAULT                                               0x00000000
4062 #define regGL1H_BURST_MASK_DEFAULT                                                0x000000cf
4063 #define regGL1H_BURST_CTRL_DEFAULT                                                0x00000007
4064 #define regGL1H_ARB_STATUS_DEFAULT                                                0x00000000
4065 
4066 
4067 // addressBlock: gc_perfddec
4068 #define regCPG_PERFCOUNTER1_LO_DEFAULT                                            0x00000000
4069 #define regCPG_PERFCOUNTER1_HI_DEFAULT                                            0x00000000
4070 #define regCPG_PERFCOUNTER0_LO_DEFAULT                                            0x00000000
4071 #define regCPG_PERFCOUNTER0_HI_DEFAULT                                            0x00000000
4072 #define regCPC_PERFCOUNTER1_LO_DEFAULT                                            0x00000000
4073 #define regCPC_PERFCOUNTER1_HI_DEFAULT                                            0x00000000
4074 #define regCPC_PERFCOUNTER0_LO_DEFAULT                                            0x00000000
4075 #define regCPC_PERFCOUNTER0_HI_DEFAULT                                            0x00000000
4076 #define regCPF_PERFCOUNTER1_LO_DEFAULT                                            0x00000000
4077 #define regCPF_PERFCOUNTER1_HI_DEFAULT                                            0x00000000
4078 #define regCPF_PERFCOUNTER0_LO_DEFAULT                                            0x00000000
4079 #define regCPF_PERFCOUNTER0_HI_DEFAULT                                            0x00000000
4080 #define regCPF_LATENCY_STATS_DATA_DEFAULT                                         0x00000000
4081 #define regCPG_LATENCY_STATS_DATA_DEFAULT                                         0x00000000
4082 #define regCPC_LATENCY_STATS_DATA_DEFAULT                                         0x00000000
4083 #define regGRBM_PERFCOUNTER0_LO_DEFAULT                                           0x00000000
4084 #define regGRBM_PERFCOUNTER0_HI_DEFAULT                                           0x00000000
4085 #define regGRBM_PERFCOUNTER1_LO_DEFAULT                                           0x00000000
4086 #define regGRBM_PERFCOUNTER1_HI_DEFAULT                                           0x00000000
4087 #define regGRBM_SE0_PERFCOUNTER_LO_DEFAULT                                        0x00000000
4088 #define regGRBM_SE0_PERFCOUNTER_HI_DEFAULT                                        0x00000000
4089 #define regGRBM_SE1_PERFCOUNTER_LO_DEFAULT                                        0x00000000
4090 #define regGRBM_SE1_PERFCOUNTER_HI_DEFAULT                                        0x00000000
4091 #define regGRBM_SE2_PERFCOUNTER_LO_DEFAULT                                        0x00000000
4092 #define regGRBM_SE2_PERFCOUNTER_HI_DEFAULT                                        0x00000000
4093 #define regGRBM_SE3_PERFCOUNTER_LO_DEFAULT                                        0x00000000
4094 #define regGRBM_SE3_PERFCOUNTER_HI_DEFAULT                                        0x00000000
4095 #define regGRBM_SE4_PERFCOUNTER_LO_DEFAULT                                        0x00000000
4096 #define regGRBM_SE4_PERFCOUNTER_HI_DEFAULT                                        0x00000000
4097 #define regGRBM_SE5_PERFCOUNTER_LO_DEFAULT                                        0x00000000
4098 #define regGRBM_SE5_PERFCOUNTER_HI_DEFAULT                                        0x00000000
4099 #define regGRBM_SE6_PERFCOUNTER_LO_DEFAULT                                        0x00000000
4100 #define regGRBM_SE6_PERFCOUNTER_HI_DEFAULT                                        0x00000000
4101 #define regGE1_PERFCOUNTER0_LO_DEFAULT                                            0x00000000
4102 #define regGE1_PERFCOUNTER0_HI_DEFAULT                                            0x00000000
4103 #define regGE1_PERFCOUNTER1_LO_DEFAULT                                            0x00000000
4104 #define regGE1_PERFCOUNTER1_HI_DEFAULT                                            0x00000000
4105 #define regGE1_PERFCOUNTER2_LO_DEFAULT                                            0x00000000
4106 #define regGE1_PERFCOUNTER2_HI_DEFAULT                                            0x00000000
4107 #define regGE1_PERFCOUNTER3_LO_DEFAULT                                            0x00000000
4108 #define regGE1_PERFCOUNTER3_HI_DEFAULT                                            0x00000000
4109 #define regGE2_DIST_PERFCOUNTER0_LO_DEFAULT                                       0x00000000
4110 #define regGE2_DIST_PERFCOUNTER0_HI_DEFAULT                                       0x00000000
4111 #define regGE2_DIST_PERFCOUNTER1_LO_DEFAULT                                       0x00000000
4112 #define regGE2_DIST_PERFCOUNTER1_HI_DEFAULT                                       0x00000000
4113 #define regGE2_DIST_PERFCOUNTER2_LO_DEFAULT                                       0x00000000
4114 #define regGE2_DIST_PERFCOUNTER2_HI_DEFAULT                                       0x00000000
4115 #define regGE2_DIST_PERFCOUNTER3_LO_DEFAULT                                       0x00000000
4116 #define regGE2_DIST_PERFCOUNTER3_HI_DEFAULT                                       0x00000000
4117 #define regGE2_SE_PERFCOUNTER0_LO_DEFAULT                                         0x00000000
4118 #define regGE2_SE_PERFCOUNTER0_HI_DEFAULT                                         0x00000000
4119 #define regGE2_SE_PERFCOUNTER1_LO_DEFAULT                                         0x00000000
4120 #define regGE2_SE_PERFCOUNTER1_HI_DEFAULT                                         0x00000000
4121 #define regGE2_SE_PERFCOUNTER2_LO_DEFAULT                                         0x00000000
4122 #define regGE2_SE_PERFCOUNTER2_HI_DEFAULT                                         0x00000000
4123 #define regGE2_SE_PERFCOUNTER3_LO_DEFAULT                                         0x00000000
4124 #define regGE2_SE_PERFCOUNTER3_HI_DEFAULT                                         0x00000000
4125 #define regPA_SU_PERFCOUNTER0_LO_DEFAULT                                          0x00000000
4126 #define regPA_SU_PERFCOUNTER0_HI_DEFAULT                                          0x00000000
4127 #define regPA_SU_PERFCOUNTER1_LO_DEFAULT                                          0x00000000
4128 #define regPA_SU_PERFCOUNTER1_HI_DEFAULT                                          0x00000000
4129 #define regPA_SU_PERFCOUNTER2_LO_DEFAULT                                          0x00000000
4130 #define regPA_SU_PERFCOUNTER2_HI_DEFAULT                                          0x00000000
4131 #define regPA_SU_PERFCOUNTER3_LO_DEFAULT                                          0x00000000
4132 #define regPA_SU_PERFCOUNTER3_HI_DEFAULT                                          0x00000000
4133 #define regPA_SC_PERFCOUNTER0_LO_DEFAULT                                          0x00000000
4134 #define regPA_SC_PERFCOUNTER0_HI_DEFAULT                                          0x00000000
4135 #define regPA_SC_PERFCOUNTER1_LO_DEFAULT                                          0x00000000
4136 #define regPA_SC_PERFCOUNTER1_HI_DEFAULT                                          0x00000000
4137 #define regPA_SC_PERFCOUNTER2_LO_DEFAULT                                          0x00000000
4138 #define regPA_SC_PERFCOUNTER2_HI_DEFAULT                                          0x00000000
4139 #define regPA_SC_PERFCOUNTER3_LO_DEFAULT                                          0x00000000
4140 #define regPA_SC_PERFCOUNTER3_HI_DEFAULT                                          0x00000000
4141 #define regPA_SC_PERFCOUNTER4_LO_DEFAULT                                          0x00000000
4142 #define regPA_SC_PERFCOUNTER4_HI_DEFAULT                                          0x00000000
4143 #define regPA_SC_PERFCOUNTER5_LO_DEFAULT                                          0x00000000
4144 #define regPA_SC_PERFCOUNTER5_HI_DEFAULT                                          0x00000000
4145 #define regPA_SC_PERFCOUNTER6_LO_DEFAULT                                          0x00000000
4146 #define regPA_SC_PERFCOUNTER6_HI_DEFAULT                                          0x00000000
4147 #define regPA_SC_PERFCOUNTER7_LO_DEFAULT                                          0x00000000
4148 #define regPA_SC_PERFCOUNTER7_HI_DEFAULT                                          0x00000000
4149 #define regSPI_PERFCOUNTER0_HI_DEFAULT                                            0x00000000
4150 #define regSPI_PERFCOUNTER0_LO_DEFAULT                                            0x00000000
4151 #define regSPI_PERFCOUNTER1_HI_DEFAULT                                            0x00000000
4152 #define regSPI_PERFCOUNTER1_LO_DEFAULT                                            0x00000000
4153 #define regSPI_PERFCOUNTER2_HI_DEFAULT                                            0x00000000
4154 #define regSPI_PERFCOUNTER2_LO_DEFAULT                                            0x00000000
4155 #define regSPI_PERFCOUNTER3_HI_DEFAULT                                            0x00000000
4156 #define regSPI_PERFCOUNTER3_LO_DEFAULT                                            0x00000000
4157 #define regSPI_PERFCOUNTER4_HI_DEFAULT                                            0x00000000
4158 #define regSPI_PERFCOUNTER4_LO_DEFAULT                                            0x00000000
4159 #define regSPI_PERFCOUNTER5_HI_DEFAULT                                            0x00000000
4160 #define regSPI_PERFCOUNTER5_LO_DEFAULT                                            0x00000000
4161 #define regPC_PERFCOUNTER0_HI_DEFAULT                                             0x00000000
4162 #define regPC_PERFCOUNTER0_LO_DEFAULT                                             0x00000000
4163 #define regPC_PERFCOUNTER1_HI_DEFAULT                                             0x00000000
4164 #define regPC_PERFCOUNTER1_LO_DEFAULT                                             0x00000000
4165 #define regPC_PERFCOUNTER2_HI_DEFAULT                                             0x00000000
4166 #define regPC_PERFCOUNTER2_LO_DEFAULT                                             0x00000000
4167 #define regPC_PERFCOUNTER3_HI_DEFAULT                                             0x00000000
4168 #define regPC_PERFCOUNTER3_LO_DEFAULT                                             0x00000000
4169 #define regSQ_PERFCOUNTER0_LO_DEFAULT                                             0x00000000
4170 #define regSQ_PERFCOUNTER1_LO_DEFAULT                                             0x00000000
4171 #define regSQ_PERFCOUNTER2_LO_DEFAULT                                             0x00000000
4172 #define regSQ_PERFCOUNTER3_LO_DEFAULT                                             0x00000000
4173 #define regSQ_PERFCOUNTER4_LO_DEFAULT                                             0x00000000
4174 #define regSQ_PERFCOUNTER5_LO_DEFAULT                                             0x00000000
4175 #define regSQ_PERFCOUNTER6_LO_DEFAULT                                             0x00000000
4176 #define regSQ_PERFCOUNTER7_LO_DEFAULT                                             0x00000000
4177 #define regSQG_PERFCOUNTER0_LO_DEFAULT                                            0x00000000
4178 #define regSQG_PERFCOUNTER0_HI_DEFAULT                                            0x00000000
4179 #define regSQG_PERFCOUNTER1_LO_DEFAULT                                            0x00000000
4180 #define regSQG_PERFCOUNTER1_HI_DEFAULT                                            0x00000000
4181 #define regSQG_PERFCOUNTER2_LO_DEFAULT                                            0x00000000
4182 #define regSQG_PERFCOUNTER2_HI_DEFAULT                                            0x00000000
4183 #define regSQG_PERFCOUNTER3_LO_DEFAULT                                            0x00000000
4184 #define regSQG_PERFCOUNTER3_HI_DEFAULT                                            0x00000000
4185 #define regSQG_PERFCOUNTER4_LO_DEFAULT                                            0x00000000
4186 #define regSQG_PERFCOUNTER4_HI_DEFAULT                                            0x00000000
4187 #define regSQG_PERFCOUNTER5_LO_DEFAULT                                            0x00000000
4188 #define regSQG_PERFCOUNTER5_HI_DEFAULT                                            0x00000000
4189 #define regSQG_PERFCOUNTER6_LO_DEFAULT                                            0x00000000
4190 #define regSQG_PERFCOUNTER6_HI_DEFAULT                                            0x00000000
4191 #define regSQG_PERFCOUNTER7_LO_DEFAULT                                            0x00000000
4192 #define regSQG_PERFCOUNTER7_HI_DEFAULT                                            0x00000000
4193 #define regSX_PERFCOUNTER0_LO_DEFAULT                                             0x00000000
4194 #define regSX_PERFCOUNTER0_HI_DEFAULT                                             0x00000000
4195 #define regSX_PERFCOUNTER1_LO_DEFAULT                                             0x00000000
4196 #define regSX_PERFCOUNTER1_HI_DEFAULT                                             0x00000000
4197 #define regSX_PERFCOUNTER2_LO_DEFAULT                                             0x00000000
4198 #define regSX_PERFCOUNTER2_HI_DEFAULT                                             0x00000000
4199 #define regSX_PERFCOUNTER3_LO_DEFAULT                                             0x00000000
4200 #define regSX_PERFCOUNTER3_HI_DEFAULT                                             0x00000000
4201 #define regGCEA_PERFCOUNTER2_LO_DEFAULT                                           0x00000000
4202 #define regGCEA_PERFCOUNTER2_HI_DEFAULT                                           0x00000000
4203 #define regGCEA_PERFCOUNTER_LO_DEFAULT                                            0x00000000
4204 #define regGCEA_PERFCOUNTER_HI_DEFAULT                                            0x00000000
4205 #define regGDS_PERFCOUNTER0_LO_DEFAULT                                            0x00000000
4206 #define regGDS_PERFCOUNTER0_HI_DEFAULT                                            0x00000000
4207 #define regGDS_PERFCOUNTER1_LO_DEFAULT                                            0x00000000
4208 #define regGDS_PERFCOUNTER1_HI_DEFAULT                                            0x00000000
4209 #define regGDS_PERFCOUNTER2_LO_DEFAULT                                            0x00000000
4210 #define regGDS_PERFCOUNTER2_HI_DEFAULT                                            0x00000000
4211 #define regGDS_PERFCOUNTER3_LO_DEFAULT                                            0x00000000
4212 #define regGDS_PERFCOUNTER3_HI_DEFAULT                                            0x00000000
4213 #define regTA_PERFCOUNTER0_LO_DEFAULT                                             0x00000000
4214 #define regTA_PERFCOUNTER0_HI_DEFAULT                                             0x00000000
4215 #define regTA_PERFCOUNTER1_LO_DEFAULT                                             0x00000000
4216 #define regTA_PERFCOUNTER1_HI_DEFAULT                                             0x00000000
4217 #define regTD_PERFCOUNTER0_LO_DEFAULT                                             0x00000000
4218 #define regTD_PERFCOUNTER0_HI_DEFAULT                                             0x00000000
4219 #define regTD_PERFCOUNTER1_LO_DEFAULT                                             0x00000000
4220 #define regTD_PERFCOUNTER1_HI_DEFAULT                                             0x00000000
4221 #define regTCP_PERFCOUNTER0_LO_DEFAULT                                            0x00000000
4222 #define regTCP_PERFCOUNTER0_HI_DEFAULT                                            0x00000000
4223 #define regTCP_PERFCOUNTER1_LO_DEFAULT                                            0x00000000
4224 #define regTCP_PERFCOUNTER1_HI_DEFAULT                                            0x00000000
4225 #define regTCP_PERFCOUNTER2_LO_DEFAULT                                            0x00000000
4226 #define regTCP_PERFCOUNTER2_HI_DEFAULT                                            0x00000000
4227 #define regTCP_PERFCOUNTER3_LO_DEFAULT                                            0x00000000
4228 #define regTCP_PERFCOUNTER3_HI_DEFAULT                                            0x00000000
4229 #define regTCP_PERFCOUNTER_FILTER_DEFAULT                                         0x00000000
4230 #define regTCP_PERFCOUNTER_FILTER2_DEFAULT                                        0x00000000
4231 #define regTCP_PERFCOUNTER_FILTER_EN_DEFAULT                                      0x00000000
4232 #define regGL2C_PERFCOUNTER0_LO_DEFAULT                                           0x00000000
4233 #define regGL2C_PERFCOUNTER0_HI_DEFAULT                                           0x00000000
4234 #define regGL2C_PERFCOUNTER1_LO_DEFAULT                                           0x00000000
4235 #define regGL2C_PERFCOUNTER1_HI_DEFAULT                                           0x00000000
4236 #define regGL2C_PERFCOUNTER2_LO_DEFAULT                                           0x00000000
4237 #define regGL2C_PERFCOUNTER2_HI_DEFAULT                                           0x00000000
4238 #define regGL2C_PERFCOUNTER3_LO_DEFAULT                                           0x00000000
4239 #define regGL2C_PERFCOUNTER3_HI_DEFAULT                                           0x00000000
4240 #define regGL2A_PERFCOUNTER0_LO_DEFAULT                                           0x00000000
4241 #define regGL2A_PERFCOUNTER0_HI_DEFAULT                                           0x00000000
4242 #define regGL2A_PERFCOUNTER1_LO_DEFAULT                                           0x00000000
4243 #define regGL2A_PERFCOUNTER1_HI_DEFAULT                                           0x00000000
4244 #define regGL2A_PERFCOUNTER2_LO_DEFAULT                                           0x00000000
4245 #define regGL2A_PERFCOUNTER2_HI_DEFAULT                                           0x00000000
4246 #define regGL2A_PERFCOUNTER3_LO_DEFAULT                                           0x00000000
4247 #define regGL2A_PERFCOUNTER3_HI_DEFAULT                                           0x00000000
4248 #define regGL1C_PERFCOUNTER0_LO_DEFAULT                                           0x00000000
4249 #define regGL1C_PERFCOUNTER0_HI_DEFAULT                                           0x00000000
4250 #define regGL1C_PERFCOUNTER1_LO_DEFAULT                                           0x00000000
4251 #define regGL1C_PERFCOUNTER1_HI_DEFAULT                                           0x00000000
4252 #define regGL1C_PERFCOUNTER2_LO_DEFAULT                                           0x00000000
4253 #define regGL1C_PERFCOUNTER2_HI_DEFAULT                                           0x00000000
4254 #define regGL1C_PERFCOUNTER3_LO_DEFAULT                                           0x00000000
4255 #define regGL1C_PERFCOUNTER3_HI_DEFAULT                                           0x00000000
4256 #define regCHC_PERFCOUNTER0_LO_DEFAULT                                            0x00000000
4257 #define regCHC_PERFCOUNTER0_HI_DEFAULT                                            0x00000000
4258 #define regCHC_PERFCOUNTER1_LO_DEFAULT                                            0x00000000
4259 #define regCHC_PERFCOUNTER1_HI_DEFAULT                                            0x00000000
4260 #define regCHC_PERFCOUNTER2_LO_DEFAULT                                            0x00000000
4261 #define regCHC_PERFCOUNTER2_HI_DEFAULT                                            0x00000000
4262 #define regCHC_PERFCOUNTER3_LO_DEFAULT                                            0x00000000
4263 #define regCHC_PERFCOUNTER3_HI_DEFAULT                                            0x00000000
4264 #define regCHCG_PERFCOUNTER0_LO_DEFAULT                                           0x00000000
4265 #define regCHCG_PERFCOUNTER0_HI_DEFAULT                                           0x00000000
4266 #define regCHCG_PERFCOUNTER1_LO_DEFAULT                                           0x00000000
4267 #define regCHCG_PERFCOUNTER1_HI_DEFAULT                                           0x00000000
4268 #define regCHCG_PERFCOUNTER2_LO_DEFAULT                                           0x00000000
4269 #define regCHCG_PERFCOUNTER2_HI_DEFAULT                                           0x00000000
4270 #define regCHCG_PERFCOUNTER3_LO_DEFAULT                                           0x00000000
4271 #define regCHCG_PERFCOUNTER3_HI_DEFAULT                                           0x00000000
4272 #define regCB_PERFCOUNTER0_LO_DEFAULT                                             0x00000000
4273 #define regCB_PERFCOUNTER0_HI_DEFAULT                                             0x00000000
4274 #define regCB_PERFCOUNTER1_LO_DEFAULT                                             0x00000000
4275 #define regCB_PERFCOUNTER1_HI_DEFAULT                                             0x00000000
4276 #define regCB_PERFCOUNTER2_LO_DEFAULT                                             0x00000000
4277 #define regCB_PERFCOUNTER2_HI_DEFAULT                                             0x00000000
4278 #define regCB_PERFCOUNTER3_LO_DEFAULT                                             0x00000000
4279 #define regCB_PERFCOUNTER3_HI_DEFAULT                                             0x00000000
4280 #define regDB_PERFCOUNTER0_LO_DEFAULT                                             0x00000000
4281 #define regDB_PERFCOUNTER0_HI_DEFAULT                                             0x00000000
4282 #define regDB_PERFCOUNTER1_LO_DEFAULT                                             0x00000000
4283 #define regDB_PERFCOUNTER1_HI_DEFAULT                                             0x00000000
4284 #define regDB_PERFCOUNTER2_LO_DEFAULT                                             0x00000000
4285 #define regDB_PERFCOUNTER2_HI_DEFAULT                                             0x00000000
4286 #define regDB_PERFCOUNTER3_LO_DEFAULT                                             0x00000000
4287 #define regDB_PERFCOUNTER3_HI_DEFAULT                                             0x00000000
4288 #define regRLC_PERFCOUNTER0_LO_DEFAULT                                            0x00000000
4289 #define regRLC_PERFCOUNTER0_HI_DEFAULT                                            0x00000000
4290 #define regRLC_PERFCOUNTER1_LO_DEFAULT                                            0x00000000
4291 #define regRLC_PERFCOUNTER1_HI_DEFAULT                                            0x00000000
4292 #define regRMI_PERFCOUNTER0_LO_DEFAULT                                            0x00000000
4293 #define regRMI_PERFCOUNTER0_HI_DEFAULT                                            0x00000000
4294 #define regRMI_PERFCOUNTER1_LO_DEFAULT                                            0x00000000
4295 #define regRMI_PERFCOUNTER1_HI_DEFAULT                                            0x00000000
4296 #define regRMI_PERFCOUNTER2_LO_DEFAULT                                            0x00000000
4297 #define regRMI_PERFCOUNTER2_HI_DEFAULT                                            0x00000000
4298 #define regRMI_PERFCOUNTER3_LO_DEFAULT                                            0x00000000
4299 #define regRMI_PERFCOUNTER3_HI_DEFAULT                                            0x00000000
4300 #define regGCR_PERFCOUNTER0_LO_DEFAULT                                            0x00000000
4301 #define regGCR_PERFCOUNTER0_HI_DEFAULT                                            0x00000000
4302 #define regGCR_PERFCOUNTER1_LO_DEFAULT                                            0x00000000
4303 #define regGCR_PERFCOUNTER1_HI_DEFAULT                                            0x00000000
4304 #define regPA_PH_PERFCOUNTER0_LO_DEFAULT                                          0x00000000
4305 #define regPA_PH_PERFCOUNTER0_HI_DEFAULT                                          0x00000000
4306 #define regPA_PH_PERFCOUNTER1_LO_DEFAULT                                          0x00000000
4307 #define regPA_PH_PERFCOUNTER1_HI_DEFAULT                                          0x00000000
4308 #define regPA_PH_PERFCOUNTER2_LO_DEFAULT                                          0x00000000
4309 #define regPA_PH_PERFCOUNTER2_HI_DEFAULT                                          0x00000000
4310 #define regPA_PH_PERFCOUNTER3_LO_DEFAULT                                          0x00000000
4311 #define regPA_PH_PERFCOUNTER3_HI_DEFAULT                                          0x00000000
4312 #define regPA_PH_PERFCOUNTER4_LO_DEFAULT                                          0x00000000
4313 #define regPA_PH_PERFCOUNTER4_HI_DEFAULT                                          0x00000000
4314 #define regPA_PH_PERFCOUNTER5_LO_DEFAULT                                          0x00000000
4315 #define regPA_PH_PERFCOUNTER5_HI_DEFAULT                                          0x00000000
4316 #define regPA_PH_PERFCOUNTER6_LO_DEFAULT                                          0x00000000
4317 #define regPA_PH_PERFCOUNTER6_HI_DEFAULT                                          0x00000000
4318 #define regPA_PH_PERFCOUNTER7_LO_DEFAULT                                          0x00000000
4319 #define regPA_PH_PERFCOUNTER7_HI_DEFAULT                                          0x00000000
4320 #define regUTCL1_PERFCOUNTER0_LO_DEFAULT                                          0x00000000
4321 #define regUTCL1_PERFCOUNTER0_HI_DEFAULT                                          0x00000000
4322 #define regUTCL1_PERFCOUNTER1_LO_DEFAULT                                          0x00000000
4323 #define regUTCL1_PERFCOUNTER1_HI_DEFAULT                                          0x00000000
4324 #define regUTCL1_PERFCOUNTER2_LO_DEFAULT                                          0x00000000
4325 #define regUTCL1_PERFCOUNTER2_HI_DEFAULT                                          0x00000000
4326 #define regUTCL1_PERFCOUNTER3_LO_DEFAULT                                          0x00000000
4327 #define regUTCL1_PERFCOUNTER3_HI_DEFAULT                                          0x00000000
4328 #define regGL1A_PERFCOUNTER0_LO_DEFAULT                                           0x00000000
4329 #define regGL1A_PERFCOUNTER0_HI_DEFAULT                                           0x00000000
4330 #define regGL1A_PERFCOUNTER1_LO_DEFAULT                                           0x00000000
4331 #define regGL1A_PERFCOUNTER1_HI_DEFAULT                                           0x00000000
4332 #define regGL1A_PERFCOUNTER2_LO_DEFAULT                                           0x00000000
4333 #define regGL1A_PERFCOUNTER2_HI_DEFAULT                                           0x00000000
4334 #define regGL1A_PERFCOUNTER3_LO_DEFAULT                                           0x00000000
4335 #define regGL1A_PERFCOUNTER3_HI_DEFAULT                                           0x00000000
4336 #define regGL1H_PERFCOUNTER0_LO_DEFAULT                                           0x00000000
4337 #define regGL1H_PERFCOUNTER0_HI_DEFAULT                                           0x00000000
4338 #define regGL1H_PERFCOUNTER1_LO_DEFAULT                                           0x00000000
4339 #define regGL1H_PERFCOUNTER1_HI_DEFAULT                                           0x00000000
4340 #define regGL1H_PERFCOUNTER2_LO_DEFAULT                                           0x00000000
4341 #define regGL1H_PERFCOUNTER2_HI_DEFAULT                                           0x00000000
4342 #define regGL1H_PERFCOUNTER3_LO_DEFAULT                                           0x00000000
4343 #define regGL1H_PERFCOUNTER3_HI_DEFAULT                                           0x00000000
4344 #define regCHA_PERFCOUNTER0_LO_DEFAULT                                            0x00000000
4345 #define regCHA_PERFCOUNTER0_HI_DEFAULT                                            0x00000000
4346 #define regCHA_PERFCOUNTER1_LO_DEFAULT                                            0x00000000
4347 #define regCHA_PERFCOUNTER1_HI_DEFAULT                                            0x00000000
4348 #define regCHA_PERFCOUNTER2_LO_DEFAULT                                            0x00000000
4349 #define regCHA_PERFCOUNTER2_HI_DEFAULT                                            0x00000000
4350 #define regCHA_PERFCOUNTER3_LO_DEFAULT                                            0x00000000
4351 #define regCHA_PERFCOUNTER3_HI_DEFAULT                                            0x00000000
4352 #define regGUS_PERFCOUNTER2_LO_DEFAULT                                            0x00000000
4353 #define regGUS_PERFCOUNTER2_HI_DEFAULT                                            0x00000000
4354 #define regGUS_PERFCOUNTER_LO_DEFAULT                                             0x00000000
4355 #define regGUS_PERFCOUNTER_HI_DEFAULT                                             0x00000000
4356 
4357 
4358 // addressBlock: gc_gcvml2perfddec
4359 #define regGCVML2_PERFCOUNTER2_0_LO_DEFAULT                                       0x00000000
4360 #define regGCVML2_PERFCOUNTER2_1_LO_DEFAULT                                       0x00000000
4361 #define regGCVML2_PERFCOUNTER2_0_HI_DEFAULT                                       0x00000000
4362 #define regGCVML2_PERFCOUNTER2_1_HI_DEFAULT                                       0x00000000
4363 
4364 
4365 // addressBlock: gc_gcvml2prdec
4366 #define regGCMC_VM_L2_PERFCOUNTER_LO_DEFAULT                                      0x00000000
4367 #define regGCMC_VM_L2_PERFCOUNTER_HI_DEFAULT                                      0x00000000
4368 #define regGCUTCL2_PERFCOUNTER_LO_DEFAULT                                         0x00000000
4369 #define regGCUTCL2_PERFCOUNTER_HI_DEFAULT                                         0x00000000
4370 
4371 
4372 // addressBlock: gc_sdma0_sdma0perfddec
4373 #define regSDMA0_PERFCNT_PERFCOUNTER_LO_DEFAULT                                   0x00000000
4374 #define regSDMA0_PERFCNT_PERFCOUNTER_HI_DEFAULT                                   0x00000000
4375 #define regSDMA0_PERFCOUNTER0_LO_DEFAULT                                          0x00000000
4376 #define regSDMA0_PERFCOUNTER0_HI_DEFAULT                                          0x00000000
4377 #define regSDMA0_PERFCOUNTER1_LO_DEFAULT                                          0x00000000
4378 #define regSDMA0_PERFCOUNTER1_HI_DEFAULT                                          0x00000000
4379 
4380 
4381 // addressBlock: gc_sdma0_sdma1perfddec
4382 #define regSDMA1_PERFCNT_PERFCOUNTER_LO_DEFAULT                                   0x00000000
4383 #define regSDMA1_PERFCNT_PERFCOUNTER_HI_DEFAULT                                   0x00000000
4384 #define regSDMA1_PERFCOUNTER0_LO_DEFAULT                                          0x00000000
4385 #define regSDMA1_PERFCOUNTER0_HI_DEFAULT                                          0x00000000
4386 #define regSDMA1_PERFCOUNTER1_LO_DEFAULT                                          0x00000000
4387 #define regSDMA1_PERFCOUNTER1_HI_DEFAULT                                          0x00000000
4388 
4389 
4390 // addressBlock: gc_perfsdec
4391 #define regCPG_PERFCOUNTER1_SELECT_DEFAULT                                        0x000003ff
4392 #define regCPG_PERFCOUNTER0_SELECT1_DEFAULT                                       0x000fffff
4393 #define regCPG_PERFCOUNTER0_SELECT_DEFAULT                                        0x000fffff
4394 #define regCPC_PERFCOUNTER1_SELECT_DEFAULT                                        0x000003ff
4395 #define regCPC_PERFCOUNTER0_SELECT1_DEFAULT                                       0x000fffff
4396 #define regCPF_PERFCOUNTER1_SELECT_DEFAULT                                        0x000003ff
4397 #define regCPF_PERFCOUNTER0_SELECT1_DEFAULT                                       0x000fffff
4398 #define regCPF_PERFCOUNTER0_SELECT_DEFAULT                                        0x000fffff
4399 #define regCP_PERFMON_CNTL_DEFAULT                                                0x00000000
4400 #define regCPC_PERFCOUNTER0_SELECT_DEFAULT                                        0x000fffff
4401 #define regCPF_TC_PERF_COUNTER_WINDOW_SELECT_DEFAULT                              0x00000000
4402 #define regCPG_TC_PERF_COUNTER_WINDOW_SELECT_DEFAULT                              0x00000000
4403 #define regCPF_LATENCY_STATS_SELECT_DEFAULT                                       0x00000000
4404 #define regCPG_LATENCY_STATS_SELECT_DEFAULT                                       0x00000000
4405 #define regCPC_LATENCY_STATS_SELECT_DEFAULT                                       0x00000000
4406 #define regCPC_TC_PERF_COUNTER_WINDOW_SELECT_DEFAULT                              0x00000000
4407 #define regCP_DRAW_OBJECT_DEFAULT                                                 0x00000000
4408 #define regCP_DRAW_OBJECT_COUNTER_DEFAULT                                         0x00000000
4409 #define regCP_DRAW_WINDOW_MASK_HI_DEFAULT                                         0x00000000
4410 #define regCP_DRAW_WINDOW_HI_DEFAULT                                              0x00000000
4411 #define regCP_DRAW_WINDOW_LO_DEFAULT                                              0x00000000
4412 #define regCP_DRAW_WINDOW_CNTL_DEFAULT                                            0x00000007
4413 #define regGRBM_PERFCOUNTER0_SELECT_DEFAULT                                       0x00000000
4414 #define regGRBM_PERFCOUNTER1_SELECT_DEFAULT                                       0x00000000
4415 #define regGRBM_SE0_PERFCOUNTER_SELECT_DEFAULT                                    0x00000000
4416 #define regGRBM_SE1_PERFCOUNTER_SELECT_DEFAULT                                    0x00000000
4417 #define regGRBM_SE2_PERFCOUNTER_SELECT_DEFAULT                                    0x00000000
4418 #define regGRBM_SE3_PERFCOUNTER_SELECT_DEFAULT                                    0x00000000
4419 #define regGRBM_SE4_PERFCOUNTER_SELECT_DEFAULT                                    0x00000000
4420 #define regGRBM_SE5_PERFCOUNTER_SELECT_DEFAULT                                    0x00000000
4421 #define regGRBM_SE6_PERFCOUNTER_SELECT_DEFAULT                                    0x00000000
4422 #define regGRBM_PERFCOUNTER0_SELECT_HI_DEFAULT                                    0x00000000
4423 #define regGRBM_PERFCOUNTER1_SELECT_HI_DEFAULT                                    0x00000000
4424 #define regGE1_PERFCOUNTER0_SELECT_DEFAULT                                        0x000fffff
4425 #define regGE1_PERFCOUNTER0_SELECT1_DEFAULT                                       0x000fffff
4426 #define regGE1_PERFCOUNTER1_SELECT_DEFAULT                                        0x000fffff
4427 #define regGE1_PERFCOUNTER1_SELECT1_DEFAULT                                       0x000fffff
4428 #define regGE1_PERFCOUNTER2_SELECT_DEFAULT                                        0x000fffff
4429 #define regGE1_PERFCOUNTER2_SELECT1_DEFAULT                                       0x000fffff
4430 #define regGE1_PERFCOUNTER3_SELECT_DEFAULT                                        0x000fffff
4431 #define regGE1_PERFCOUNTER3_SELECT1_DEFAULT                                       0x000fffff
4432 #define regGE2_DIST_PERFCOUNTER0_SELECT_DEFAULT                                   0x000fffff
4433 #define regGE2_DIST_PERFCOUNTER0_SELECT1_DEFAULT                                  0x000fffff
4434 #define regGE2_DIST_PERFCOUNTER1_SELECT_DEFAULT                                   0x000fffff
4435 #define regGE2_DIST_PERFCOUNTER1_SELECT1_DEFAULT                                  0x000fffff
4436 #define regGE2_DIST_PERFCOUNTER2_SELECT_DEFAULT                                   0x000fffff
4437 #define regGE2_DIST_PERFCOUNTER2_SELECT1_DEFAULT                                  0x000fffff
4438 #define regGE2_DIST_PERFCOUNTER3_SELECT_DEFAULT                                   0x000fffff
4439 #define regGE2_DIST_PERFCOUNTER3_SELECT1_DEFAULT                                  0x000fffff
4440 #define regGE2_SE_PERFCOUNTER0_SELECT_DEFAULT                                     0x000fffff
4441 #define regGE2_SE_PERFCOUNTER0_SELECT1_DEFAULT                                    0x000fffff
4442 #define regGE2_SE_PERFCOUNTER1_SELECT_DEFAULT                                     0x000fffff
4443 #define regGE2_SE_PERFCOUNTER1_SELECT1_DEFAULT                                    0x000fffff
4444 #define regGE2_SE_PERFCOUNTER2_SELECT_DEFAULT                                     0x000fffff
4445 #define regGE2_SE_PERFCOUNTER2_SELECT1_DEFAULT                                    0x000fffff
4446 #define regGE2_SE_PERFCOUNTER3_SELECT_DEFAULT                                     0x000fffff
4447 #define regGE2_SE_PERFCOUNTER3_SELECT1_DEFAULT                                    0x000fffff
4448 #define regPA_SU_PERFCOUNTER0_SELECT_DEFAULT                                      0x000fffff
4449 #define regPA_SU_PERFCOUNTER0_SELECT1_DEFAULT                                     0x000fffff
4450 #define regPA_SU_PERFCOUNTER1_SELECT_DEFAULT                                      0x000fffff
4451 #define regPA_SU_PERFCOUNTER1_SELECT1_DEFAULT                                     0x000fffff
4452 #define regPA_SU_PERFCOUNTER2_SELECT_DEFAULT                                      0x000fffff
4453 #define regPA_SU_PERFCOUNTER2_SELECT1_DEFAULT                                     0x000fffff
4454 #define regPA_SU_PERFCOUNTER3_SELECT_DEFAULT                                      0x000fffff
4455 #define regPA_SU_PERFCOUNTER3_SELECT1_DEFAULT                                     0x000fffff
4456 #define regPA_SC_PERFCOUNTER0_SELECT_DEFAULT                                      0x000fffff
4457 #define regPA_SC_PERFCOUNTER0_SELECT1_DEFAULT                                     0x000fffff
4458 #define regPA_SC_PERFCOUNTER1_SELECT_DEFAULT                                      0x000003ff
4459 #define regPA_SC_PERFCOUNTER2_SELECT_DEFAULT                                      0x000003ff
4460 #define regPA_SC_PERFCOUNTER3_SELECT_DEFAULT                                      0x000003ff
4461 #define regPA_SC_PERFCOUNTER4_SELECT_DEFAULT                                      0x000003ff
4462 #define regPA_SC_PERFCOUNTER5_SELECT_DEFAULT                                      0x000003ff
4463 #define regPA_SC_PERFCOUNTER6_SELECT_DEFAULT                                      0x000003ff
4464 #define regPA_SC_PERFCOUNTER7_SELECT_DEFAULT                                      0x000003ff
4465 #define regSPI_PERFCOUNTER0_SELECT_DEFAULT                                        0x000fffff
4466 #define regSPI_PERFCOUNTER1_SELECT_DEFAULT                                        0x000fffff
4467 #define regSPI_PERFCOUNTER2_SELECT_DEFAULT                                        0x000fffff
4468 #define regSPI_PERFCOUNTER3_SELECT_DEFAULT                                        0x000fffff
4469 #define regSPI_PERFCOUNTER0_SELECT1_DEFAULT                                       0x000fffff
4470 #define regSPI_PERFCOUNTER1_SELECT1_DEFAULT                                       0x000fffff
4471 #define regSPI_PERFCOUNTER2_SELECT1_DEFAULT                                       0x000fffff
4472 #define regSPI_PERFCOUNTER3_SELECT1_DEFAULT                                       0x000fffff
4473 #define regSPI_PERFCOUNTER4_SELECT_DEFAULT                                        0x000003ff
4474 #define regSPI_PERFCOUNTER5_SELECT_DEFAULT                                        0x000003ff
4475 #define regSPI_PERFCOUNTER_BINS_DEFAULT                                           0xfcb87430
4476 #define regPC_PERFCOUNTER0_SELECT_DEFAULT                                         0x000fffff
4477 #define regPC_PERFCOUNTER1_SELECT_DEFAULT                                         0x000fffff
4478 #define regPC_PERFCOUNTER2_SELECT_DEFAULT                                         0x000fffff
4479 #define regPC_PERFCOUNTER3_SELECT_DEFAULT                                         0x000fffff
4480 #define regPC_PERFCOUNTER0_SELECT1_DEFAULT                                        0x000fffff
4481 #define regPC_PERFCOUNTER1_SELECT1_DEFAULT                                        0x000fffff
4482 #define regPC_PERFCOUNTER2_SELECT1_DEFAULT                                        0x000fffff
4483 #define regPC_PERFCOUNTER3_SELECT1_DEFAULT                                        0x000fffff
4484 #define regSQ_PERFCOUNTER0_SELECT_DEFAULT                                         0x000001ff
4485 #define regSQ_PERFCOUNTER1_SELECT_DEFAULT                                         0x000001ff
4486 #define regSQ_PERFCOUNTER2_SELECT_DEFAULT                                         0x000001ff
4487 #define regSQ_PERFCOUNTER3_SELECT_DEFAULT                                         0x000001ff
4488 #define regSQ_PERFCOUNTER4_SELECT_DEFAULT                                         0x000001ff
4489 #define regSQ_PERFCOUNTER5_SELECT_DEFAULT                                         0x000001ff
4490 #define regSQ_PERFCOUNTER6_SELECT_DEFAULT                                         0x000001ff
4491 #define regSQ_PERFCOUNTER7_SELECT_DEFAULT                                         0x000001ff
4492 #define regSQ_PERFCOUNTER8_SELECT_DEFAULT                                         0x000001ff
4493 #define regSQ_PERFCOUNTER9_SELECT_DEFAULT                                         0x000001ff
4494 #define regSQ_PERFCOUNTER10_SELECT_DEFAULT                                        0x000001ff
4495 #define regSQ_PERFCOUNTER11_SELECT_DEFAULT                                        0x000001ff
4496 #define regSQ_PERFCOUNTER12_SELECT_DEFAULT                                        0x000001ff
4497 #define regSQ_PERFCOUNTER13_SELECT_DEFAULT                                        0x000001ff
4498 #define regSQ_PERFCOUNTER14_SELECT_DEFAULT                                        0x000001ff
4499 #define regSQ_PERFCOUNTER15_SELECT_DEFAULT                                        0x000001ff
4500 #define regSQG_PERFCOUNTER0_SELECT_DEFAULT                                        0x000001ff
4501 #define regSQG_PERFCOUNTER1_SELECT_DEFAULT                                        0x000001ff
4502 #define regSQG_PERFCOUNTER2_SELECT_DEFAULT                                        0x000001ff
4503 #define regSQG_PERFCOUNTER3_SELECT_DEFAULT                                        0x000001ff
4504 #define regSQG_PERFCOUNTER4_SELECT_DEFAULT                                        0x000001ff
4505 #define regSQG_PERFCOUNTER5_SELECT_DEFAULT                                        0x000001ff
4506 #define regSQG_PERFCOUNTER6_SELECT_DEFAULT                                        0x000001ff
4507 #define regSQG_PERFCOUNTER7_SELECT_DEFAULT                                        0x000001ff
4508 #define regSQG_PERFCOUNTER_CTRL_DEFAULT                                           0x00000000
4509 #define regSQG_PERFCOUNTER_CTRL2_DEFAULT                                          0x0001fffe
4510 #define regSQG_PERF_SAMPLE_FINISH_DEFAULT                                         0x00000000
4511 #define regSQ_PERFCOUNTER_CTRL_DEFAULT                                            0x00000000
4512 #define regSQ_PERFCOUNTER_CTRL2_DEFAULT                                           0x0001fffe
4513 #define regSQ_THREAD_TRACE_BUF0_BASE_DEFAULT                                      0x00000000
4514 #define regSQ_THREAD_TRACE_BUF0_SIZE_DEFAULT                                      0x00000000
4515 #define regSQ_THREAD_TRACE_BUF1_BASE_DEFAULT                                      0x00000000
4516 #define regSQ_THREAD_TRACE_BUF1_SIZE_DEFAULT                                      0x00000000
4517 #define regSQ_THREAD_TRACE_CTRL_DEFAULT                                           0x00400000
4518 #define regSQ_THREAD_TRACE_MASK_DEFAULT                                           0x00000000
4519 #define regSQ_THREAD_TRACE_TOKEN_MASK_DEFAULT                                     0x00000000
4520 #define regSQ_THREAD_TRACE_WPTR_DEFAULT                                           0x00000000
4521 #define regSQ_THREAD_TRACE_STATUS_DEFAULT                                         0x00000000
4522 #define regSQ_THREAD_TRACE_STATUS2_DEFAULT                                        0x00000000
4523 #define regSQ_THREAD_TRACE_GFX_DRAW_CNTR_DEFAULT                                  0x00000000
4524 #define regSQ_THREAD_TRACE_GFX_MARKER_CNTR_DEFAULT                                0x00000000
4525 #define regSQ_THREAD_TRACE_HP3D_DRAW_CNTR_DEFAULT                                 0x00000000
4526 #define regSQ_THREAD_TRACE_HP3D_MARKER_CNTR_DEFAULT                               0x00000000
4527 #define regSQ_THREAD_TRACE_DROPPED_CNTR_DEFAULT                                   0x00000000
4528 #define regGCEA_PERFCOUNTER2_SELECT_DEFAULT                                       0x000fffff
4529 #define regGCEA_PERFCOUNTER2_SELECT1_DEFAULT                                      0x000fffff
4530 #define regGCEA_PERFCOUNTER2_MODE_DEFAULT                                         0x00000000
4531 #define regGCEA_PERFCOUNTER0_CFG_DEFAULT                                          0x00000000
4532 #define regGCEA_PERFCOUNTER1_CFG_DEFAULT                                          0x00000000
4533 #define regGCEA_PERFCOUNTER_RSLT_CNTL_DEFAULT                                     0x04000000
4534 #define regSX_PERFCOUNTER0_SELECT_DEFAULT                                         0x000fffff
4535 #define regSX_PERFCOUNTER1_SELECT_DEFAULT                                         0x000fffff
4536 #define regSX_PERFCOUNTER2_SELECT_DEFAULT                                         0x000003ff
4537 #define regSX_PERFCOUNTER3_SELECT_DEFAULT                                         0x000003ff
4538 #define regSX_PERFCOUNTER0_SELECT1_DEFAULT                                        0x000fffff
4539 #define regSX_PERFCOUNTER1_SELECT1_DEFAULT                                        0x000fffff
4540 #define regGDS_PERFCOUNTER0_SELECT_DEFAULT                                        0x000fffff
4541 #define regGDS_PERFCOUNTER1_SELECT_DEFAULT                                        0x000fffff
4542 #define regGDS_PERFCOUNTER2_SELECT_DEFAULT                                        0x000fffff
4543 #define regGDS_PERFCOUNTER3_SELECT_DEFAULT                                        0x000fffff
4544 #define regGDS_PERFCOUNTER0_SELECT1_DEFAULT                                       0x000fffff
4545 #define regGDS_PERFCOUNTER1_SELECT1_DEFAULT                                       0x000fffff
4546 #define regGDS_PERFCOUNTER2_SELECT1_DEFAULT                                       0x000fffff
4547 #define regGDS_PERFCOUNTER3_SELECT1_DEFAULT                                       0x000fffff
4548 #define regTA_PERFCOUNTER0_SELECT_DEFAULT                                         0x000fffff
4549 #define regTA_PERFCOUNTER0_SELECT1_DEFAULT                                        0x000fffff
4550 #define regTA_PERFCOUNTER1_SELECT_DEFAULT                                         0x000003ff
4551 #define regTD_PERFCOUNTER0_SELECT_DEFAULT                                         0x000fffff
4552 #define regTD_PERFCOUNTER0_SELECT1_DEFAULT                                        0x000fffff
4553 #define regTD_PERFCOUNTER1_SELECT_DEFAULT                                         0x000003ff
4554 #define regTCP_PERFCOUNTER0_SELECT_DEFAULT                                        0x000fffff
4555 #define regTCP_PERFCOUNTER0_SELECT1_DEFAULT                                       0x000fffff
4556 #define regTCP_PERFCOUNTER1_SELECT_DEFAULT                                        0x000fffff
4557 #define regTCP_PERFCOUNTER1_SELECT1_DEFAULT                                       0x000fffff
4558 #define regTCP_PERFCOUNTER2_SELECT_DEFAULT                                        0x000003ff
4559 #define regTCP_PERFCOUNTER3_SELECT_DEFAULT                                        0x000003ff
4560 #define regGL2C_PERFCOUNTER0_SELECT_DEFAULT                                       0x000fffff
4561 #define regGL2C_PERFCOUNTER0_SELECT1_DEFAULT                                      0x000fffff
4562 #define regGL2C_PERFCOUNTER1_SELECT_DEFAULT                                       0x000fffff
4563 #define regGL2C_PERFCOUNTER1_SELECT1_DEFAULT                                      0x000fffff
4564 #define regGL2C_PERFCOUNTER2_SELECT_DEFAULT                                       0x000003ff
4565 #define regGL2C_PERFCOUNTER3_SELECT_DEFAULT                                       0x000003ff
4566 #define regGL2A_PERFCOUNTER0_SELECT_DEFAULT                                       0x000fffff
4567 #define regGL2A_PERFCOUNTER0_SELECT1_DEFAULT                                      0x000fffff
4568 #define regGL2A_PERFCOUNTER1_SELECT_DEFAULT                                       0x000fffff
4569 #define regGL2A_PERFCOUNTER1_SELECT1_DEFAULT                                      0x000fffff
4570 #define regGL2A_PERFCOUNTER2_SELECT_DEFAULT                                       0x000003ff
4571 #define regGL2A_PERFCOUNTER3_SELECT_DEFAULT                                       0x000003ff
4572 #define regGL1C_PERFCOUNTER0_SELECT_DEFAULT                                       0x000fffff
4573 #define regGL1C_PERFCOUNTER0_SELECT1_DEFAULT                                      0x000fffff
4574 #define regGL1C_PERFCOUNTER1_SELECT_DEFAULT                                       0x000003ff
4575 #define regGL1C_PERFCOUNTER2_SELECT_DEFAULT                                       0x000003ff
4576 #define regGL1C_PERFCOUNTER3_SELECT_DEFAULT                                       0x000003ff
4577 #define regCHC_PERFCOUNTER0_SELECT_DEFAULT                                        0x000fffff
4578 #define regCHC_PERFCOUNTER0_SELECT1_DEFAULT                                       0x000fffff
4579 #define regCHC_PERFCOUNTER1_SELECT_DEFAULT                                        0x000003ff
4580 #define regCHC_PERFCOUNTER2_SELECT_DEFAULT                                        0x000003ff
4581 #define regCHC_PERFCOUNTER3_SELECT_DEFAULT                                        0x000003ff
4582 #define regCHCG_PERFCOUNTER0_SELECT_DEFAULT                                       0x000fffff
4583 #define regCHCG_PERFCOUNTER0_SELECT1_DEFAULT                                      0x000fffff
4584 #define regCHCG_PERFCOUNTER1_SELECT_DEFAULT                                       0x000003ff
4585 #define regCHCG_PERFCOUNTER2_SELECT_DEFAULT                                       0x000003ff
4586 #define regCHCG_PERFCOUNTER3_SELECT_DEFAULT                                       0x000003ff
4587 #define regCB_PERFCOUNTER_FILTER_DEFAULT                                          0x00000000
4588 #define regCB_PERFCOUNTER0_SELECT_DEFAULT                                         0x000fffff
4589 #define regCB_PERFCOUNTER0_SELECT1_DEFAULT                                        0x000fffff
4590 #define regCB_PERFCOUNTER1_SELECT_DEFAULT                                         0x000003ff
4591 #define regCB_PERFCOUNTER2_SELECT_DEFAULT                                         0x000003ff
4592 #define regCB_PERFCOUNTER3_SELECT_DEFAULT                                         0x000003ff
4593 #define regDB_PERFCOUNTER0_SELECT_DEFAULT                                         0x000fffff
4594 #define regDB_PERFCOUNTER0_SELECT1_DEFAULT                                        0x000fffff
4595 #define regDB_PERFCOUNTER1_SELECT_DEFAULT                                         0x000fffff
4596 #define regDB_PERFCOUNTER1_SELECT1_DEFAULT                                        0x000fffff
4597 #define regDB_PERFCOUNTER2_SELECT_DEFAULT                                         0x000003ff
4598 #define regDB_PERFCOUNTER3_SELECT_DEFAULT                                         0x000003ff
4599 #define regRLC_SPM_PERFMON_CNTL_DEFAULT                                           0x00000000
4600 #define regRLC_SPM_PERFMON_RING_BASE_LO_DEFAULT                                   0x00000000
4601 #define regRLC_SPM_PERFMON_RING_BASE_HI_DEFAULT                                   0x00000000
4602 #define regRLC_SPM_PERFMON_RING_SIZE_DEFAULT                                      0x00000000
4603 #define regRLC_SPM_RING_WRPTR_DEFAULT                                             0x00000000
4604 #define regRLC_SPM_RING_RDPTR_DEFAULT                                             0x00000000
4605 #define regRLC_SPM_SEGMENT_THRESHOLD_DEFAULT                                      0x00000000
4606 #define regRLC_SPM_PERFMON_SEGMENT_SIZE_DEFAULT                                   0x00000000
4607 #define regRLC_SPM_GLOBAL_MUXSEL_ADDR_DEFAULT                                     0x00000000
4608 #define regRLC_SPM_GLOBAL_MUXSEL_DATA_DEFAULT                                     0x00000000
4609 #define regRLC_SPM_SE_MUXSEL_ADDR_DEFAULT                                         0x00000000
4610 #define regRLC_SPM_SE_MUXSEL_DATA_DEFAULT                                         0x00000000
4611 #define regRLC_SPM_ACCUM_DATARAM_ADDR_DEFAULT                                     0x00000000
4612 #define regRLC_SPM_ACCUM_DATARAM_DATA_DEFAULT                                     0x00000000
4613 #define regRLC_SPM_ACCUM_SWA_DATARAM_ADDR_DEFAULT                                 0x00000000
4614 #define regRLC_SPM_ACCUM_SWA_DATARAM_DATA_DEFAULT                                 0x00000000
4615 #define regRLC_SPM_ACCUM_CTRLRAM_ADDR_DEFAULT                                     0x00000000
4616 #define regRLC_SPM_ACCUM_CTRLRAM_DATA_DEFAULT                                     0x00000000
4617 #define regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_DEFAULT                              0x00000008
4618 #define regRLC_SPM_ACCUM_STATUS_DEFAULT                                           0x00184800
4619 #define regRLC_SPM_ACCUM_CTRL_DEFAULT                                             0x00000000
4620 #define regRLC_SPM_ACCUM_MODE_DEFAULT                                             0x007fe004
4621 #define regRLC_SPM_ACCUM_THRESHOLD_DEFAULT                                        0x00000001
4622 #define regRLC_SPM_ACCUM_SAMPLES_REQUESTED_DEFAULT                                0x00000001
4623 #define regRLC_SPM_ACCUM_DATARAM_WRCOUNT_DEFAULT                                  0x00000000
4624 #define regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_DEFAULT                       0x0000ffff
4625 #define regRLC_SPM_PAUSE_DEFAULT                                                  0x00000000
4626 #define regRLC_SPM_STATUS_DEFAULT                                                 0x00000000
4627 #define regRLC_SPM_GFXCLOCK_LOWCOUNT_DEFAULT                                      0x00000000
4628 #define regRLC_SPM_GFXCLOCK_HIGHCOUNT_DEFAULT                                     0x00000000
4629 #define regRLC_SPM_MODE_DEFAULT                                                   0x00000000
4630 #define regRLC_SPM_RSPM_REQ_DATA_LO_DEFAULT                                       0x00000000
4631 #define regRLC_SPM_RSPM_REQ_DATA_HI_DEFAULT                                       0x00000000
4632 #define regRLC_SPM_RSPM_REQ_OP_DEFAULT                                            0x00000000
4633 #define regRLC_SPM_RSPM_RET_DATA_DEFAULT                                          0x00000000
4634 #define regRLC_SPM_RSPM_RET_OP_DEFAULT                                            0x00000000
4635 #define regRLC_SPM_SE_RSPM_REQ_DATA_LO_DEFAULT                                    0x00000000
4636 #define regRLC_SPM_SE_RSPM_REQ_DATA_HI_DEFAULT                                    0x00000000
4637 #define regRLC_SPM_SE_RSPM_REQ_OP_DEFAULT                                         0x00000000
4638 #define regRLC_SPM_SE_RSPM_RET_DATA_DEFAULT                                       0x00000000
4639 #define regRLC_SPM_SE_RSPM_RET_OP_DEFAULT                                         0x00000000
4640 #define regRLC_SPM_RSPM_CMD_DEFAULT                                               0x00000000
4641 #define regRLC_SPM_RSPM_CMD_ACK_DEFAULT                                           0x00000000
4642 #define regRLC_SPM_SPARE_DEFAULT                                                  0x00000000
4643 #define regRLC_PERFMON_CNTL_DEFAULT                                               0x00000000
4644 #define regRLC_PERFCOUNTER0_SELECT_DEFAULT                                        0x00000000
4645 #define regRLC_PERFCOUNTER1_SELECT_DEFAULT                                        0x00000000
4646 #define regRLC_GPU_IOV_PERF_CNT_CNTL_DEFAULT                                      0x00000000
4647 #define regRLC_GPU_IOV_PERF_CNT_WR_ADDR_DEFAULT                                   0x00000000
4648 #define regRLC_GPU_IOV_PERF_CNT_WR_DATA_DEFAULT                                   0x00000000
4649 #define regRLC_GPU_IOV_PERF_CNT_RD_ADDR_DEFAULT                                   0x00000000
4650 #define regRLC_GPU_IOV_PERF_CNT_RD_DATA_DEFAULT                                   0x00000000
4651 #define regRMI_PERFCOUNTER0_SELECT_DEFAULT                                        0x000fffff
4652 #define regRMI_PERFCOUNTER0_SELECT1_DEFAULT                                       0x000fffff
4653 #define regRMI_PERFCOUNTER1_SELECT_DEFAULT                                        0x000003ff
4654 #define regRMI_PERFCOUNTER2_SELECT_DEFAULT                                        0x000fffff
4655 #define regRMI_PERFCOUNTER2_SELECT1_DEFAULT                                       0x000fffff
4656 #define regRMI_PERFCOUNTER3_SELECT_DEFAULT                                        0x000003ff
4657 #define regRMI_PERF_COUNTER_CNTL_DEFAULT                                          0x00080240
4658 #define regGCR_PERFCOUNTER0_SELECT_DEFAULT                                        0x000fffff
4659 #define regGCR_PERFCOUNTER0_SELECT1_DEFAULT                                       0x000fffff
4660 #define regGCR_PERFCOUNTER1_SELECT_DEFAULT                                        0x000003ff
4661 #define regPA_PH_PERFCOUNTER0_SELECT_DEFAULT                                      0x000fffff
4662 #define regPA_PH_PERFCOUNTER0_SELECT1_DEFAULT                                     0x000fffff
4663 #define regPA_PH_PERFCOUNTER1_SELECT_DEFAULT                                      0x000fffff
4664 #define regPA_PH_PERFCOUNTER2_SELECT_DEFAULT                                      0x000fffff
4665 #define regPA_PH_PERFCOUNTER3_SELECT_DEFAULT                                      0x000fffff
4666 #define regPA_PH_PERFCOUNTER4_SELECT_DEFAULT                                      0x000003ff
4667 #define regPA_PH_PERFCOUNTER5_SELECT_DEFAULT                                      0x000003ff
4668 #define regPA_PH_PERFCOUNTER6_SELECT_DEFAULT                                      0x000003ff
4669 #define regPA_PH_PERFCOUNTER7_SELECT_DEFAULT                                      0x000003ff
4670 #define regPA_PH_PERFCOUNTER1_SELECT1_DEFAULT                                     0x000fffff
4671 #define regPA_PH_PERFCOUNTER2_SELECT1_DEFAULT                                     0x000fffff
4672 #define regPA_PH_PERFCOUNTER3_SELECT1_DEFAULT                                     0x000fffff
4673 #define regUTCL1_PERFCOUNTER0_SELECT_DEFAULT                                      0x000003ff
4674 #define regUTCL1_PERFCOUNTER1_SELECT_DEFAULT                                      0x000003ff
4675 #define regUTCL1_PERFCOUNTER2_SELECT_DEFAULT                                      0x000003ff
4676 #define regUTCL1_PERFCOUNTER3_SELECT_DEFAULT                                      0x000003ff
4677 #define regGL1A_PERFCOUNTER0_SELECT_DEFAULT                                       0x000fffff
4678 #define regGL1A_PERFCOUNTER0_SELECT1_DEFAULT                                      0x000fffff
4679 #define regGL1A_PERFCOUNTER1_SELECT_DEFAULT                                       0x000003ff
4680 #define regGL1A_PERFCOUNTER2_SELECT_DEFAULT                                       0x000003ff
4681 #define regGL1A_PERFCOUNTER3_SELECT_DEFAULT                                       0x000003ff
4682 #define regGL1H_PERFCOUNTER0_SELECT_DEFAULT                                       0x000fffff
4683 #define regGL1H_PERFCOUNTER0_SELECT1_DEFAULT                                      0x000fffff
4684 #define regGL1H_PERFCOUNTER1_SELECT_DEFAULT                                       0x000003ff
4685 #define regGL1H_PERFCOUNTER2_SELECT_DEFAULT                                       0x000003ff
4686 #define regGL1H_PERFCOUNTER3_SELECT_DEFAULT                                       0x000003ff
4687 #define regCHA_PERFCOUNTER0_SELECT_DEFAULT                                        0x000fffff
4688 #define regCHA_PERFCOUNTER0_SELECT1_DEFAULT                                       0x000fffff
4689 #define regCHA_PERFCOUNTER1_SELECT_DEFAULT                                        0x000003ff
4690 #define regCHA_PERFCOUNTER2_SELECT_DEFAULT                                        0x000003ff
4691 #define regCHA_PERFCOUNTER3_SELECT_DEFAULT                                        0x000003ff
4692 #define regGUS_PERFCOUNTER2_SELECT_DEFAULT                                        0x000fffff
4693 #define regGUS_PERFCOUNTER2_SELECT1_DEFAULT                                       0x000fffff
4694 #define regGUS_PERFCOUNTER2_MODE_DEFAULT                                          0x00000000
4695 #define regGUS_PERFCOUNTER0_CFG_DEFAULT                                           0x00000000
4696 #define regGUS_PERFCOUNTER1_CFG_DEFAULT                                           0x00000000
4697 #define regGUS_PERFCOUNTER_RSLT_CNTL_DEFAULT                                      0x04000000
4698 
4699 
4700 // addressBlock: gc_gcvml2perfsdec
4701 #define regGCVML2_PERFCOUNTER2_0_SELECT_DEFAULT                                   0x000fffff
4702 #define regGCVML2_PERFCOUNTER2_1_SELECT_DEFAULT                                   0x000fffff
4703 #define regGCVML2_PERFCOUNTER2_0_SELECT1_DEFAULT                                  0x000fffff
4704 #define regGCVML2_PERFCOUNTER2_1_SELECT1_DEFAULT                                  0x000fffff
4705 #define regGCVML2_PERFCOUNTER2_0_MODE_DEFAULT                                     0x00000000
4706 #define regGCVML2_PERFCOUNTER2_1_MODE_DEFAULT                                     0x00000000
4707 
4708 
4709 // addressBlock: gc_gcvml2pldec
4710 #define regGCMC_VM_L2_PERFCOUNTER0_CFG_DEFAULT                                    0x00000000
4711 #define regGCMC_VM_L2_PERFCOUNTER1_CFG_DEFAULT                                    0x00000000
4712 #define regGCMC_VM_L2_PERFCOUNTER2_CFG_DEFAULT                                    0x00000000
4713 #define regGCMC_VM_L2_PERFCOUNTER3_CFG_DEFAULT                                    0x00000000
4714 #define regGCMC_VM_L2_PERFCOUNTER4_CFG_DEFAULT                                    0x00000000
4715 #define regGCMC_VM_L2_PERFCOUNTER5_CFG_DEFAULT                                    0x00000000
4716 #define regGCMC_VM_L2_PERFCOUNTER6_CFG_DEFAULT                                    0x00000000
4717 #define regGCMC_VM_L2_PERFCOUNTER7_CFG_DEFAULT                                    0x00000000
4718 #define regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT                               0x04000000
4719 #define regGCUTCL2_PERFCOUNTER0_CFG_DEFAULT                                       0x00000000
4720 #define regGCUTCL2_PERFCOUNTER1_CFG_DEFAULT                                       0x00000000
4721 #define regGCUTCL2_PERFCOUNTER2_CFG_DEFAULT                                       0x00000000
4722 #define regGCUTCL2_PERFCOUNTER3_CFG_DEFAULT                                       0x00000000
4723 #define regGCUTCL2_PERFCOUNTER_RSLT_CNTL_DEFAULT                                  0x04000000
4724 
4725 
4726 // addressBlock: gc_sdma0_sdma0perfsdec
4727 #define regSDMA0_PERFCNT_PERFCOUNTER0_CFG_DEFAULT                                 0x0000ffff
4728 #define regSDMA0_PERFCNT_PERFCOUNTER1_CFG_DEFAULT                                 0x0000ffff
4729 #define regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_DEFAULT                            0x04000000
4730 #define regSDMA0_PERFCNT_MISC_CNTL_DEFAULT                                        0x00000000
4731 #define regSDMA0_PERFCOUNTER0_SELECT_DEFAULT                                      0x000fffff
4732 #define regSDMA0_PERFCOUNTER0_SELECT1_DEFAULT                                     0x000fffff
4733 #define regSDMA0_PERFCOUNTER1_SELECT_DEFAULT                                      0x000fffff
4734 #define regSDMA0_PERFCOUNTER1_SELECT1_DEFAULT                                     0x000fffff
4735 
4736 
4737 // addressBlock: gc_sdma0_sdma1perfsdec
4738 #define regSDMA1_PERFCNT_PERFCOUNTER0_CFG_DEFAULT                                 0x0000ffff
4739 #define regSDMA1_PERFCNT_PERFCOUNTER1_CFG_DEFAULT                                 0x0000ffff
4740 #define regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_DEFAULT                            0x04000000
4741 #define regSDMA1_PERFCNT_MISC_CNTL_DEFAULT                                        0x00000000
4742 #define regSDMA1_PERFCOUNTER0_SELECT_DEFAULT                                      0x000fffff
4743 #define regSDMA1_PERFCOUNTER0_SELECT1_DEFAULT                                     0x000fffff
4744 #define regSDMA1_PERFCOUNTER1_SELECT_DEFAULT                                      0x000fffff
4745 #define regSDMA1_PERFCOUNTER1_SELECT1_DEFAULT                                     0x000fffff
4746 
4747 
4748 // addressBlock: gc_gfx_imu_gfx_imudec
4749 #define regGFX_IMU_C2PMSG_0_DEFAULT                                               0x00000000
4750 #define regGFX_IMU_C2PMSG_1_DEFAULT                                               0x00000000
4751 #define regGFX_IMU_C2PMSG_2_DEFAULT                                               0x00000000
4752 #define regGFX_IMU_C2PMSG_3_DEFAULT                                               0x00000000
4753 #define regGFX_IMU_C2PMSG_4_DEFAULT                                               0x00000000
4754 #define regGFX_IMU_C2PMSG_5_DEFAULT                                               0x00000000
4755 #define regGFX_IMU_C2PMSG_6_DEFAULT                                               0x00000000
4756 #define regGFX_IMU_C2PMSG_7_DEFAULT                                               0x00000000
4757 #define regGFX_IMU_C2PMSG_8_DEFAULT                                               0x00000000
4758 #define regGFX_IMU_C2PMSG_9_DEFAULT                                               0x00000000
4759 #define regGFX_IMU_C2PMSG_10_DEFAULT                                              0x00000000
4760 #define regGFX_IMU_C2PMSG_11_DEFAULT                                              0x00000000
4761 #define regGFX_IMU_C2PMSG_12_DEFAULT                                              0x00000000
4762 #define regGFX_IMU_C2PMSG_13_DEFAULT                                              0x00000000
4763 #define regGFX_IMU_C2PMSG_14_DEFAULT                                              0x00000000
4764 #define regGFX_IMU_C2PMSG_15_DEFAULT                                              0x00000000
4765 #define regGFX_IMU_C2PMSG_16_DEFAULT                                              0x00000000
4766 #define regGFX_IMU_C2PMSG_17_DEFAULT                                              0x00000000
4767 #define regGFX_IMU_C2PMSG_18_DEFAULT                                              0x00000000
4768 #define regGFX_IMU_C2PMSG_19_DEFAULT                                              0x00000000
4769 #define regGFX_IMU_C2PMSG_20_DEFAULT                                              0x00000000
4770 #define regGFX_IMU_C2PMSG_21_DEFAULT                                              0x00000000
4771 #define regGFX_IMU_C2PMSG_22_DEFAULT                                              0x00000000
4772 #define regGFX_IMU_C2PMSG_23_DEFAULT                                              0x00000000
4773 #define regGFX_IMU_C2PMSG_24_DEFAULT                                              0x00000000
4774 #define regGFX_IMU_C2PMSG_25_DEFAULT                                              0x00000000
4775 #define regGFX_IMU_C2PMSG_26_DEFAULT                                              0x00000000
4776 #define regGFX_IMU_C2PMSG_27_DEFAULT                                              0x00000000
4777 #define regGFX_IMU_C2PMSG_28_DEFAULT                                              0x00000000
4778 #define regGFX_IMU_C2PMSG_29_DEFAULT                                              0x00000000
4779 #define regGFX_IMU_C2PMSG_30_DEFAULT                                              0x00000000
4780 #define regGFX_IMU_C2PMSG_31_DEFAULT                                              0x00000000
4781 #define regGFX_IMU_C2PMSG_32_DEFAULT                                              0x00000000
4782 #define regGFX_IMU_C2PMSG_33_DEFAULT                                              0x00000000
4783 #define regGFX_IMU_C2PMSG_34_DEFAULT                                              0x00000000
4784 #define regGFX_IMU_C2PMSG_35_DEFAULT                                              0x00000000
4785 #define regGFX_IMU_C2PMSG_36_DEFAULT                                              0x00000000
4786 #define regGFX_IMU_C2PMSG_37_DEFAULT                                              0x00000000
4787 #define regGFX_IMU_C2PMSG_38_DEFAULT                                              0x00000000
4788 #define regGFX_IMU_C2PMSG_39_DEFAULT                                              0x00000000
4789 #define regGFX_IMU_C2PMSG_40_DEFAULT                                              0x00000000
4790 #define regGFX_IMU_C2PMSG_41_DEFAULT                                              0x00000000
4791 #define regGFX_IMU_C2PMSG_42_DEFAULT                                              0x00000000
4792 #define regGFX_IMU_C2PMSG_43_DEFAULT                                              0x00000000
4793 #define regGFX_IMU_C2PMSG_44_DEFAULT                                              0x00000000
4794 #define regGFX_IMU_C2PMSG_45_DEFAULT                                              0x00000000
4795 #define regGFX_IMU_C2PMSG_46_DEFAULT                                              0x00000000
4796 #define regGFX_IMU_C2PMSG_47_DEFAULT                                              0x00000000
4797 #define regGFX_IMU_MSG_FLAGS_DEFAULT                                              0x00000000
4798 #define regGFX_IMU_C2PMSG_ACCESS_CTRL0_DEFAULT                                    0x00000000
4799 #define regGFX_IMU_C2PMSG_ACCESS_CTRL1_DEFAULT                                    0x00000000
4800 #define regGFX_IMU_PWRMGT_IRQ_CTRL_DEFAULT                                        0x00000000
4801 #define regGFX_IMU_MP1_MUTEX_DEFAULT                                              0x00000000
4802 #define regGFX_IMU_RLC_DATA_4_DEFAULT                                             0x00000000
4803 #define regGFX_IMU_RLC_DATA_3_DEFAULT                                             0x00000000
4804 #define regGFX_IMU_RLC_DATA_2_DEFAULT                                             0x00000000
4805 #define regGFX_IMU_RLC_DATA_1_DEFAULT                                             0x00000000
4806 #define regGFX_IMU_RLC_DATA_0_DEFAULT                                             0x00000000
4807 #define regGFX_IMU_RLC_CMD_DEFAULT                                                0x00000000
4808 #define regGFX_IMU_RLC_MUTEX_DEFAULT                                              0x00000000
4809 #define regGFX_IMU_RLC_MSG_STATUS_DEFAULT                                         0x00000000
4810 #define regRLC_GFX_IMU_DATA_0_DEFAULT                                             0x00000000
4811 #define regRLC_GFX_IMU_CMD_DEFAULT                                                0x00000000
4812 #define regGFX_IMU_RLC_STATUS_DEFAULT                                             0x00000000
4813 #define regGFX_IMU_STATUS_DEFAULT                                                 0x00000000
4814 #define regGFX_IMU_SOC_DATA_DEFAULT                                               0x00000000
4815 #define regGFX_IMU_SOC_ADDR_DEFAULT                                               0x00000000
4816 #define regGFX_IMU_SOC_REQ_DEFAULT                                                0x00000000
4817 #define regGFX_IMU_VF_CTRL_DEFAULT                                                0x00000080
4818 #define regGFX_IMU_TELEMETRY_DEFAULT                                              0x00003000
4819 #define regGFX_IMU_TELEMETRY_DATA_DEFAULT                                         0x00000000
4820 #define regGFX_IMU_TELEMETRY_TEMPERATURE_DEFAULT                                  0x00000000
4821 #define regGFX_IMU_SCRATCH_0_DEFAULT                                              0x00000000
4822 #define regGFX_IMU_SCRATCH_1_DEFAULT                                              0x00000000
4823 #define regGFX_IMU_SCRATCH_2_DEFAULT                                              0x00000000
4824 #define regGFX_IMU_SCRATCH_3_DEFAULT                                              0x00000000
4825 #define regGFX_IMU_SCRATCH_4_DEFAULT                                              0x00000000
4826 #define regGFX_IMU_SCRATCH_5_DEFAULT                                              0x00000000
4827 #define regGFX_IMU_SCRATCH_6_DEFAULT                                              0x00000000
4828 #define regGFX_IMU_SCRATCH_7_DEFAULT                                              0x00000000
4829 #define regGFX_IMU_SCRATCH_8_DEFAULT                                              0x00000000
4830 #define regGFX_IMU_SCRATCH_9_DEFAULT                                              0x00000000
4831 #define regGFX_IMU_SCRATCH_10_DEFAULT                                             0x00000000
4832 #define regGFX_IMU_SCRATCH_11_DEFAULT                                             0x00000000
4833 #define regGFX_IMU_SCRATCH_12_DEFAULT                                             0x00000000
4834 #define regGFX_IMU_SCRATCH_13_DEFAULT                                             0x00000000
4835 #define regGFX_IMU_SCRATCH_14_DEFAULT                                             0x00000000
4836 #define regGFX_IMU_SCRATCH_15_DEFAULT                                             0x00000000
4837 #define regGFX_IMU_FW_GTS_LO_DEFAULT                                              0x00000000
4838 #define regGFX_IMU_FW_GTS_HI_DEFAULT                                              0x00000000
4839 #define regGFX_IMU_GTS_OFFSET_LO_DEFAULT                                          0x00000000
4840 #define regGFX_IMU_GTS_OFFSET_HI_DEFAULT                                          0x00000000
4841 #define regGFX_IMU_RLC_GTS_OFFSET_LO_DEFAULT                                      0x00000000
4842 #define regGFX_IMU_RLC_GTS_OFFSET_HI_DEFAULT                                      0x00000000
4843 #define regGFX_IMU_CORE_INT_STATUS_DEFAULT                                        0x00000000
4844 #define regGFX_IMU_PIC_INT_MASK_DEFAULT                                           0x00000000
4845 #define regGFX_IMU_PIC_INT_LVL_DEFAULT                                            0x00000000
4846 #define regGFX_IMU_PIC_INT_EDGE_DEFAULT                                           0x00000000
4847 #define regGFX_IMU_PIC_INT_PRI_0_DEFAULT                                          0x03020100
4848 #define regGFX_IMU_PIC_INT_PRI_1_DEFAULT                                          0x07060504
4849 #define regGFX_IMU_PIC_INT_PRI_2_DEFAULT                                          0x0b0a0908
4850 #define regGFX_IMU_PIC_INT_PRI_3_DEFAULT                                          0x0f0e0d0c
4851 #define regGFX_IMU_PIC_INT_PRI_4_DEFAULT                                          0x13121110
4852 #define regGFX_IMU_PIC_INT_PRI_5_DEFAULT                                          0x17161514
4853 #define regGFX_IMU_PIC_INT_PRI_6_DEFAULT                                          0x1b1a1918
4854 #define regGFX_IMU_PIC_INT_PRI_7_DEFAULT                                          0x1f1e1d1c
4855 #define regGFX_IMU_PIC_INT_STATUS_DEFAULT                                         0x00000000
4856 #define regGFX_IMU_PIC_INTR_DEFAULT                                               0x00000001
4857 #define regGFX_IMU_PIC_INTR_ID_DEFAULT                                            0x00000000
4858 #define regGFX_IMU_IH_CTRL_1_DEFAULT                                              0x00000000
4859 #define regGFX_IMU_IH_CTRL_2_DEFAULT                                              0x80000000
4860 #define regGFX_IMU_IH_CTRL_3_DEFAULT                                              0x00000000
4861 #define regGFX_IMU_IH_STATUS_DEFAULT                                              0x00000000
4862 #define regGFX_IMU_FUSESTRAP_DEFAULT                                              0x00000000
4863 #define regGFX_IMU_SMUIO_VIDCHG_CTRL_DEFAULT                                      0x00000000
4864 #define regGFX_IMU_GFXCLK_BYPASS_CTRL_DEFAULT                                     0x00000001
4865 #define regGFX_IMU_CLK_CTRL_DEFAULT                                               0x20680013
4866 #define regGFX_IMU_DOORBELL_CONTROL_DEFAULT                                       0x00000000
4867 #define regGFX_IMU_RLC_CG_CTRL_DEFAULT                                            0x00000000
4868 #define regGFX_IMU_RLC_THROTTLE_GFX_DEFAULT                                       0x00000000
4869 #define regGFX_IMU_RLC_RESET_VECTOR_DEFAULT                                       0x00000000
4870 #define regGFX_IMU_RLC_OVERRIDE_DEFAULT                                           0x00000000
4871 #define regGFX_IMU_DPM_CONTROL_DEFAULT                                            0x00000000
4872 #define regGFX_IMU_DPM_ACC_DEFAULT                                                0x00000000
4873 #define regGFX_IMU_DPM_REF_COUNTER_DEFAULT                                        0x00000000
4874 #define regGFX_IMU_RLC_RAM_INDEX_DEFAULT                                          0x00000000
4875 #define regGFX_IMU_RLC_RAM_ADDR_HIGH_DEFAULT                                      0x00000000
4876 #define regGFX_IMU_RLC_RAM_ADDR_LOW_DEFAULT                                       0x00000000
4877 #define regGFX_IMU_RLC_RAM_DATA_DEFAULT                                           0x00000000
4878 #define regGFX_IMU_FENCE_CTRL_DEFAULT                                             0x00000002
4879 #define regGFX_IMU_FENCE_LOG_INIT_DEFAULT                                         0x00000000
4880 #define regGFX_IMU_FENCE_LOG_ADDR_DEFAULT                                         0x00000000
4881 #define regGFX_IMU_PROGRAM_CTR_DEFAULT                                            0x00000000
4882 #define regGFX_IMU_CORE_CTRL_DEFAULT                                              0x00000009
4883 #define regGFX_IMU_CORE_STATUS_DEFAULT                                            0x00000000
4884 #define regGFX_IMU_PWROKRAW_DEFAULT                                               0x00000000
4885 #define regGFX_IMU_PWROK_DEFAULT                                                  0x00000000
4886 #define regGFX_IMU_GAP_PWROK_DEFAULT                                              0x00000000
4887 #define regGFX_IMU_RESETn_DEFAULT                                                 0x00000000
4888 #define regGFX_IMU_GFX_RESET_CTRL_DEFAULT                                         0x00000010
4889 #define regGFX_IMU_AEB_OVERRIDE_DEFAULT                                           0x00000000
4890 #define regGFX_IMU_VDCI_RESET_CTRL_DEFAULT                                        0x0000000e
4891 #define regGFX_IMU_GFX_ISO_CTRL_DEFAULT                                           0x00000000
4892 #define regGFX_IMU_TIMER0_CTRL0_DEFAULT                                           0x00000000
4893 #define regGFX_IMU_TIMER0_CTRL1_DEFAULT                                           0x00000000
4894 #define regGFX_IMU_TIMER0_CMP_AUTOINC_DEFAULT                                     0x00000000
4895 #define regGFX_IMU_TIMER0_CMP_INTEN_DEFAULT                                       0x00000000
4896 #define regGFX_IMU_TIMER0_CMP0_DEFAULT                                            0x00000000
4897 #define regGFX_IMU_TIMER0_CMP1_DEFAULT                                            0x00000000
4898 #define regGFX_IMU_TIMER0_CMP3_DEFAULT                                            0x00000000
4899 #define regGFX_IMU_TIMER0_VALUE_DEFAULT                                           0x00000000
4900 #define regGFX_IMU_TIMER1_CTRL0_DEFAULT                                           0x00000000
4901 #define regGFX_IMU_TIMER1_CTRL1_DEFAULT                                           0x00000000
4902 #define regGFX_IMU_TIMER1_CMP_AUTOINC_DEFAULT                                     0x00000000
4903 #define regGFX_IMU_TIMER1_CMP_INTEN_DEFAULT                                       0x00000000
4904 #define regGFX_IMU_TIMER1_CMP0_DEFAULT                                            0x00000000
4905 #define regGFX_IMU_TIMER1_CMP1_DEFAULT                                            0x00000000
4906 #define regGFX_IMU_TIMER1_CMP3_DEFAULT                                            0x00000000
4907 #define regGFX_IMU_TIMER1_VALUE_DEFAULT                                           0x00000000
4908 #define regGFX_IMU_TIMER2_CTRL0_DEFAULT                                           0x00000000
4909 #define regGFX_IMU_TIMER2_CTRL1_DEFAULT                                           0x00000000
4910 #define regGFX_IMU_TIMER2_CMP_AUTOINC_DEFAULT                                     0x00000000
4911 #define regGFX_IMU_TIMER2_CMP_INTEN_DEFAULT                                       0x00000000
4912 #define regGFX_IMU_TIMER2_CMP0_DEFAULT                                            0x00000000
4913 #define regGFX_IMU_TIMER2_CMP1_DEFAULT                                            0x00000000
4914 #define regGFX_IMU_TIMER2_CMP3_DEFAULT                                            0x00000000
4915 #define regGFX_IMU_TIMER2_VALUE_DEFAULT                                           0x00000000
4916 #define regGFX_IMU_FUSE_CTRL_DEFAULT                                              0x00000000
4917 #define regGFX_IMU_D_RAM_ADDR_DEFAULT                                             0x00000000
4918 #define regGFX_IMU_D_RAM_DATA_DEFAULT                                             0x00000000
4919 #define regGFX_IMU_GFX_IH_GASKET_CTRL_DEFAULT                                     0x00000001
4920 
4921 
4922 // addressBlock: gc_gdfll_gdfll_dec
4923 #define regGDFLL_EDC_HYSTERESIS_CNTL_DEFAULT                                      0x00000001
4924 #define regGDFLL_EDC_HYSTERESIS_STAT_DEFAULT                                      0x00000000
4925 
4926 
4927 // addressBlock: gc_gdfll_se_gdfll_dec
4928 #define regGDFLL_SE_EDC_HYSTERESIS_CNTL_DEFAULT                                   0x00000001
4929 #define regGDFLL_SE_EDC_HYSTERESIS_STAT_DEFAULT                                   0x00000000
4930 
4931 
4932 // addressBlock: gc_grtavfs_grtavfs_dec
4933 #define regGRTAVFS_RTAVFS_REG_ADDR_DEFAULT                                        0x00000000
4934 #define regGRTAVFS_RTAVFS_WR_DATA_DEFAULT                                         0x00000000
4935 #define regGRTAVFS_GENERAL_0_DEFAULT                                              0x00000000
4936 #define regGRTAVFS_RTAVFS_RD_DATA_DEFAULT                                         0x00000000
4937 #define regGRTAVFS_RTAVFS_REG_CTRL_DEFAULT                                        0x00000000
4938 #define regGRTAVFS_RTAVFS_REG_STATUS_DEFAULT                                      0x00000000
4939 #define regGRTAVFS_TARG_FREQ_DEFAULT                                              0x00000000
4940 #define regGRTAVFS_TARG_VOLT_DEFAULT                                              0x00000000
4941 #define regGRTAVFS_SOFT_RESET_DEFAULT                                             0x00000001
4942 #define regGRTAVFS_PSM_CNTL_DEFAULT                                               0x00000000
4943 #define regGRTAVFS_CLK_CNTL_DEFAULT                                               0x00000003
4944 
4945 
4946 // addressBlock: gc_grtavfsdec
4947 #define regRTAVFS_RTAVFS_REG_ADDR_DEFAULT                                         0x00000000
4948 #define regRTAVFS_RTAVFS_WR_DATA_DEFAULT                                          0x00000000
4949 
4950 
4951 // addressBlock: gc_grtavfs_se_grtavfs_dec
4952 #define regGRTAVFS_SE_RTAVFS_REG_ADDR_DEFAULT                                     0x00000000
4953 #define regGRTAVFS_SE_RTAVFS_WR_DATA_DEFAULT                                      0x00000000
4954 #define regGRTAVFS_SE_GENERAL_0_DEFAULT                                           0x00000000
4955 #define regGRTAVFS_SE_RTAVFS_RD_DATA_DEFAULT                                      0x00000000
4956 #define regGRTAVFS_SE_RTAVFS_REG_CTRL_DEFAULT                                     0x00000000
4957 #define regGRTAVFS_SE_RTAVFS_REG_STATUS_DEFAULT                                   0x00000000
4958 #define regGRTAVFS_SE_TARG_FREQ_DEFAULT                                           0x00000000
4959 #define regGRTAVFS_SE_TARG_VOLT_DEFAULT                                           0x00000000
4960 #define regGRTAVFS_SE_SOFT_RESET_DEFAULT                                          0x00000001
4961 #define regGRTAVFS_SE_PSM_CNTL_DEFAULT                                            0x00000000
4962 #define regGRTAVFS_SE_CLK_CNTL_DEFAULT                                            0x00000003
4963 
4964 
4965 // addressBlock: gc_rlcdec
4966 #define regRLC_CNTL_DEFAULT                                                       0x00000001
4967 #define regRLC_F32_UCODE_VERSION_DEFAULT                                          0x00000000
4968 #define regRLC_STAT_DEFAULT                                                       0x00000000
4969 #define regRLC_REFCLOCK_TIMESTAMP_LSB_DEFAULT                                     0x00000000
4970 #define regRLC_REFCLOCK_TIMESTAMP_MSB_DEFAULT                                     0x00000000
4971 #define regRLC_GPM_TIMER_INT_0_DEFAULT                                            0x00000063
4972 #define regRLC_GPM_TIMER_INT_1_DEFAULT                                            0x00000063
4973 #define regRLC_GPM_TIMER_INT_2_DEFAULT                                            0x00000063
4974 #define regRLC_GPM_TIMER_INT_3_DEFAULT                                            0x00000063
4975 #define regRLC_GPM_TIMER_INT_4_DEFAULT                                            0x00000063
4976 #define regRLC_GPM_TIMER_CTRL_DEFAULT                                             0x00000000
4977 #define regRLC_GPM_TIMER_STAT_DEFAULT                                             0x00000000
4978 #define regRLC_GPM_LEGACY_INT_STAT_DEFAULT                                        0x00000000
4979 #define regRLC_GPM_LEGACY_INT_CLEAR_DEFAULT                                       0x00000000
4980 #define regRLC_INT_STAT_DEFAULT                                                   0x00000000
4981 #define regRLC_MGCG_CTRL_DEFAULT                                                  0x00000800
4982 #define regRLC_JUMP_TABLE_RESTORE_DEFAULT                                         0x00000000
4983 #define regRLC_PG_DELAY_2_DEFAULT                                                 0x00000004
4984 #define regRLC_GPU_CLOCK_COUNT_LSB_DEFAULT                                        0x00000000
4985 #define regRLC_GPU_CLOCK_COUNT_MSB_DEFAULT                                        0x00000000
4986 #define regRLC_CAPTURE_GPU_CLOCK_COUNT_DEFAULT                                    0x00000000
4987 #define regRLC_UCODE_CNTL_DEFAULT                                                 0x00000000
4988 #define regRLC_GPM_THREAD_RESET_DEFAULT                                           0x00000004
4989 #define regRLC_GPM_CP_DMA_COMPLETE_T0_DEFAULT                                     0x00000000
4990 #define regRLC_GPM_CP_DMA_COMPLETE_T1_DEFAULT                                     0x00000000
4991 #define regRLC_GPM_THREAD_INVALIDATE_CACHE_DEFAULT                                0x00000004
4992 #define regRLC_CLK_COUNT_GFXCLK_LSB_DEFAULT                                       0x00000000
4993 #define regRLC_CLK_COUNT_GFXCLK_MSB_DEFAULT                                       0x00000000
4994 #define regRLC_CLK_COUNT_REFCLK_LSB_DEFAULT                                       0x00000000
4995 #define regRLC_CLK_COUNT_REFCLK_MSB_DEFAULT                                       0x00000000
4996 #define regRLC_CLK_COUNT_CTRL_DEFAULT                                             0x00000000
4997 #define regRLC_CLK_COUNT_STAT_DEFAULT                                             0x00000000
4998 #define regRLC_RLCG_DOORBELL_CNTL_DEFAULT                                         0x00260000
4999 #define regRLC_RLCG_DOORBELL_STAT_DEFAULT                                         0x00000000
5000 #define regRLC_RLCG_DOORBELL_0_DATA_LO_DEFAULT                                    0x00000000
5001 #define regRLC_RLCG_DOORBELL_0_DATA_HI_DEFAULT                                    0x00000000
5002 #define regRLC_RLCG_DOORBELL_1_DATA_LO_DEFAULT                                    0x00000000
5003 #define regRLC_RLCG_DOORBELL_1_DATA_HI_DEFAULT                                    0x00000000
5004 #define regRLC_RLCG_DOORBELL_2_DATA_LO_DEFAULT                                    0x00000000
5005 #define regRLC_RLCG_DOORBELL_2_DATA_HI_DEFAULT                                    0x00000000
5006 #define regRLC_RLCG_DOORBELL_3_DATA_LO_DEFAULT                                    0x00000000
5007 #define regRLC_RLCG_DOORBELL_3_DATA_HI_DEFAULT                                    0x00000000
5008 #define regRLC_GPU_CLOCK_32_RES_SEL_DEFAULT                                       0x00000000
5009 #define regRLC_GPU_CLOCK_32_DEFAULT                                               0x00000000
5010 #define regRLC_PG_CNTL_DEFAULT                                                    0x00000000
5011 #define regRLC_GPM_THREAD_PRIORITY_DEFAULT                                        0x08080808
5012 #define regRLC_GPM_THREAD_ENABLE_DEFAULT                                          0x00000001
5013 #define regRLC_RLCG_DOORBELL_RANGE_DEFAULT                                        0x00000000
5014 #define regRLC_CGTT_MGCG_OVERRIDE_DEFAULT                                         0x000607ff
5015 #define regRLC_CGCG_CGLS_CTRL_DEFAULT                                             0x0001003c
5016 #define regRLC_CGCG_RAMP_CTRL_DEFAULT                                             0x00021711
5017 #define regRLC_DYN_PG_STATUS_DEFAULT                                              0xffffffff
5018 #define regRLC_DYN_PG_REQUEST_DEFAULT                                             0xffffffff
5019 #define regRLC_PG_DELAY_DEFAULT                                                   0x00101010
5020 #define regRLC_WGP_STATUS_DEFAULT                                                 0x00000000
5021 #define regRLC_PG_ALWAYS_ON_WGP_MASK_DEFAULT                                      0x00000003
5022 #define regRLC_MAX_PG_WGP_DEFAULT                                                 0x00000008
5023 #define regRLC_AUTO_PG_CTRL_DEFAULT                                               0x00000000
5024 #define regRLC_SERDES_RD_INDEX_DEFAULT                                            0x00000000
5025 #define regRLC_SERDES_RD_DATA_0_DEFAULT                                           0x00000000
5026 #define regRLC_SERDES_RD_DATA_1_DEFAULT                                           0x00000000
5027 #define regRLC_SERDES_RD_DATA_2_DEFAULT                                           0x00000000
5028 #define regRLC_SERDES_RD_DATA_3_DEFAULT                                           0x00000000
5029 #define regRLC_SERDES_MASK_DEFAULT                                                0x00000000
5030 #define regRLC_SERDES_CTRL_DEFAULT                                                0x00000000
5031 #define regRLC_SERDES_DATA_DEFAULT                                                0x00000000
5032 #define regRLC_SERDES_BUSY_DEFAULT                                                0x00000000
5033 #define regRLC_GPM_GENERAL_0_DEFAULT                                              0x00000000
5034 #define regRLC_GPM_GENERAL_1_DEFAULT                                              0x00000000
5035 #define regRLC_GPM_GENERAL_2_DEFAULT                                              0x00000000
5036 #define regRLC_GPM_GENERAL_3_DEFAULT                                              0x00000000
5037 #define regRLC_GPM_GENERAL_4_DEFAULT                                              0x00000000
5038 #define regRLC_GPM_GENERAL_5_DEFAULT                                              0x00000000
5039 #define regRLC_GPM_GENERAL_6_DEFAULT                                              0x00000000
5040 #define regRLC_GPM_GENERAL_7_DEFAULT                                              0x00000000
5041 #define regRLC_STATIC_PG_STATUS_DEFAULT                                           0xffffffff
5042 #define regRLC_GPM_GENERAL_16_DEFAULT                                             0x00000000
5043 #define regRLC_PG_DELAY_3_DEFAULT                                                 0x00000000
5044 #define regRLC_GPR_REG1_DEFAULT                                                   0x00000000
5045 #define regRLC_GPR_REG2_DEFAULT                                                   0x00000000
5046 #define regRLC_GPM_INT_DISABLE_TH0_DEFAULT                                        0xffffffff
5047 #define regRLC_GPM_LEGACY_INT_DISABLE_DEFAULT                                     0x0000000f
5048 #define regRLC_GPM_INT_FORCE_TH0_DEFAULT                                          0x00000000
5049 #define regRLC_SRM_CNTL_DEFAULT                                                   0x00000002
5050 #define regRLC_SRM_GPM_COMMAND_STATUS_DEFAULT                                     0x00000001
5051 #define regRLC_SRM_INDEX_CNTL_ADDR_0_DEFAULT                                      0x00000000
5052 #define regRLC_SRM_INDEX_CNTL_ADDR_1_DEFAULT                                      0x00000000
5053 #define regRLC_SRM_INDEX_CNTL_ADDR_2_DEFAULT                                      0x00000000
5054 #define regRLC_SRM_INDEX_CNTL_ADDR_3_DEFAULT                                      0x00000000
5055 #define regRLC_SRM_INDEX_CNTL_ADDR_4_DEFAULT                                      0x00000000
5056 #define regRLC_SRM_INDEX_CNTL_ADDR_5_DEFAULT                                      0x00000000
5057 #define regRLC_SRM_INDEX_CNTL_ADDR_6_DEFAULT                                      0x00000000
5058 #define regRLC_SRM_INDEX_CNTL_ADDR_7_DEFAULT                                      0x00000000
5059 #define regRLC_SRM_INDEX_CNTL_DATA_0_DEFAULT                                      0x00000000
5060 #define regRLC_SRM_INDEX_CNTL_DATA_1_DEFAULT                                      0x00000000
5061 #define regRLC_SRM_INDEX_CNTL_DATA_2_DEFAULT                                      0x00000000
5062 #define regRLC_SRM_INDEX_CNTL_DATA_3_DEFAULT                                      0x00000000
5063 #define regRLC_SRM_INDEX_CNTL_DATA_4_DEFAULT                                      0x00000000
5064 #define regRLC_SRM_INDEX_CNTL_DATA_5_DEFAULT                                      0x00000000
5065 #define regRLC_SRM_INDEX_CNTL_DATA_6_DEFAULT                                      0x00000000
5066 #define regRLC_SRM_INDEX_CNTL_DATA_7_DEFAULT                                      0x00000000
5067 #define regRLC_SRM_STAT_DEFAULT                                                   0x00000000
5068 #define regRLC_GPM_GENERAL_8_DEFAULT                                              0x00000000
5069 #define regRLC_GPM_GENERAL_9_DEFAULT                                              0x00000000
5070 #define regRLC_GPM_GENERAL_10_DEFAULT                                             0x00000000
5071 #define regRLC_GPM_GENERAL_11_DEFAULT                                             0x00000000
5072 #define regRLC_GPM_GENERAL_12_DEFAULT                                             0x00000000
5073 #define regRLC_GPM_UTCL1_CNTL_0_DEFAULT                                           0x00000080
5074 #define regRLC_GPM_UTCL1_CNTL_1_DEFAULT                                           0x00000080
5075 #define regRLC_GPM_UTCL1_CNTL_2_DEFAULT                                           0x00000080
5076 #define regRLC_SPM_UTCL1_CNTL_DEFAULT                                             0x00000080
5077 #define regRLC_UTCL1_STATUS_2_DEFAULT                                             0x00000000
5078 #define regRLC_SPM_UTCL1_ERROR_1_DEFAULT                                          0x00000000
5079 #define regRLC_SPM_UTCL1_ERROR_2_DEFAULT                                          0x00000000
5080 #define regRLC_GPM_UTCL1_TH0_ERROR_1_DEFAULT                                      0x00000000
5081 #define regRLC_GPM_UTCL1_TH0_ERROR_2_DEFAULT                                      0x00000000
5082 #define regRLC_GPM_UTCL1_TH1_ERROR_1_DEFAULT                                      0x00000000
5083 #define regRLC_GPM_UTCL1_TH1_ERROR_2_DEFAULT                                      0x00000000
5084 #define regRLC_GPM_UTCL1_TH2_ERROR_1_DEFAULT                                      0x00000000
5085 #define regRLC_GPM_UTCL1_TH2_ERROR_2_DEFAULT                                      0x00000000
5086 #define regRLC_CGCG_CGLS_CTRL_3D_DEFAULT                                          0x0001003c
5087 #define regRLC_CGCG_RAMP_CTRL_3D_DEFAULT                                          0x00021711
5088 #define regRLC_SEMAPHORE_0_DEFAULT                                                0x00000000
5089 #define regRLC_SEMAPHORE_1_DEFAULT                                                0x00000000
5090 #define regRLC_SEMAPHORE_2_DEFAULT                                                0x00000000
5091 #define regRLC_SEMAPHORE_3_DEFAULT                                                0x00000000
5092 #define regRLC_PACE_INT_STAT_DEFAULT                                              0x00000000
5093 #define regRLC_UTCL1_STATUS_DEFAULT                                               0x00000000
5094 #define regRLC_R2I_CNTL_0_DEFAULT                                                 0x00000000
5095 #define regRLC_R2I_CNTL_1_DEFAULT                                                 0x00000000
5096 #define regRLC_R2I_CNTL_2_DEFAULT                                                 0x00000000
5097 #define regRLC_R2I_CNTL_3_DEFAULT                                                 0x00000000
5098 #define regRLC_GPM_INT_STAT_TH0_DEFAULT                                           0x00000000
5099 #define regRLC_GPM_GENERAL_13_DEFAULT                                             0x00000000
5100 #define regRLC_GPM_GENERAL_14_DEFAULT                                             0x00000000
5101 #define regRLC_GPM_GENERAL_15_DEFAULT                                             0x00000000
5102 #define regRLC_CAPTURE_GPU_CLOCK_COUNT_1_DEFAULT                                  0x00000000
5103 #define regRLC_GPU_CLOCK_COUNT_LSB_2_DEFAULT                                      0x00000000
5104 #define regRLC_GPU_CLOCK_COUNT_MSB_2_DEFAULT                                      0x00000000
5105 #define regRLC_PACE_INT_DISABLE_DEFAULT                                           0xffffffff
5106 #define regRLC_CAPTURE_GPU_CLOCK_COUNT_2_DEFAULT                                  0x00000000
5107 #define regRLC_RLCV_DOORBELL_RANGE_DEFAULT                                        0x00000000
5108 #define regRLC_RLCV_DOORBELL_CNTL_DEFAULT                                         0x00260000
5109 #define regRLC_RLCV_DOORBELL_STAT_DEFAULT                                         0x00000000
5110 #define regRLC_RLCV_DOORBELL_0_DATA_LO_DEFAULT                                    0x00000000
5111 #define regRLC_RLCV_DOORBELL_0_DATA_HI_DEFAULT                                    0x00000000
5112 #define regRLC_RLCV_DOORBELL_1_DATA_LO_DEFAULT                                    0x00000000
5113 #define regRLC_RLCV_DOORBELL_1_DATA_HI_DEFAULT                                    0x00000000
5114 #define regRLC_RLCV_DOORBELL_2_DATA_LO_DEFAULT                                    0x00000000
5115 #define regRLC_RLCV_DOORBELL_2_DATA_HI_DEFAULT                                    0x00000000
5116 #define regRLC_RLCV_DOORBELL_3_DATA_LO_DEFAULT                                    0x00000000
5117 #define regRLC_RLCV_DOORBELL_3_DATA_HI_DEFAULT                                    0x00000000
5118 #define regRLC_GPU_CLOCK_COUNT_LSB_1_DEFAULT                                      0x00000000
5119 #define regRLC_GPU_CLOCK_COUNT_MSB_1_DEFAULT                                      0x00000000
5120 #define regRLC_RLCV_SPARE_INT_DEFAULT                                             0x00000000
5121 #define regRLC_PACE_TIMER_INT_0_DEFAULT                                           0x00000063
5122 #define regRLC_PACE_TIMER_INT_1_DEFAULT                                           0x00000063
5123 #define regRLC_PACE_TIMER_CTRL_DEFAULT                                            0x00000000
5124 #define regRLC_SMU_CLK_REQ_DEFAULT                                                0x00000000
5125 #define regRLC_CP_STAT_INVAL_STAT_DEFAULT                                         0x00000000
5126 #define regRLC_CP_STAT_INVAL_CTRL_DEFAULT                                         0x00000007
5127 #define regRLC_SPARE_DEFAULT                                                      0x00000000
5128 #define regRLC_SPP_CTRL_DEFAULT                                                   0x00000000
5129 #define regRLC_SPP_SHADER_PROFILE_EN_DEFAULT                                      0x00000000
5130 #define regRLC_SPP_SSF_CAPTURE_EN_DEFAULT                                         0x00000000
5131 #define regRLC_SPP_SSF_THRESHOLD_0_DEFAULT                                        0x01100110
5132 #define regRLC_SPP_SSF_THRESHOLD_1_DEFAULT                                        0x01100110
5133 #define regRLC_SPP_SSF_THRESHOLD_2_DEFAULT                                        0x01100110
5134 #define regRLC_SPP_INFLIGHT_RD_ADDR_DEFAULT                                       0x00000000
5135 #define regRLC_SPP_INFLIGHT_RD_DATA_DEFAULT                                       0x00000000
5136 #define regRLC_SPP_PROF_INFO_1_DEFAULT                                            0x00000000
5137 #define regRLC_SPP_PROF_INFO_2_DEFAULT                                            0x00000000
5138 #define regRLC_SPP_GLOBAL_SH_ID_DEFAULT                                           0x00000000
5139 #define regRLC_SPP_GLOBAL_SH_ID_VALID_DEFAULT                                     0x00000000
5140 #define regRLC_SPP_STATUS_DEFAULT                                                 0x00000000
5141 #define regRLC_SPP_PVT_STAT_0_DEFAULT                                             0x00000000
5142 #define regRLC_SPP_PVT_STAT_1_DEFAULT                                             0x00000000
5143 #define regRLC_SPP_PVT_STAT_2_DEFAULT                                             0x00000000
5144 #define regRLC_SPP_PVT_STAT_3_DEFAULT                                             0x00000000
5145 #define regRLC_SPP_PVT_LEVEL_MAX_DEFAULT                                          0x00000000
5146 #define regRLC_SPP_STALL_STATE_UPDATE_DEFAULT                                     0x00000000
5147 #define regRLC_SPP_PBB_INFO_DEFAULT                                               0x00000000
5148 #define regRLC_SPP_RESET_DEFAULT                                                  0x00000000
5149 #define regRLC_RLCP_DOORBELL_RANGE_DEFAULT                                        0x00000000
5150 #define regRLC_RLCP_DOORBELL_CNTL_DEFAULT                                         0x00260000
5151 #define regRLC_RLCP_DOORBELL_STAT_DEFAULT                                         0x00000000
5152 #define regRLC_RLCP_DOORBELL_0_DATA_LO_DEFAULT                                    0x00000000
5153 #define regRLC_RLCP_DOORBELL_0_DATA_HI_DEFAULT                                    0x00000000
5154 #define regRLC_RLCP_DOORBELL_1_DATA_LO_DEFAULT                                    0x00000000
5155 #define regRLC_RLCP_DOORBELL_1_DATA_HI_DEFAULT                                    0x00000000
5156 #define regRLC_RLCP_DOORBELL_2_DATA_LO_DEFAULT                                    0x00000000
5157 #define regRLC_RLCP_DOORBELL_2_DATA_HI_DEFAULT                                    0x00000000
5158 #define regRLC_RLCP_DOORBELL_3_DATA_LO_DEFAULT                                    0x00000000
5159 #define regRLC_RLCP_DOORBELL_3_DATA_HI_DEFAULT                                    0x00000000
5160 #define regRLC_CAC_MASK_CNTL_DEFAULT                                              0x000000bf
5161 #define regRLC_POWER_RESIDENCY_CNTR_CTRL_DEFAULT                                  0x00000000
5162 #define regRLC_CLK_RESIDENCY_CNTR_CTRL_DEFAULT                                    0x00000000
5163 #define regRLC_DS_RESIDENCY_CNTR_CTRL_DEFAULT                                     0x00000000
5164 #define regRLC_ULV_RESIDENCY_CNTR_CTRL_DEFAULT                                    0x00000000
5165 #define regRLC_PCC_RESIDENCY_CNTR_CTRL_DEFAULT                                    0x00000000
5166 #define regRLC_GENERAL_RESIDENCY_CNTR_CTRL_DEFAULT                                0x00000000
5167 #define regRLC_POWER_RESIDENCY_EVENT_CNTR_DEFAULT                                 0x00000000
5168 #define regRLC_CLK_RESIDENCY_EVENT_CNTR_DEFAULT                                   0x00000000
5169 #define regRLC_DS_RESIDENCY_EVENT_CNTR_DEFAULT                                    0x00000000
5170 #define regRLC_ULV_RESIDENCY_EVENT_CNTR_DEFAULT                                   0x00000000
5171 #define regRLC_PCC_RESIDENCY_EVENT_CNTR_DEFAULT                                   0x00000000
5172 #define regRLC_GENERAL_RESIDENCY_EVENT_CNTR_DEFAULT                               0x00000000
5173 #define regRLC_POWER_RESIDENCY_REF_CNTR_DEFAULT                                   0x00000000
5174 #define regRLC_CLK_RESIDENCY_REF_CNTR_DEFAULT                                     0x00000000
5175 #define regRLC_DS_RESIDENCY_REF_CNTR_DEFAULT                                      0x00000000
5176 #define regRLC_ULV_RESIDENCY_REF_CNTR_DEFAULT                                     0x00000000
5177 #define regRLC_PCC_RESIDENCY_REF_CNTR_DEFAULT                                     0x00000000
5178 #define regRLC_GENERAL_RESIDENCY_REF_CNTR_DEFAULT                                 0x00000000
5179 #define regRLC_GFX_IH_CLIENT_CTRL_DEFAULT                                         0x00000000
5180 #define regRLC_GFX_IH_ARBITER_STAT_DEFAULT                                        0x00000000
5181 #define regRLC_GFX_IH_CLIENT_SE_STAT_L_DEFAULT                                    0x00000000
5182 #define regRLC_GFX_IH_CLIENT_SE_STAT_H_DEFAULT                                    0x00000000
5183 #define regRLC_GFX_IH_CLIENT_SDMA_STAT_DEFAULT                                    0x00000000
5184 #define regRLC_GFX_IH_CLIENT_OTHER_STAT_DEFAULT                                   0x00000000
5185 #define regRLC_SPM_GLOBAL_DELAY_IND_ADDR_DEFAULT                                  0x00000000
5186 #define regRLC_SPM_GLOBAL_DELAY_IND_DATA_DEFAULT                                  0x00000000
5187 #define regRLC_SPM_SE_DELAY_IND_ADDR_DEFAULT                                      0x00000000
5188 #define regRLC_SPM_SE_DELAY_IND_DATA_DEFAULT                                      0x00000000
5189 #define regRLC_LX6_CNTL_DEFAULT                                                   0x00000001
5190 #define regRLC_XT_CORE_STATUS_DEFAULT                                             0x00000000
5191 #define regRLC_XT_CORE_INTERRUPT_DEFAULT                                          0x00000000
5192 #define regRLC_XT_CORE_FAULT_INFO_DEFAULT                                         0x00000000
5193 #define regRLC_XT_CORE_ALT_RESET_VEC_DEFAULT                                      0x00000000
5194 #define regRLC_XT_CORE_RESERVED_DEFAULT                                           0x00000000
5195 #define regRLC_XT_INT_VEC_FORCE_DEFAULT                                           0x00000000
5196 #define regRLC_XT_INT_VEC_CLEAR_DEFAULT                                           0x00000000
5197 #define regRLC_XT_INT_VEC_MUX_SEL_DEFAULT                                         0x00000000
5198 #define regRLC_XT_INT_VEC_MUX_INT_SEL_DEFAULT                                     0x00000000
5199 #define regRLC_GPU_CLOCK_COUNT_SPM_LSB_DEFAULT                                    0x00000000
5200 #define regRLC_GPU_CLOCK_COUNT_SPM_MSB_DEFAULT                                    0x00000000
5201 #define regRLC_SPM_THREAD_TRACE_CTRL_DEFAULT                                      0x00000000
5202 #define regRLC_SPP_CAM_ADDR_DEFAULT                                               0x00000000
5203 #define regRLC_SPP_CAM_DATA_DEFAULT                                               0x00000000
5204 #define regRLC_SPP_CAM_EXT_ADDR_DEFAULT                                           0x00000000
5205 #define regRLC_SPP_CAM_EXT_DATA_DEFAULT                                           0x00000000
5206 #define regRLC_XT_DOORBELL_RANGE_DEFAULT                                          0x00000000
5207 #define regRLC_XT_DOORBELL_CNTL_DEFAULT                                           0x00260000
5208 #define regRLC_XT_DOORBELL_STAT_DEFAULT                                           0x00000000
5209 #define regRLC_XT_DOORBELL_0_DATA_LO_DEFAULT                                      0x00000000
5210 #define regRLC_XT_DOORBELL_0_DATA_HI_DEFAULT                                      0x00000000
5211 #define regRLC_XT_DOORBELL_1_DATA_LO_DEFAULT                                      0x00000000
5212 #define regRLC_XT_DOORBELL_1_DATA_HI_DEFAULT                                      0x00000000
5213 #define regRLC_XT_DOORBELL_2_DATA_LO_DEFAULT                                      0x00000000
5214 #define regRLC_XT_DOORBELL_2_DATA_HI_DEFAULT                                      0x00000000
5215 #define regRLC_XT_DOORBELL_3_DATA_LO_DEFAULT                                      0x00000000
5216 #define regRLC_XT_DOORBELL_3_DATA_HI_DEFAULT                                      0x00000000
5217 #define regRLC_MEM_SLP_CNTL_DEFAULT                                               0x00020200
5218 #define regSMU_RLC_RESPONSE_DEFAULT                                               0x00000000
5219 #define regRLC_RLCV_SAFE_MODE_DEFAULT                                             0x00000000
5220 #define regRLC_SMU_SAFE_MODE_DEFAULT                                              0x00000000
5221 #define regRLC_RLCV_COMMAND_DEFAULT                                               0x00000000
5222 #define regRLC_SMU_MESSAGE_DEFAULT                                                0x00000000
5223 #define regRLC_SMU_MESSAGE_1_DEFAULT                                              0x00000000
5224 #define regRLC_SMU_MESSAGE_2_DEFAULT                                              0x00000000
5225 #define regRLC_SRM_GPM_COMMAND_DEFAULT                                            0x00000000
5226 #define regRLC_SRM_GPM_ABORT_DEFAULT                                              0x00000000
5227 #define regRLC_SMU_COMMAND_DEFAULT                                                0x00000000
5228 #define regRLC_SMU_ARGUMENT_1_DEFAULT                                             0x00000000
5229 #define regRLC_SMU_ARGUMENT_2_DEFAULT                                             0x00000000
5230 #define regRLC_SMU_ARGUMENT_3_DEFAULT                                             0x00000000
5231 #define regRLC_SMU_ARGUMENT_4_DEFAULT                                             0x00000000
5232 #define regRLC_SMU_ARGUMENT_5_DEFAULT                                             0x00000000
5233 #define regRLC_IMU_BOOTLOAD_ADDR_HI_DEFAULT                                       0x00000000
5234 #define regRLC_IMU_BOOTLOAD_ADDR_LO_DEFAULT                                       0x00000000
5235 #define regRLC_IMU_BOOTLOAD_SIZE_DEFAULT                                          0x00000000
5236 #define regRLC_IMU_MISC_DEFAULT                                                   0x00000000
5237 #define regRLC_IMU_RESET_VECTOR_DEFAULT                                           0x00000000
5238 
5239 
5240 // addressBlock: gc_rlcsdec
5241 #define regRLC_RLCS_DEC_START_DEFAULT                                             0x00000000
5242 #define regRLC_RLCS_DEC_DUMP_ADDR_DEFAULT                                         0x00000000
5243 #define regRLC_RLCS_EXCEPTION_REG_1_DEFAULT                                       0x0003b984
5244 #define regRLC_RLCS_EXCEPTION_REG_2_DEFAULT                                       0x0003b984
5245 #define regRLC_RLCS_EXCEPTION_REG_3_DEFAULT                                       0x0003b984
5246 #define regRLC_RLCS_EXCEPTION_REG_4_DEFAULT                                       0x0003b984
5247 #define regRLC_RLCS_CGCG_REQUEST_DEFAULT                                          0x00000003
5248 #define regRLC_RLCS_CGCG_STATUS_DEFAULT                                           0x00000024
5249 #define regRLC_RLCS_SOC_DS_CNTL_DEFAULT                                           0x00ff00c6
5250 #define regRLC_RLCS_GFX_DS_CNTL_DEFAULT                                           0x00ff01c6
5251 #define regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL_DEFAULT                                0x0000007f
5252 #define regRLC_GPM_STAT_DEFAULT                                                   0x00b40016
5253 #define regRLC_RLCS_GPM_STAT_DEFAULT                                              0x00b40016
5254 #define regRLC_RLCS_ABORTED_PD_SEQUENCE_DEFAULT                                   0x00000000
5255 #define regRLC_RLCS_DIDT_FORCE_STALL_DEFAULT                                      0x00000000
5256 #define regRLC_RLCS_IOV_CMD_STATUS_DEFAULT                                        0x00000000
5257 #define regRLC_RLCS_IOV_CNTX_LOC_SIZE_DEFAULT                                     0x00000000
5258 #define regRLC_RLCS_IOV_SCH_BLOCK_DEFAULT                                         0x00000000
5259 #define regRLC_RLCS_IOV_VM_BUSY_STATUS_DEFAULT                                    0x00000000
5260 #define regRLC_RLCS_GPM_STAT_2_DEFAULT                                            0x00000000
5261 #define regRLC_RLCS_GRBM_SOFT_RESET_DEFAULT                                       0x00000001
5262 #define regRLC_RLCS_PG_CHANGE_STATUS_DEFAULT                                      0x00000000
5263 #define regRLC_RLCS_PG_CHANGE_READ_DEFAULT                                        0x00000000
5264 #define regRLC_RLCS_IH_SEMAPHORE_DEFAULT                                          0x00000000
5265 #define regRLC_RLCS_IH_COOKIE_SEMAPHORE_DEFAULT                                   0x00000000
5266 #define regRLC_RLCS_WGP_STATUS_DEFAULT                                            0x00000000
5267 #define regRLC_RLCS_WGP_READ_DEFAULT                                              0x00000000
5268 #define regRLC_RLCS_CP_INT_CTRL_1_DEFAULT                                         0x00000000
5269 #define regRLC_RLCS_CP_INT_CTRL_2_DEFAULT                                         0x00000000
5270 #define regRLC_RLCS_CP_INT_INFO_1_DEFAULT                                         0x00000000
5271 #define regRLC_RLCS_CP_INT_INFO_2_DEFAULT                                         0x00000000
5272 #define regRLC_RLCS_SPM_INT_CTRL_DEFAULT                                          0x00000000
5273 #define regRLC_RLCS_SPM_INT_INFO_1_DEFAULT                                        0x00000000
5274 #define regRLC_RLCS_SPM_INT_INFO_2_DEFAULT                                        0x00000000
5275 #define regRLC_RLCS_DSM_TRIG_DEFAULT                                              0x00000000
5276 #define regRLC_RLCS_BOOTLOAD_STATUS_DEFAULT                                       0x00000000
5277 #define regRLC_RLCS_POWER_BRAKE_CNTL_DEFAULT                                      0x00000004
5278 #define regRLC_RLCS_POWER_BRAKE_CNTL_TH1_DEFAULT                                  0x00000004
5279 #define regRLC_RLCS_GRBM_IDLE_BUSY_STAT_DEFAULT                                   0x00000000
5280 #define regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_DEFAULT                               0x00000000
5281 #define regRLC_RLCS_CMP_IDLE_CNTL_DEFAULT                                         0x00000100
5282 #define regRLC_RLCS_GENERAL_0_DEFAULT                                             0x00000000
5283 #define regRLC_RLCS_GENERAL_1_DEFAULT                                             0x00000000
5284 #define regRLC_RLCS_GENERAL_2_DEFAULT                                             0x00000000
5285 #define regRLC_RLCS_GENERAL_3_DEFAULT                                             0x00000000
5286 #define regRLC_RLCS_GENERAL_4_DEFAULT                                             0x00000000
5287 #define regRLC_RLCS_GENERAL_5_DEFAULT                                             0x00000000
5288 #define regRLC_RLCS_GENERAL_6_DEFAULT                                             0x00000000
5289 #define regRLC_RLCS_GENERAL_7_DEFAULT                                             0x00000000
5290 #define regRLC_RLCS_GENERAL_8_DEFAULT                                             0x00000000
5291 #define regRLC_RLCS_GENERAL_9_DEFAULT                                             0x00000000
5292 #define regRLC_RLCS_GENERAL_10_DEFAULT                                            0x00000000
5293 #define regRLC_RLCS_GENERAL_11_DEFAULT                                            0x00000000
5294 #define regRLC_RLCS_GENERAL_12_DEFAULT                                            0x00000000
5295 #define regRLC_RLCS_GENERAL_13_DEFAULT                                            0x00000000
5296 #define regRLC_RLCS_GENERAL_14_DEFAULT                                            0x00000000
5297 #define regRLC_RLCS_GENERAL_15_DEFAULT                                            0x00000000
5298 #define regRLC_RLCS_GENERAL_16_DEFAULT                                            0x00000000
5299 #define regRLC_RLCS_AUXILIARY_REG_1_DEFAULT                                       0x0003b984
5300 #define regRLC_RLCS_AUXILIARY_REG_2_DEFAULT                                       0x0003b984
5301 #define regRLC_RLCS_AUXILIARY_REG_3_DEFAULT                                       0x0003b984
5302 #define regRLC_RLCS_AUXILIARY_REG_4_DEFAULT                                       0x0003b984
5303 #define regRLC_RLCS_SPM_SQTT_MODE_DEFAULT                                         0x00000000
5304 #define regRLC_RLCS_CP_DMA_SRCID_OVER_DEFAULT                                     0x00000000
5305 #define regRLC_RLCS_BOOTLOAD_ID_STATUS1_DEFAULT                                   0x00000000
5306 #define regRLC_RLCS_BOOTLOAD_ID_STATUS2_DEFAULT                                   0x00000000
5307 #define regRLC_RLCS_IMU_VIDCHG_CNTL_DEFAULT                                       0x00000000
5308 #define regRLC_RLCS_EDC_INT_CNTL_DEFAULT                                          0x00000000
5309 #define regRLC_RLCS_KMD_LOG_CNTL1_DEFAULT                                         0x00000000
5310 #define regRLC_RLCS_KMD_LOG_CNTL2_DEFAULT                                         0x00000000
5311 #define regRLC_RLCS_GPM_LEGACY_INT_STAT_DEFAULT                                   0x00000000
5312 #define regRLC_RLCS_GPM_LEGACY_INT_DISABLE_DEFAULT                                0x00000003
5313 #define regRLC_RLCS_SRM_SRCID_CNTL_DEFAULT                                        0x00000006
5314 #define regRLC_RLCS_GCR_DATA_0_DEFAULT                                            0x00000000
5315 #define regRLC_RLCS_GCR_DATA_1_DEFAULT                                            0x00000000
5316 #define regRLC_RLCS_GCR_DATA_2_DEFAULT                                            0x00000000
5317 #define regRLC_RLCS_GCR_DATA_3_DEFAULT                                            0x00000000
5318 #define regRLC_RLCS_GCR_STATUS_DEFAULT                                            0x00000000
5319 #define regRLC_RLCS_PERFMON_CLK_CNTL_UCODE_DEFAULT                                0x00000001
5320 #define regRLC_RLCS_UTCL2_CNTL_DEFAULT                                            0x00000018
5321 #define regRLC_RLCS_IMU_RLC_MSG_DATA0_DEFAULT                                     0x00000000
5322 #define regRLC_RLCS_IMU_RLC_MSG_DATA1_DEFAULT                                     0x00000000
5323 #define regRLC_RLCS_IMU_RLC_MSG_DATA2_DEFAULT                                     0x00000000
5324 #define regRLC_RLCS_IMU_RLC_MSG_DATA3_DEFAULT                                     0x00000000
5325 #define regRLC_RLCS_IMU_RLC_MSG_DATA4_DEFAULT                                     0x00000000
5326 #define regRLC_RLCS_IMU_RLC_MSG_CONTROL_DEFAULT                                   0x00000000
5327 #define regRLC_RLCS_IMU_RLC_MSG_CNTL_DEFAULT                                      0x00000000
5328 #define regRLC_RLCS_RLC_IMU_MSG_DATA0_DEFAULT                                     0x00000000
5329 #define regRLC_RLCS_RLC_IMU_MSG_CONTROL_DEFAULT                                   0x00000000
5330 #define regRLC_RLCS_RLC_IMU_MSG_CNTL_DEFAULT                                      0x00000000
5331 #define regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0_DEFAULT                              0x00000000
5332 #define regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1_DEFAULT                              0x00000000
5333 #define regRLC_RLCS_IMU_RLC_MUTEX_CNTL_DEFAULT                                    0x00000000
5334 #define regRLC_RLCS_IMU_RLC_STATUS_DEFAULT                                        0x00000000
5335 #define regRLC_RLCS_RLC_IMU_STATUS_DEFAULT                                        0x00000000
5336 #define regRLC_RLCS_IMU_RAM_DATA_1_DEFAULT                                        0x00000000
5337 #define regRLC_RLCS_IMU_RAM_ADDR_1_LSB_DEFAULT                                    0x00000000
5338 #define regRLC_RLCS_IMU_RAM_ADDR_1_MSB_DEFAULT                                    0x00000000
5339 #define regRLC_RLCS_IMU_RAM_DATA_0_DEFAULT                                        0x00000000
5340 #define regRLC_RLCS_IMU_RAM_ADDR_0_LSB_DEFAULT                                    0x00000000
5341 #define regRLC_RLCS_IMU_RAM_ADDR_0_MSB_DEFAULT                                    0x00000000
5342 #define regRLC_RLCS_IMU_RAM_CNTL_DEFAULT                                          0x00000000
5343 #define regRLC_RLCS_IMU_GFX_DOORBELL_FENCE_DEFAULT                                0x00000001
5344 #define regRLC_RLCS_SDMA_INT_CNTL_1_DEFAULT                                       0x00000000
5345 #define regRLC_RLCS_SDMA_INT_CNTL_2_DEFAULT                                       0x00000000
5346 #define regRLC_RLCS_SDMA_INT_STAT_DEFAULT                                         0x00000300
5347 #define regRLC_RLCS_SDMA_INT_INFO_DEFAULT                                         0x00000000
5348 #define regRLC_RLCS_PMM_CGCG_CNTL_DEFAULT                                         0x00000000
5349 #define regRLC_RLCS_GFX_MEM_POWER_CTRL_LO_DEFAULT                                 0x00000000
5350 #define regRLC_RLCS_GFX_RM_CNTL_DEFAULT                                           0x00000000
5351 #define regRLC_RLCS_DEC_END_DEFAULT                                               0x00000000
5352 
5353 
5354 // addressBlock: gc_pwrdec
5355 #define regCGTS_TCC_DISABLE_DEFAULT                                               0x00000000
5356 #define regCGTT_GS_NGG_CLK_CTRL_DEFAULT                                           0x00018000
5357 #define regCGTT_PA_CLK_CTRL_DEFAULT                                               0x00000000
5358 #define regCGTT_SC_CLK_CTRL0_DEFAULT                                              0x00000100
5359 #define regCGTT_SC_CLK_CTRL1_DEFAULT                                              0x00000100
5360 #define regCGTT_SC_CLK_CTRL2_DEFAULT                                              0x00020100
5361 #define regCGTT_SQG_CLK_CTRL_DEFAULT                                              0x00000100
5362 #define regSQ_ALU_CLK_CTRL_DEFAULT                                                0x00000000
5363 #define regSQ_TEX_CLK_CTRL_DEFAULT                                                0x00000000
5364 #define regSQ_LDS_CLK_CTRL_DEFAULT                                                0x00000000
5365 #define regICG_SP_CLK_CTRL_DEFAULT                                                0x00000000
5366 #define regTA_CGTT_CTRL_DEFAULT                                                   0x00000100
5367 #define regDB_CGTT_CLK_CTRL_0_DEFAULT                                             0x00000000
5368 #define regCB_CGTT_SCLK_CTRL_DEFAULT                                              0x00000100
5369 #define regCGTT_CP_CLK_CTRL_DEFAULT                                               0x00000100
5370 #define regCGTT_CPF_CLK_CTRL_DEFAULT                                              0x00000100
5371 #define regCGTT_CPC_CLK_CTRL_DEFAULT                                              0x00000100
5372 #define regCGTT_RLC_CLK_CTRL_DEFAULT                                              0x00000000
5373 #define regCGTT_SC_CLK_CTRL3_DEFAULT                                              0x00000000
5374 #define regCGTT_SC_CLK_CTRL4_DEFAULT                                              0x00000000
5375 #define regGCEA_ICG_CTRL_DEFAULT                                                  0x00000000
5376 #define regGL1I_GL1R_MGCG_OVERRIDE_DEFAULT                                        0x00000000
5377 #define regGL1H_ICG_CTRL_DEFAULT                                                  0x00000000
5378 #define regCHI_CHR_MGCG_OVERRIDE_DEFAULT                                          0x00000000
5379 #define regICG_GL1C_CLK_CTRL_DEFAULT                                              0x00000000
5380 #define regICG_GL1A_CTRL_DEFAULT                                                  0x00000000
5381 #define regICG_CHA_CTRL_DEFAULT                                                   0x00000000
5382 #define regGUS_ICG_CTRL_DEFAULT                                                   0x00000000
5383 #define regCGTT_PH_CLK_CTRL0_DEFAULT                                              0x00000100
5384 #define regCGTT_PH_CLK_CTRL1_DEFAULT                                              0x00000100
5385 #define regCGTT_PH_CLK_CTRL2_DEFAULT                                              0x00000100
5386 #define regCGTT_PH_CLK_CTRL3_DEFAULT                                              0x00000100
5387 #define regGFX_ICG_GL2C_CTRL_DEFAULT                                              0x00000000
5388 #define regGFX_ICG_GL2C_CTRL1_DEFAULT                                             0x00000000
5389 #define regICG_LDS_CLK_CTRL_DEFAULT                                               0x00000000
5390 #define regICG_CHC_CLK_CTRL_DEFAULT                                               0x00000000
5391 #define regICG_CHCG_CLK_CTRL_DEFAULT                                              0x00000000
5392 
5393 
5394 // addressBlock: gc_cphypdec
5395 #define regCP_HYP_PFP_UCODE_ADDR_DEFAULT                                          0x00000000
5396 #define regCP_PFP_UCODE_ADDR_DEFAULT                                              0x00000000
5397 #define regCP_HYP_PFP_UCODE_DATA_DEFAULT                                          0x00000000
5398 #define regCP_PFP_UCODE_DATA_DEFAULT                                              0x00000000
5399 #define regCP_HYP_ME_UCODE_ADDR_DEFAULT                                           0x00000000
5400 #define regCP_ME_RAM_RADDR_DEFAULT                                                0x00000000
5401 #define regCP_ME_RAM_WADDR_DEFAULT                                                0x00000000
5402 #define regCP_HYP_ME_UCODE_DATA_DEFAULT                                           0x00000000
5403 #define regCP_ME_RAM_DATA_DEFAULT                                                 0x00000000
5404 #define regCP_HYP_MEC1_UCODE_ADDR_DEFAULT                                         0x00000000
5405 #define regCP_MEC_ME1_UCODE_ADDR_DEFAULT                                          0x00000000
5406 #define regCP_HYP_MEC1_UCODE_DATA_DEFAULT                                         0x00000000
5407 #define regCP_MEC_ME1_UCODE_DATA_DEFAULT                                          0x00000000
5408 #define regCP_HYP_MEC2_UCODE_ADDR_DEFAULT                                         0x00000000
5409 #define regCP_MEC_ME2_UCODE_ADDR_DEFAULT                                          0x00000000
5410 #define regCP_HYP_MEC2_UCODE_DATA_DEFAULT                                         0x00000000
5411 #define regCP_MEC_ME2_UCODE_DATA_DEFAULT                                          0x00000000
5412 #define regCP_PFP_IC_BASE_LO_DEFAULT                                              0x00000000
5413 #define regCP_PFP_IC_BASE_HI_DEFAULT                                              0x00000000
5414 #define regCP_PFP_IC_BASE_CNTL_DEFAULT                                            0x00000010
5415 #define regCP_PFP_IC_OP_CNTL_DEFAULT                                              0x00000000
5416 #define regCP_ME_IC_BASE_LO_DEFAULT                                               0x00000000
5417 #define regCP_ME_IC_BASE_HI_DEFAULT                                               0x00000000
5418 #define regCP_ME_IC_BASE_CNTL_DEFAULT                                             0x00000010
5419 #define regCP_ME_IC_OP_CNTL_DEFAULT                                               0x00000000
5420 #define regCP_CPC_IC_BASE_LO_DEFAULT                                              0x00000000
5421 #define regCP_CPC_IC_BASE_HI_DEFAULT                                              0x00000000
5422 #define regCP_CPC_IC_BASE_CNTL_DEFAULT                                            0x00000010
5423 #define regCP_MES_IC_BASE_LO_DEFAULT                                              0x00000000
5424 #define regCP_MES_MIBASE_LO_DEFAULT                                               0x00000000
5425 #define regCP_MES_IC_BASE_HI_DEFAULT                                              0x00000000
5426 #define regCP_MES_MIBASE_HI_DEFAULT                                               0x00000000
5427 #define regCP_MES_IC_BASE_CNTL_DEFAULT                                            0x00000000
5428 #define regCP_MES_DC_BASE_LO_DEFAULT                                              0x00000000
5429 #define regCP_MES_MDBASE_LO_DEFAULT                                               0x00000000
5430 #define regCP_MES_DC_BASE_HI_DEFAULT                                              0x00000000
5431 #define regCP_MES_MDBASE_HI_DEFAULT                                               0x00000000
5432 #define regCP_MES_MIBOUND_LO_DEFAULT                                              0x0000ffff
5433 #define regCP_MES_MIBOUND_HI_DEFAULT                                              0x00000000
5434 #define regCP_MES_MDBOUND_LO_DEFAULT                                              0x0000ffff
5435 #define regCP_MES_MDBOUND_HI_DEFAULT                                              0x0000ffff
5436 #define regCP_GFX_RS64_DC_BASE0_LO_DEFAULT                                        0x00000000
5437 #define regCP_GFX_RS64_DC_BASE1_LO_DEFAULT                                        0x00000000
5438 #define regCP_GFX_RS64_DC_BASE0_HI_DEFAULT                                        0x00000000
5439 #define regCP_GFX_RS64_DC_BASE1_HI_DEFAULT                                        0x00000000
5440 #define regCP_GFX_RS64_MIBOUND_LO_DEFAULT                                         0x000fffff
5441 #define regCP_GFX_RS64_MIBOUND_HI_DEFAULT                                         0x000fffff
5442 #define regCP_MEC_DC_BASE_LO_DEFAULT                                              0x00000000
5443 #define regCP_MEC_MDBASE_LO_DEFAULT                                               0x00000000
5444 #define regCP_MEC_DC_BASE_HI_DEFAULT                                              0x00000000
5445 #define regCP_MEC_MDBASE_HI_DEFAULT                                               0x00000000
5446 #define regCP_MEC_MIBOUND_LO_DEFAULT                                              0x0000ffff
5447 #define regCP_MEC_MIBOUND_HI_DEFAULT                                              0x00000000
5448 #define regCP_MEC_MDBOUND_LO_DEFAULT                                              0x0000ffff
5449 #define regCP_MEC_MDBOUND_HI_DEFAULT                                              0x0000ffff
5450 
5451 
5452 // addressBlock: gc_hypdec
5453 #define regGFX_PIPE_PRIORITY_DEFAULT                                              0x00000001
5454 #define regGRBM_GFX_INDEX_SR_SELECT_DEFAULT                                       0x00000000
5455 #define regGRBM_GFX_INDEX_SR_DATA_DEFAULT                                         0xe0000000
5456 #define regGRBM_GFX_CNTL_SR_SELECT_DEFAULT                                        0x00000000
5457 #define regGRBM_GFX_CNTL_SR_DATA_DEFAULT                                          0x00000000
5458 #define regGC_IH_COOKIE_0_PTR_DEFAULT                                             0x00004300
5459 #define regGRBM_SE_REMAP_CNTL_DEFAULT                                             0xeca86420
5460 #define regRLC_GPU_IOV_VF_ENABLE_DEFAULT                                          0x00000000
5461 #define regRLC_GPU_IOV_CFG_REG6_DEFAULT                                           0x00000000
5462 #define regRLC_SDMA0_STATUS_DEFAULT                                               0x00000000
5463 #define regRLC_SDMA1_STATUS_DEFAULT                                               0x00000000
5464 #define regRLC_SDMA2_STATUS_DEFAULT                                               0x00000000
5465 #define regRLC_SDMA3_STATUS_DEFAULT                                               0x00000000
5466 #define regRLC_SDMA0_BUSY_STATUS_DEFAULT                                          0x00000000
5467 #define regRLC_SDMA1_BUSY_STATUS_DEFAULT                                          0x00000000
5468 #define regRLC_SDMA2_BUSY_STATUS_DEFAULT                                          0x00000000
5469 #define regRLC_SDMA3_BUSY_STATUS_DEFAULT                                          0x00000000
5470 #define regRLC_GPU_IOV_CFG_REG8_DEFAULT                                           0x00000000
5471 #define regRLC_RLCV_TIMER_INT_0_DEFAULT                                           0x00000063
5472 #define regRLC_RLCV_TIMER_INT_1_DEFAULT                                           0x00000063
5473 #define regRLC_RLCV_TIMER_CTRL_DEFAULT                                            0x00000000
5474 #define regRLC_RLCV_TIMER_STAT_DEFAULT                                            0x00000000
5475 #define regRLC_GPU_IOV_VF_DOORBELL_STATUS_DEFAULT                                 0x7fffffff
5476 #define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_DEFAULT                             0x00000000
5477 #define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_DEFAULT                             0x00000000
5478 #define regRLC_GPU_IOV_VF_MASK_DEFAULT                                            0x7fffffff
5479 #define regRLC_HYP_SEMAPHORE_0_DEFAULT                                            0x00000000
5480 #define regRLC_HYP_SEMAPHORE_1_DEFAULT                                            0x00000000
5481 #define regRLC_BUSY_CLK_CNTL_DEFAULT                                              0x00000800
5482 #define regRLC_CLK_CNTL_DEFAULT                                                   0x00000000
5483 #define regRLC_PACE_TIMER_STAT_DEFAULT                                            0x00000000
5484 #define regRLC_GPU_IOV_SCH_BLOCK_DEFAULT                                          0x00000000
5485 #define regRLC_GPU_IOV_CFG_REG1_DEFAULT                                           0x00000000
5486 #define regRLC_GPU_IOV_CFG_REG2_DEFAULT                                           0x00000000
5487 #define regRLC_GPU_IOV_VM_BUSY_STATUS_DEFAULT                                     0x00000000
5488 #define regRLC_GPU_IOV_SCH_0_DEFAULT                                              0x00000000
5489 #define regRLC_GPU_IOV_SCH_3_DEFAULT                                              0x00000000
5490 #define regRLC_GPU_IOV_SCH_1_DEFAULT                                              0x00000000
5491 #define regRLC_GPU_IOV_SCH_2_DEFAULT                                              0x00000000
5492 #define regRLC_PACE_INT_FORCE_DEFAULT                                             0x00000000
5493 #define regRLC_PACE_INT_CLEAR_DEFAULT                                             0x00000000
5494 #define regRLC_GPU_IOV_INT_STAT_DEFAULT                                           0x00000000
5495 #define regRLC_IH_COOKIE_DEFAULT                                                  0x00000000
5496 #define regRLC_IH_COOKIE_CNTL_DEFAULT                                             0x00000002
5497 #define regRLC_HYP_RLCG_UCODE_CHKSUM_DEFAULT                                      0x00000000
5498 #define regRLC_HYP_RLCP_UCODE_CHKSUM_DEFAULT                                      0x00000000
5499 #define regRLC_HYP_RLCV_UCODE_CHKSUM_DEFAULT                                      0x00000000
5500 #define regRLC_GPU_IOV_F32_CNTL_DEFAULT                                           0x00000000
5501 #define regRLC_GPU_IOV_F32_RESET_DEFAULT                                          0x00000000
5502 #define regRLC_GPU_IOV_UCODE_ADDR_DEFAULT                                         0x00000000
5503 #define regRLC_GPU_IOV_UCODE_DATA_DEFAULT                                         0x00000000
5504 #define regRLC_GPU_IOV_SMU_RESPONSE_DEFAULT                                       0x00000000
5505 #define regRLC_GPU_IOV_F32_INVALIDATE_CACHE_DEFAULT                               0x00000000
5506 #define regRLC_GPU_IOV_RLC_RESPONSE_DEFAULT                                       0x00000000
5507 #define regRLC_GPU_IOV_INT_DISABLE_DEFAULT                                        0xffffffff
5508 #define regRLC_GPU_IOV_INT_FORCE_DEFAULT                                          0x00000000
5509 #define regRLC_GPU_IOV_SCRATCH_ADDR_DEFAULT                                       0x00000000
5510 #define regRLC_GPU_IOV_SCRATCH_DATA_DEFAULT                                       0x00000000
5511 #define regRLC_HYP_SEMAPHORE_2_DEFAULT                                            0x00000000
5512 #define regRLC_HYP_SEMAPHORE_3_DEFAULT                                            0x00000000
5513 #define regRLC_GPM_UCODE_ADDR_DEFAULT                                             0x00000000
5514 #define regRLC_GPM_UCODE_DATA_DEFAULT                                             0x00000000
5515 #define regRLC_GPM_IRAM_ADDR_DEFAULT                                              0x00000000
5516 #define regRLC_GPM_IRAM_DATA_DEFAULT                                              0x00000000
5517 #define regRLC_RLCP_IRAM_ADDR_DEFAULT                                             0x00000000
5518 #define regRLC_RLCP_IRAM_DATA_DEFAULT                                             0x00000000
5519 #define regRLC_RLCV_IRAM_ADDR_DEFAULT                                             0x00000000
5520 #define regRLC_RLCV_IRAM_DATA_DEFAULT                                             0x00000000
5521 #define regRLC_LX6_DRAM_ADDR_DEFAULT                                              0x00000000
5522 #define regRLC_LX6_DRAM_DATA_DEFAULT                                              0x00000000
5523 #define regRLC_LX6_IRAM_ADDR_DEFAULT                                              0x00000000
5524 #define regRLC_LX6_IRAM_DATA_DEFAULT                                              0x00000000
5525 #define regRLC_PACE_UCODE_ADDR_DEFAULT                                            0x00000000
5526 #define regRLC_PACE_UCODE_DATA_DEFAULT                                            0x00000000
5527 #define regRLC_GPM_SCRATCH_ADDR_DEFAULT                                           0x00000000
5528 #define regRLC_GPM_SCRATCH_DATA_DEFAULT                                           0x00000000
5529 #define regRLC_SRM_DRAM_ADDR_DEFAULT                                              0x00000000
5530 #define regRLC_SRM_DRAM_DATA_DEFAULT                                              0x00000000
5531 #define regRLC_SRM_ARAM_ADDR_DEFAULT                                              0x00000000
5532 #define regRLC_SRM_ARAM_DATA_DEFAULT                                              0x00000000
5533 #define regRLC_PACE_SCRATCH_ADDR_DEFAULT                                          0x00000000
5534 #define regRLC_PACE_SCRATCH_DATA_DEFAULT                                          0x00000000
5535 #define regRLC_GTS_OFFSET_LSB_DEFAULT                                             0x00000000
5536 #define regRLC_GTS_OFFSET_MSB_DEFAULT                                             0x00000000
5537 #define regGL2_PIPE_STEER_0_DEFAULT                                               0x32103210
5538 #define regGL2_PIPE_STEER_1_DEFAULT                                               0x32103210
5539 #define regGL2_PIPE_STEER_2_DEFAULT                                               0x76547654
5540 #define regGL2_PIPE_STEER_3_DEFAULT                                               0x76547654
5541 #define regGL1_PIPE_STEER_DEFAULT                                                 0x000000e4
5542 #define regCH_PIPE_STEER_DEFAULT                                                  0x000000e4
5543 #define regGC_USER_SHADER_ARRAY_CONFIG_DEFAULT                                    0x00000000
5544 #define regGC_USER_PRIM_CONFIG_DEFAULT                                            0x000faaa0
5545 #define regGC_USER_SA_UNIT_DISABLE_DEFAULT                                        0x00f00000
5546 #define regGC_USER_RB_REDUNDANCY_DEFAULT                                          0x00000000
5547 #define regGC_USER_RB_BACKEND_DISABLE_DEFAULT                                     0x00000000
5548 #define regGC_USER_RMI_REDUNDANCY_DEFAULT                                         0x00000010
5549 #define regCGTS_USER_TCC_DISABLE_DEFAULT                                          0x00000000
5550 #define regGC_USER_SHADER_RATE_CONFIG_DEFAULT                                     0x00000000
5551 #define regRLC_GPU_IOV_SDMA0_STATUS_DEFAULT                                       0x0000000f
5552 #define regRLC_GPU_IOV_SDMA1_STATUS_DEFAULT                                       0x0000000f
5553 #define regRLC_GPU_IOV_SDMA2_STATUS_DEFAULT                                       0x0000000f
5554 #define regRLC_GPU_IOV_SDMA3_STATUS_DEFAULT                                       0x0000000f
5555 #define regRLC_GPU_IOV_SDMA4_STATUS_DEFAULT                                       0x0000000f
5556 #define regRLC_GPU_IOV_SDMA5_STATUS_DEFAULT                                       0x0000000f
5557 #define regRLC_GPU_IOV_SDMA6_STATUS_DEFAULT                                       0x0000000f
5558 #define regRLC_GPU_IOV_SDMA7_STATUS_DEFAULT                                       0x0000000f
5559 #define regRLC_GPU_IOV_SDMA0_BUSY_STATUS_DEFAULT                                  0x00000000
5560 #define regRLC_GPU_IOV_SDMA1_BUSY_STATUS_DEFAULT                                  0x00000000
5561 #define regRLC_GPU_IOV_SDMA2_BUSY_STATUS_DEFAULT                                  0x00000000
5562 #define regRLC_GPU_IOV_SDMA3_BUSY_STATUS_DEFAULT                                  0x00000000
5563 #define regRLC_GPU_IOV_SDMA4_BUSY_STATUS_DEFAULT                                  0x00000000
5564 #define regRLC_GPU_IOV_SDMA5_BUSY_STATUS_DEFAULT                                  0x00000000
5565 #define regRLC_GPU_IOV_SDMA6_BUSY_STATUS_DEFAULT                                  0x00000000
5566 #define regRLC_GPU_IOV_SDMA7_BUSY_STATUS_DEFAULT                                  0x00000000
5567 
5568 
5569 // addressBlock: gc_sdma0_sdma0hypdec
5570 #define regSDMA0_UCODE_ADDR_DEFAULT                                               0x00000000
5571 #define regSDMA0_UCODE_DATA_DEFAULT                                               0x00000000
5572 #define regSDMA0_UCODE_SELFLOAD_CONTROL_DEFAULT                                   0x00000223
5573 #define regSDMA0_BROADCAST_UCODE_ADDR_DEFAULT                                     0x00000000
5574 #define regSDMA0_BROADCAST_UCODE_DATA_DEFAULT                                     0x00000000
5575 #define regSDMA0_F32_CNTL_DEFAULT                                                 0x08084001
5576 
5577 
5578 // addressBlock: gc_sdma0_sdma1hypdec
5579 #define regSDMA1_UCODE_ADDR_DEFAULT                                               0x00000000
5580 #define regSDMA1_UCODE_DATA_DEFAULT                                               0x00000000
5581 #define regSDMA1_UCODE_SELFLOAD_CONTROL_DEFAULT                                   0x00000223
5582 #define regSDMA1_BROADCAST_UCODE_ADDR_DEFAULT                                     0x00000000
5583 #define regSDMA1_BROADCAST_UCODE_DATA_DEFAULT                                     0x00000000
5584 #define regSDMA1_F32_CNTL_DEFAULT                                                 0x08084001
5585 
5586 
5587 // addressBlock: gc_gcvmsharedhvdec
5588 #define regGCMC_VM_FB_SIZE_OFFSET_VF0_DEFAULT                                     0x00000000
5589 #define regGCMC_VM_FB_SIZE_OFFSET_VF1_DEFAULT                                     0x00000000
5590 #define regGCMC_VM_FB_SIZE_OFFSET_VF2_DEFAULT                                     0x00000000
5591 #define regGCMC_VM_FB_SIZE_OFFSET_VF3_DEFAULT                                     0x00000000
5592 #define regGCMC_VM_FB_SIZE_OFFSET_VF4_DEFAULT                                     0x00000000
5593 #define regGCMC_VM_FB_SIZE_OFFSET_VF5_DEFAULT                                     0x00000000
5594 #define regGCMC_VM_FB_SIZE_OFFSET_VF6_DEFAULT                                     0x00000000
5595 #define regGCMC_VM_FB_SIZE_OFFSET_VF7_DEFAULT                                     0x00000000
5596 #define regGCMC_VM_FB_SIZE_OFFSET_VF8_DEFAULT                                     0x00000000
5597 #define regGCMC_VM_FB_SIZE_OFFSET_VF9_DEFAULT                                     0x00000000
5598 #define regGCMC_VM_FB_SIZE_OFFSET_VF10_DEFAULT                                    0x00000000
5599 #define regGCMC_VM_FB_SIZE_OFFSET_VF11_DEFAULT                                    0x00000000
5600 #define regGCMC_VM_FB_SIZE_OFFSET_VF12_DEFAULT                                    0x00000000
5601 #define regGCMC_VM_FB_SIZE_OFFSET_VF13_DEFAULT                                    0x00000000
5602 #define regGCMC_VM_FB_SIZE_OFFSET_VF14_DEFAULT                                    0x00000000
5603 #define regGCMC_VM_FB_SIZE_OFFSET_VF15_DEFAULT                                    0x00000000
5604 
5605 
5606 // addressBlock: gc_pspdec
5607 #define regCP_MES_DM_INDEX_ADDR_DEFAULT                                           0x00000000
5608 #define regCP_MES_DM_INDEX_DATA_DEFAULT                                           0x00000000
5609 #define regCP_MEC_DM_INDEX_ADDR_DEFAULT                                           0x00000000
5610 #define regCP_MEC_DM_INDEX_DATA_DEFAULT                                           0x00000000
5611 #define regCP_GFX_RS64_DM_INDEX_ADDR_DEFAULT                                      0x00000000
5612 #define regCP_GFX_RS64_DM_INDEX_DATA_DEFAULT                                      0x00000000
5613 #define regCPG_PSP_DEBUG_DEFAULT                                                  0x00000000
5614 #define regCPC_PSP_DEBUG_DEFAULT                                                  0x00000000
5615 #define regGRBM_SEC_CNTL_DEFAULT                                                  0x00000000
5616 #define regGRBM_CAM_INDEX_DEFAULT                                                 0x00000000
5617 #define regGRBM_HYP_CAM_INDEX_DEFAULT                                             0x00000000
5618 #define regGRBM_CAM_DATA_DEFAULT                                                  0x00000000
5619 #define regGRBM_HYP_CAM_DATA_DEFAULT                                              0x00000000
5620 #define regGRBM_CAM_DATA_UPPER_DEFAULT                                            0x00000000
5621 #define regGRBM_HYP_CAM_DATA_UPPER_DEFAULT                                        0x00000000
5622 #define regRLC_FWL_FIRST_VIOL_ADDR_DEFAULT                                        0x00000000
5623 
5624 
5625 // addressBlock: gc_gcvml2pspdec
5626 #define regGCUTCL2_TRANSLATION_BYPASS_BY_VMID_DEFAULT                             0x00000000
5627 #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_DEFAULT                       0x00000000
5628 #define regGCMC_VM_MARC_BASE_LO_0_DEFAULT                                         0x00000000
5629 #define regGCMC_VM_MARC_BASE_LO_1_DEFAULT                                         0x00000000
5630 #define regGCMC_VM_MARC_BASE_LO_2_DEFAULT                                         0x00000000
5631 #define regGCMC_VM_MARC_BASE_LO_3_DEFAULT                                         0x00000000
5632 #define regGCMC_VM_MARC_BASE_LO_4_DEFAULT                                         0x00000000
5633 #define regGCMC_VM_MARC_BASE_LO_5_DEFAULT                                         0x00000000
5634 #define regGCMC_VM_MARC_BASE_LO_6_DEFAULT                                         0x00000000
5635 #define regGCMC_VM_MARC_BASE_LO_7_DEFAULT                                         0x00000000
5636 #define regGCMC_VM_MARC_BASE_LO_8_DEFAULT                                         0x00000000
5637 #define regGCMC_VM_MARC_BASE_LO_9_DEFAULT                                         0x00000000
5638 #define regGCMC_VM_MARC_BASE_LO_10_DEFAULT                                        0x00000000
5639 #define regGCMC_VM_MARC_BASE_LO_11_DEFAULT                                        0x00000000
5640 #define regGCMC_VM_MARC_BASE_LO_12_DEFAULT                                        0x00000000
5641 #define regGCMC_VM_MARC_BASE_LO_13_DEFAULT                                        0x00000000
5642 #define regGCMC_VM_MARC_BASE_LO_14_DEFAULT                                        0x00000000
5643 #define regGCMC_VM_MARC_BASE_LO_15_DEFAULT                                        0x00000000
5644 #define regGCMC_VM_MARC_BASE_HI_0_DEFAULT                                         0x00000000
5645 #define regGCMC_VM_MARC_BASE_HI_1_DEFAULT                                         0x00000000
5646 #define regGCMC_VM_MARC_BASE_HI_2_DEFAULT                                         0x00000000
5647 #define regGCMC_VM_MARC_BASE_HI_3_DEFAULT                                         0x00000000
5648 #define regGCMC_VM_MARC_BASE_HI_4_DEFAULT                                         0x00000000
5649 #define regGCMC_VM_MARC_BASE_HI_5_DEFAULT                                         0x00000000
5650 #define regGCMC_VM_MARC_BASE_HI_6_DEFAULT                                         0x00000000
5651 #define regGCMC_VM_MARC_BASE_HI_7_DEFAULT                                         0x00000000
5652 #define regGCMC_VM_MARC_BASE_HI_8_DEFAULT                                         0x00000000
5653 #define regGCMC_VM_MARC_BASE_HI_9_DEFAULT                                         0x00000000
5654 #define regGCMC_VM_MARC_BASE_HI_10_DEFAULT                                        0x00000000
5655 #define regGCMC_VM_MARC_BASE_HI_11_DEFAULT                                        0x00000000
5656 #define regGCMC_VM_MARC_BASE_HI_12_DEFAULT                                        0x00000000
5657 #define regGCMC_VM_MARC_BASE_HI_13_DEFAULT                                        0x00000000
5658 #define regGCMC_VM_MARC_BASE_HI_14_DEFAULT                                        0x00000000
5659 #define regGCMC_VM_MARC_BASE_HI_15_DEFAULT                                        0x00000000
5660 #define regGCMC_VM_MARC_RELOC_LO_0_DEFAULT                                        0x00000000
5661 #define regGCMC_VM_MARC_RELOC_LO_1_DEFAULT                                        0x00000000
5662 #define regGCMC_VM_MARC_RELOC_LO_2_DEFAULT                                        0x00000000
5663 #define regGCMC_VM_MARC_RELOC_LO_3_DEFAULT                                        0x00000000
5664 #define regGCMC_VM_MARC_RELOC_LO_4_DEFAULT                                        0x00000000
5665 #define regGCMC_VM_MARC_RELOC_LO_5_DEFAULT                                        0x00000000
5666 #define regGCMC_VM_MARC_RELOC_LO_6_DEFAULT                                        0x00000000
5667 #define regGCMC_VM_MARC_RELOC_LO_7_DEFAULT                                        0x00000000
5668 #define regGCMC_VM_MARC_RELOC_LO_8_DEFAULT                                        0x00000000
5669 #define regGCMC_VM_MARC_RELOC_LO_9_DEFAULT                                        0x00000000
5670 #define regGCMC_VM_MARC_RELOC_LO_10_DEFAULT                                       0x00000000
5671 #define regGCMC_VM_MARC_RELOC_LO_11_DEFAULT                                       0x00000000
5672 #define regGCMC_VM_MARC_RELOC_LO_12_DEFAULT                                       0x00000000
5673 #define regGCMC_VM_MARC_RELOC_LO_13_DEFAULT                                       0x00000000
5674 #define regGCMC_VM_MARC_RELOC_LO_14_DEFAULT                                       0x00000000
5675 #define regGCMC_VM_MARC_RELOC_LO_15_DEFAULT                                       0x00000000
5676 #define regGCMC_VM_MARC_RELOC_HI_0_DEFAULT                                        0x00000000
5677 #define regGCMC_VM_MARC_RELOC_HI_1_DEFAULT                                        0x00000000
5678 #define regGCMC_VM_MARC_RELOC_HI_2_DEFAULT                                        0x00000000
5679 #define regGCMC_VM_MARC_RELOC_HI_3_DEFAULT                                        0x00000000
5680 #define regGCMC_VM_MARC_RELOC_HI_4_DEFAULT                                        0x00000000
5681 #define regGCMC_VM_MARC_RELOC_HI_5_DEFAULT                                        0x00000000
5682 #define regGCMC_VM_MARC_RELOC_HI_6_DEFAULT                                        0x00000000
5683 #define regGCMC_VM_MARC_RELOC_HI_7_DEFAULT                                        0x00000000
5684 #define regGCMC_VM_MARC_RELOC_HI_8_DEFAULT                                        0x00000000
5685 #define regGCMC_VM_MARC_RELOC_HI_9_DEFAULT                                        0x00000000
5686 #define regGCMC_VM_MARC_RELOC_HI_10_DEFAULT                                       0x00000000
5687 #define regGCMC_VM_MARC_RELOC_HI_11_DEFAULT                                       0x00000000
5688 #define regGCMC_VM_MARC_RELOC_HI_12_DEFAULT                                       0x00000000
5689 #define regGCMC_VM_MARC_RELOC_HI_13_DEFAULT                                       0x00000000
5690 #define regGCMC_VM_MARC_RELOC_HI_14_DEFAULT                                       0x00000000
5691 #define regGCMC_VM_MARC_RELOC_HI_15_DEFAULT                                       0x00000000
5692 #define regGCMC_VM_MARC_LEN_LO_0_DEFAULT                                          0x00000000
5693 #define regGCMC_VM_MARC_LEN_LO_1_DEFAULT                                          0x00000000
5694 #define regGCMC_VM_MARC_LEN_LO_2_DEFAULT                                          0x00000000
5695 #define regGCMC_VM_MARC_LEN_LO_3_DEFAULT                                          0x00000000
5696 #define regGCMC_VM_MARC_LEN_LO_4_DEFAULT                                          0x00000000
5697 #define regGCMC_VM_MARC_LEN_LO_5_DEFAULT                                          0x00000000
5698 #define regGCMC_VM_MARC_LEN_LO_6_DEFAULT                                          0x00000000
5699 #define regGCMC_VM_MARC_LEN_LO_7_DEFAULT                                          0x00000000
5700 #define regGCMC_VM_MARC_LEN_LO_8_DEFAULT                                          0x00000000
5701 #define regGCMC_VM_MARC_LEN_LO_9_DEFAULT                                          0x00000000
5702 #define regGCMC_VM_MARC_LEN_LO_10_DEFAULT                                         0x00000000
5703 #define regGCMC_VM_MARC_LEN_LO_11_DEFAULT                                         0x00000000
5704 #define regGCMC_VM_MARC_LEN_LO_12_DEFAULT                                         0x00000000
5705 #define regGCMC_VM_MARC_LEN_LO_13_DEFAULT                                         0x00000000
5706 #define regGCMC_VM_MARC_LEN_LO_14_DEFAULT                                         0x00000000
5707 #define regGCMC_VM_MARC_LEN_LO_15_DEFAULT                                         0x00000000
5708 #define regGCMC_VM_MARC_LEN_HI_0_DEFAULT                                          0x00000000
5709 #define regGCMC_VM_MARC_LEN_HI_1_DEFAULT                                          0x00000000
5710 #define regGCMC_VM_MARC_LEN_HI_2_DEFAULT                                          0x00000000
5711 #define regGCMC_VM_MARC_LEN_HI_3_DEFAULT                                          0x00000000
5712 #define regGCMC_VM_MARC_LEN_HI_4_DEFAULT                                          0x00000000
5713 #define regGCMC_VM_MARC_LEN_HI_5_DEFAULT                                          0x00000000
5714 #define regGCMC_VM_MARC_LEN_HI_6_DEFAULT                                          0x00000000
5715 #define regGCMC_VM_MARC_LEN_HI_7_DEFAULT                                          0x00000000
5716 #define regGCMC_VM_MARC_LEN_HI_8_DEFAULT                                          0x00000000
5717 #define regGCMC_VM_MARC_LEN_HI_9_DEFAULT                                          0x00000000
5718 #define regGCMC_VM_MARC_LEN_HI_10_DEFAULT                                         0x00000000
5719 #define regGCMC_VM_MARC_LEN_HI_11_DEFAULT                                         0x00000000
5720 #define regGCMC_VM_MARC_LEN_HI_12_DEFAULT                                         0x00000000
5721 #define regGCMC_VM_MARC_LEN_HI_13_DEFAULT                                         0x00000000
5722 #define regGCMC_VM_MARC_LEN_HI_14_DEFAULT                                         0x00000000
5723 #define regGCMC_VM_MARC_LEN_HI_15_DEFAULT                                         0x00000000
5724 #define regGCMC_VM_MARC_PFVF_MAPPING_0_DEFAULT                                    0x0001ffff
5725 #define regGCMC_VM_MARC_PFVF_MAPPING_1_DEFAULT                                    0x0001ffff
5726 #define regGCMC_VM_MARC_PFVF_MAPPING_2_DEFAULT                                    0x0001ffff
5727 #define regGCMC_VM_MARC_PFVF_MAPPING_3_DEFAULT                                    0x0001ffff
5728 #define regGCMC_VM_MARC_PFVF_MAPPING_4_DEFAULT                                    0x0001ffff
5729 #define regGCMC_VM_MARC_PFVF_MAPPING_5_DEFAULT                                    0x0001ffff
5730 #define regGCMC_VM_MARC_PFVF_MAPPING_6_DEFAULT                                    0x0001ffff
5731 #define regGCMC_VM_MARC_PFVF_MAPPING_7_DEFAULT                                    0x0001ffff
5732 #define regGCMC_VM_MARC_PFVF_MAPPING_8_DEFAULT                                    0x0001ffff
5733 #define regGCMC_VM_MARC_PFVF_MAPPING_9_DEFAULT                                    0x0001ffff
5734 #define regGCMC_VM_MARC_PFVF_MAPPING_10_DEFAULT                                   0x0001ffff
5735 #define regGCMC_VM_MARC_PFVF_MAPPING_11_DEFAULT                                   0x0001ffff
5736 #define regGCMC_VM_MARC_PFVF_MAPPING_12_DEFAULT                                   0x0001ffff
5737 #define regGCMC_VM_MARC_PFVF_MAPPING_13_DEFAULT                                   0x0001ffff
5738 #define regGCMC_VM_MARC_PFVF_MAPPING_14_DEFAULT                                   0x0001ffff
5739 #define regGCMC_VM_MARC_PFVF_MAPPING_15_DEFAULT                                   0x0001ffff
5740 #define regGCUTC_TRANSLATION_FAULT_CNTL0_DEFAULT                                  0x00000000
5741 #define regGCUTC_TRANSLATION_FAULT_CNTL1_DEFAULT                                  0x00000000
5742 
5743 
5744 // addressBlock: gc_gfx_imu_gfx_imu_pspdec
5745 #define regGFX_IMU_RLC_BOOTLOADER_ADDR_HI_DEFAULT                                 0x00000000
5746 #define regGFX_IMU_RLC_BOOTLOADER_ADDR_LO_DEFAULT                                 0x00000000
5747 #define regGFX_IMU_RLC_BOOTLOADER_SIZE_DEFAULT                                    0x00000000
5748 #define regGFX_IMU_I_RAM_ADDR_DEFAULT                                             0x00000000
5749 #define regGFX_IMU_I_RAM_DATA_DEFAULT                                             0x00000000
5750 
5751 
5752 // addressBlock: gccacind
5753 #define ixGC_CAC_ID_DEFAULT                                                      0x00000000
5754 #define ixGC_CAC_CNTL_DEFAULT                                                    0x000000ff
5755 #define ixGC_CAC_ACC_CP0_DEFAULT                                                 0x00000000
5756 #define ixGC_CAC_ACC_CP1_DEFAULT                                                 0x00000000
5757 #define ixGC_CAC_ACC_CP2_DEFAULT                                                 0x00000000
5758 #define ixGC_CAC_ACC_EA0_DEFAULT                                                 0x00000000
5759 #define ixGC_CAC_ACC_EA1_DEFAULT                                                 0x00000000
5760 #define ixGC_CAC_ACC_EA2_DEFAULT                                                 0x00000000
5761 #define ixGC_CAC_ACC_EA3_DEFAULT                                                 0x00000000
5762 #define ixGC_CAC_ACC_EA4_DEFAULT                                                 0x00000000
5763 #define ixGC_CAC_ACC_EA5_DEFAULT                                                 0x00000000
5764 #define ixGC_CAC_ACC_UTCL2_ROUTER0_DEFAULT                                       0x00000000
5765 #define ixGC_CAC_ACC_UTCL2_ROUTER1_DEFAULT                                       0x00000000
5766 #define ixGC_CAC_ACC_UTCL2_ROUTER2_DEFAULT                                       0x00000000
5767 #define ixGC_CAC_ACC_UTCL2_ROUTER3_DEFAULT                                       0x00000000
5768 #define ixGC_CAC_ACC_UTCL2_ROUTER4_DEFAULT                                       0x00000000
5769 #define ixGC_CAC_ACC_UTCL2_ROUTER5_DEFAULT                                       0x00000000
5770 #define ixGC_CAC_ACC_UTCL2_ROUTER6_DEFAULT                                       0x00000000
5771 #define ixGC_CAC_ACC_UTCL2_ROUTER7_DEFAULT                                       0x00000000
5772 #define ixGC_CAC_ACC_UTCL2_ROUTER8_DEFAULT                                       0x00000000
5773 #define ixGC_CAC_ACC_UTCL2_ROUTER9_DEFAULT                                       0x00000000
5774 #define ixGC_CAC_ACC_UTCL2_VML20_DEFAULT                                         0x00000000
5775 #define ixGC_CAC_ACC_UTCL2_VML21_DEFAULT                                         0x00000000
5776 #define ixGC_CAC_ACC_UTCL2_VML22_DEFAULT                                         0x00000000
5777 #define ixGC_CAC_ACC_UTCL2_VML23_DEFAULT                                         0x00000000
5778 #define ixGC_CAC_ACC_UTCL2_VML24_DEFAULT                                         0x00000000
5779 #define ixGC_CAC_ACC_UTCL2_WALKER0_DEFAULT                                       0x00000000
5780 #define ixGC_CAC_ACC_UTCL2_WALKER1_DEFAULT                                       0x00000000
5781 #define ixGC_CAC_ACC_UTCL2_WALKER2_DEFAULT                                       0x00000000
5782 #define ixGC_CAC_ACC_UTCL2_WALKER3_DEFAULT                                       0x00000000
5783 #define ixGC_CAC_ACC_UTCL2_WALKER4_DEFAULT                                       0x00000000
5784 #define ixGC_CAC_ACC_GDS0_DEFAULT                                                0x00000000
5785 #define ixGC_CAC_ACC_GDS1_DEFAULT                                                0x00000000
5786 #define ixGC_CAC_ACC_GDS2_DEFAULT                                                0x00000000
5787 #define ixGC_CAC_ACC_GDS3_DEFAULT                                                0x00000000
5788 #define ixGC_CAC_ACC_GDS4_DEFAULT                                                0x00000000
5789 #define ixGC_CAC_ACC_GE0_DEFAULT                                                 0x00000000
5790 #define ixGC_CAC_ACC_GE1_DEFAULT                                                 0x00000000
5791 #define ixGC_CAC_ACC_GE2_DEFAULT                                                 0x00000000
5792 #define ixGC_CAC_ACC_GE3_DEFAULT                                                 0x00000000
5793 #define ixGC_CAC_ACC_GE4_DEFAULT                                                 0x00000000
5794 #define ixGC_CAC_ACC_GE5_DEFAULT                                                 0x00000000
5795 #define ixGC_CAC_ACC_GE6_DEFAULT                                                 0x00000000
5796 #define ixGC_CAC_ACC_GE7_DEFAULT                                                 0x00000000
5797 #define ixGC_CAC_ACC_GE8_DEFAULT                                                 0x00000000
5798 #define ixGC_CAC_ACC_GE9_DEFAULT                                                 0x00000000
5799 #define ixGC_CAC_ACC_GE10_DEFAULT                                                0x00000000
5800 #define ixGC_CAC_ACC_GE11_DEFAULT                                                0x00000000
5801 #define ixGC_CAC_ACC_GE12_DEFAULT                                                0x00000000
5802 #define ixGC_CAC_ACC_GE13_DEFAULT                                                0x00000000
5803 #define ixGC_CAC_ACC_GE14_DEFAULT                                                0x00000000
5804 #define ixGC_CAC_ACC_GE15_DEFAULT                                                0x00000000
5805 #define ixGC_CAC_ACC_GE16_DEFAULT                                                0x00000000
5806 #define ixGC_CAC_ACC_GE17_DEFAULT                                                0x00000000
5807 #define ixGC_CAC_ACC_GE18_DEFAULT                                                0x00000000
5808 #define ixGC_CAC_ACC_GE19_DEFAULT                                                0x00000000
5809 #define ixGC_CAC_ACC_GE20_DEFAULT                                                0x00000000
5810 #define ixGC_CAC_ACC_PMM0_DEFAULT                                                0x00000000
5811 #define ixGC_CAC_ACC_GL2C0_DEFAULT                                               0x00000000
5812 #define ixGC_CAC_ACC_GL2C1_DEFAULT                                               0x00000000
5813 #define ixGC_CAC_ACC_GL2C2_DEFAULT                                               0x00000000
5814 #define ixGC_CAC_ACC_GL2C3_DEFAULT                                               0x00000000
5815 #define ixGC_CAC_ACC_GL2C4_DEFAULT                                               0x00000000
5816 #define ixGC_CAC_ACC_PH0_DEFAULT                                                 0x00000000
5817 #define ixGC_CAC_ACC_PH1_DEFAULT                                                 0x00000000
5818 #define ixGC_CAC_ACC_PH2_DEFAULT                                                 0x00000000
5819 #define ixGC_CAC_ACC_PH3_DEFAULT                                                 0x00000000
5820 #define ixGC_CAC_ACC_PH4_DEFAULT                                                 0x00000000
5821 #define ixGC_CAC_ACC_PH5_DEFAULT                                                 0x00000000
5822 #define ixGC_CAC_ACC_PH6_DEFAULT                                                 0x00000000
5823 #define ixGC_CAC_ACC_PH7_DEFAULT                                                 0x00000000
5824 #define ixGC_CAC_ACC_SDMA0_DEFAULT                                               0x00000000
5825 #define ixGC_CAC_ACC_SDMA1_DEFAULT                                               0x00000000
5826 #define ixGC_CAC_ACC_SDMA2_DEFAULT                                               0x00000000
5827 #define ixGC_CAC_ACC_SDMA3_DEFAULT                                               0x00000000
5828 #define ixGC_CAC_ACC_SDMA4_DEFAULT                                               0x00000000
5829 #define ixGC_CAC_ACC_SDMA5_DEFAULT                                               0x00000000
5830 #define ixGC_CAC_ACC_SDMA6_DEFAULT                                               0x00000000
5831 #define ixGC_CAC_ACC_SDMA7_DEFAULT                                               0x00000000
5832 #define ixGC_CAC_ACC_SDMA8_DEFAULT                                               0x00000000
5833 #define ixGC_CAC_ACC_SDMA9_DEFAULT                                               0x00000000
5834 #define ixGC_CAC_ACC_SDMA10_DEFAULT                                              0x00000000
5835 #define ixGC_CAC_ACC_SDMA11_DEFAULT                                              0x00000000
5836 #define ixGC_CAC_ACC_CHC0_DEFAULT                                                0x00000000
5837 #define ixGC_CAC_ACC_CHC1_DEFAULT                                                0x00000000
5838 #define ixGC_CAC_ACC_CHC2_DEFAULT                                                0x00000000
5839 #define ixGC_CAC_ACC_GUS0_DEFAULT                                                0x00000000
5840 #define ixGC_CAC_ACC_GUS1_DEFAULT                                                0x00000000
5841 #define ixGC_CAC_ACC_GUS2_DEFAULT                                                0x00000000
5842 #define ixGC_CAC_ACC_RLC0_DEFAULT                                                0x00000000
5843 #define ixRELEASE_TO_STALL_LUT_1_8_DEFAULT                                       0x00000000
5844 #define ixRELEASE_TO_STALL_LUT_9_16_DEFAULT                                      0x00000000
5845 #define ixRELEASE_TO_STALL_LUT_17_20_DEFAULT                                     0x00000000
5846 #define ixSTALL_TO_RELEASE_LUT_1_4_DEFAULT                                       0x00000000
5847 #define ixSTALL_TO_RELEASE_LUT_5_7_DEFAULT                                       0x00000000
5848 #define ixSTALL_TO_PWRBRK_LUT_1_4_DEFAULT                                        0x00000000
5849 #define ixSTALL_TO_PWRBRK_LUT_5_7_DEFAULT                                        0x00000000
5850 #define ixPWRBRK_STALL_TO_RELEASE_LUT_1_4_DEFAULT                                0x00000000
5851 #define ixPWRBRK_STALL_TO_RELEASE_LUT_5_7_DEFAULT                                0x00000000
5852 #define ixPWRBRK_RELEASE_TO_STALL_LUT_1_8_DEFAULT                                0x00000000
5853 #define ixPWRBRK_RELEASE_TO_STALL_LUT_9_16_DEFAULT                               0x00000000
5854 #define ixPWRBRK_RELEASE_TO_STALL_LUT_17_20_DEFAULT                              0x00000000
5855 #define ixFIXED_PATTERN_PERF_COUNTER_1_DEFAULT                                   0x00000000
5856 #define ixFIXED_PATTERN_PERF_COUNTER_2_DEFAULT                                   0x00000000
5857 #define ixFIXED_PATTERN_PERF_COUNTER_3_DEFAULT                                   0x00000000
5858 #define ixFIXED_PATTERN_PERF_COUNTER_4_DEFAULT                                   0x00000000
5859 #define ixFIXED_PATTERN_PERF_COUNTER_5_DEFAULT                                   0x00000000
5860 #define ixFIXED_PATTERN_PERF_COUNTER_6_DEFAULT                                   0x00000000
5861 #define ixFIXED_PATTERN_PERF_COUNTER_7_DEFAULT                                   0x00000000
5862 #define ixFIXED_PATTERN_PERF_COUNTER_8_DEFAULT                                   0x00000000
5863 #define ixFIXED_PATTERN_PERF_COUNTER_9_DEFAULT                                   0x00000000
5864 #define ixFIXED_PATTERN_PERF_COUNTER_10_DEFAULT                                  0x00000000
5865 #define ixHW_LUT_UPDATE_STATUS_DEFAULT                                           0x00000000
5866 
5867 
5868 // addressBlock: secacind
5869 #define ixSE_CAC_ID_DEFAULT                                                      0x00000000
5870 #define ixSE_CAC_CNTL_DEFAULT                                                    0x000000ff
5871 
5872 
5873 // addressBlock: grtavfsind
5874 #define ixRTAVFS_REG0_DEFAULT                                                    0x01000000
5875 #define ixRTAVFS_REG1_DEFAULT                                                    0x01000000
5876 #define ixRTAVFS_REG2_DEFAULT                                                    0x01000000
5877 #define ixRTAVFS_REG3_DEFAULT                                                    0x01000000
5878 #define ixRTAVFS_REG4_DEFAULT                                                    0x01000000
5879 #define ixRTAVFS_REG5_DEFAULT                                                    0x00000000
5880 #define ixRTAVFS_REG6_DEFAULT                                                    0x00000000
5881 #define ixRTAVFS_REG7_DEFAULT                                                    0x00000000
5882 #define ixRTAVFS_REG8_DEFAULT                                                    0x00000000
5883 #define ixRTAVFS_REG9_DEFAULT                                                    0x00000000
5884 #define ixRTAVFS_REG10_DEFAULT                                                   0x00000000
5885 #define ixRTAVFS_REG11_DEFAULT                                                   0x00000000
5886 #define ixRTAVFS_REG12_DEFAULT                                                   0x00000000
5887 #define ixRTAVFS_REG13_DEFAULT                                                   0x00000000
5888 #define ixRTAVFS_REG14_DEFAULT                                                   0x00000000
5889 #define ixRTAVFS_REG15_DEFAULT                                                   0x00000000
5890 #define ixRTAVFS_REG16_DEFAULT                                                   0x00000000
5891 #define ixRTAVFS_REG17_DEFAULT                                                   0x00000000
5892 #define ixRTAVFS_REG18_DEFAULT                                                   0x00000000
5893 #define ixRTAVFS_REG19_DEFAULT                                                   0x00000000
5894 #define ixRTAVFS_REG20_DEFAULT                                                   0x00000000
5895 #define ixRTAVFS_REG21_DEFAULT                                                   0x00000000
5896 #define ixRTAVFS_REG22_DEFAULT                                                   0x00000000
5897 #define ixRTAVFS_REG23_DEFAULT                                                   0x00000000
5898 #define ixRTAVFS_REG24_DEFAULT                                                   0x00000000
5899 #define ixRTAVFS_REG25_DEFAULT                                                   0x00000000
5900 #define ixRTAVFS_REG26_DEFAULT                                                   0x00000000
5901 #define ixRTAVFS_REG27_DEFAULT                                                   0x00000000
5902 #define ixRTAVFS_REG28_DEFAULT                                                   0x00000000
5903 #define ixRTAVFS_REG29_DEFAULT                                                   0x00000000
5904 #define ixRTAVFS_REG30_DEFAULT                                                   0x00000000
5905 #define ixRTAVFS_REG31_DEFAULT                                                   0x00000000
5906 #define ixRTAVFS_REG32_DEFAULT                                                   0x000000ff
5907 #define ixRTAVFS_REG33_DEFAULT                                                   0x000000ff
5908 #define ixRTAVFS_REG34_DEFAULT                                                   0x000000ff
5909 #define ixRTAVFS_REG35_DEFAULT                                                   0x000000ff
5910 #define ixRTAVFS_REG36_DEFAULT                                                   0x000000ff
5911 #define ixRTAVFS_REG37_DEFAULT                                                   0x000000ff
5912 #define ixRTAVFS_REG38_DEFAULT                                                   0x000000ff
5913 #define ixRTAVFS_REG39_DEFAULT                                                   0x000000ff
5914 #define ixRTAVFS_REG40_DEFAULT                                                   0x000000ff
5915 #define ixRTAVFS_REG41_DEFAULT                                                   0x000000ff
5916 #define ixRTAVFS_REG42_DEFAULT                                                   0x000000ff
5917 #define ixRTAVFS_REG43_DEFAULT                                                   0xcccdbcdd
5918 #define ixRTAVFS_REG44_DEFAULT                                                   0x2587d190
5919 #define ixRTAVFS_REG45_DEFAULT                                                   0x00000000
5920 #define ixRTAVFS_REG46_DEFAULT                                                   0x000211cd
5921 #define ixRTAVFS_REG47_DEFAULT                                                   0x000af12c
5922 #define ixRTAVFS_REG48_DEFAULT                                                   0x00000010
5923 #define ixRTAVFS_REG49_DEFAULT                                                   0x00000000
5924 #define ixRTAVFS_REG50_DEFAULT                                                   0x00000000
5925 #define ixRTAVFS_REG51_DEFAULT                                                   0x00000008
5926 #define ixRTAVFS_REG52_DEFAULT                                                   0x00000000
5927 #define ixRTAVFS_REG53_DEFAULT                                                   0x00000000
5928 #define ixRTAVFS_REG54_DEFAULT                                                   0x01000000
5929 #define ixRTAVFS_REG55_DEFAULT                                                   0x01000000
5930 #define ixRTAVFS_REG56_DEFAULT                                                   0x01000000
5931 #define ixRTAVFS_REG57_DEFAULT                                                   0x01000000
5932 #define ixRTAVFS_REG58_DEFAULT                                                   0x01000000
5933 #define ixRTAVFS_REG59_DEFAULT                                                   0x01000000
5934 #define ixRTAVFS_REG60_DEFAULT                                                   0x01000000
5935 #define ixRTAVFS_REG61_DEFAULT                                                   0x01000000
5936 #define ixRTAVFS_REG62_DEFAULT                                                   0x01000000
5937 #define ixRTAVFS_REG63_DEFAULT                                                   0x01000000
5938 #define ixRTAVFS_REG64_DEFAULT                                                   0x01000000
5939 #define ixRTAVFS_REG65_DEFAULT                                                   0x01000000
5940 #define ixRTAVFS_REG66_DEFAULT                                                   0x01000000
5941 #define ixRTAVFS_REG67_DEFAULT                                                   0x01000000
5942 #define ixRTAVFS_REG68_DEFAULT                                                   0x01000000
5943 #define ixRTAVFS_REG69_DEFAULT                                                   0x01000000
5944 #define ixRTAVFS_REG70_DEFAULT                                                   0x01000000
5945 #define ixRTAVFS_REG71_DEFAULT                                                   0x01000000
5946 #define ixRTAVFS_REG72_DEFAULT                                                   0x01000000
5947 #define ixRTAVFS_REG73_DEFAULT                                                   0x00000100
5948 #define ixRTAVFS_REG74_DEFAULT                                                   0x00000100
5949 #define ixRTAVFS_REG75_DEFAULT                                                   0x00000100
5950 #define ixRTAVFS_REG76_DEFAULT                                                   0x00000100
5951 #define ixRTAVFS_REG77_DEFAULT                                                   0x00000100
5952 #define ixRTAVFS_REG78_DEFAULT                                                   0x00000100
5953 #define ixRTAVFS_REG79_DEFAULT                                                   0x00000100
5954 #define ixRTAVFS_REG80_DEFAULT                                                   0x01000000
5955 #define ixRTAVFS_REG81_DEFAULT                                                   0x01000000
5956 #define ixRTAVFS_REG82_DEFAULT                                                   0x01000000
5957 #define ixRTAVFS_REG83_DEFAULT                                                   0x01000000
5958 #define ixRTAVFS_REG84_DEFAULT                                                   0x01000000
5959 #define ixRTAVFS_REG85_DEFAULT                                                   0x01000000
5960 #define ixRTAVFS_REG86_DEFAULT                                                   0x01000000
5961 #define ixRTAVFS_REG87_DEFAULT                                                   0x01000000
5962 #define ixRTAVFS_REG88_DEFAULT                                                   0x01000000
5963 #define ixRTAVFS_REG89_DEFAULT                                                   0x01000000
5964 #define ixRTAVFS_REG90_DEFAULT                                                   0x01000000
5965 #define ixRTAVFS_REG91_DEFAULT                                                   0x01000000
5966 #define ixRTAVFS_REG92_DEFAULT                                                   0x01000000
5967 #define ixRTAVFS_REG93_DEFAULT                                                   0x01000000
5968 #define ixRTAVFS_REG94_DEFAULT                                                   0x01000000
5969 #define ixRTAVFS_REG95_DEFAULT                                                   0x01000000
5970 #define ixRTAVFS_REG96_DEFAULT                                                   0x01000000
5971 #define ixRTAVFS_REG97_DEFAULT                                                   0x01000000
5972 #define ixRTAVFS_REG98_DEFAULT                                                   0x01000000
5973 #define ixRTAVFS_REG99_DEFAULT                                                   0x01000000
5974 #define ixRTAVFS_REG100_DEFAULT                                                  0x01000000
5975 #define ixRTAVFS_REG101_DEFAULT                                                  0x01000000
5976 #define ixRTAVFS_REG102_DEFAULT                                                  0x00000100
5977 #define ixRTAVFS_REG103_DEFAULT                                                  0x00000100
5978 #define ixRTAVFS_REG104_DEFAULT                                                  0x00000100
5979 #define ixRTAVFS_REG105_DEFAULT                                                  0x00000100
5980 #define ixRTAVFS_REG106_DEFAULT                                                  0x00000100
5981 #define ixRTAVFS_REG107_DEFAULT                                                  0x00000100
5982 #define ixRTAVFS_REG108_DEFAULT                                                  0x00000100
5983 #define ixRTAVFS_REG109_DEFAULT                                                  0x01000000
5984 #define ixRTAVFS_REG110_DEFAULT                                                  0x01000000
5985 #define ixRTAVFS_REG111_DEFAULT                                                  0x01000000
5986 #define ixRTAVFS_REG112_DEFAULT                                                  0x00000100
5987 #define ixRTAVFS_REG113_DEFAULT                                                  0x00000100
5988 #define ixRTAVFS_REG114_DEFAULT                                                  0x00000100
5989 #define ixRTAVFS_REG115_DEFAULT                                                  0x01000000
5990 #define ixRTAVFS_REG116_DEFAULT                                                  0x01000000
5991 #define ixRTAVFS_REG117_DEFAULT                                                  0x01000000
5992 #define ixRTAVFS_REG118_DEFAULT                                                  0x00000000
5993 #define ixRTAVFS_REG119_DEFAULT                                                  0x00000000
5994 #define ixRTAVFS_REG120_DEFAULT                                                  0x00000000
5995 #define ixRTAVFS_REG121_DEFAULT                                                  0x00000000
5996 #define ixRTAVFS_REG122_DEFAULT                                                  0x00000000
5997 #define ixRTAVFS_REG123_DEFAULT                                                  0x00000000
5998 #define ixRTAVFS_REG124_DEFAULT                                                  0x00000000
5999 #define ixRTAVFS_REG125_DEFAULT                                                  0x00000000
6000 #define ixRTAVFS_REG126_DEFAULT                                                  0x00000000
6001 #define ixRTAVFS_REG127_DEFAULT                                                  0x00000000
6002 #define ixRTAVFS_REG128_DEFAULT                                                  0x00000000
6003 #define ixRTAVFS_REG129_DEFAULT                                                  0x00000000
6004 #define ixRTAVFS_REG130_DEFAULT                                                  0x00000000
6005 #define ixRTAVFS_REG131_DEFAULT                                                  0x00000000
6006 #define ixRTAVFS_REG132_DEFAULT                                                  0x00000000
6007 #define ixRTAVFS_REG133_DEFAULT                                                  0x00000000
6008 #define ixRTAVFS_REG134_DEFAULT                                                  0x00000000
6009 #define ixRTAVFS_REG135_DEFAULT                                                  0x00000000
6010 #define ixRTAVFS_REG136_DEFAULT                                                  0x00000000
6011 #define ixRTAVFS_REG137_DEFAULT                                                  0x00000000
6012 #define ixRTAVFS_REG138_DEFAULT                                                  0x00000000
6013 #define ixRTAVFS_REG139_DEFAULT                                                  0x00000000
6014 #define ixRTAVFS_REG140_DEFAULT                                                  0x00000000
6015 #define ixRTAVFS_REG141_DEFAULT                                                  0x00000000
6016 #define ixRTAVFS_REG142_DEFAULT                                                  0x00000000
6017 #define ixRTAVFS_REG143_DEFAULT                                                  0x00000000
6018 #define ixRTAVFS_REG144_DEFAULT                                                  0x00000000
6019 #define ixRTAVFS_REG145_DEFAULT                                                  0x00000000
6020 #define ixRTAVFS_REG146_DEFAULT                                                  0x00000000
6021 #define ixRTAVFS_REG147_DEFAULT                                                  0x00000000
6022 #define ixRTAVFS_REG148_DEFAULT                                                  0x00000000
6023 #define ixRTAVFS_REG149_DEFAULT                                                  0x00000000
6024 #define ixRTAVFS_REG150_DEFAULT                                                  0x00000000
6025 #define ixRTAVFS_REG151_DEFAULT                                                  0x00000000
6026 #define ixRTAVFS_REG152_DEFAULT                                                  0x00000000
6027 #define ixRTAVFS_REG153_DEFAULT                                                  0x00000000
6028 #define ixRTAVFS_REG154_DEFAULT                                                  0x00000000
6029 #define ixRTAVFS_REG155_DEFAULT                                                  0x00000000
6030 #define ixRTAVFS_REG156_DEFAULT                                                  0x00000000
6031 #define ixRTAVFS_REG157_DEFAULT                                                  0x00000000
6032 #define ixRTAVFS_REG158_DEFAULT                                                  0x00000000
6033 #define ixRTAVFS_REG159_DEFAULT                                                  0x00000000
6034 #define ixRTAVFS_REG160_DEFAULT                                                  0x00000000
6035 #define ixRTAVFS_REG161_DEFAULT                                                  0x00000000
6036 #define ixRTAVFS_REG162_DEFAULT                                                  0x00000000
6037 #define ixRTAVFS_REG163_DEFAULT                                                  0x00000000
6038 #define ixRTAVFS_REG164_DEFAULT                                                  0x00000000
6039 #define ixRTAVFS_REG165_DEFAULT                                                  0x00000000
6040 #define ixRTAVFS_REG166_DEFAULT                                                  0x00000000
6041 #define ixRTAVFS_REG167_DEFAULT                                                  0x00000000
6042 #define ixRTAVFS_REG168_DEFAULT                                                  0x00000000
6043 #define ixRTAVFS_REG169_DEFAULT                                                  0x00000000
6044 #define ixRTAVFS_REG170_DEFAULT                                                  0x00000000
6045 #define ixRTAVFS_REG171_DEFAULT                                                  0x00000000
6046 #define ixRTAVFS_REG172_DEFAULT                                                  0x00000000
6047 #define ixRTAVFS_REG173_DEFAULT                                                  0x00000000
6048 #define ixRTAVFS_REG174_DEFAULT                                                  0x00000000
6049 #define ixRTAVFS_REG175_DEFAULT                                                  0x00000000
6050 #define ixRTAVFS_REG176_DEFAULT                                                  0x00000000
6051 #define ixRTAVFS_REG177_DEFAULT                                                  0x00000000
6052 #define ixRTAVFS_REG178_DEFAULT                                                  0x00000000
6053 #define ixRTAVFS_REG179_DEFAULT                                                  0x00000000
6054 #define ixRTAVFS_REG180_DEFAULT                                                  0x00000000
6055 #define ixRTAVFS_REG181_DEFAULT                                                  0x00000000
6056 #define ixRTAVFS_REG182_DEFAULT                                                  0x00000000
6057 #define ixRTAVFS_REG183_DEFAULT                                                  0x00000000
6058 #define ixRTAVFS_REG184_DEFAULT                                                  0x00000000
6059 #define ixRTAVFS_REG185_DEFAULT                                                  0x00000000
6060 #define ixRTAVFS_REG186_DEFAULT                                                  0x00000000
6061 #define ixRTAVFS_REG187_DEFAULT                                                  0x00000000
6062 #define ixRTAVFS_REG188_DEFAULT                                                  0x00000000
6063 #define ixRTAVFS_REG189_DEFAULT                                                  0x0007d12c
6064 #define ixRTAVFS_REG190_DEFAULT                                                  0x00000000
6065 #define ixRTAVFS_REG191_DEFAULT                                                  0x00000000
6066 #define ixRTAVFS_REG192_DEFAULT                                                  0x00000000
6067 #define ixRTAVFS_REG193_DEFAULT                                                  0x00000001
6068 #define ixRTAVFS_REG194_DEFAULT                                                  0x00000000
6069 
6070 
6071 // addressBlock: sqind
6072 #define ixSQ_DEBUG_STS_LOCAL_DEFAULT                                             0x00000000
6073 #define ixSQ_DEBUG_CTRL_LOCAL_DEFAULT                                            0x00000000
6074 #define ixSQ_WAVE_ACTIVE_DEFAULT                                                 0x00000000
6075 #define ixSQ_WAVE_VALID_AND_IDLE_DEFAULT                                         0x00000000
6076 #define ixSQ_WAVE_MODE_DEFAULT                                                   0x00000000
6077 #define ixSQ_WAVE_STATUS_DEFAULT                                                 0x00000000
6078 #define ixSQ_WAVE_TRAPSTS_DEFAULT                                                0x00000000
6079 #define ixSQ_WAVE_GPR_ALLOC_DEFAULT                                              0x00000000
6080 #define ixSQ_WAVE_LDS_ALLOC_DEFAULT                                              0x00000000
6081 #define ixSQ_WAVE_IB_STS_DEFAULT                                                 0x00000000
6082 #define ixSQ_WAVE_PC_LO_DEFAULT                                                  0x00000000
6083 #define ixSQ_WAVE_PC_HI_DEFAULT                                                  0x00000000
6084 #define ixSQ_WAVE_IB_DBG1_DEFAULT                                                0x00000000
6085 #define ixSQ_WAVE_FLUSH_IB_DEFAULT                                               0x00000000
6086 #define ixSQ_WAVE_FLAT_SCRATCH_LO_DEFAULT                                        0x00000000
6087 #define ixSQ_WAVE_FLAT_SCRATCH_HI_DEFAULT                                        0x00000000
6088 #define ixSQ_WAVE_HW_ID1_DEFAULT                                                 0x00000000
6089 #define ixSQ_WAVE_HW_ID2_DEFAULT                                                 0x00000000
6090 #define ixSQ_WAVE_POPS_PACKER_DEFAULT                                            0x00000000
6091 #define ixSQ_WAVE_SCHED_MODE_DEFAULT                                             0x00000000
6092 #define ixSQ_WAVE_IB_STS2_DEFAULT                                                0x00000000
6093 #define ixSQ_WAVE_SHADER_CYCLES_DEFAULT                                          0x00000000
6094 #define ixSQ_WAVE_TTMP0_DEFAULT                                                  0x00000000
6095 #define ixSQ_WAVE_TTMP1_DEFAULT                                                  0x00000000
6096 #define ixSQ_WAVE_TTMP3_DEFAULT                                                  0x00000000
6097 #define ixSQ_WAVE_TTMP4_DEFAULT                                                  0x00000000
6098 #define ixSQ_WAVE_TTMP5_DEFAULT                                                  0x00000000
6099 #define ixSQ_WAVE_TTMP6_DEFAULT                                                  0x00000000
6100 #define ixSQ_WAVE_TTMP7_DEFAULT                                                  0x00000000
6101 #define ixSQ_WAVE_TTMP8_DEFAULT                                                  0x00000000
6102 #define ixSQ_WAVE_TTMP9_DEFAULT                                                  0x00000000
6103 #define ixSQ_WAVE_TTMP10_DEFAULT                                                 0x00000000
6104 #define ixSQ_WAVE_TTMP11_DEFAULT                                                 0x00000000
6105 #define ixSQ_WAVE_TTMP12_DEFAULT                                                 0x00000000
6106 #define ixSQ_WAVE_TTMP13_DEFAULT                                                 0x00000000
6107 #define ixSQ_WAVE_TTMP14_DEFAULT                                                 0x00000000
6108 #define ixSQ_WAVE_TTMP15_DEFAULT                                                 0x00000000
6109 #define ixSQ_WAVE_M0_DEFAULT                                                     0x00000000
6110 #define ixSQ_WAVE_EXEC_LO_DEFAULT                                                0x00000000
6111 #define ixSQ_WAVE_EXEC_HI_DEFAULT                                                0x00000000
6112 
6113 
6114 #endif
6115