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Searched refs:DPU_CLK_CTRL_VIG1 (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_3_2_sdm660.h28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
78 .clk_ctrl = DPU_CLK_CTRL_VIG1,
H A Ddpu_4_0_sdm845.h29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
81 .clk_ctrl = DPU_CLK_CTRL_VIG1,
H A Ddpu_3_0_msm8998.h29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
83 .clk_ctrl = DPU_CLK_CTRL_VIG1,
H A Ddpu_5_2_sm7150.h29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
87 .clk_ctrl = DPU_CLK_CTRL_VIG1,
H A Ddpu_4_1_sdm670.h17 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
H A Ddpu_7_0_sm8350.h26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
89 .clk_ctrl = DPU_CLK_CTRL_VIG1,
H A Ddpu_5_0_sm8150.h29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
91 .clk_ctrl = DPU_CLK_CTRL_VIG1,
H A Ddpu_5_1_sc8180x.h29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
90 .clk_ctrl = DPU_CLK_CTRL_VIG1,
H A Ddpu_6_0_sm8250.h26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
89 .clk_ctrl = DPU_CLK_CTRL_VIG1,
H A Ddpu_8_1_sm8450.h27 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
90 .clk_ctrl = DPU_CLK_CTRL_VIG1,
H A Ddpu_8_0_sc8280xp.h27 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
89 .clk_ctrl = DPU_CLK_CTRL_VIG1,
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_catalog.h436 DPU_CLK_CTRL_VIG1, enumerator