1 /* 2 * Copyright 2014-2017 Cavium, Inc. 3 * The contents of this file are subject to the terms of the Common Development 4 * and Distribution License, v.1, (the "License"). 5 * 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the License at available 9 * at http://opensource.org/licenses/CDDL-1.0 10 * 11 * See the License for the specific language governing permissions and 12 * limitations under the License. 13 */ 14 15 #include "bcmtype.h" 16 17 #ifndef _5709_reg_h_ 18 #define _5709_reg_h_ 19 20 // ???? #pragma pack(4) 21 22 #ifndef STATUS_BLOCK_SPACING 23 #define STATUS_BLOCK_SPACING 64 24 #endif 25 26 #if !defined(LITTLE_ENDIAN) && !defined(BIG_ENDIAN) 27 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition." 28 #endif 29 30 31 32 /* 33 * tx_bd_b definition 34 */ 35 typedef struct tx_bd_b 36 { 37 u32_t tx_bd_haddr_hi; 38 u32_t tx_bd_haddr_lo; 39 u16_t tx_bd_reserved; 40 #define TX_BD_RESERVED_MSS (0x3fff<<0) 41 #define TX_BD_RESERVED_BIT14_15 (0x03<<14) 42 u16_t tx_bd_nbytes; 43 u16_t tx_bd_vlan_tag; 44 u16_t tx_bd_flags; 45 #define TX_BD_FLAGS_CONN_FAULT (1<<0) 46 #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1) 47 #define TX_BD_FLAGS_IP_CKSUM (1<<2) 48 #define TX_BD_FLAGS_VLAN_TAG (1<<3) 49 #define TX_BD_FLAGS_COAL_NOW (1<<4) 50 #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5) 51 #define TX_BD_FLAGS_END (1<<6) 52 #define TX_BD_FLAGS_START (1<<7) 53 #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8) 54 #define TX_BD_FLAGS_SW_OPTION_MSB (1<<12) 55 #define TX_BD_FLAGS_SW_END (1<<12) 56 #define TX_BD_FLAGS_SW_FLAGS (1<<13) 57 #define TX_BD_FLAGS_SW_SNAP (1<<14) 58 #define TX_BD_FLAGS_SW_LSO (1<<15) 59 60 } tx_bd_b_t; 61 62 63 /* 64 * tx_bd_l definition 65 */ 66 typedef struct tx_bd_l 67 { 68 u32_t tx_bd_haddr_hi; 69 u32_t tx_bd_haddr_lo; 70 u16_t tx_bd_nbytes; 71 u16_t tx_bd_reserved; 72 #define TX_BD_RESERVED_MSS (0x3fff<<0) 73 #define TX_BD_RESERVED_BIT14_15 (0x03<<14) 74 u16_t tx_bd_flags; 75 #define TX_BD_FLAGS_CONN_FAULT (1<<0) 76 #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1) 77 #define TX_BD_FLAGS_IP_CKSUM (1<<2) 78 #define TX_BD_FLAGS_VLAN_TAG (1<<3) 79 #define TX_BD_FLAGS_COAL_NOW (1<<4) 80 #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5) 81 #define TX_BD_FLAGS_END (1<<6) 82 #define TX_BD_FLAGS_START (1<<7) 83 #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8) 84 #define TX_BD_FLAGS_SW_OPTION_MSB (1<<12) 85 #define TX_BD_FLAGS_SW_END (1<<12) 86 #define TX_BD_FLAGS_SW_FLAGS (1<<13) 87 #define TX_BD_FLAGS_SW_SNAP (1<<14) 88 #define TX_BD_FLAGS_SW_LSO (1<<15) 89 90 u16_t tx_bd_vlan_tag; 91 } tx_bd_l_t; 92 93 94 /* 95 * tx_bd select 96 */ 97 #if defined(LITTLE_ENDIAN) 98 typedef tx_bd_l_t tx_bd_t; 99 #elif defined(BIG_ENDIAN) 100 typedef tx_bd_b_t tx_bd_t; 101 #endif 102 103 104 /* 105 * tx_bd_next definition 106 */ 107 typedef struct tx_bd_next 108 { 109 u32_t tx_bd_next_paddr_hi; 110 u32_t tx_bd_next_paddr_lo; 111 u8_t tx_bd_next_reserved[8]; 112 } tx_bd_next_t; 113 114 115 /* 116 * hqc_basic_b definition 117 */ 118 typedef struct hqc_basic_b 119 { 120 u8_t hqc_type; 121 #define HQC_TYPE_N64W (0xf<<0) 122 #define HQC_TYPE_VALUE (0xf<<4) 123 #define HQC_TYPE_VALUE_BASIC (0<<4) 124 #define HQC_TYPE_VALUE_TOE (1<<4) 125 #define HQC_TYPE_VALUE_HOLE (2<<4) 126 #define HQC_TYPE_VALUE_LSO_CAPTURE (3<<4) 127 #define HQC_TYPE_VALUE_LSO_DUPLICATE (4<<4) 128 #define HQC_TYPE_VALUE_IWARP_STD (5<<4) 129 #define HQC_TYPE_VALUE_IWARP_EDGE (6<<4) 130 131 u8_t hqc_knum; 132 u16_t hqc_hdr_nbytes; 133 u32_t unused_0; 134 } hqc_basic_b_t; 135 136 137 /* 138 * hqc_basic_l definition 139 */ 140 typedef struct hqc_basic_l 141 { 142 u16_t hqc_hdr_nbytes; 143 u8_t hqc_knum; 144 u8_t hqc_type; 145 #define HQC_TYPE_N64W (0xf<<0) 146 #define HQC_TYPE_VALUE (0xf<<4) 147 #define HQC_TYPE_VALUE_BASIC (0<<4) 148 #define HQC_TYPE_VALUE_TOE (1<<4) 149 #define HQC_TYPE_VALUE_HOLE (2<<4) 150 #define HQC_TYPE_VALUE_LSO_CAPTURE (3<<4) 151 #define HQC_TYPE_VALUE_LSO_DUPLICATE (4<<4) 152 #define HQC_TYPE_VALUE_IWARP_STD (5<<4) 153 #define HQC_TYPE_VALUE_IWARP_EDGE (6<<4) 154 #define HQC_TYPE_VALUE_ISCSI (7<<4) 155 u32_t unused_0; 156 } hqc_basic_l_t; 157 158 159 /* 160 * hqc_basic select 161 */ 162 #if defined(LITTLE_ENDIAN) 163 typedef hqc_basic_l_t hqc_basic_t; 164 #elif defined(BIG_ENDIAN) 165 typedef hqc_basic_b_t hqc_basic_t; 166 #endif 167 168 169 /* 170 * hqc_toe_b definition 171 */ 172 typedef struct hqc_toe_b 173 { 174 u8_t hqt_type; 175 u8_t hqt_knum; 176 u16_t hqt_hdr_nbytes; 177 #define HQT_HDR_NBYTES_VALUE (0x3fff<<0) 178 #define HQT_HDR_NBYTES_PLUS_TWO (1<<15) 179 180 u16_t unused_0; 181 u16_t hqt_xsum_boff; 182 } hqc_toe_b_t; 183 184 185 /* 186 * hqc_toe_l definition 187 */ 188 typedef struct hqc_toe_l 189 { 190 u16_t hqt_hdr_nbytes; 191 #define HQT_HDR_NBYTES_VALUE (0x3fff<<0) 192 #define HQT_HDR_NBYTES_PLUS_TWO (1<<15) 193 194 u8_t hqt_knum; 195 u8_t hqt_type; 196 u16_t hqt_xsum_boff; 197 u16_t unused_0; 198 } hqc_toe_l_t; 199 200 201 /* 202 * hqc_toe select 203 */ 204 #if defined(LITTLE_ENDIAN) 205 typedef hqc_toe_l_t hqc_toe_t; 206 #elif defined(BIG_ENDIAN) 207 typedef hqc_toe_b_t hqc_toe_t; 208 #endif 209 210 211 /* 212 * hqc_hole_b definition 213 */ 214 typedef struct hqc_hole_b 215 { 216 u8_t hqh_type; 217 u8_t hqh_knum; 218 u16_t hqh_hdr_nbytes; 219 #define HQH_HDR_NBYTES_VALUE (0x3fff<<0) 220 #define HQH_HDR_NBYTES_PLUS_TWO (1<<15) 221 222 u16_t hqh_hole_bytes; 223 u16_t hqh_hole_pos; 224 u8_t hqh_value[4]; 225 u32_t unused_0; 226 } hqc_hole_b_t; 227 228 229 /* 230 * hqc_hole_l definition 231 */ 232 typedef struct hqc_hole_l 233 { 234 u16_t hqh_hdr_nbytes; 235 #define HQH_HDR_NBYTES_VALUE (0x3fff<<0) 236 #define HQH_HDR_NBYTES_PLUS_TWO (1<<15) 237 238 u8_t hqh_knum; 239 u8_t hqh_type; 240 u16_t hqh_hole_pos; 241 u16_t hqh_hole_bytes; 242 u8_t hqh_value[4]; 243 u32_t unused_0; 244 } hqc_hole_l_t; 245 246 247 /* 248 * hqc_hole select 249 */ 250 #if defined(LITTLE_ENDIAN) 251 typedef hqc_hole_l_t hqc_hole_t; 252 #elif defined(BIG_ENDIAN) 253 typedef hqc_hole_b_t hqc_hole_t; 254 #endif 255 256 257 /* 258 * hqc_lso_cap_b definition 259 */ 260 typedef struct hqc_lso_cap_b 261 { 262 u8_t hqca_type; 263 u8_t hqca_knum; 264 u16_t hqca_hdr_nbytes; 265 #define HQCA_HDR_NBYTES_VALUE (0x3fff<<0) 266 #define HQCA_HDR_NBYTES_PLUS_TWO (1<<15) 267 268 u16_t hqca_cap_hdr_nbytes; 269 u16_t hqca_l2hdr_nbytes; 270 u32_t hqca_vlan_tag; 271 u32_t hqca_ipv6_exthdr_len; 272 #define HQDU_FLAGS_IPV6_EXTHDR_LEN (0x7fffffffUL<<0) 273 #define HQDU_FLAGS_BSEQ_FLAGS_LAST_PKT (1UL<<31) 274 } hqc_lso_cap_b_t; 275 276 277 /* 278 * hqc_lso_cap_l definition 279 */ 280 typedef struct hqc_lso_cap_l 281 { 282 u16_t hqca_hdr_nbytes; 283 #define HQCA_HDR_NBYTES_VALUE (0x3fff<<0) 284 #define HQCA_HDR_NBYTES_PLUS_TWO (1<<15) 285 286 u8_t hqca_knum; 287 u8_t hqca_type; 288 u16_t hqca_l2hdr_nbytes; 289 u16_t hqca_cap_hdr_nbytes; 290 u32_t hqca_vlan_tag; 291 u32_t hqca_ipv6_exthdr_len; 292 #define HQDU_FLAGS_IPV6_EXTHDR_LEN (0x7fffffffUL<<0) 293 #define HQDU_FLAGS_BSEQ_FLAGS_LAST_PKT (1UL<<31) 294 } hqc_lso_cap_l_t; 295 296 297 /* 298 * hqc_lso_cap select 299 */ 300 #if defined(LITTLE_ENDIAN) 301 typedef hqc_lso_cap_l_t hqc_lso_cap_t; 302 #elif defined(BIG_ENDIAN) 303 typedef hqc_lso_cap_b_t hqc_lso_cap_t; 304 #endif 305 306 307 /* 308 * hqc_lso_dup_b definition 309 */ 310 typedef struct hqc_lso_dup_b 311 { 312 u8_t hqdu_type; 313 u8_t hqdu_knum; 314 u16_t hqdu_hdr_nbytes; 315 #define HQDU_HDR_NBYTES_VALUE (0x3fff<<0) 316 #define HQDU_HDR_NBYTES_PLUS_TWO (1<<15) 317 318 u32_t hqdu_flags_bseq; 319 #define HQDU_FLAGS_BSEQ_BSEQ_VALUE (0x7fffffffUL<<0) 320 #define HQDU_FLAGS_BSEQ_FLAGS_LAST_PKT (1UL<<31) 321 322 } hqc_lso_dup_b_t; 323 324 325 /* 326 * hqc_lso_dup_l definition 327 */ 328 typedef struct hqc_lso_dup_l 329 { 330 u16_t hqdu_hdr_nbytes; 331 #define HQDU_HDR_NBYTES_VALUE (0x3fff<<0) 332 #define HQDU_HDR_NBYTES_PLUS_TWO (1<<15) 333 334 u8_t hqdu_knum; 335 u8_t hqdu_type; 336 u32_t hqdu_flags_bseq; 337 #define HQDU_FLAGS_BSEQ_BSEQ_VALUE (0x7fffffffUL<<0) 338 #define HQDU_FLAGS_BSEQ_FLAGS_LAST_PKT (1UL<<31) 339 340 } hqc_lso_dup_l_t; 341 342 343 /* 344 * hqc_lso_dup select 345 */ 346 #if defined(LITTLE_ENDIAN) 347 typedef hqc_lso_dup_l_t hqc_lso_dup_t; 348 #elif defined(BIG_ENDIAN) 349 typedef hqc_lso_dup_b_t hqc_lso_dup_t; 350 #endif 351 352 353 /* 354 * hqc_iwarp_std_b definition 355 */ 356 typedef struct hqc_iwarp_std_b 357 { 358 u8_t hqis_type; 359 u8_t hqis_knum; 360 u16_t hqis_hdr_nbytes; 361 #define HQIS_HDR_NBYTES_HDR_NBYTES_VALUE (0x3fff<<0) 362 363 u16_t hqis_l5_hdr_nbytes; 364 u16_t hqis_xsum_boff; 365 } hqc_iwarp_std_b_t; 366 367 368 /* 369 * hqc_iwarp_std_l definition 370 */ 371 typedef struct hqc_iwarp_std_l 372 { 373 u16_t hqis_hdr_nbytes; 374 #define HQIS_HDR_NBYTES_HDR_NBYTES_VALUE (0x3fff<<0) 375 376 u8_t hqis_knum; 377 u8_t hqis_type; 378 u16_t hqis_xsum_boff; 379 u16_t hqis_l5_hdr_nbytes; 380 } hqc_iwarp_std_l_t; 381 382 383 /* 384 * hqc_iwarp_std select 385 */ 386 #if defined(LITTLE_ENDIAN) 387 typedef hqc_iwarp_std_l_t hqc_iwarp_std_t; 388 #elif defined(BIG_ENDIAN) 389 typedef hqc_iwarp_std_b_t hqc_iwarp_std_t; 390 #endif 391 392 393 /* 394 * hqc_iwarp_edge_b definition 395 */ 396 typedef struct hqc_iwarp_edge_b 397 { 398 u8_t hqie_type; 399 u8_t hqie_knum; 400 u16_t hqie_hdr_nbytes; 401 #define HQIE_HDR_NBYTES_HDR_NBYTES_VALUE (0x3fff<<0) 402 403 u16_t hqie_l5_hdr_nbytes; 404 u16_t hqie_xsum_boff; 405 u32_t hqie_marker_value; 406 u32_t unused_0; 407 } hqc_iwarp_edge_b_t; 408 409 410 /* 411 * hqc_iwarp_edge_l definition 412 */ 413 typedef struct hqc_iwarp_edge_l 414 { 415 u16_t hqie_hdr_nbytes; 416 #define HQIE_HDR_NBYTES_HDR_NBYTES_VALUE (0x3fff<<0) 417 418 u8_t hqie_knum; 419 u8_t hqie_type; 420 u16_t hqie_xsum_boff; 421 u16_t hqie_l5_hdr_nbytes; 422 u32_t hqie_marker_value; 423 u32_t unused_0; 424 } hqc_iwarp_edge_l_t; 425 426 427 /* 428 * hqc_iwarp_edge select 429 */ 430 #if defined(LITTLE_ENDIAN) 431 typedef hqc_iwarp_edge_l_t hqc_iwarp_edge_t; 432 #elif defined(BIG_ENDIAN) 433 typedef hqc_iwarp_edge_b_t hqc_iwarp_edge_t; 434 #endif 435 436 437 /* 438 * rx_bd_b definition 439 */ 440 typedef struct rx_bd_b 441 { 442 u32_t rx_bd_haddr_hi; 443 u32_t rx_bd_haddr_lo; 444 u32_t rx_bd_len; 445 u16_t unused_0; 446 u16_t rx_bd_flags; 447 #define RX_BD_FLAGS_NOPUSH (1<<0) 448 #define RX_BD_FLAGS_DUMMY (1<<1) 449 #define RX_BD_FLAGS_END (1<<2) 450 #define RX_BD_FLAGS_START (1<<3) 451 #define RX_BD_FLAGS_INTRMDT (1<<4) // intermediate boundary for partial io buffer 452 #define RX_BD_FLAGS_HEADERSPLIT (1<<5) 453 } rx_bd_b_t; 454 455 456 /* 457 * rx_bd_l definition 458 */ 459 typedef struct rx_bd_l 460 { 461 u32_t rx_bd_haddr_hi; 462 u32_t rx_bd_haddr_lo; 463 u32_t rx_bd_len; 464 u16_t rx_bd_flags; 465 #define RX_BD_FLAGS_NOPUSH (1<<0) 466 #define RX_BD_FLAGS_DUMMY (1<<1) 467 #define RX_BD_FLAGS_END (1<<2) 468 #define RX_BD_FLAGS_START (1<<3) 469 #define RX_BD_FLAGS_INTRMDT (1<<4) // intermediate boundary for partial io buffer 470 #define RX_BD_FLAGS_HEADERSPLIT (1<<5) 471 u16_t unused_0; 472 } rx_bd_l_t; 473 474 475 /* 476 * rx_bd select 477 */ 478 #if defined(LITTLE_ENDIAN) 479 typedef rx_bd_l_t rx_bd_t; 480 #elif defined(BIG_ENDIAN) 481 typedef rx_bd_b_t rx_bd_t; 482 #endif 483 484 485 /* 486 * rx_generic_bd_b definition 487 */ 488 typedef struct rx_generic_bd_b 489 { 490 u16_t rx_generic_bd_tag; 491 u16_t rx_generic_bd_haddr_hi; 492 u32_t rx_generic_bd_haddr_lo; 493 #define RX_GENERIC_BD_HADDR_LO_SELECT (0x3UL<<0) 494 #define RX_GENERIC_BD_HADDR_LO_ADDR (0x3fffUL<<2) 495 496 u32_t rx_generic_bd_len; 497 u16_t unused_0; 498 u16_t rx_generic_bd_flags; 499 #define RX_GENERIC_BD_FLAGS_END (1<<2) 500 #define RX_GENERIC_BD_FLAGS_START (1<<3) 501 502 } rx_generic_bd_b_t; 503 504 505 /* 506 * rx_generic_bd_l definition 507 */ 508 typedef struct rx_generic_bd_l 509 { 510 u16_t rx_generic_bd_haddr_hi; 511 u16_t rx_generic_bd_tag; 512 u32_t rx_generic_bd_haddr_lo; 513 #define RX_GENERIC_BD_HADDR_LO_SELECT (0x3UL<<0) 514 #define RX_GENERIC_BD_HADDR_LO_ADDR (0x3fffUL<<2) 515 516 u32_t rx_generic_bd_len; 517 u16_t rx_generic_bd_flags; 518 #define RX_GENERIC_BD_FLAGS_END (1<<2) 519 #define RX_GENERIC_BD_FLAGS_START (1<<3) 520 521 u16_t unused_0; 522 } rx_generic_bd_l_t; 523 524 525 /* 526 * rx_generic_bd select 527 */ 528 #if defined(LITTLE_ENDIAN) 529 typedef rx_generic_bd_l_t rx_generic_bd_t; 530 #elif defined(BIG_ENDIAN) 531 typedef rx_generic_bd_b_t rx_generic_bd_t; 532 #endif 533 534 535 /* 536 * attentions definition 537 */ 538 typedef struct attentions 539 { 540 u32_t attentions_bits; 541 #define ATTENTIONS_BITS_LINK_STATE (1UL<<0) 542 #define ATTENTIONS_BITS_TX_SCHEDULER_ABORT (1UL<<1) 543 #define ATTENTIONS_BITS_TX_BD_READ_ABORT (1UL<<2) 544 #define ATTENTIONS_BITS_TX_BD_CACHE_ABORT (1UL<<3) 545 #define ATTENTIONS_BITS_TX_PROCESSOR_ABORT (1UL<<4) 546 #define ATTENTIONS_BITS_TX_DMA_ABORT (1UL<<5) 547 #define ATTENTIONS_BITS_TX_PATCHUP_ABORT (1UL<<6) 548 #define ATTENTIONS_BITS_TX_ASSEMBLER_ABORT (1UL<<7) 549 #define ATTENTIONS_BITS_RX_PARSER_MAC_ABORT (1UL<<8) 550 #define ATTENTIONS_BITS_RX_PARSER_CATCHUP_ABORT (1UL<<9) 551 #define ATTENTIONS_BITS_RX_MBUF_ABORT (1UL<<10) 552 #define ATTENTIONS_BITS_RX_LOOKUP_ABORT (1UL<<11) 553 #define ATTENTIONS_BITS_RX_PROCESSOR_ABORT (1UL<<12) 554 #define ATTENTIONS_BITS_RX_V2P_ABORT (1UL<<13) 555 #define ATTENTIONS_BITS_RX_BD_CACHE_ABORT (1UL<<14) 556 #define ATTENTIONS_BITS_RX_DMA_ABORT (1UL<<15) 557 #define ATTENTIONS_BITS_COMPLETION_ABORT (1UL<<16) 558 #define ATTENTIONS_BITS_HOST_COALESCE_ABORT (1UL<<17) 559 #define ATTENTIONS_BITS_MAILBOX_QUEUE_ABORT (1UL<<18) 560 #define ATTENTIONS_BITS_CONTEXT_ABORT (1UL<<19) 561 #define ATTENTIONS_BITS_CMD_SCHEDULER_ABORT (1UL<<20) 562 #define ATTENTIONS_BITS_CMD_PROCESSOR_ABORT (1UL<<21) 563 #define ATTENTIONS_BITS_MGMT_PROCESSOR_ABORT (1UL<<22) 564 #define ATTENTIONS_BITS_MAC_ABORT (1UL<<23) 565 #define ATTENTIONS_BITS_TIMER_ABORT (1UL<<24) 566 #define ATTENTIONS_BITS_DMAE_ABORT (1UL<<25) 567 #define ATTENTIONS_BITS_FLSH_ABORT (1UL<<26) 568 #define ATTENTIONS_BITS_GRC_ABORT (1UL<<27) 569 #define ATTENTIONS_BITS_EPB_ERROR (1UL<<30) 570 #define ATTENTIONS_BITS_PARITY_ERROR (1UL<<31) 571 572 } attentions_t; 573 574 575 /* 576 * status_block_b definition 577 */ 578 typedef struct status_block_b 579 { 580 u32_t status_attn_bits; 581 #define STATUS_ATTN_BITS_LINK_STATE (1UL<<0) 582 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1UL<<1) 583 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1UL<<2) 584 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1UL<<3) 585 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1UL<<4) 586 #define STATUS_ATTN_BITS_TX_DMA_ABORT (1UL<<5) 587 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1UL<<6) 588 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1UL<<7) 589 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1UL<<8) 590 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1UL<<9) 591 #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1UL<<10) 592 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1UL<<11) 593 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1UL<<12) 594 #define STATUS_ATTN_BITS_RX_V2P_ABORT (1UL<<13) 595 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1UL<<14) 596 #define STATUS_ATTN_BITS_RX_DMA_ABORT (1UL<<15) 597 #define STATUS_ATTN_BITS_COMPLETION_ABORT (1UL<<16) 598 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1UL<<17) 599 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1UL<<18) 600 #define STATUS_ATTN_BITS_CONTEXT_ABORT (1UL<<19) 601 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1UL<<20) 602 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1UL<<21) 603 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1UL<<22) 604 #define STATUS_ATTN_BITS_MAC_ABORT (1UL<<23) 605 #define STATUS_ATTN_BITS_TIMER_ABORT (1UL<<24) 606 #define STATUS_ATTN_BITS_DMAE_ABORT (1UL<<25) 607 #define STATUS_ATTN_BITS_FLSH_ABORT (1UL<<26) 608 #define STATUS_ATTN_BITS_GRC_ABORT (1UL<<27) 609 #define STATUS_ATTN_BITS_EPB_ERROR (1UL<<30) 610 #define STATUS_ATTN_BITS_PARITY_ERROR (1UL<<31) 611 612 u32_t status_attn_bits_ack; 613 u16_t status_tx_quick_consumer_index0; 614 u16_t status_tx_quick_consumer_index1; 615 u16_t status_tx_quick_consumer_index2; 616 u16_t status_tx_quick_consumer_index3; 617 u16_t status_rx_quick_consumer_index0; 618 u16_t status_rx_quick_consumer_index1; 619 u16_t status_rx_quick_consumer_index2; 620 u16_t status_rx_quick_consumer_index3; 621 u16_t status_rx_quick_consumer_index4; 622 u16_t status_rx_quick_consumer_index5; 623 u16_t status_rx_quick_consumer_index6; 624 u16_t status_rx_quick_consumer_index7; 625 u16_t status_rx_quick_consumer_index8; 626 u16_t status_rx_quick_consumer_index9; 627 u16_t status_rx_quick_consumer_index10; 628 u16_t status_rx_quick_consumer_index11; 629 u16_t status_rx_quick_consumer_index12; 630 u16_t status_rx_quick_consumer_index13; 631 u16_t status_rx_quick_consumer_index14; 632 u16_t status_rx_quick_consumer_index15; 633 u16_t status_completion_producer_index; 634 u16_t status_cmd_consumer_index; 635 u16_t status_idx; 636 u8_t unused_0; 637 u8_t status_blk_num; 638 u32_t unused_1[2]; 639 #if (STATUS_BLOCK_SPACING > 64) 640 u32_t unused_z[STATUS_BLOCK_SPACING/4-64/4]; 641 #endif 642 643 } status_block_b_t; 644 645 646 /* 647 * status_block_l definition 648 */ 649 typedef struct status_block_l 650 { 651 u32_t status_attn_bits; 652 #define STATUS_ATTN_BITS_LINK_STATE (1UL<<0) 653 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1UL<<1) 654 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1UL<<2) 655 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1UL<<3) 656 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1UL<<4) 657 #define STATUS_ATTN_BITS_TX_DMA_ABORT (1UL<<5) 658 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1UL<<6) 659 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1UL<<7) 660 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1UL<<8) 661 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1UL<<9) 662 #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1UL<<10) 663 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1UL<<11) 664 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1UL<<12) 665 #define STATUS_ATTN_BITS_RX_V2P_ABORT (1UL<<13) 666 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1UL<<14) 667 #define STATUS_ATTN_BITS_RX_DMA_ABORT (1UL<<15) 668 #define STATUS_ATTN_BITS_COMPLETION_ABORT (1UL<<16) 669 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1UL<<17) 670 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1UL<<18) 671 #define STATUS_ATTN_BITS_CONTEXT_ABORT (1UL<<19) 672 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1UL<<20) 673 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1UL<<21) 674 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1UL<<22) 675 #define STATUS_ATTN_BITS_MAC_ABORT (1UL<<23) 676 #define STATUS_ATTN_BITS_TIMER_ABORT (1UL<<24) 677 #define STATUS_ATTN_BITS_DMAE_ABORT (1UL<<25) 678 #define STATUS_ATTN_BITS_FLSH_ABORT (1UL<<26) 679 #define STATUS_ATTN_BITS_GRC_ABORT (1UL<<27) 680 #define STATUS_ATTN_BITS_EPB_ERROR (1UL<<30) 681 #define STATUS_ATTN_BITS_PARITY_ERROR (1UL<<31) 682 683 u32_t status_attn_bits_ack; 684 u16_t status_tx_quick_consumer_index1; 685 u16_t status_tx_quick_consumer_index0; 686 u16_t status_tx_quick_consumer_index3; 687 u16_t status_tx_quick_consumer_index2; 688 u16_t status_rx_quick_consumer_index1; 689 u16_t status_rx_quick_consumer_index0; 690 u16_t status_rx_quick_consumer_index3; 691 u16_t status_rx_quick_consumer_index2; 692 u16_t status_rx_quick_consumer_index5; 693 u16_t status_rx_quick_consumer_index4; 694 u16_t status_rx_quick_consumer_index7; 695 u16_t status_rx_quick_consumer_index6; 696 u16_t status_rx_quick_consumer_index9; 697 u16_t status_rx_quick_consumer_index8; 698 u16_t status_rx_quick_consumer_index11; 699 u16_t status_rx_quick_consumer_index10; 700 u16_t status_rx_quick_consumer_index13; 701 u16_t status_rx_quick_consumer_index12; 702 u16_t status_rx_quick_consumer_index15; 703 u16_t status_rx_quick_consumer_index14; 704 u16_t status_cmd_consumer_index; 705 u16_t status_completion_producer_index; 706 u8_t status_blk_num; 707 u8_t unused_0; 708 u16_t status_idx; 709 u32_t unused_1[2]; 710 #if (STATUS_BLOCK_SPACING > 64) 711 u32_t unused_z[STATUS_BLOCK_SPACING/4-64/4]; 712 #endif 713 714 } status_block_l_t; 715 716 717 /* 718 * status_block select 719 */ 720 #if defined(LITTLE_ENDIAN) 721 typedef status_block_l_t status_block_t; 722 #elif defined(BIG_ENDIAN) 723 typedef status_block_b_t status_block_t; 724 #endif 725 726 727 /* 728 * status_per_cpu_block_b definition 729 */ 730 typedef struct status_per_cpu_block_b 731 { 732 u16_t status_pcpu_tx_quick_consumer_index; 733 u16_t status_pcpu_rx_quick_consumer_index; 734 u16_t status_pcpu_completion_producer_index; 735 u16_t status_pcpu_cmd_consumer_index; 736 u32_t unused_0; 737 u16_t status_pcpu_idx; 738 u8_t unused_1; 739 u8_t status_pcpu_blk_num; 740 u32_t unused_z[STATUS_BLOCK_SPACING/4-16/4]; 741 742 } status_per_cpu_block_b_t; 743 744 745 /* 746 * status_per_cpu_block_l definition 747 */ 748 typedef struct status_per_cpu_block_l 749 { 750 u16_t status_pcpu_rx_quick_consumer_index; 751 u16_t status_pcpu_tx_quick_consumer_index; 752 u16_t status_pcpu_cmd_consumer_index; 753 u16_t status_pcpu_completion_producer_index; 754 u32_t unused_0; 755 u8_t status_pcpu_blk_num; 756 u8_t unused_1; 757 u16_t status_pcpu_idx; 758 u32_t unused_z[STATUS_BLOCK_SPACING/4-16/4]; 759 760 } status_per_cpu_block_l_t; 761 762 763 /* 764 * status_per_cpu_block select 765 */ 766 #if defined(LITTLE_ENDIAN) 767 typedef status_per_cpu_block_l_t status_per_cpu_block_t; 768 #elif defined(BIG_ENDIAN) 769 typedef status_per_cpu_block_b_t status_per_cpu_block_t; 770 #endif 771 772 773 /* 774 * status_blk_combined definition 775 */ 776 typedef struct status_blk_combined 777 { 778 status_block_t deflt; 779 status_per_cpu_block_t proc[8]; 780 } status_blk_combined_t; 781 782 783 /* 784 * statistics_block definition 785 */ 786 typedef struct statistics_block 787 { 788 u32_t stat_IfHCInOctets_hi; 789 u32_t stat_IfHCInOctets_lo; 790 u32_t stat_IfHCInBadOctets_hi; 791 u32_t stat_IfHCInBadOctets_lo; 792 u32_t stat_IfHCOutOctets_hi; 793 u32_t stat_IfHCOutOctets_lo; 794 u32_t stat_IfHCOutBadOctets_hi; 795 u32_t stat_IfHCOutBadOctets_lo; 796 u32_t stat_IfHCInUcastPkts_hi; 797 u32_t stat_IfHCInUcastPkts_lo; 798 u32_t stat_IfHCInMulticastPkts_hi; 799 u32_t stat_IfHCInMulticastPkts_lo; 800 u32_t stat_IfHCInBroadcastPkts_hi; 801 u32_t stat_IfHCInBroadcastPkts_lo; 802 u32_t stat_IfHCOutUcastPkts_hi; 803 u32_t stat_IfHCOutUcastPkts_lo; 804 u32_t stat_IfHCOutMulticastPkts_hi; 805 u32_t stat_IfHCOutMulticastPkts_lo; 806 u32_t stat_IfHCOutBroadcastPkts_hi; 807 u32_t stat_IfHCOutBroadcastPkts_lo; 808 u32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 809 u32_t stat_Dot3StatsCarrierSenseErrors; 810 u32_t stat_Dot3StatsFCSErrors; 811 u32_t stat_Dot3StatsAlignmentErrors; 812 u32_t stat_Dot3StatsSingleCollisionFrames; 813 u32_t stat_Dot3StatsMultipleCollisionFrames; 814 u32_t stat_Dot3StatsDeferredTransmissions; 815 u32_t stat_Dot3StatsExcessiveCollisions; 816 u32_t stat_Dot3StatsLateCollisions; 817 u32_t stat_EtherStatsCollisions; 818 u32_t stat_EtherStatsFragments; 819 u32_t stat_EtherStatsJabbers; 820 u32_t stat_EtherStatsUndersizePkts; 821 u32_t stat_EtherStatsOverrsizePkts; 822 u32_t stat_EtherStatsPktsRx64Octets; 823 u32_t stat_EtherStatsPktsRx65Octetsto127Octets; 824 u32_t stat_EtherStatsPktsRx128Octetsto255Octets; 825 u32_t stat_EtherStatsPktsRx256Octetsto511Octets; 826 u32_t stat_EtherStatsPktsRx512Octetsto1023Octets; 827 u32_t stat_EtherStatsPktsRx1024Octetsto1522Octets; 828 u32_t stat_EtherStatsPktsRx1523Octetsto9022Octets; 829 u32_t stat_EtherStatsPktsTx64Octets; 830 u32_t stat_EtherStatsPktsTx65Octetsto127Octets; 831 u32_t stat_EtherStatsPktsTx128Octetsto255Octets; 832 u32_t stat_EtherStatsPktsTx256Octetsto511Octets; 833 u32_t stat_EtherStatsPktsTx512Octetsto1023Octets; 834 u32_t stat_EtherStatsPktsTx1024Octetsto1522Octets; 835 u32_t stat_EtherStatsPktsTx1523Octetsto9022Octets; 836 u32_t stat_XonPauseFramesReceived; 837 u32_t stat_XoffPauseFramesReceived; 838 u32_t stat_OutXonSent; 839 u32_t stat_OutXoffSent; 840 u32_t stat_FlowControlDone; 841 u32_t stat_MacControlFramesReceived; 842 u32_t stat_XoffStateEntered; 843 u32_t stat_IfInFramesL2FilterDiscards; 844 u32_t stat_IfInRuleCheckerDiscards; 845 u32_t stat_IfInFTQDiscards; 846 u32_t stat_IfInMBUFDiscards; 847 u32_t stat_IfInRuleCheckerP4Hit; 848 u32_t stat_CatchupInRuleCheckerDiscards; 849 u32_t stat_CatchupInFTQDiscards; 850 u32_t stat_CatchupInMBUFDiscards; 851 u32_t stat_CatchupInRuleCheckerP4Hit; 852 u32_t stat_GenStat00; 853 u32_t stat_GenStat01; 854 u32_t stat_GenStat02; 855 u32_t stat_GenStat03; 856 u32_t stat_GenStat04; 857 u32_t stat_GenStat05; 858 u32_t stat_GenStat06; 859 u32_t stat_GenStat07; 860 u32_t stat_GenStat08; 861 u32_t stat_GenStat09; 862 u32_t stat_GenStat10; 863 u32_t stat_GenStat11; 864 u32_t stat_GenStat12; 865 u32_t stat_GenStat13; 866 u32_t stat_GenStat14; 867 u32_t stat_GenStat15; 868 } statistics_block_t; 869 870 871 /* 872 * l2_fhdr_b definition 873 */ 874 typedef struct l2_fhdr_b 875 { 876 u16_t l2_fhdr_errors; 877 #define L2_FHDR_ERRORS_ABORT_PKT (1<<0) 878 #define L2_FHDR_ERRORS_BAD_CRC (1<<1) 879 #define L2_FHDR_ERRORS_PHY_DECODE (1<<2) 880 #define L2_FHDR_ERRORS_ALIGNMENT (1<<3) 881 #define L2_FHDR_ERRORS_TOO_SHORT (1<<4) 882 #define L2_FHDR_ERRORS_GIANT_FRAME (1<<5) 883 #define L2_FHDR_ERRORS_IP_BAD_XSUM (1<<10) 884 #define L2_FHDR_ERRORS_TCP_BAD_XSUM (1<<12) 885 #define L2_FHDR_ERRORS_UDP_BAD_XSUM (1<<15) 886 887 u16_t l2_fhdr_status; 888 #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0) 889 #define L2_FHDR_STATUS_RULE_P2 (1<<3) 890 #define L2_FHDR_STATUS_RULE_P3 (1<<4) 891 #define L2_FHDR_STATUS_RULE_P4 (1<<5) 892 #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6) 893 #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7) 894 #define L2_FHDR_STATUS_RSS_HASH (1<<8) 895 #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13) 896 #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14) 897 #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15) 898 899 u32_t l2_fhdr_hash; 900 u16_t l2_fhdr_pkt_len; 901 u16_t l2_fhdr_vlan_tag; 902 u16_t l2_fhdr_ip_xsum; 903 u16_t l2_fhdr_tcp_udp_xsum; 904 } l2_fhdr_b_t; 905 906 907 /* 908 * l2_fhdr_l definition 909 */ 910 typedef struct l2_fhdr_l 911 { 912 u16_t l2_fhdr_status; 913 #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0) 914 #define L2_FHDR_STATUS_RULE_P2 (1<<3) 915 #define L2_FHDR_STATUS_RULE_P3 (1<<4) 916 #define L2_FHDR_STATUS_RULE_P4 (1<<5) 917 #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6) 918 #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7) 919 #define L2_FHDR_STATUS_RSS_HASH (1<<8) 920 #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13) 921 #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14) 922 #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15) 923 924 u16_t l2_fhdr_errors; 925 #define L2_FHDR_ERRORS_ABORT_PKT (1<<0) 926 #define L2_FHDR_ERRORS_BAD_CRC (1<<1) 927 #define L2_FHDR_ERRORS_PHY_DECODE (1<<2) 928 #define L2_FHDR_ERRORS_ALIGNMENT (1<<3) 929 #define L2_FHDR_ERRORS_TOO_SHORT (1<<4) 930 #define L2_FHDR_ERRORS_GIANT_FRAME (1<<5) 931 #define L2_FHDR_ERRORS_IP_BAD_XSUM (1<<10) 932 #define L2_FHDR_ERRORS_TCP_BAD_XSUM (1<<12) 933 #define L2_FHDR_ERRORS_UDP_BAD_XSUM (1<<15) 934 935 u32_t l2_fhdr_hash; 936 u16_t l2_fhdr_vlan_tag; 937 u16_t l2_fhdr_pkt_len; 938 u16_t l2_fhdr_tcp_udp_xsum; 939 u16_t l2_fhdr_ip_xsum; 940 } l2_fhdr_l_t; 941 942 943 /* 944 * l2_fhdr select 945 */ 946 #if defined(LITTLE_ENDIAN) 947 typedef l2_fhdr_l_t l2_fhdr_t; 948 #elif defined(BIG_ENDIAN) 949 typedef l2_fhdr_b_t l2_fhdr_t; 950 #endif 951 952 /* 953 * l2_fhdr_ooo_b definition 954 */ 955 typedef struct l2_fhdr_ooo_b 956 { 957 u8_t l2_fhdr_block_idx; 958 u8_t l2_fhdr_opcode; 959 #define L2_FHDR_OPCODE_ADD_PEN (0) 960 #define L2_FHDR_OPCODE_ADD_NEW (1) 961 #define L2_FHDR_OPCODE_ADD_RIGHT (2) 962 #define L2_FHDR_OPCODE_ADD_LEFT (3) 963 #define L2_FHDR_OPCODE_JOIN (4) 964 #define L2_FHDR_OPCODE_NOOP (5) 965 #define L2_FHDR_OPCODE_CLEAN_UP (10) 966 u8_t l2_fhdr_drop_size; 967 u8_t l2_fhdr_drop_block_idx; 968 u32_t l2_fhdr_icid; 969 970 u16_t l2_fhdr_pkt_len; 971 u16_t l2_fhdr_vlan_tag; 972 u16_t l2_fhdr_ip_xsum; 973 u16_t l2_fhdr_tcp_udp_xsum; 974 } l2_fhdr_ooo_b_t; 975 976 977 /* 978 * l2_fhdr_ooo_l definition 979 */ 980 typedef struct l2_fhdr_ooo_l 981 { 982 u8_t l2_fhdr_drop_block_idx; 983 u8_t l2_fhdr_drop_size; 984 u8_t l2_fhdr_opcode; 985 u8_t l2_fhdr_block_idx; 986 u32_t l2_fhdr_icid; 987 988 u16_t l2_fhdr_vlan_tag; 989 u16_t l2_fhdr_pkt_len; 990 u16_t l2_fhdr_tcp_udp_xsum; 991 u16_t l2_fhdr_ip_xsum; 992 } l2_fhdr_ooo_l_t; 993 994 /* 995 * l2_fhdr_ooo select 996 */ 997 #if defined(LITTLE_ENDIAN) 998 typedef l2_fhdr_ooo_l_t l2_fhdr_ooo_t; 999 #elif defined(BIG_ENDIAN) 1000 typedef l2_fhdr_ooo_b_t l2_fhdr_ooo_t; 1001 #endif 1002 1003 /* 1004 * pci_config definition 1005 * offset: 0000 1006 */ 1007 typedef struct pci_config 1008 { 1009 u16_t pcicfg_vendor_id; 1010 u16_t pcicfg_device_id; 1011 u16_t pcicfg_command; 1012 #define PCICFG_COMMAND_IO_SPACE (1<<0) 1013 #define PCICFG_COMMAND_MEM_SPACE (1<<1) 1014 #define PCICFG_COMMAND_BUS_MASTER (1<<2) 1015 #define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3) 1016 #define PCICFG_COMMAND_MWI_CYCLES (1<<4) 1017 #define PCICFG_COMMAND_VGA_SNOOP (1<<5) 1018 #define PCICFG_COMMAND_PERR_ENA (1<<6) 1019 #define PCICFG_COMMAND_STEPPING (1<<7) 1020 #define PCICFG_COMMAND_SERR_ENA (1<<8) 1021 #define PCICFG_COMMAND_FAST_B2B (1<<9) 1022 #define PCICFG_COMMAND_INT_DISABLE (1<<10) 1023 #define PCICFG_COMMAND_RESERVED (0x1f<<11) 1024 1025 u16_t pcicfg_status; 1026 #define PCICFG_STATUS_RESERVED1 (0x7<<0) 1027 #define PCICFG_STATUS_INT_STATUS (1<<3) 1028 #define PCICFG_STATUS_CAP_LIST (1<<4) 1029 #define PCICFG_STATUS_66MHZ_CAP (1<<5) 1030 #define PCICFG_STATUS_RESERVED2 (1<<6) 1031 #define PCICFG_STATUS_FAST_B2B_CAP (1<<7) 1032 #define PCICFG_STATUS_SIG_PERR_TE (1<<8) 1033 #define PCICFG_STATUS_MSTR_PERR_XI (1<<8) 1034 #define PCICFG_STATUS_DEVSEL_TIMING (0x3<<9) 1035 #define PCICFG_STATUS_SIG_TGT_ABT (1<<11) 1036 #define PCICFG_STATUS_RCV_TGT_ABT (1<<12) 1037 #define PCICFG_STATUS_RCV_MSTR_ABT (1<<13) 1038 #define PCICFG_STATUS_SIG_SERR (1<<14) 1039 #define PCICFG_STATUS_PAR_ERR (1<<15) 1040 1041 u32_t pcicfg_class_code; 1042 #define PCICFG_CLASS_CODE_REV_ID (0xffUL<<0) 1043 #define PCICFG_CLASS_CODE_VALUE (0xffffffUL<<8) 1044 1045 u8_t pcicfg_cache_line_size; 1046 u8_t pcicfg_latency_timer; 1047 u8_t pcicfg_header_type; 1048 u8_t pcicfg_bist; 1049 u32_t pcicfg_bar_1; 1050 #define PCICFG_BAR_1_MEM_SPACE (1UL<<0) 1051 #define PCICFG_BAR_1_SPACE_TYPE (0x3UL<<1) 1052 #define PCICFG_BAR_1_PREFETCH (1UL<<3) 1053 #define PCICFG_BAR_1_ADDRESS (0xfffffffUL<<4) 1054 1055 u32_t pcicfg_bar_2; 1056 #define PCICFG_BAR_2_ADDR (0xffffffffUL<<0) 1057 1058 u32_t pcicfg_bar_3; 1059 #define PCICFG_BAR_3_MEM_SPACE (1UL<<0) 1060 #define PCICFG_BAR_3_SPACE_TYPE (0x3UL<<1) 1061 #define PCICFG_BAR_3_PREFETCH (1UL<<3) 1062 #define PCICFG_BAR_3_ADDRESS (0xfffffffUL<<4) 1063 1064 u32_t pcicfg_bar_4; 1065 #define PCICFG_BAR_4_ADDR (0xffffffffUL<<0) 1066 1067 u32_t pcicfg_bar_5; 1068 u32_t pcicfg_bar_6; 1069 u32_t pcicfg_cardbus_cis; 1070 u16_t pcicfg_subsystem_vendor_id; 1071 u16_t pcicfg_subsystem_id; 1072 u32_t pcicfg_exp_rom_bar; 1073 #define PCICFG_EXP_ROM_BAR_BAR_ENA (1UL<<0) 1074 #define PCICFG_EXP_ROM_BAR_LOW_TE (0x1ffUL<<1) 1075 #define PCICFG_EXP_ROM_BAR_SIZE_TE (0x3fffUL<<10) 1076 #define PCICFG_EXP_ROM_BAR_LOW_XI (0x3ffUL<<1) 1077 #define PCICFG_EXP_ROM_BAR_SIZE_XI (0x1fffUL<<11) 1078 #define PCICFG_EXP_ROM_BAR_ADDRESS (0xffUL<<24) 1079 1080 u8_t pcicfg_cap_pointer; 1081 u8_t unused_0; 1082 u16_t unused_1; 1083 u32_t unused_2; 1084 u8_t pcicfg_int_line; 1085 u8_t pcicfg_int_pin; 1086 u8_t pcicfg_min_grant; 1087 u8_t pcicfg_maximum_latency; 1088 u8_t pcicfg_pcix_cap_id; 1089 u8_t pcicfg_pcix_next_cap_ptr; 1090 u16_t pcicfg_pcix_command; 1091 #define PCICFG_PCIX_COMMAND_DATA_PAR_ERR (1<<0) 1092 #define PCICFG_PCIX_COMMAND_RELAX_ORDER (1<<1) 1093 #define PCICFG_PCIX_COMMAND_MAX_MEM_READ (0x3<<2) 1094 #define PCICFG_PCIX_COMMAND_MAX_MEM_READ_512 (0<<2) 1095 #define PCICFG_PCIX_COMMAND_MAX_MEM_READ_1K (1<<2) 1096 #define PCICFG_PCIX_COMMAND_MAX_MEM_READ_2K (2<<2) 1097 #define PCICFG_PCIX_COMMAND_MAX_MEM_READ_4K (3<<2) 1098 #define PCICFG_PCIX_COMMAND_MAX_SPLIT (0x7<<4) 1099 #define PCICFG_PCIX_COMMAND_MAX_SPLIT_MAX_SPLIT_1 (0<<4) 1100 #define PCICFG_PCIX_COMMAND_MAX_SPLIT_MAX_SPLIT_2 (1<<4) 1101 #define PCICFG_PCIX_COMMAND_MAX_SPLIT_MAX_SPLIT_3 (2<<4) 1102 #define PCICFG_PCIX_COMMAND_MAX_SPLIT_MAX_SPLIT_4 (3<<4) 1103 #define PCICFG_PCIX_COMMAND_MAX_SPLIT_MAX_SPLIT_8 (4<<4) 1104 #define PCICFG_PCIX_COMMAND_MAX_SPLIT_MAX_SPLIT_12 (5<<4) 1105 #define PCICFG_PCIX_COMMAND_MAX_SPLIT_MAX_SPLIT_16 (6<<4) 1106 #define PCICFG_PCIX_COMMAND_MAX_SPLIT_MAX_SPLIT_32 (7<<4) 1107 #define PCICFG_PCIX_COMMAND_MAX_SPLIT_RESERVED (511<<4) 1108 1109 u32_t pcicfg_pcix_status; 1110 #define PCICFG_PCIX_STATUS_FUNC_NUM (0x7UL<<0) 1111 #define PCICFG_PCIX_STATUS_DEV_NUM (0x1fUL<<3) 1112 #define PCICFG_PCIX_STATUS_BUS_NUM (0xffUL<<8) 1113 #define PCICFG_PCIX_STATUS_64_BIT (1UL<<16) 1114 #define PCICFG_PCIX_STATUS_MAX_133_ADVERTIZE (1UL<<17) 1115 #define PCICFG_PCIX_STATUS_SPLIT_DISCARD (1UL<<18) 1116 #define PCICFG_PCIX_STATUS_UNEXPECTED_SPLIT (1UL<<19) 1117 #define PCICFG_PCIX_STATUS_DEV_COMPLEX (1UL<<20) 1118 #define PCICFG_PCIX_STATUS_MAX_MEM_READ (0x3UL<<21) 1119 #define PCICFG_PCIX_STATUS_MAX_MEM_READ_512 (0UL<<21) 1120 #define PCICFG_PCIX_STATUS_MAX_MEM_READ_1K (1UL<<21) 1121 #define PCICFG_PCIX_STATUS_MAX_MEM_READ_2K (2UL<<21) 1122 #define PCICFG_PCIX_STATUS_MAX_MEM_READ_4K (3UL<<21) 1123 #define PCICFG_PCIX_STATUS_MAX_SPLIT (0x7UL<<23) 1124 #define PCICFG_PCIX_STATUS_MAX_SPLIT_1 (0UL<<23) 1125 #define PCICFG_PCIX_STATUS_MAX_SPLIT_2 (1UL<<23) 1126 #define PCICFG_PCIX_STATUS_MAX_SPLIT_3 (2UL<<23) 1127 #define PCICFG_PCIX_STATUS_MAX_SPLIT_4 (3UL<<23) 1128 #define PCICFG_PCIX_STATUS_MAX_SPLIT_8 (4UL<<23) 1129 #define PCICFG_PCIX_STATUS_MAX_SPLIT_12 (5UL<<23) 1130 #define PCICFG_PCIX_STATUS_MAX_SPLIT_16 (6UL<<23) 1131 #define PCICFG_PCIX_STATUS_MAX_SPLIT_32 (7UL<<23) 1132 #define PCICFG_PCIX_STATUS_MAX_CUM_SIZE (0x7UL<<26) 1133 #define PCICFG_PCIX_STATUS_MAX_CUM_SIZE_1KB (0UL<<26) 1134 #define PCICFG_PCIX_STATUS_MAX_CUM_SIZE_2KB (1UL<<26) 1135 #define PCICFG_PCIX_STATUS_MAX_CUM_SIZE_4KB (2UL<<26) 1136 #define PCICFG_PCIX_STATUS_MAX_CUM_SIZE_8KB (3UL<<26) 1137 #define PCICFG_PCIX_STATUS_MAX_CUM_SIZE_16KB (4UL<<26) 1138 #define PCICFG_PCIX_STATUS_MAX_CUM_SIZE_32KB (5UL<<26) 1139 #define PCICFG_PCIX_STATUS_MAX_CUM_SIZE_64KB (6UL<<26) 1140 #define PCICFG_PCIX_STATUS_MAX_CUM_SIZE_128KB (7UL<<26) 1141 #define PCICFG_PCIX_STATUS_SPLIT_ERR (1UL<<29) 1142 #define PCICFG_PCIX_STATUS_RESERVED (0x3UL<<30) 1143 1144 u8_t pcicfg_pm_cap_id; 1145 u8_t pcicfg_pm_next_cap_ptr; 1146 u16_t pcicfg_pm_capability; 1147 #define PCICFG_PM_CAPABILITY_VERSION (0x3<<0) 1148 #define PCICFG_PM_CAPABILITY_CLOCK (1<<3) 1149 #define PCICFG_PM_CAPABILITY_RESERVED (1<<4) 1150 #define PCICFG_PM_CAPABILITY_DSI (1<<5) 1151 #define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<6) 1152 #define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<9) 1153 #define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<10) 1154 #define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<11) 1155 #define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<12) 1156 #define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<13) 1157 #define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<14) 1158 #define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<15) 1159 1160 u16_t pcicfg_pm_csr; 1161 #define PCICFG_PM_CSR_STATE (0x3<<0) 1162 #define PCICFG_PM_CSR_STATE_D0 (0<<0) 1163 #define PCICFG_PM_CSR_STATE_D1 (1<<0) 1164 #define PCICFG_PM_CSR_STATE_D2 (2<<0) 1165 #define PCICFG_PM_CSR_STATE_D3_HOT (3<<0) 1166 #define PCICFG_PM_CSR_RESERVED_TE (0x3f<<2) 1167 #define PCICFG_PM_CSR_RESERVED0_XI (1<<2) 1168 #define PCICFG_PM_CSR_NO_SOFT_RESET_XI (1<<3) 1169 #define PCICFG_PM_CSR_RESERVED1_XI (0xf<<4) 1170 #define PCICFG_PM_CSR_PME_ENABLE (1<<8) 1171 #define PCICFG_PM_CSR_DATA_SEL (0xf<<9) 1172 #define PCICFG_PM_CSR_DATA_SEL_0 (0<<9) 1173 #define PCICFG_PM_CSR_DATA_SEL_1 (1<<9) 1174 #define PCICFG_PM_CSR_DATA_SEL_2 (2<<9) 1175 #define PCICFG_PM_CSR_DATA_SEL_3 (3<<9) 1176 #define PCICFG_PM_CSR_DATA_SEL_4 (4<<9) 1177 #define PCICFG_PM_CSR_DATA_SEL_5 (5<<9) 1178 #define PCICFG_PM_CSR_DATA_SEL_6 (6<<9) 1179 #define PCICFG_PM_CSR_DATA_SEL_7 (7<<9) 1180 #define PCICFG_PM_CSR_DATA_SCALE (0x3<<13) 1181 #define PCICFG_PM_CSR_DATA_SCALE_0 (0<<13) 1182 #define PCICFG_PM_CSR_DATA_SCALE_1 (1<<13) 1183 #define PCICFG_PM_CSR_DATA_SCALE_2 (2<<13) 1184 #define PCICFG_PM_CSR_DATA_SCALE_3 (3<<13) 1185 #define PCICFG_PM_CSR_PME_STATUS (1<<15) 1186 1187 u8_t pcicfg_pm_csr_bse; 1188 u8_t pcicfg_pm_data; 1189 u8_t pcicfg_vpd_cap_id; 1190 u8_t pcicfg_vpd_next_cap_ptr; 1191 u16_t pcicfg_vpd_flag_addr; 1192 #define PCICFG_VPD_FLAG_ADDR_ADDRESS (0x1fff<<2) 1193 #define PCICFG_VPD_FLAG_ADDR_FLAG (1<<15) 1194 1195 u32_t pcicfg_vpd_data; 1196 u8_t pcicfg_msi_cap_id; 1197 u8_t pcicfg_msi_next_cap_ptr; 1198 u16_t pcicfg_msi_control; 1199 #define PCICFG_MSI_CONTROL_ENABLE (1<<0) 1200 #define PCICFG_MSI_CONTROL_MCAP (0x7<<1) 1201 #define PCICFG_MSI_CONTROL_MCAP_1 (0<<1) 1202 #define PCICFG_MSI_CONTROL_MCAP_2 (1<<1) 1203 #define PCICFG_MSI_CONTROL_MCAP_4 (2<<1) 1204 #define PCICFG_MSI_CONTROL_MCAP_8 (3<<1) 1205 #define PCICFG_MSI_CONTROL_MCAP_16 (4<<1) 1206 #define PCICFG_MSI_CONTROL_MCAP_32 (5<<1) 1207 #define PCICFG_MSI_CONTROL_MENA (0x7<<4) 1208 #define PCICFG_MSI_CONTROL_MENA_1 (0<<4) 1209 #define PCICFG_MSI_CONTROL_MENA_2 (1<<4) 1210 #define PCICFG_MSI_CONTROL_MENA_4 (2<<4) 1211 #define PCICFG_MSI_CONTROL_MENA_8 (3<<4) 1212 #define PCICFG_MSI_CONTROL_MENA_16 (4<<4) 1213 #define PCICFG_MSI_CONTROL_MENA_32 (5<<4) 1214 #define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (1<<7) 1215 #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (1<<8) 1216 1217 u32_t pcicfg_msi_addr_l; 1218 #define PCICFG_MSI_ADDR_L_VAL (0x3fffffffUL<<2) 1219 1220 u32_t pcicfg_msi_addr_h; 1221 u16_t pcicfg_msi_data; 1222 u16_t pcicfg_reserved; 1223 u32_t pcicfg_misc_config; 1224 #define PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1UL<<2) 1225 #define PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1UL<<3) 1226 #define PCICFG_MISC_CONFIG_RESERVED1 (1UL<<4) 1227 #define PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1UL<<5) 1228 #define PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1UL<<6) 1229 #define PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1UL<<7) 1230 #define PCICFG_MISC_CONFIG_CORE_RST_REQ (1UL<<8) 1231 #define PCICFG_MISC_CONFIG_CORE_RST_BSY (1UL<<9) 1232 #define PCICFG_MISC_CONFIG_GRC_WIN1_SWAP_EN (1UL<<10) 1233 #define PCICFG_MISC_CONFIG_GRC_WIN2_SWAP_EN (1UL<<11) 1234 #define PCICFG_MISC_CONFIG_GRC_WIN3_SWAP_EN (1UL<<12) 1235 #define PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffUL<<16) 1236 #define PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfUL<<24) 1237 #define PCICFG_MISC_CONFIG_ASIC_ID (0xfUL<<28) 1238 1239 u32_t pcicfg_misc_status; 1240 #define PCICFG_MISC_STATUS_INTA_VALUE (1UL<<0) 1241 #define PCICFG_MISC_STATUS_32BIT_DET (1UL<<1) 1242 #define PCICFG_MISC_STATUS_M66EN (1UL<<2) 1243 #define PCICFG_MISC_STATUS_PCIX_DET (1UL<<3) 1244 #define PCICFG_MISC_STATUS_PCIX_SPEED (0x3UL<<4) 1245 #define PCICFG_MISC_STATUS_PCIX_SPEED_66 (0UL<<4) 1246 #define PCICFG_MISC_STATUS_PCIX_SPEED_100 (1UL<<4) 1247 #define PCICFG_MISC_STATUS_PCIX_SPEED_133 (2UL<<4) 1248 #define PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3UL<<4) 1249 #define PCICFG_MISC_STATUS_BAD_MEM_WRITE_BE (1UL<<8) 1250 1251 u32_t pcicfg_pci_clock_control_bits; 1252 #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfUL<<0) 1253 #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0UL<<0) 1254 #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1UL<<0) 1255 #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2UL<<0) 1256 #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3UL<<0) 1257 #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4UL<<0) 1258 #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5UL<<0) 1259 #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6UL<<0) 1260 #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7UL<<0) 1261 #define PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (15UL<<0) 1262 #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1UL<<6) 1263 #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1UL<<7) 1264 #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7UL<<8) 1265 #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0UL<<8) 1266 #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1UL<<8) 1267 #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2UL<<8) 1268 #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4UL<<8) 1269 #define PCICFG_PCI_CLOCK_CONTROL_BITS_MIN_POWER (1UL<<11) 1270 #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfUL<<12) 1271 #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0UL<<12) 1272 #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1UL<<12) 1273 #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2UL<<12) 1274 #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4UL<<12) 1275 #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8UL<<12) 1276 #define PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1UL<<16) 1277 #define PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_17 (1UL<<17) 1278 #define PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1UL<<18) 1279 #define PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_19 (1UL<<19) 1280 #define PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffUL<<20) 1281 1282 u32_t unused_3; 1283 u32_t pcicfg_reg_window_address; 1284 #define PCICFG_REG_WINDOW_ADDRESS_VAL (0xfffffUL<<2) 1285 1286 u32_t unused_4; 1287 u32_t pcicfg_reg_window; 1288 u32_t pcicfg_int_ack_cmd; 1289 #define PCICFG_INT_ACK_CMD_INDEX (0xffffUL<<0) 1290 #define PCICFG_INT_ACK_CMD_INDEX_VALID (1UL<<16) 1291 #define PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1UL<<17) 1292 #define PCICFG_INT_ACK_CMD_MASK_INT (1UL<<18) 1293 #define PCICFG_INT_ACK_CMD_INTERRUPT_NUM (0xfUL<<24) 1294 1295 u32_t pcicfg_status_bit_set_cmd; 1296 u32_t pcicfg_status_bit_clear_cmd; 1297 u32_t pcicfg_mailbox_queue_addr; 1298 u32_t pcicfg_mailbox_queue_data; 1299 u32_t unused_5[2]; 1300 u8_t pcicfg_msix_cap_id; 1301 u8_t pcicfg_msix_next_cap_ptr; 1302 u16_t pcicfg_msix_control; 1303 #define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<0) 1304 #define PCICFG_MSIX_CONTROL_RESERVED (0x7<<11) 1305 #define PCICFG_MSIX_CONTROL_FUNC_MASK (1<<14) 1306 #define PCICFG_MSIX_CONTROL_MSIX_ENABLE (1<<15) 1307 1308 u32_t pcicfg_msix_tbl_off_bir; 1309 #define PCICFG_MSIX_TBL_OFF_BIR_TABLE_BIR (0x7UL<<0) 1310 #define PCICFG_MSIX_TBL_OFF_BIR_TABLE_OFFSET (0x1fffffffUL<<3) 1311 1312 u32_t pcicfg_msix_pba_off_bir; 1313 #define PCICFG_MSIX_PBA_OFF_BIR_PBA_BIR (0x7UL<<0) 1314 #define PCICFG_MSIX_PBA_OFF_BIR_PBA_OFFSET (0x1fffffffUL<<3) 1315 1316 u8_t pcicfg_pcie_cap_id; 1317 u8_t pcicfg_pcie_next_cap_ptr; 1318 u16_t pcicfg_pcie_capability; 1319 #define PCICFG_PCIE_CAPABILITY_VER (0xf<<0) 1320 #define PCICFG_PCIE_CAPABILITY_TYPE (0xf<<4) 1321 1322 u32_t pcicfg_device_capability; 1323 #define PCICFG_DEVICE_CAPABILITY_MAX_PAYLOAD (0x7UL<<0) 1324 #define PCICFG_DEVICE_CAPABILITY_PHANTOM_SUPPT (0x3UL<<3) 1325 #define PCICFG_DEVICE_CAPABILITY_EXT_TAG_SUPPT (1UL<<5) 1326 #define PCICFG_DEVICE_CAPABILITY_EP_L0S_ACCP_LAT (0x7UL<<6) 1327 #define PCICFG_DEVICE_CAPABILITY_EP_L1_ACCP_LAT (0x7UL<<9) 1328 1329 u16_t pcicfg_device_control; 1330 #define PCICFG_DEVICE_CONTROL_CORR_ERR_REP_ENA (1<<0) 1331 #define PCICFG_DEVICE_CONTROL_NON_FATAL_REP_ENA (1<<1) 1332 #define PCICFG_DEVICE_CONTROL_FATAL_REP_ENA (1<<2) 1333 #define PCICFG_DEVICE_CONTROL_UNSUP_REQ_ENA (1<<3) 1334 #define PCICFG_DEVICE_CONTROL_RELAX_ENA (1<<4) 1335 #define PCICFG_DEVICE_CONTROL_MAX_PAYLOAD (0x7<<5) 1336 #define PCICFG_DEVICE_CONTROL_EXT_TAG_ENA (1<<8) 1337 #define PCICFG_DEVICE_CONTROL_AUX_PWR_PM_ENA (1<<10) 1338 #define PCICFG_DEVICE_CONTROL_ENA_NO_SNOOP (1<<11) 1339 #define PCICFG_DEVICE_CONTROL_MAX_RD_REQ (0x7<<12) 1340 1341 u16_t pcicfg_device_status; 1342 #define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0) 1343 #define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1) 1344 #define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2) 1345 #define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3) 1346 #define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4) 1347 #define PCICFG_DEVICE_STATUS_NO_PEND (1<<5) 1348 1349 u32_t pcicfg_link_capability; 1350 #define PCICFG_LINK_CAPABILITY_MAX_LINK_SPEED (0xfUL<<0) 1351 #define PCICFG_LINK_CAPABILITY_MAX_LINK_SPEED_2_5 (1UL<<0) 1352 #define PCICFG_LINK_CAPABILITY_MAX_LINK_SPEED_5 (2UL<<0) 1353 #define PCICFG_LINK_CAPABILITY_MAX_LINK_WIDTH (0x3fUL<<4) 1354 #define PCICFG_LINK_CAPABILITY_MAX_LINK_WIDTH_1 (1UL<<4) 1355 #define PCICFG_LINK_CAPABILITY_MAX_LINK_WIDTH_2 (2UL<<4) 1356 #define PCICFG_LINK_CAPABILITY_MAX_LINK_WIDTH_4 (4UL<<4) 1357 #define PCICFG_LINK_CAPABILITY_MAX_LINK_WIDTH_8 (8UL<<4) 1358 #define PCICFG_LINK_CAPABILITY_ASPM_SUPT (0x3UL<<10) 1359 #define PCICFG_LINK_CAPABILITY_ASPM_SUPT_RES_0 (0UL<<10) 1360 #define PCICFG_LINK_CAPABILITY_ASPM_SUPT_L0S (0UL<<10) 1361 #define PCICFG_LINK_CAPABILITY_ASPM_SUPT_RES_2 (0UL<<10) 1362 #define PCICFG_LINK_CAPABILITY_ASPM_SUPT_L0S_L1 (0UL<<10) 1363 #define PCICFG_LINK_CAPABILITY_L0S_EXIT_LAT (0x7UL<<12) 1364 #define PCICFG_LINK_CAPABILITY_L0S_EXIT_LAT_1_2 (5UL<<12) 1365 #define PCICFG_LINK_CAPABILITY_L0S_EXIT_LAT_2_4 (6UL<<12) 1366 #define PCICFG_LINK_CAPABILITY_L1_EXIT_LAT (0x7UL<<15) 1367 #define PCICFG_LINK_CAPABILITY_L1_EXIT_LAT_1_2 (1UL<<15) 1368 #define PCICFG_LINK_CAPABILITY_L1_EXIT_LAT_2_4 (2UL<<15) 1369 #define PCICFG_LINK_CAPABILITY_CLK_PWR_MGMT (1UL<<18) 1370 #define PCICFG_LINK_CAPABILITY_PORT_NUMBER (0xffUL<<24) 1371 1372 u16_t pcicfg_link_control; 1373 #define PCICFG_LINK_CONTROL_ASPM_CTRL (0x3<<0) 1374 #define PCICFG_LINK_CONTROL_RD_COMP_BOUND (1<<3) 1375 #define PCICFG_LINK_CONTROL_RD_COMP_BOUND_64 (0<<3) 1376 #define PCICFG_LINK_CONTROL_RD_COMP_BOUND_128 (1<<3) 1377 #define PCICFG_LINK_CONTROL_LINK_CR_COMMON_CLK (1<<6) 1378 #define PCICFG_LINK_CONTROL_LINK_CR_EXT_SYNC (1<<7) 1379 1380 u16_t pcicfg_link_status; 1381 #define PCICFG_LINK_STATUS_SPEED (0xf<<0) 1382 #define PCICFG_LINK_STATUS_NEG_LINK_WIDTH (0x3f<<4) 1383 #define PCICFG_LINK_STATUS_TRAINING_ERR (1<<10) 1384 #define PCICFG_LINK_STATUS_TRAINING (1<<11) 1385 #define PCICFG_LINK_STATUS_SLOT_CLK (1<<12) 1386 1387 u32_t pcicfg_slot_capability; 1388 u16_t pcicfg_slot_control; 1389 u16_t pcicfg_slot_status; 1390 u16_t pcicfg_root_control; 1391 u16_t pcicfg_root_cap; 1392 u32_t pcicfg_root_status; 1393 u32_t pcicfg_device_capability_2; 1394 #define PCICFG_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP (0xfUL<<0) 1395 #define PCICFG_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP_ABCD (15UL<<0) 1396 #define PCICFG_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP (1UL<<4) 1397 1398 u16_t pcicfg_device_control_2; 1399 #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE (0xf<<0) 1400 #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_50MS (0<<0) 1401 #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_100US (1<<0) 1402 #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_10MS (2<<0) 1403 #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_55MS (3<<0) 1404 #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_210MS (4<<0) 1405 #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_900MS (5<<0) 1406 #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_3_5S (6<<0) 1407 #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_13S (7<<0) 1408 #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_64S (8<<0) 1409 #define PCICFG_DEVICE_CONTROL_2_CMPL_TO_DISABLE (1<<4) 1410 1411 u16_t pcicfg_device_status_2; 1412 u32_t pcicfg_link_capability_2; 1413 u16_t pcicfg_link_control_2; 1414 #define PCICFG_LINK_CONTROL_2_TARGET_LINK_SPEED (0xf<<0) 1415 #define PCICFG_LINK_CONTROL_2_TARGET_LINK_SPEED_2_5 (0<<0) 1416 #define PCICFG_LINK_CONTROL_2_TARGET_LINK_SPEED_5_0 (1<<0) 1417 #define PCICFG_LINK_CONTROL_2_ENTER_COMPLIANCE (1<<4) 1418 #define PCICFG_LINK_CONTROL_2_HW_AUTO_SPEED_DISABLE (1<<5) 1419 #define PCICFG_LINK_CONTROL_2_SEL_DEEMPHASIS (1<<6) 1420 #define PCICFG_LINK_CONTROL_2_SEL_DEEMPHASIS_0 (0<<6) 1421 #define PCICFG_LINK_CONTROL_2_SEL_DEEMPHASIS_1 (1<<6) 1422 #define PCICFG_LINK_CONTROL_2_TX_MARGIN (0x7<<7) 1423 #define PCICFG_LINK_CONTROL_2_TX_MARGIN_000 (0<<7) 1424 #define PCICFG_LINK_CONTROL_2_TX_MARGIN_001 (1<<7) 1425 #define PCICFG_LINK_CONTROL_2_TX_MARGIN_010 (2<<7) 1426 #define PCICFG_LINK_CONTROL_2_TX_MARGIN_011 (3<<7) 1427 #define PCICFG_LINK_CONTROL_2_TX_MARGIN_100 (4<<7) 1428 #define PCICFG_LINK_CONTROL_2_TX_MARGIN_101 (5<<7) 1429 #define PCICFG_LINK_CONTROL_2_TX_MARGIN_110 (6<<7) 1430 #define PCICFG_LINK_CONTROL_2_TX_MARGIN_111 (7<<7) 1431 1432 u16_t pcicfg_link_status_2; 1433 u32_t unused_6[8]; 1434 u16_t pcicfg_device_ser_num_cap_id; 1435 u16_t pcicfg_device_ser_num_cap_off; 1436 #define PCICFG_DEVICE_SER_NUM_CAP_OFF_VER (0xf<<0) 1437 #define PCICFG_DEVICE_SER_NUM_CAP_OFF_NEXT (0xfff<<4) 1438 1439 u32_t pcicfg_lower_ser_num; 1440 u32_t pcicfg_upper_ser_num; 1441 u32_t unused_7; 1442 u16_t pcicfg_adv_err_cap_id; 1443 u16_t pcicfg_adv_err_cap_off; 1444 #define PCICFG_ADV_ERR_CAP_OFF_VER (0xf<<0) 1445 #define PCICFG_ADV_ERR_CAP_OFF_NEXT (0xfff<<4) 1446 1447 u32_t pcicfg_ucorr_err_status; 1448 #define PCICFG_UCORR_ERR_STATUS_DLPES (1UL<<4) 1449 #define PCICFG_UCORR_ERR_STATUS_PTLPS (1UL<<12) 1450 #define PCICFG_UCORR_ERR_STATUS_FCPES (1UL<<13) 1451 #define PCICFG_UCORR_ERR_STATUS_CTS (1UL<<14) 1452 #define PCICFG_UCORR_ERR_STATUS_CAS (1UL<<15) 1453 #define PCICFG_UCORR_ERR_STATUS_UCS (1UL<<16) 1454 #define PCICFG_UCORR_ERR_STATUS_ROS (1UL<<17) 1455 #define PCICFG_UCORR_ERR_STATUS_MTLPS (1UL<<18) 1456 #define PCICFG_UCORR_ERR_STATUS_ECRCS (1UL<<19) 1457 #define PCICFG_UCORR_ERR_STATUS_URES (1UL<<20) 1458 1459 u32_t pcicfg_ucorr_err_mask; 1460 #define PCICFG_UCORR_ERR_MASK_DLPEM (1UL<<4) 1461 #define PCICFG_UCORR_ERR_MASK_SDEM (1UL<<5) 1462 #define PCICFG_UCORR_ERR_MASK_PTLPM (1UL<<12) 1463 #define PCICFG_UCORR_ERR_MASK_FCPEM (1UL<<13) 1464 #define PCICFG_UCORR_ERR_MASK_CTM (1UL<<14) 1465 #define PCICFG_UCORR_ERR_MASK_CAM (1UL<<15) 1466 #define PCICFG_UCORR_ERR_MASK_UCM (1UL<<16) 1467 #define PCICFG_UCORR_ERR_MASK_ROM (1UL<<17) 1468 #define PCICFG_UCORR_ERR_MASK_MTLPM (1UL<<18) 1469 #define PCICFG_UCORR_ERR_MASK_ECRCEM (1UL<<19) 1470 #define PCICFG_UCORR_ERR_MASK_UREM (1UL<<20) 1471 1472 u32_t pcicfg_ucorr_err_sevr; 1473 #define PCICFG_UCORR_ERR_SEVR_DLPES (1UL<<4) 1474 #define PCICFG_UCORR_ERR_SEVR_SDES (1UL<<5) 1475 #define PCICFG_UCORR_ERR_SEVR_PTLPS (1UL<<12) 1476 #define PCICFG_UCORR_ERR_SEVR_FCPES (1UL<<13) 1477 #define PCICFG_UCORR_ERR_SEVR_CTS (1UL<<14) 1478 #define PCICFG_UCORR_ERR_SEVR_CAS (1UL<<15) 1479 #define PCICFG_UCORR_ERR_SEVR_UCS (1UL<<16) 1480 #define PCICFG_UCORR_ERR_SEVR_ROS (1UL<<17) 1481 #define PCICFG_UCORR_ERR_SEVR_MTLPS (1UL<<18) 1482 #define PCICFG_UCORR_ERR_SEVR_ECRCES (1UL<<19) 1483 #define PCICFG_UCORR_ERR_SEVR_URES (1UL<<20) 1484 1485 u32_t pcicfg_corr_err_status; 1486 #define PCICFG_CORR_ERR_STATUS_RES (1UL<<0) 1487 #define PCICFG_CORR_ERR_STATUS_BDLLPS (1UL<<7) 1488 #define PCICFG_CORR_ERR_STATUS_BTLPS (1UL<<7) 1489 #define PCICFG_CORR_ERR_STATUS_RNRS (1UL<<8) 1490 #define PCICFG_CORR_ERR_STATUS_RTTS (1UL<<12) 1491 #define PCICFG_CORR_ERR_STATUS_ANFS (1UL<<13) 1492 1493 u32_t pcicfg_corr_err_mask; 1494 #define PCICFG_CORR_ERR_MASK_RES (1UL<<0) 1495 #define PCICFG_CORR_ERR_MASK_BTLPS (1UL<<6) 1496 #define PCICFG_CORR_ERR_MASK_BDLLPS (1UL<<7) 1497 #define PCICFG_CORR_ERR_MASK_RNRS (1UL<<8) 1498 #define PCICFG_CORR_ERR_MASK_RTTS (1UL<<12) 1499 #define PCICFG_CORR_ERR_MASK_ANFM (1UL<<13) 1500 1501 u32_t pcicfg_adv_err_cap_control; 1502 #define PCICFG_ADV_ERR_CAP_CONTROL_FIRST_UERR_PTR (0x1fUL<<0) 1503 #define PCICFG_ADV_ERR_CAP_CONTROL_ECRCGCAP (1UL<<5) 1504 #define PCICFG_ADV_ERR_CAP_CONTROL_ECRCGEN (1UL<<6) 1505 #define PCICFG_ADV_ERR_CAP_CONTROL_ECRCCAP (1UL<<7) 1506 #define PCICFG_ADV_ERR_CAP_CONTROL_ECRCEN (1UL<<8) 1507 1508 u32_t pcicfg_header_log1; 1509 u32_t pcicfg_header_log2; 1510 u32_t pcicfg_header_log3; 1511 u32_t pcicfg_header_log4; 1512 u32_t unused_8[5]; 1513 u16_t pcicfg_pwr_bdgt_cap_id; 1514 u16_t pcicfg_pwr_bdgt_cap_off; 1515 #define PCICFG_PWR_BDGT_CAP_OFF_VER (0xf<<0) 1516 #define PCICFG_PWR_BDGT_CAP_OFF_NEXT (0xfff<<4) 1517 1518 u32_t pcicfg_pwr_bdgt_data_sel; 1519 #define PCICFG_PWR_BDGT_DATA_SEL_DS_VALUE (0xffUL<<0) 1520 #define PCICFG_PWR_BDGT_DATA_SEL_DS_VALUE_0 (0UL<<0) 1521 #define PCICFG_PWR_BDGT_DATA_SEL_DS_VALUE_1 (1UL<<0) 1522 #define PCICFG_PWR_BDGT_DATA_SEL_DS_VALUE_2 (2UL<<0) 1523 #define PCICFG_PWR_BDGT_DATA_SEL_DS_VALUE_3 (3UL<<0) 1524 #define PCICFG_PWR_BDGT_DATA_SEL_DS_VALUE_4 (4UL<<0) 1525 #define PCICFG_PWR_BDGT_DATA_SEL_DS_VALUE_5 (5UL<<0) 1526 #define PCICFG_PWR_BDGT_DATA_SEL_DS_VALUE_6 (6UL<<0) 1527 #define PCICFG_PWR_BDGT_DATA_SEL_DS_VALUE_7 (7UL<<0) 1528 1529 u32_t pcicfg_pwr_bdgt_data; 1530 #define PCICFG_PWR_BDGT_DATA_BASE_PWR (0xffUL<<0) 1531 #define PCICFG_PWR_BDGT_DATA_DSCALE (0x3UL<<8) 1532 #define PCICFG_PWR_BDGT_DATA_PM_STATE (0x3UL<<13) 1533 #define PCICFG_PWR_BDGT_DATA_TYPE (0x7UL<<15) 1534 #define PCICFG_PWR_BDGT_DATA_RAIL (0x7UL<<18) 1535 1536 u32_t pcicfg_pwr_bdgt_capability; 1537 #define PCICFG_PWR_BDGT_CAPABILITY_PCIE_CFG_PB_CAP_SYS_ALLOC (1UL<<0) 1538 1539 u16_t pcicfg_vc_cap_id; 1540 u16_t pcicfg_vc_cap_off; 1541 #define PCICFG_VC_CAP_OFF_VER (0xf<<0) 1542 #define PCICFG_VC_CAP_OFF_NEXT (0xfff<<4) 1543 1544 u32_t pcicfg_port_vc_capability; 1545 u32_t pcicfg_port_vc_capability2; 1546 u16_t pcicfg_port_vc_control; 1547 u16_t pcicfg_port_vc_status; 1548 u32_t pcicfg_port_arb_table; 1549 u32_t pcicfg_vc_rsrc_control; 1550 #define PCICFG_VC_RSRC_CONTROL_TC_VC_MAP (0xffUL<<0) 1551 #define PCICFG_VC_RSRC_CONTROL_VC_ENABLE (1UL<<31) 1552 1553 u16_t pcicfg_rsvdp; 1554 u16_t pcicfg_vc_rsrc_status; 1555 u32_t unused_9[161]; 1556 } pci_config_t; 1557 1558 1559 /* 1560 * pci_reg definition 1561 * offset: 0x400 1562 */ 1563 typedef struct pci_reg 1564 { 1565 u32_t pci_grc_window_addr; 1566 #define PCI_GRC_WINDOW_ADDR_VALUE (0x1ffUL<<13) 1567 #define PCI_GRC_WINDOW_ADDR_SEP_WIN (1UL<<31) 1568 1569 u32_t pci_config_1; 1570 #define PCI_CONFIG_1_RESERVED0 (0xffUL<<0) 1571 #define PCI_CONFIG_1_READ_BOUNDARY (0x7UL<<8) 1572 #define PCI_CONFIG_1_READ_BOUNDARY_OFF (0UL<<8) 1573 #define PCI_CONFIG_1_READ_BOUNDARY_16 (1UL<<8) 1574 #define PCI_CONFIG_1_READ_BOUNDARY_32 (2UL<<8) 1575 #define PCI_CONFIG_1_READ_BOUNDARY_64 (3UL<<8) 1576 #define PCI_CONFIG_1_READ_BOUNDARY_128 (4UL<<8) 1577 #define PCI_CONFIG_1_READ_BOUNDARY_256 (5UL<<8) 1578 #define PCI_CONFIG_1_READ_BOUNDARY_512 (6UL<<8) 1579 #define PCI_CONFIG_1_READ_BOUNDARY_1024 (7UL<<8) 1580 #define PCI_CONFIG_1_WRITE_BOUNDARY (0x7UL<<11) 1581 #define PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0UL<<11) 1582 #define PCI_CONFIG_1_WRITE_BOUNDARY_16 (1UL<<11) 1583 #define PCI_CONFIG_1_WRITE_BOUNDARY_32 (2UL<<11) 1584 #define PCI_CONFIG_1_WRITE_BOUNDARY_64 (3UL<<11) 1585 #define PCI_CONFIG_1_WRITE_BOUNDARY_128 (4UL<<11) 1586 #define PCI_CONFIG_1_WRITE_BOUNDARY_256 (5UL<<11) 1587 #define PCI_CONFIG_1_WRITE_BOUNDARY_512 (6UL<<11) 1588 #define PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7UL<<11) 1589 #define PCI_CONFIG_1_RESERVED1 (0x3ffffUL<<14) 1590 1591 u32_t pci_config_2; 1592 #define PCI_CONFIG_2_BAR1_SIZE (0xfUL<<0) 1593 #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0UL<<0) 1594 #define PCI_CONFIG_2_BAR1_SIZE_64K (1UL<<0) 1595 #define PCI_CONFIG_2_BAR1_SIZE_128K (2UL<<0) 1596 #define PCI_CONFIG_2_BAR1_SIZE_256K (3UL<<0) 1597 #define PCI_CONFIG_2_BAR1_SIZE_512K (4UL<<0) 1598 #define PCI_CONFIG_2_BAR1_SIZE_1M (5UL<<0) 1599 #define PCI_CONFIG_2_BAR1_SIZE_2M (6UL<<0) 1600 #define PCI_CONFIG_2_BAR1_SIZE_4M (7UL<<0) 1601 #define PCI_CONFIG_2_BAR1_SIZE_8M (8UL<<0) 1602 #define PCI_CONFIG_2_BAR1_SIZE_16M (9UL<<0) 1603 #define PCI_CONFIG_2_BAR1_SIZE_32M (10UL<<0) 1604 #define PCI_CONFIG_2_BAR1_SIZE_64M (11UL<<0) 1605 #define PCI_CONFIG_2_BAR1_SIZE_128M (12UL<<0) 1606 #define PCI_CONFIG_2_BAR1_SIZE_256M (13UL<<0) 1607 #define PCI_CONFIG_2_BAR1_SIZE_512M (14UL<<0) 1608 #define PCI_CONFIG_2_BAR1_SIZE_1G (15UL<<0) 1609 #define PCI_CONFIG_2_BAR1_64ENA (1UL<<4) 1610 #define PCI_CONFIG_2_EXP_ROM_RETRY (1UL<<5) 1611 #define PCI_CONFIG_2_CFG_CYCLE_RETRY (1UL<<6) 1612 #define PCI_CONFIG_2_FIRST_CFG_DONE (1UL<<7) 1613 #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffUL<<8) 1614 #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0UL<<8) 1615 #define PCI_CONFIG_2_EXP_ROM_SIZE_1K_TE (1UL<<8) 1616 #define PCI_CONFIG_2_EXP_ROM_SIZE_2K_TE (2UL<<8) 1617 #define PCI_CONFIG_2_EXP_ROM_SIZE_4K_TE (3UL<<8) 1618 #define PCI_CONFIG_2_EXP_ROM_SIZE_8K_TE (4UL<<8) 1619 #define PCI_CONFIG_2_EXP_ROM_SIZE_16K_TE (5UL<<8) 1620 #define PCI_CONFIG_2_EXP_ROM_SIZE_32K_TE (6UL<<8) 1621 #define PCI_CONFIG_2_EXP_ROM_SIZE_64K_TE (7UL<<8) 1622 #define PCI_CONFIG_2_EXP_ROM_SIZE_128K_TE (8UL<<8) 1623 #define PCI_CONFIG_2_EXP_ROM_SIZE_256K_TE (9UL<<8) 1624 #define PCI_CONFIG_2_EXP_ROM_SIZE_512K_TE (10UL<<8) 1625 #define PCI_CONFIG_2_EXP_ROM_SIZE_1M_TE (11UL<<8) 1626 #define PCI_CONFIG_2_EXP_ROM_SIZE_2M_TE (12UL<<8) 1627 #define PCI_CONFIG_2_EXP_ROM_SIZE_4M_TE (13UL<<8) 1628 #define PCI_CONFIG_2_EXP_ROM_SIZE_8M_TE (14UL<<8) 1629 #define PCI_CONFIG_2_EXP_ROM_SIZE_16M_TE (15UL<<8) 1630 #define PCI_CONFIG_2_EXP_ROM_SIZE_2K_XI (1UL<<8) 1631 #define PCI_CONFIG_2_EXP_ROM_SIZE_4K_XI (2UL<<8) 1632 #define PCI_CONFIG_2_EXP_ROM_SIZE_8K_XI (3UL<<8) 1633 #define PCI_CONFIG_2_EXP_ROM_SIZE_16K_XI (4UL<<8) 1634 #define PCI_CONFIG_2_EXP_ROM_SIZE_32K_XI (5UL<<8) 1635 #define PCI_CONFIG_2_EXP_ROM_SIZE_64K_XI (6UL<<8) 1636 #define PCI_CONFIG_2_EXP_ROM_SIZE_128K_XI (7UL<<8) 1637 #define PCI_CONFIG_2_EXP_ROM_SIZE_256K_XI (8UL<<8) 1638 #define PCI_CONFIG_2_EXP_ROM_SIZE_512K_XI (9UL<<8) 1639 #define PCI_CONFIG_2_EXP_ROM_SIZE_1M_XI (10UL<<8) 1640 #define PCI_CONFIG_2_EXP_ROM_SIZE_2M_XI (11UL<<8) 1641 #define PCI_CONFIG_2_EXP_ROM_SIZE_4M_XI (12UL<<8) 1642 #define PCI_CONFIG_2_EXP_ROM_SIZE_8M_XI (13UL<<8) 1643 #define PCI_CONFIG_2_EXP_ROM_SIZE_16M_XI (14UL<<8) 1644 #define PCI_CONFIG_2_EXP_ROM_SIZE_32M_XI (15UL<<8) 1645 #define PCI_CONFIG_2_MAX_SPLIT_LIMIT_TE (0x1fUL<<16) 1646 #define PCI_CONFIG_2_MAX_READ_LIMIT_TE (0x3UL<<21) 1647 #define PCI_CONFIG_2_MAX_READ_LIMIT_512_TE (0UL<<21) 1648 #define PCI_CONFIG_2_MAX_READ_LIMIT_1K_TE (1UL<<21) 1649 #define PCI_CONFIG_2_MAX_READ_LIMIT_2K_TE (2UL<<21) 1650 #define PCI_CONFIG_2_MAX_READ_LIMIT_4K_TE (3UL<<21) 1651 #define PCI_CONFIG_2_FORCE_32_BIT_MSTR_TE (1UL<<23) 1652 #define PCI_CONFIG_2_FORCE_32_BIT_TGT_TE (1UL<<24) 1653 #define PCI_CONFIG_2_KEEP_REQ_ASSERT_TE (1UL<<25) 1654 #define PCI_CONFIG_2_RESERVED0_TE (0x3fUL<<26) 1655 #define PCI_CONFIG_2_BAR_PREFETCH_XI (1UL<<16) 1656 #define PCI_CONFIG_2_RESERVED0_XI (0x7fffUL<<17) 1657 1658 u32_t pci_config_3; 1659 #define PCI_CONFIG_3_STICKY_BYTE (0xffUL<<0) 1660 #define PCI_CONFIG_3_REG_STICKY_BYTE (0xffUL<<8) 1661 #define PCI_CONFIG_3_FORCE_PME (1UL<<24) 1662 #define PCI_CONFIG_3_PME_STATUS (1UL<<25) 1663 #define PCI_CONFIG_3_PME_ENABLE (1UL<<26) 1664 #define PCI_CONFIG_3_PM_STATE (0x3UL<<27) 1665 #define PCI_CONFIG_3_VAUX_PRESET (1UL<<30) 1666 #define PCI_CONFIG_3_PCI_POWER (1UL<<31) 1667 1668 u32_t pci_pm_data_a; 1669 #define PCI_PM_DATA_A_PM_DATA_0_PRG (0xffUL<<0) 1670 #define PCI_PM_DATA_A_PM_DATA_1_PRG (0xffUL<<8) 1671 #define PCI_PM_DATA_A_PM_DATA_2_PRG (0xffUL<<16) 1672 #define PCI_PM_DATA_A_PM_DATA_3_PRG (0xffUL<<24) 1673 1674 u32_t pci_pm_data_b; 1675 #define PCI_PM_DATA_B_PM_DATA_4_PRG (0xffUL<<0) 1676 #define PCI_PM_DATA_B_PM_DATA_5_PRG (0xffUL<<8) 1677 #define PCI_PM_DATA_B_PM_DATA_6_PRG (0xffUL<<16) 1678 #define PCI_PM_DATA_B_PM_DATA_7_PRG (0xffUL<<24) 1679 1680 u32_t pci_swap_diag0; 1681 u32_t pci_swap_diag1; 1682 u32_t pci_exp_rom_addr; 1683 #define PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffUL<<2) 1684 #define PCI_EXP_ROM_ADDR_REQ (1UL<<31) 1685 1686 u32_t pci_exp_rom_data; 1687 u32_t pci_vpd_intf; 1688 #define PCI_VPD_INTF_INTF_REQ (1UL<<0) 1689 1690 u16_t unused_0; 1691 u16_t pci_vpd_addr_flag; 1692 #define PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2) 1693 #define PCI_VPD_ADDR_FLAG_WR (1<<15) 1694 1695 u32_t pci_vpd_data; 1696 u32_t pci_id_val1; 1697 #define PCI_ID_VAL1_DEVICE_ID (0xffffUL<<0) 1698 #define PCI_ID_VAL1_VENDOR_ID (0xffffUL<<16) 1699 1700 u32_t pci_id_val2; 1701 #define PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffUL<<0) 1702 #define PCI_ID_VAL2_SUBSYSTEM_ID (0xffffUL<<16) 1703 1704 u32_t pci_id_val3; 1705 #define PCI_ID_VAL3_CLASS_CODE (0xffffffUL<<0) 1706 #define PCI_ID_VAL3_REVISION_ID (0xffUL<<24) 1707 1708 u32_t pci_id_val4; 1709 #define PCI_ID_VAL4_CAP_ENA (0xfUL<<0) 1710 #define PCI_ID_VAL4_CAP_ENA_0 (0UL<<0) 1711 #define PCI_ID_VAL4_CAP_ENA_1 (1UL<<0) 1712 #define PCI_ID_VAL4_CAP_ENA_2 (2UL<<0) 1713 #define PCI_ID_VAL4_CAP_ENA_3 (3UL<<0) 1714 #define PCI_ID_VAL4_CAP_ENA_4 (4UL<<0) 1715 #define PCI_ID_VAL4_CAP_ENA_5 (5UL<<0) 1716 #define PCI_ID_VAL4_CAP_ENA_6 (6UL<<0) 1717 #define PCI_ID_VAL4_CAP_ENA_7 (7UL<<0) 1718 #define PCI_ID_VAL4_CAP_ENA_8 (8UL<<0) 1719 #define PCI_ID_VAL4_CAP_ENA_9 (9UL<<0) 1720 #define PCI_ID_VAL4_CAP_ENA_10 (10UL<<0) 1721 #define PCI_ID_VAL4_CAP_ENA_11 (11UL<<0) 1722 #define PCI_ID_VAL4_CAP_ENA_12 (12UL<<0) 1723 #define PCI_ID_VAL4_CAP_ENA_13 (13UL<<0) 1724 #define PCI_ID_VAL4_CAP_ENA_14 (14UL<<0) 1725 #define PCI_ID_VAL4_CAP_ENA_15 (15UL<<0) 1726 #define PCI_ID_VAL4_RESERVED0 (0x3UL<<4) 1727 #define PCI_ID_VAL4_PM_SCALE_PRG (0x3UL<<6) 1728 #define PCI_ID_VAL4_PM_SCALE_PRG_0 (0UL<<6) 1729 #define PCI_ID_VAL4_PM_SCALE_PRG_1 (1UL<<6) 1730 #define PCI_ID_VAL4_PM_SCALE_PRG_2 (2UL<<6) 1731 #define PCI_ID_VAL4_PM_SCALE_PRG_3 (3UL<<6) 1732 #define PCI_ID_VAL4_MSI_PV_MASK_CAP (1UL<<8) 1733 #define PCI_ID_VAL4_MSI_LIMIT (0x7UL<<9) 1734 #define PCI_ID_VAL4_MULTI_MSG_CAP (0x7UL<<12) 1735 #define PCI_ID_VAL4_MSI_ENABLE (1UL<<15) 1736 #define PCI_ID_VAL4_MAX_64_ADVERTIZE_TE (1UL<<16) 1737 #define PCI_ID_VAL4_MAX_133_ADVERTIZE_TE (1UL<<17) 1738 #define PCI_ID_VAL4_RESERVED2_TE (0x7UL<<18) 1739 #define PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B21_TE (0x3UL<<21) 1740 #define PCI_ID_VAL4_MAX_SPLIT_SIZE_B21_TE (0x3UL<<23) 1741 #define PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B0_TE (1UL<<25) 1742 #define PCI_ID_VAL4_MAX_MEM_READ_SIZE_B10_TE (0x3UL<<26) 1743 #define PCI_ID_VAL4_MAX_SPLIT_SIZE_B0_TE (1UL<<28) 1744 #define PCI_ID_VAL4_RESERVED3_TE (0x7UL<<29) 1745 #define PCI_ID_VAL4_RESERVED3_XI (0xffffUL<<16) 1746 1747 u32_t pci_id_val5; 1748 #define PCI_ID_VAL5_D1_SUPPORT (1UL<<0) 1749 #define PCI_ID_VAL5_D2_SUPPORT (1UL<<1) 1750 #define PCI_ID_VAL5_PME_IN_D0 (1UL<<2) 1751 #define PCI_ID_VAL5_PME_IN_D1 (1UL<<3) 1752 #define PCI_ID_VAL5_PME_IN_D2 (1UL<<4) 1753 #define PCI_ID_VAL5_PME_IN_D3_HOT (1UL<<5) 1754 #define PCI_ID_VAL5_RESERVED0_TE (0x3ffffffUL<<6) 1755 #define PCI_ID_VAL5_PM_VERSION_XI (0x7UL<<6) 1756 #define PCI_ID_VAL5_NO_SOFT_RESET_XI (1UL<<9) 1757 #define PCI_ID_VAL5_RESERVED0_XI (0x3fffffUL<<10) 1758 1759 u32_t pci_pcix_extended_status; 1760 #define PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1UL<<8) 1761 #define PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1UL<<9) 1762 #define PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfUL<<16) 1763 #define PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffUL<<24) 1764 1765 u32_t pci_id_val6; 1766 #define PCI_ID_VAL6_MAX_LAT (0xffUL<<0) 1767 #define PCI_ID_VAL6_MIN_GNT (0xffUL<<8) 1768 #define PCI_ID_VAL6_BIST (0xffUL<<16) 1769 #define PCI_ID_VAL6_RESERVED0 (0xffUL<<24) 1770 1771 u32_t pci_msi_data; 1772 #define PCI_MSI_DATA_MSI_DATA (0xffffUL<<0) 1773 1774 u32_t pci_msi_addr_h; 1775 u32_t pci_msi_addr_l; 1776 #define PCI_MSI_ADDR_L_VAL (0x3fffffffUL<<2) 1777 1778 u32_t pci_cfg_access_cmd; 1779 #define PCI_CFG_ACCESS_CMD_ADR (0x3fUL<<2) 1780 #define PCI_CFG_ACCESS_CMD_RD_REQ (1UL<<27) 1781 #define PCI_CFG_ACCESS_CMD_WR_REQ (0xfUL<<28) 1782 1783 u32_t pci_cfg_access_data; 1784 u32_t pci_msi_mask; 1785 #define PCI_MSI_MASK_MSI_MASK (0xffffffffUL<<0) 1786 1787 u32_t pci_msi_pend; 1788 #define PCI_MSI_PEND_MSI_PEND (0xffffffffUL<<0) 1789 1790 u32_t pci_pm_data_c; 1791 #define PCI_PM_DATA_C_PM_DATA_8_PRG (0xffUL<<0) 1792 #define PCI_PM_DATA_C_RESERVED0 (0xffffffUL<<8) 1793 1794 u32_t unused_1[20]; 1795 u32_t pci_msix_control; 1796 #define PCI_MSIX_CONTROL_MSIX_TBL_SIZ (0x7ffUL<<0) 1797 #define PCI_MSIX_CONTROL_RESERVED0 (0x1fffffUL<<11) 1798 1799 u32_t pci_msix_tbl_off_bir; 1800 #define PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_BIR (0x7UL<<0) 1801 #define PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_OFF (0x1fffffffUL<<3) 1802 1803 u32_t pci_msix_pba_off_bit; 1804 #define PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_BIR (0x7UL<<0) 1805 #define PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_OFF (0x1fffffffUL<<3) 1806 1807 u32_t unused_2; 1808 u32_t pci_pcie_capability; 1809 #define PCI_PCIE_CAPABILITY_INTERRUPT_MSG_NUM (0x1fUL<<0) 1810 #define PCI_PCIE_CAPABILITY_COMPLY_PCIE_1_1 (1UL<<5) 1811 1812 u32_t pci_device_capability; 1813 #define PCI_DEVICE_CAPABILITY_MAX_PL_SIZ_SUPPORTED (0x7UL<<0) 1814 #define PCI_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT (1UL<<5) 1815 #define PCI_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY (0x7UL<<6) 1816 #define PCI_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY (0x7UL<<9) 1817 #define PCI_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT (1UL<<15) 1818 1819 u32_t unused_3; 1820 u32_t pci_link_capability; 1821 #define PCI_LINK_CAPABILITY_MAX_LINK_SPEED (0xfUL<<0) 1822 #define PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0001 (1UL<<0) 1823 #define PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0010 (2UL<<0) 1824 #define PCI_LINK_CAPABILITY_MAX_LINK_WIDTH (0x1fUL<<4) 1825 #define PCI_LINK_CAPABILITY_CLK_POWER_MGMT (1UL<<9) 1826 #define PCI_LINK_CAPABILITY_ASPM_SUPPORT (0x3UL<<10) 1827 #define PCI_LINK_CAPABILITY_L0S_EXIT_LAT (0x7UL<<12) 1828 #define PCI_LINK_CAPABILITY_L0S_EXIT_LAT_101 (5UL<<12) 1829 #define PCI_LINK_CAPABILITY_L0S_EXIT_LAT_110 (6UL<<12) 1830 #define PCI_LINK_CAPABILITY_L1_EXIT_LAT (0x7UL<<15) 1831 #define PCI_LINK_CAPABILITY_L1_EXIT_LAT_001 (1UL<<15) 1832 #define PCI_LINK_CAPABILITY_L1_EXIT_LAT_010 (2UL<<15) 1833 #define PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT (0x7UL<<18) 1834 #define PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_101 (5UL<<18) 1835 #define PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_110 (6UL<<18) 1836 #define PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT (0x7UL<<21) 1837 #define PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_001 (1UL<<21) 1838 #define PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_010 (2UL<<21) 1839 #define PCI_LINK_CAPABILITY_PORT_NUM (0xffUL<<24) 1840 1841 u32_t pci_bar2_config; 1842 #define PCI_BAR2_CONFIG_BAR2_SIZE (0xfUL<<0) 1843 #define PCI_BAR2_CONFIG_BAR2_SIZE_DISABLED (0UL<<0) 1844 #define PCI_BAR2_CONFIG_BAR2_SIZE_64K (1UL<<0) 1845 #define PCI_BAR2_CONFIG_BAR2_SIZE_128K (2UL<<0) 1846 #define PCI_BAR2_CONFIG_BAR2_SIZE_256K (3UL<<0) 1847 #define PCI_BAR2_CONFIG_BAR2_SIZE_512K (4UL<<0) 1848 #define PCI_BAR2_CONFIG_BAR2_SIZE_1M (5UL<<0) 1849 #define PCI_BAR2_CONFIG_BAR2_SIZE_2M (6UL<<0) 1850 #define PCI_BAR2_CONFIG_BAR2_SIZE_4M (7UL<<0) 1851 #define PCI_BAR2_CONFIG_BAR2_SIZE_8M (8UL<<0) 1852 #define PCI_BAR2_CONFIG_BAR2_SIZE_16M (9UL<<0) 1853 #define PCI_BAR2_CONFIG_BAR2_SIZE_32M (10UL<<0) 1854 #define PCI_BAR2_CONFIG_BAR2_SIZE_64M (11UL<<0) 1855 #define PCI_BAR2_CONFIG_BAR2_SIZE_128M (12UL<<0) 1856 #define PCI_BAR2_CONFIG_BAR2_SIZE_256M (13UL<<0) 1857 #define PCI_BAR2_CONFIG_BAR2_SIZE_512M (14UL<<0) 1858 #define PCI_BAR2_CONFIG_BAR2_SIZE_1G (15UL<<0) 1859 #define PCI_BAR2_CONFIG_BAR2_64ENA (1UL<<4) 1860 #define PCI_BAR2_CONFIG_BAR2_PREFETCH (1UL<<5) 1861 #define PCI_BAR2_CONFIG_RESERVED (0x3ffffffUL<<6) 1862 1863 u32_t pci_pcie_device_capability_2; 1864 #define PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP (0xfUL<<0) 1865 #define PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP (1UL<<4) 1866 #define PCI_PCIE_DEVICE_CAPABILITY_2_RESERVED (0x7ffffffUL<<5) 1867 1868 u32_t pci_pcie_link_capability_2; 1869 #define PCI_PCIE_LINK_CAPABILITY_2_RESERVED (0xffffffffUL<<0) 1870 1871 u32_t unused_4[5]; 1872 u32_t pci_dev_ser_num_cap_id; 1873 #define PCI_DEV_SER_NUM_CAP_ID_CAP_ID (0xffffUL<<0) 1874 #define PCI_DEV_SER_NUM_CAP_ID_CAP_VER (0xfUL<<16) 1875 #define PCI_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA (0xfUL<<20) 1876 #define PCI_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_8 (8UL<<20) 1877 #define PCI_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_9 (9UL<<20) 1878 #define PCI_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_10 (10UL<<20) 1879 #define PCI_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_11 (11UL<<20) 1880 #define PCI_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_12 (12UL<<20) 1881 #define PCI_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_13 (13UL<<20) 1882 #define PCI_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_14 (14UL<<20) 1883 #define PCI_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_15 (15UL<<20) 1884 1885 u32_t pci_lower_ser_num; 1886 #define PCI_LOWER_SER_NUM_LOWER_SER_NUM (0xffffffffUL<<0) 1887 1888 u32_t pci_upper_ser_num; 1889 #define PCI_UPPER_SER_NUM_UPPER_SER_NUM (0xffffffffUL<<0) 1890 1891 u32_t pci_adv_err_cap; 1892 #define PCI_ADV_ERR_CAP_ECRC_CHK_CAP (1UL<<0) 1893 #define PCI_ADV_ERR_CAP_ECRC_GEN_CAP (1UL<<1) 1894 1895 u32_t pci_pwr_bdgt_data_0; 1896 #define PCI_PWR_BDGT_DATA_0_PWR_BDGT_DATA_0 (0x1fffffUL<<0) 1897 #define PCI_PWR_BDGT_DATA_0_RESERVED (0x7ffUL<<21) 1898 1899 u32_t pci_pwr_bdgt_data_1; 1900 #define PCI_PWR_BDGT_DATA_1_PWR_BDGT_DATA_1 (0x1fffffUL<<0) 1901 #define PCI_PWR_BDGT_DATA_1_RW (0x7ffUL<<21) 1902 1903 u32_t pci_pwr_bdgt_data_2; 1904 #define PCI_PWR_BDGT_DATA_2_PWR_BDGT_DATA_2 (0x1fffffUL<<0) 1905 #define PCI_PWR_BDGT_DATA_2_RW (0x7ffUL<<21) 1906 1907 u32_t pci_pwd_bdgt_data_3; 1908 #define PCI_PWD_BDGT_DATA_3_PWR_BDGT_DATA_3 (0x1fffffUL<<0) 1909 #define PCI_PWD_BDGT_DATA_3_RW (0x7ffUL<<21) 1910 1911 u32_t pci_pwr_bdgt_data_4; 1912 #define PCI_PWR_BDGT_DATA_4_PWR_BDGT_DATA_4 (0x1fffffUL<<0) 1913 #define PCI_PWR_BDGT_DATA_4_RW (0x7ffUL<<21) 1914 1915 u32_t pci_pwr_bdgt_data_5; 1916 #define PCI_PWR_BDGT_DATA_5_PWR_BDGT_DATA_5 (0x1fffffUL<<0) 1917 #define PCI_PWR_BDGT_DATA_5_RW (0x7ffUL<<21) 1918 1919 u32_t pci_pwr_bdgt_data_6; 1920 #define PCI_PWR_BDGT_DATA_6_PWR_BDGT_DATA_6 (0x1fffffUL<<0) 1921 #define PCI_PWR_BDGT_DATA_6_RW (0x7ffUL<<21) 1922 1923 u32_t pci_pwr_bdgt_data_7; 1924 #define PCI_PWR_BDGT_DATA_7_PWR_BDGT_DATA_7 (0x1fffffUL<<0) 1925 #define PCI_PWR_BDGT_DATA_7_RW (0x7ffUL<<21) 1926 1927 u32_t unused_5[8]; 1928 u32_t pci_pwr_bdgt_capability_ctl; 1929 #define PCI_PWR_BDGT_CAPABILITY_CTL_PWR_SYSTEM_ALLOC (1UL<<0) 1930 #define PCI_PWR_BDGT_CAPABILITY_CTL_RESERVED (0x7fffffffUL<<1) 1931 1932 u32_t unused_6[47]; 1933 u32_t pci_grc_window1_addr; 1934 #define PCI_GRC_WINDOW1_ADDR_VALUE (0x1ffUL<<13) 1935 1936 u32_t pci_grc_window2_addr; 1937 #define PCI_GRC_WINDOW2_ADDR_VALUE (0x1ffUL<<13) 1938 1939 u32_t pci_grc_window3_addr; 1940 #define PCI_GRC_WINDOW3_ADDR_VALUE (0x1ffUL<<13) 1941 1942 u32_t unused_7[9]; 1943 u32_t pci_exp_rom_adr; 1944 #define PCI_EXP_ROM_ADR_ADDRESS (0x3fffffUL<<2) 1945 #define PCI_EXP_ROM_ADR_ADDR_SIZE (0x3UL<<24) 1946 #define PCI_EXP_ROM_ADR_REQ (1UL<<31) 1947 1948 u32_t pci_exp_rom_data0; 1949 u32_t pci_exp_rom_data1; 1950 u32_t pci_exp_rom_data2; 1951 u32_t pci_exp_rom_ctrl; 1952 #define PCI_EXP_ROM_CTRL_ENA (1UL<<0) 1953 #define PCI_EXP_ROM_CTRL_BFRD (1UL<<1) 1954 #define PCI_EXP_ROM_CTRL_ARB_NUM (0x3UL<<4) 1955 #define PCI_EXP_ROM_CTRL_STATE (0xfUL<<16) 1956 #define PCI_EXP_ROM_CTRL_CACHE_VALID (1UL<<28) 1957 #define PCI_EXP_ROM_CTRL_ARB_TIMEOUT (1UL<<29) 1958 #define PCI_EXP_ROM_CTRL_READ_TIMEOUT (1UL<<30) 1959 #define PCI_EXP_ROM_CTRL_ACTIVE (1UL<<31) 1960 1961 u32_t pci_exp_rom_baddr; 1962 #define PCI_EXP_ROM_BADDR_VALUE (0x3fffffUL<<2) 1963 1964 u32_t pci_exp_rom_cfg; 1965 #define PCI_EXP_ROM_CFG_ARB_TIMEOUT_SHFT (0xfUL<<0) 1966 #define PCI_EXP_ROM_CFG_READ_TIMEOUT_SHFT (0xfUL<<4) 1967 1968 u32_t unused_8[41]; 1969 u32_t pci_debug_vect_peek; 1970 #define PCI_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) 1971 #define PCI_DEBUG_VECT_PEEK_1_EN (1UL<<11) 1972 #define PCI_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) 1973 #define PCI_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) 1974 #define PCI_DEBUG_VECT_PEEK_2_EN (1UL<<27) 1975 #define PCI_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) 1976 1977 u32_t unused_9[63]; 1978 } pci_reg_t; 1979 1980 1981 /* 1982 * pcie_reg definition 1983 * offset: 0x300000 1984 */ 1985 typedef struct pcie_reg 1986 { 1987 u16_t pci1_cfg_device_id; 1988 u16_t pci1_cfg_vendor_id; 1989 u16_t pci1_cfg_status; 1990 #define PCI1_CFG_STATUS_RESERVED1 (0x7<<0) 1991 #define PCI1_CFG_STATUS_INT_STATUS (1<<3) 1992 #define PCI1_CFG_STATUS_CAP_LIST (1<<4) 1993 #define PCI1_CFG_STATUS_66MHZ_CAP (1<<5) 1994 #define PCI1_CFG_STATUS_RESERVED2 (1<<6) 1995 #define PCI1_CFG_STATUS_FAST_B2B_CAP (1<<7) 1996 #define PCI1_CFG_STATUS_MSTR_PERR (1<<8) 1997 #define PCI1_CFG_STATUS_DEVSEL_TIMING (0x3<<9) 1998 #define PCI1_CFG_STATUS_SIG_TGT_ABT (1<<11) 1999 #define PCI1_CFG_STATUS_RCV_TGT_ABT (1<<12) 2000 #define PCI1_CFG_STATUS_RCV_MSTR_ABT (1<<13) 2001 #define PCI1_CFG_STATUS_SIG_SERR (1<<14) 2002 #define PCI1_CFG_STATUS_PAR_ERR (1<<15) 2003 2004 u16_t pci1_cfg_command; 2005 #define PCI1_CFG_COMMAND_IO_SPACE (1<<0) 2006 #define PCI1_CFG_COMMAND_MEM_SPACE (1<<1) 2007 #define PCI1_CFG_COMMAND_BUS_MASTER (1<<2) 2008 #define PCI1_CFG_COMMAND_SPECIAL_CYCLES (1<<3) 2009 #define PCI1_CFG_COMMAND_MWI_CYCLES (1<<4) 2010 #define PCI1_CFG_COMMAND_VGA_SNOOP (1<<5) 2011 #define PCI1_CFG_COMMAND_PERR_ENA (1<<6) 2012 #define PCI1_CFG_COMMAND_STEPPING (1<<7) 2013 #define PCI1_CFG_COMMAND_SERR_ENA (1<<8) 2014 #define PCI1_CFG_COMMAND_FAST_B2B (1<<9) 2015 #define PCI1_CFG_COMMAND_INT_DISABLE (1<<10) 2016 #define PCI1_CFG_COMMAND_RESERVED (0x1f<<11) 2017 2018 u32_t pci1_cfg_class_code; 2019 #define PCI1_CFG_CLASS_CODE_REV_ID (0xffUL<<0) 2020 #define PCI1_CFG_CLASS_CODE_VALUE (0xffffffUL<<8) 2021 2022 u8_t pci1_cfg_bist; 2023 u8_t pci1_cfg_header_type; 2024 u8_t pci1_cfg_latency_timer; 2025 u8_t pci1_cfg_cache_line_size; 2026 u32_t pci1_cfg_bar_1; 2027 #define PCI1_CFG_BAR_1_MEM_SPACE (1UL<<0) 2028 #define PCI1_CFG_BAR_1_SPACE_TYPE (0x3UL<<1) 2029 #define PCI1_CFG_BAR_1_PREFETCH (1UL<<3) 2030 #define PCI1_CFG_BAR_1_ADDRESS (0xfffffffUL<<4) 2031 2032 u32_t pci1_cfg_bar_2; 2033 #define PCI1_CFG_BAR_2_ADDR (0xffffffffUL<<0) 2034 2035 u32_t pci1_cfg_bar_3; 2036 #define PCI1_CFG_BAR_3_MEM_SPACE (1UL<<0) 2037 #define PCI1_CFG_BAR_3_SPACE_TYPE (0x3UL<<1) 2038 #define PCI1_CFG_BAR_3_PREFETCH (1UL<<3) 2039 #define PCI1_CFG_BAR_3_ADDRESS (0xfffffffUL<<4) 2040 2041 u32_t pci1_cfg_bar_4; 2042 #define PCI1_CFG_BAR_4_ADDR (0xffffffffUL<<0) 2043 2044 u32_t pci1_cfg_bar_5; 2045 u32_t pci1_cfg_bar_6; 2046 u32_t pci1_cfg_cardbus_cis; 2047 u16_t pci1_cfg_subsystem_id; 2048 u16_t pci1_cfg_subsystem_vendor_id; 2049 u32_t pci1_cfg_exp_rom_bar; 2050 #define PCI1_CFG_EXP_ROM_BAR_BAR_ENA (1UL<<0) 2051 #define PCI1_CFG_EXP_ROM_BAR_LOW (0x3ffUL<<1) 2052 #define PCI1_CFG_EXP_ROM_BAR_SIZE (0x1fffUL<<11) 2053 #define PCI1_CFG_EXP_ROM_BAR_ADDRESS (0xffUL<<24) 2054 2055 u16_t unused_0; 2056 u8_t unused_1; 2057 u8_t pci1_cfg_cap_pointer; 2058 u32_t unused_2; 2059 u8_t pci1_cfg_maximum_latency; 2060 u8_t pci1_cfg_min_grant; 2061 u8_t pci1_cfg_int_pin; 2062 u8_t pci1_cfg_int_line; 2063 u32_t unused_3[2]; 2064 u16_t pci1_cfg_pm_capability; 2065 #define PCI1_CFG_PM_CAPABILITY_VERSION (0x3<<0) 2066 #define PCI1_CFG_PM_CAPABILITY_CLOCK (1<<3) 2067 #define PCI1_CFG_PM_CAPABILITY_RESERVED (1<<4) 2068 #define PCI1_CFG_PM_CAPABILITY_DSI (1<<5) 2069 #define PCI1_CFG_PM_CAPABILITY_AUX_CURRENT (0x7<<6) 2070 #define PCI1_CFG_PM_CAPABILITY_D1_SUPPORT (1<<9) 2071 #define PCI1_CFG_PM_CAPABILITY_D2_SUPPORT (1<<10) 2072 #define PCI1_CFG_PM_CAPABILITY_PME_IN_D0 (1<<11) 2073 #define PCI1_CFG_PM_CAPABILITY_PME_IN_D1 (1<<12) 2074 #define PCI1_CFG_PM_CAPABILITY_PME_IN_D2 (1<<13) 2075 #define PCI1_CFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<14) 2076 #define PCI1_CFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<15) 2077 2078 u8_t pci1_cfg_pm_next_cap_ptr; 2079 u8_t pci1_cfg_pm_cap_id; 2080 u8_t pci1_cfg_pm_data; 2081 u8_t pci1_cfg_pm_csr_bse; 2082 u16_t pci1_cfg_pm_csr; 2083 #define PCI1_CFG_PM_CSR_STATE (0x3<<0) 2084 #define PCI1_CFG_PM_CSR_STATE_D0 (0<<0) 2085 #define PCI1_CFG_PM_CSR_STATE_D1 (1<<0) 2086 #define PCI1_CFG_PM_CSR_STATE_D2 (2<<0) 2087 #define PCI1_CFG_PM_CSR_STATE_D3_HOT (3<<0) 2088 #define PCI1_CFG_PM_CSR_RESERVED0 (1<<2) 2089 #define PCI1_CFG_PM_CSR_NO_SOFT_RESET (1<<3) 2090 #define PCI1_CFG_PM_CSR_RESERVED1 (0xf<<4) 2091 #define PCI1_CFG_PM_CSR_PME_ENABLE (1<<8) 2092 #define PCI1_CFG_PM_CSR_DATA_SEL (0xf<<9) 2093 #define PCI1_CFG_PM_CSR_DATA_SEL_0 (0<<9) 2094 #define PCI1_CFG_PM_CSR_DATA_SEL_1 (1<<9) 2095 #define PCI1_CFG_PM_CSR_DATA_SEL_2 (2<<9) 2096 #define PCI1_CFG_PM_CSR_DATA_SEL_3 (3<<9) 2097 #define PCI1_CFG_PM_CSR_DATA_SEL_4 (4<<9) 2098 #define PCI1_CFG_PM_CSR_DATA_SEL_5 (5<<9) 2099 #define PCI1_CFG_PM_CSR_DATA_SEL_6 (6<<9) 2100 #define PCI1_CFG_PM_CSR_DATA_SEL_7 (7<<9) 2101 #define PCI1_CFG_PM_CSR_DATA_SCALE (0x3<<13) 2102 #define PCI1_CFG_PM_CSR_DATA_SCALE_0 (0<<13) 2103 #define PCI1_CFG_PM_CSR_DATA_SCALE_1 (1<<13) 2104 #define PCI1_CFG_PM_CSR_DATA_SCALE_2 (2<<13) 2105 #define PCI1_CFG_PM_CSR_DATA_SCALE_3 (3<<13) 2106 #define PCI1_CFG_PM_CSR_PME_STATUS (1<<15) 2107 2108 u16_t pci1_cfg_vpd_flag_addr; 2109 #define PCI1_CFG_VPD_FLAG_ADDR_ADDRESS (0x1fff<<2) 2110 #define PCI1_CFG_VPD_FLAG_ADDR_FLAG (1<<15) 2111 2112 u8_t pci1_cfg_vpd_next_cap_ptr; 2113 u8_t pci1_cfg_vpd_cap_id; 2114 u32_t pci1_cfg_vpd_data; 2115 u16_t pci1_cfg_msi_control; 2116 #define PCI1_CFG_MSI_CONTROL_ENABLE (1<<0) 2117 #define PCI1_CFG_MSI_CONTROL_MCAP (0x7<<1) 2118 #define PCI1_CFG_MSI_CONTROL_MCAP_1 (0<<1) 2119 #define PCI1_CFG_MSI_CONTROL_MCAP_2 (1<<1) 2120 #define PCI1_CFG_MSI_CONTROL_MCAP_4 (2<<1) 2121 #define PCI1_CFG_MSI_CONTROL_MCAP_8 (3<<1) 2122 #define PCI1_CFG_MSI_CONTROL_MCAP_16 (4<<1) 2123 #define PCI1_CFG_MSI_CONTROL_MCAP_32 (5<<1) 2124 #define PCI1_CFG_MSI_CONTROL_MENA (0x7<<4) 2125 #define PCI1_CFG_MSI_CONTROL_MENA_1 (0<<4) 2126 #define PCI1_CFG_MSI_CONTROL_MENA_2 (1<<4) 2127 #define PCI1_CFG_MSI_CONTROL_MENA_4 (2<<4) 2128 #define PCI1_CFG_MSI_CONTROL_MENA_8 (3<<4) 2129 #define PCI1_CFG_MSI_CONTROL_MENA_16 (4<<4) 2130 #define PCI1_CFG_MSI_CONTROL_MENA_32 (5<<4) 2131 #define PCI1_CFG_MSI_CONTROL_64_BIT_ADDR_CAP (1<<7) 2132 #define PCI1_CFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (1<<8) 2133 2134 u8_t pci1_cfg_msi_next_cap_ptr; 2135 u8_t pci1_cfg_msi_cap_id; 2136 u32_t pci1_cfg_msi_addr_l; 2137 #define PCI1_CFG_MSI_ADDR_L_VAL (0x3fffffffUL<<2) 2138 2139 u32_t pci1_cfg_msi_addr_h; 2140 u16_t unused_4; 2141 u16_t pci1_cfg_msi_data; 2142 u32_t pci1_cfg_misc_config; 2143 #define PCI1_CFG_MISC_CONFIG_TARGET_BYTE_SWAP (1UL<<2) 2144 #define PCI1_CFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1UL<<3) 2145 #define PCI1_CFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1UL<<6) 2146 #define PCI1_CFG_MISC_CONFIG_REG_WINDOW_ENA (1UL<<7) 2147 #define PCI1_CFG_MISC_CONFIG_GRC_WIN1_SWAP_EN (1UL<<10) 2148 #define PCI1_CFG_MISC_CONFIG_GRC_WIN2_SWAP_EN (1UL<<11) 2149 #define PCI1_CFG_MISC_CONFIG_GRC_WIN3_SWAP_EN (1UL<<12) 2150 #define PCI1_CFG_MISC_CONFIG_ASIC_METAL_REV (0xffUL<<16) 2151 #define PCI1_CFG_MISC_CONFIG_ASIC_BASE_REV (0xfUL<<24) 2152 #define PCI1_CFG_MISC_CONFIG_ASIC_ID (0xfUL<<28) 2153 2154 u32_t pci1_cfg_misc_status; 2155 #define PCI1_CFG_MISC_STATUS_INTA_VALUE (1UL<<0) 2156 #define PCI1_CFG_MISC_STATUS_BAD_MEM_WRITE_BE (1UL<<8) 2157 2158 u32_t unused_5[2]; 2159 u32_t pci1_cfg_reg_window_address; 2160 u32_t unused_6; 2161 u32_t pci1_cfg_reg_window; 2162 u32_t pci1_cfg_int_ack_cmd; 2163 #define PCI1_CFG_INT_ACK_CMD_INDEX (0xffffUL<<0) 2164 #define PCI1_CFG_INT_ACK_CMD_INDEX_VALID (1UL<<16) 2165 #define PCI1_CFG_INT_ACK_CMD_USE_INT_HC_PARAM (1UL<<17) 2166 #define PCI1_CFG_INT_ACK_CMD_MASK_INT (1UL<<18) 2167 #define PCI1_CFG_INT_ACK_CMD_INTERRUPT_NUM (0xfUL<<24) 2168 2169 u32_t pci1_cfg_status_bit_set_cmd; 2170 u32_t pci1_cfg_status_bit_clear_cmd; 2171 u32_t pci1_cfg_mailbox_queue_addr; 2172 u32_t pci1_cfg_mailbox_queue_data; 2173 u32_t unused_7[2]; 2174 u16_t pci1_cfg_msix_control; 2175 #define PCI1_CFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<0) 2176 #define PCI1_CFG_MSIX_CONTROL_RESERVED (0x7<<11) 2177 #define PCI1_CFG_MSIX_CONTROL_FUNC_MASK (1<<14) 2178 #define PCI1_CFG_MSIX_CONTROL_MSIX_ENABLE (1<<15) 2179 2180 u8_t pci1_cfg_msix_next_cap_ptr; 2181 u8_t pci1_cfg_msix_cap_id; 2182 u32_t pci1_cfg_msix_tbl_off_bir; 2183 #define PCI1_CFG_MSIX_TBL_OFF_BIR_TABLE_BIR (0x7UL<<0) 2184 #define PCI1_CFG_MSIX_TBL_OFF_BIR_TABLE_OFFSET (0x1fffffffUL<<3) 2185 2186 u32_t pci1_cfg_msix_pba_off_bir; 2187 #define PCI1_CFG_MSIX_PBA_OFF_BIR_PBA_BIR (0x7UL<<0) 2188 #define PCI1_CFG_MSIX_PBA_OFF_BIR_PBA_OFFSET (0x1fffffffUL<<3) 2189 2190 u16_t pci1_cfg_pcie_capability; 2191 #define PCI1_CFG_PCIE_CAPABILITY_VER (0xf<<0) 2192 #define PCI1_CFG_PCIE_CAPABILITY_TYPE (0xf<<4) 2193 2194 u8_t pci1_cfg_pcie_next_cap_ptr; 2195 u8_t pci1_cfg_pcie_cap_id; 2196 u32_t pci1_cfg_device_capability; 2197 #define PCI1_CFG_DEVICE_CAPABILITY_MAX_PAYLOAD (0x7UL<<0) 2198 #define PCI1_CFG_DEVICE_CAPABILITY_PHANTOM_SUPPT (0x3UL<<3) 2199 #define PCI1_CFG_DEVICE_CAPABILITY_EXT_TAG_SUPPT (1UL<<5) 2200 #define PCI1_CFG_DEVICE_CAPABILITY_EP_L0S_ACCP_LAT (0x7UL<<6) 2201 #define PCI1_CFG_DEVICE_CAPABILITY_EP_L1_ACCP_LAT (0x7UL<<9) 2202 2203 u16_t pci1_cfg_device_status; 2204 #define PCI1_CFG_DEVICE_STATUS_CORR_ERR_DET (1<<0) 2205 #define PCI1_CFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1) 2206 #define PCI1_CFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2) 2207 #define PCI1_CFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3) 2208 #define PCI1_CFG_DEVICE_STATUS_AUX_PWR_DET (1<<4) 2209 #define PCI1_CFG_DEVICE_STATUS_NO_PEND (1<<5) 2210 2211 u16_t pci1_cfg_device_control; 2212 #define PCI1_CFG_DEVICE_CONTROL_CORR_ERR_REP_ENA (1<<0) 2213 #define PCI1_CFG_DEVICE_CONTROL_NON_FATAL_REP_ENA (1<<1) 2214 #define PCI1_CFG_DEVICE_CONTROL_FATAL_REP_ENA (1<<2) 2215 #define PCI1_CFG_DEVICE_CONTROL_UNSUP_REQ_ENA (1<<3) 2216 #define PCI1_CFG_DEVICE_CONTROL_RELAX_ENA (1<<4) 2217 #define PCI1_CFG_DEVICE_CONTROL_MAX_PAYLOAD (0x7<<5) 2218 #define PCI1_CFG_DEVICE_CONTROL_EXT_TAG_ENA (1<<8) 2219 #define PCI1_CFG_DEVICE_CONTROL_AUX_PWR_PM_ENA (1<<10) 2220 #define PCI1_CFG_DEVICE_CONTROL_ENA_NO_SNOOP (1<<11) 2221 #define PCI1_CFG_DEVICE_CONTROL_MAX_RD_REQ (0x7<<12) 2222 2223 u32_t pci1_cfg_link_capability; 2224 #define PCI1_CFG_LINK_CAPABILITY_MAX_LINK_SPEED (0xfUL<<0) 2225 #define PCI1_CFG_LINK_CAPABILITY_MAX_LINK_SPEED_2_5 (1UL<<0) 2226 #define PCI1_CFG_LINK_CAPABILITY_MAX_LINK_SPEED_5 (2UL<<0) 2227 #define PCI1_CFG_LINK_CAPABILITY_MAX_LINK_WIDTH (0x3fUL<<4) 2228 #define PCI1_CFG_LINK_CAPABILITY_MAX_LINK_WIDTH_1 (1UL<<4) 2229 #define PCI1_CFG_LINK_CAPABILITY_MAX_LINK_WIDTH_2 (2UL<<4) 2230 #define PCI1_CFG_LINK_CAPABILITY_MAX_LINK_WIDTH_4 (4UL<<4) 2231 #define PCI1_CFG_LINK_CAPABILITY_MAX_LINK_WIDTH_8 (8UL<<4) 2232 #define PCI1_CFG_LINK_CAPABILITY_ASPM_SUPT (0x3UL<<10) 2233 #define PCI1_CFG_LINK_CAPABILITY_ASPM_SUPT_RES_0 (0UL<<10) 2234 #define PCI1_CFG_LINK_CAPABILITY_ASPM_SUPT_L0S (0UL<<10) 2235 #define PCI1_CFG_LINK_CAPABILITY_ASPM_SUPT_RES_2 (0UL<<10) 2236 #define PCI1_CFG_LINK_CAPABILITY_ASPM_SUPT_L0S_L1 (0UL<<10) 2237 #define PCI1_CFG_LINK_CAPABILITY_L0S_EXIT_LAT (0x7UL<<12) 2238 #define PCI1_CFG_LINK_CAPABILITY_L0S_EXIT_LAT_1_2 (5UL<<12) 2239 #define PCI1_CFG_LINK_CAPABILITY_L0S_EXIT_LAT_2_4 (6UL<<12) 2240 #define PCI1_CFG_LINK_CAPABILITY_L1_EXIT_LAT (0x7UL<<15) 2241 #define PCI1_CFG_LINK_CAPABILITY_L1_EXIT_LAT_1_2 (1UL<<15) 2242 #define PCI1_CFG_LINK_CAPABILITY_L1_EXIT_LAT_2_4 (2UL<<15) 2243 #define PCI1_CFG_LINK_CAPABILITY_CLK_PWR_MGMT (1UL<<18) 2244 #define PCI1_CFG_LINK_CAPABILITY_PORT_NUMBER (0xffUL<<24) 2245 2246 u16_t pci1_cfg_link_status; 2247 #define PCI1_CFG_LINK_STATUS_SPEED (0xf<<0) 2248 #define PCI1_CFG_LINK_STATUS_NEG_LINK_WIDTH (0x3f<<4) 2249 #define PCI1_CFG_LINK_STATUS_TRAINING_ERR (1<<10) 2250 #define PCI1_CFG_LINK_STATUS_TRAINING (1<<11) 2251 #define PCI1_CFG_LINK_STATUS_SLOT_CLK (1<<12) 2252 2253 u16_t pci1_cfg_link_control; 2254 #define PCI1_CFG_LINK_CONTROL_ASPM_CTRL (0x3<<0) 2255 #define PCI1_CFG_LINK_CONTROL_RD_COMP_BOUND (1<<3) 2256 #define PCI1_CFG_LINK_CONTROL_RD_COMP_BOUND_64 (0<<3) 2257 #define PCI1_CFG_LINK_CONTROL_RD_COMP_BOUND_128 (1<<3) 2258 #define PCI1_CFG_LINK_CONTROL_LINK_CR_COMMON_CLK (1<<6) 2259 #define PCI1_CFG_LINK_CONTROL_LINK_CR_EXT_SYNC (1<<7) 2260 2261 u32_t pci1_cfg_slot_capability; 2262 u16_t pci1_cfg_slot_status; 2263 u16_t pci1_cfg_slot_control; 2264 u16_t pci1_cfg_root_cap; 2265 u16_t pci1_cfg_root_control; 2266 u32_t pci1_cfg_root_status; 2267 u32_t pci1_cfg_device_capability_2; 2268 #define PCI1_CFG_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP (0xfUL<<0) 2269 #define PCI1_CFG_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP_ABCD (15UL<<0) 2270 #define PCI1_CFG_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP (1UL<<4) 2271 2272 u16_t pci1_cfg_device_status_2; 2273 u16_t pci1_cfg_device_control_2; 2274 #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE (0xf<<0) 2275 #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_50MS (0<<0) 2276 #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_100US (1<<0) 2277 #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_10MS (2<<0) 2278 #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_55MS (3<<0) 2279 #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_210MS (4<<0) 2280 #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_900MS (5<<0) 2281 #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_3_5S (6<<0) 2282 #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_13S (7<<0) 2283 #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_VALUE_64S (8<<0) 2284 #define PCI1_CFG_DEVICE_CONTROL_2_CMPL_TO_DISABLE (1<<4) 2285 2286 u32_t pci1_cfg_link_capability_2; 2287 u16_t pci1_cfg_link_status_2; 2288 u16_t pci1_cfg_link_control_2; 2289 #define PCI1_CFG_LINK_CONTROL_2_TARGET_LINK_SPEED (0xf<<0) 2290 #define PCI1_CFG_LINK_CONTROL_2_TARGET_LINK_SPEED_2_5 (0<<0) 2291 #define PCI1_CFG_LINK_CONTROL_2_TARGET_LINK_SPEED_5_0 (1<<0) 2292 #define PCI1_CFG_LINK_CONTROL_2_ENTER_COMPLIANCE (1<<4) 2293 #define PCI1_CFG_LINK_CONTROL_2_HW_AUTO_SPEED_DISABLE (1<<5) 2294 #define PCI1_CFG_LINK_CONTROL_2_SEL_DEEMPHASIS (1<<6) 2295 #define PCI1_CFG_LINK_CONTROL_2_SEL_DEEMPHASIS_0 (0<<6) 2296 #define PCI1_CFG_LINK_CONTROL_2_SEL_DEEMPHASIS_1 (1<<6) 2297 #define PCI1_CFG_LINK_CONTROL_2_TX_MARGIN (0x7<<7) 2298 #define PCI1_CFG_LINK_CONTROL_2_TX_MARGIN_000 (0<<7) 2299 #define PCI1_CFG_LINK_CONTROL_2_TX_MARGIN_001 (1<<7) 2300 #define PCI1_CFG_LINK_CONTROL_2_TX_MARGIN_010 (2<<7) 2301 #define PCI1_CFG_LINK_CONTROL_2_TX_MARGIN_011 (3<<7) 2302 #define PCI1_CFG_LINK_CONTROL_2_TX_MARGIN_100 (4<<7) 2303 #define PCI1_CFG_LINK_CONTROL_2_TX_MARGIN_101 (5<<7) 2304 #define PCI1_CFG_LINK_CONTROL_2_TX_MARGIN_110 (6<<7) 2305 #define PCI1_CFG_LINK_CONTROL_2_TX_MARGIN_111 (7<<7) 2306 2307 u32_t unused_8[8]; 2308 u16_t pci1_cfg_device_ser_num_cap_off; 2309 #define PCI1_CFG_DEVICE_SER_NUM_CAP_OFF_VER (0xf<<0) 2310 #define PCI1_CFG_DEVICE_SER_NUM_CAP_OFF_NEXT (0xfff<<4) 2311 2312 u16_t pci1_cfg_device_ser_num_cap_id; 2313 u32_t pci1_cfg_lower_ser_num; 2314 u32_t pci1_cfg_upper_ser_num; 2315 u32_t unused_9; 2316 u16_t pci1_cfg_adv_err_cap_off; 2317 #define PCI1_CFG_ADV_ERR_CAP_OFF_VER (0xf<<0) 2318 #define PCI1_CFG_ADV_ERR_CAP_OFF_NEXT (0xfff<<4) 2319 2320 u16_t pci1_cfg_adv_err_cap_id; 2321 u32_t pci1_cfg_ucorr_err_status; 2322 #define PCI1_CFG_UCORR_ERR_STATUS_DLPES (1UL<<4) 2323 #define PCI1_CFG_UCORR_ERR_STATUS_PTLPS (1UL<<12) 2324 #define PCI1_CFG_UCORR_ERR_STATUS_FCPES (1UL<<13) 2325 #define PCI1_CFG_UCORR_ERR_STATUS_CTS (1UL<<14) 2326 #define PCI1_CFG_UCORR_ERR_STATUS_CAS (1UL<<15) 2327 #define PCI1_CFG_UCORR_ERR_STATUS_UCS (1UL<<16) 2328 #define PCI1_CFG_UCORR_ERR_STATUS_ROS (1UL<<17) 2329 #define PCI1_CFG_UCORR_ERR_STATUS_MTLPS (1UL<<18) 2330 #define PCI1_CFG_UCORR_ERR_STATUS_ECRCS (1UL<<19) 2331 #define PCI1_CFG_UCORR_ERR_STATUS_URES (1UL<<20) 2332 2333 u32_t pci1_cfg_ucorr_err_mask; 2334 #define PCI1_CFG_UCORR_ERR_MASK_DLPEM (1UL<<4) 2335 #define PCI1_CFG_UCORR_ERR_MASK_SDEM (1UL<<5) 2336 #define PCI1_CFG_UCORR_ERR_MASK_PTLPM (1UL<<12) 2337 #define PCI1_CFG_UCORR_ERR_MASK_FCPEM (1UL<<13) 2338 #define PCI1_CFG_UCORR_ERR_MASK_CTM (1UL<<14) 2339 #define PCI1_CFG_UCORR_ERR_MASK_CAM (1UL<<15) 2340 #define PCI1_CFG_UCORR_ERR_MASK_UCM (1UL<<16) 2341 #define PCI1_CFG_UCORR_ERR_MASK_ROM (1UL<<17) 2342 #define PCI1_CFG_UCORR_ERR_MASK_MTLPM (1UL<<18) 2343 #define PCI1_CFG_UCORR_ERR_MASK_ECRCEM (1UL<<19) 2344 #define PCI1_CFG_UCORR_ERR_MASK_UREM (1UL<<20) 2345 2346 u32_t pci1_cfg_ucorr_err_sevr; 2347 #define PCI1_CFG_UCORR_ERR_SEVR_DLPES (1UL<<4) 2348 #define PCI1_CFG_UCORR_ERR_SEVR_SDES (1UL<<5) 2349 #define PCI1_CFG_UCORR_ERR_SEVR_PTLPS (1UL<<12) 2350 #define PCI1_CFG_UCORR_ERR_SEVR_FCPES (1UL<<13) 2351 #define PCI1_CFG_UCORR_ERR_SEVR_CTS (1UL<<14) 2352 #define PCI1_CFG_UCORR_ERR_SEVR_CAS (1UL<<15) 2353 #define PCI1_CFG_UCORR_ERR_SEVR_UCS (1UL<<16) 2354 #define PCI1_CFG_UCORR_ERR_SEVR_ROS (1UL<<17) 2355 #define PCI1_CFG_UCORR_ERR_SEVR_MTLPS (1UL<<18) 2356 #define PCI1_CFG_UCORR_ERR_SEVR_ECRCES (1UL<<19) 2357 #define PCI1_CFG_UCORR_ERR_SEVR_URES (1UL<<20) 2358 2359 u32_t pci1_cfg_corr_err_status; 2360 #define PCI1_CFG_CORR_ERR_STATUS_RES (1UL<<0) 2361 #define PCI1_CFG_CORR_ERR_STATUS_BDLLPS (1UL<<7) 2362 #define PCI1_CFG_CORR_ERR_STATUS_BTLPS (1UL<<7) 2363 #define PCI1_CFG_CORR_ERR_STATUS_RNRS (1UL<<8) 2364 #define PCI1_CFG_CORR_ERR_STATUS_RTTS (1UL<<12) 2365 #define PCI1_CFG_CORR_ERR_STATUS_ANFS (1UL<<13) 2366 2367 u32_t pci1_cfg_corr_err_mask; 2368 #define PCI1_CFG_CORR_ERR_MASK_RES (1UL<<0) 2369 #define PCI1_CFG_CORR_ERR_MASK_BTLPS (1UL<<6) 2370 #define PCI1_CFG_CORR_ERR_MASK_BDLLPS (1UL<<7) 2371 #define PCI1_CFG_CORR_ERR_MASK_RNRS (1UL<<8) 2372 #define PCI1_CFG_CORR_ERR_MASK_RTTS (1UL<<12) 2373 #define PCI1_CFG_CORR_ERR_MASK_ANFM (1UL<<13) 2374 2375 u32_t pci1_cfg_adv_err_cap_control; 2376 #define PCI1_CFG_ADV_ERR_CAP_CONTROL_FIRST_UERR_PTR (0x1fUL<<0) 2377 #define PCI1_CFG_ADV_ERR_CAP_CONTROL_ECRCGCAP (1UL<<5) 2378 #define PCI1_CFG_ADV_ERR_CAP_CONTROL_ECRCGEN (1UL<<6) 2379 #define PCI1_CFG_ADV_ERR_CAP_CONTROL_ECRCCAP (1UL<<7) 2380 #define PCI1_CFG_ADV_ERR_CAP_CONTROL_ECRCEN (1UL<<8) 2381 2382 u32_t pci1_cfg_header_log1; 2383 u32_t pci1_cfg_header_log2; 2384 u32_t pci1_cfg_header_log3; 2385 u32_t pci1_cfg_header_log4; 2386 u32_t unused_10[5]; 2387 u16_t pci1_cfg_pwr_bdgt_cap_off; 2388 #define PCI1_CFG_PWR_BDGT_CAP_OFF_VER (0xf<<0) 2389 #define PCI1_CFG_PWR_BDGT_CAP_OFF_NEXT (0xfff<<4) 2390 2391 u16_t pci1_cfg_pwr_bdgt_cap_id; 2392 u32_t pci1_cfg_pwr_bdgt_data_sel; 2393 #define PCI1_CFG_PWR_BDGT_DATA_SEL_DS_VALUE (0xffUL<<0) 2394 #define PCI1_CFG_PWR_BDGT_DATA_SEL_DS_VALUE_0 (0UL<<0) 2395 #define PCI1_CFG_PWR_BDGT_DATA_SEL_DS_VALUE_1 (1UL<<0) 2396 #define PCI1_CFG_PWR_BDGT_DATA_SEL_DS_VALUE_2 (2UL<<0) 2397 #define PCI1_CFG_PWR_BDGT_DATA_SEL_DS_VALUE_3 (3UL<<0) 2398 #define PCI1_CFG_PWR_BDGT_DATA_SEL_DS_VALUE_4 (4UL<<0) 2399 #define PCI1_CFG_PWR_BDGT_DATA_SEL_DS_VALUE_5 (5UL<<0) 2400 #define PCI1_CFG_PWR_BDGT_DATA_SEL_DS_VALUE_6 (6UL<<0) 2401 #define PCI1_CFG_PWR_BDGT_DATA_SEL_DS_VALUE_7 (7UL<<0) 2402 2403 u32_t pci1_cfg_pwr_bdgt_data; 2404 #define PCI1_CFG_PWR_BDGT_DATA_BASE_PWR (0xffUL<<0) 2405 #define PCI1_CFG_PWR_BDGT_DATA_DSCALE (0x3UL<<8) 2406 #define PCI1_CFG_PWR_BDGT_DATA_PM_STATE (0x3UL<<13) 2407 #define PCI1_CFG_PWR_BDGT_DATA_TYPE (0x7UL<<15) 2408 #define PCI1_CFG_PWR_BDGT_DATA_RAIL (0x7UL<<18) 2409 2410 u32_t pci1_cfg_pwr_bdgt_capability; 2411 #define PCI1_CFG_PWR_BDGT_CAPABILITY_PCIE_CFG_PB_CAP_SYS_ALLOC (1UL<<0) 2412 2413 u16_t pci1_cfg_vc_cap_off; 2414 #define PCI1_CFG_VC_CAP_OFF_VER (0xf<<0) 2415 #define PCI1_CFG_VC_CAP_OFF_NEXT (0xfff<<4) 2416 2417 u16_t pci1_cfg_vc_cap_id; 2418 u32_t pci1_cfg_port_vc_capability; 2419 u32_t pci1_cfg_port_vc_capability2; 2420 u16_t pci1_cfg_port_vc_status; 2421 u16_t pci1_cfg_port_vc_control; 2422 u32_t pci1_cfg_port_arb_table; 2423 u32_t pci1_cfg_vc_rsrc_control; 2424 #define PCI1_CFG_VC_RSRC_CONTROL_TC_VC_MAP (0xffUL<<0) 2425 #define PCI1_CFG_VC_RSRC_CONTROL_VC_ENABLE (1UL<<31) 2426 2427 u16_t pci1_cfg_vc_rsrc_status; 2428 u16_t pci1_cfg_rsvdp; 2429 u32_t unused_11[161]; 2430 u32_t pci1_grc_window_addr; 2431 #define PCI1_GRC_WINDOW_ADDR_VALUE (0x1ffUL<<13) 2432 #define PCI1_GRC_WINDOW_ADDR_SEP_WIN (1UL<<31) 2433 2434 u32_t unused_12; 2435 u32_t pci1_config_2; 2436 #define PCI1_CONFIG_2_BAR1_SIZE (0xfUL<<0) 2437 #define PCI1_CONFIG_2_BAR1_SIZE_DISABLED (0UL<<0) 2438 #define PCI1_CONFIG_2_BAR1_SIZE_64K (1UL<<0) 2439 #define PCI1_CONFIG_2_BAR1_SIZE_128K (2UL<<0) 2440 #define PCI1_CONFIG_2_BAR1_SIZE_256K (3UL<<0) 2441 #define PCI1_CONFIG_2_BAR1_SIZE_512K (4UL<<0) 2442 #define PCI1_CONFIG_2_BAR1_SIZE_1M (5UL<<0) 2443 #define PCI1_CONFIG_2_BAR1_SIZE_2M (6UL<<0) 2444 #define PCI1_CONFIG_2_BAR1_SIZE_4M (7UL<<0) 2445 #define PCI1_CONFIG_2_BAR1_SIZE_8M (8UL<<0) 2446 #define PCI1_CONFIG_2_BAR1_SIZE_16M (9UL<<0) 2447 #define PCI1_CONFIG_2_BAR1_SIZE_32M (10UL<<0) 2448 #define PCI1_CONFIG_2_BAR1_SIZE_64M (11UL<<0) 2449 #define PCI1_CONFIG_2_BAR1_SIZE_128M (12UL<<0) 2450 #define PCI1_CONFIG_2_BAR1_SIZE_256M (13UL<<0) 2451 #define PCI1_CONFIG_2_BAR1_SIZE_512M (14UL<<0) 2452 #define PCI1_CONFIG_2_BAR1_SIZE_1G (15UL<<0) 2453 #define PCI1_CONFIG_2_BAR1_64ENA (1UL<<4) 2454 #define PCI1_CONFIG_2_EXP_ROM_RETRY (1UL<<5) 2455 #define PCI1_CONFIG_2_CFG_CYCLE_RETRY (1UL<<6) 2456 #define PCI1_CONFIG_2_FIRST_CFG_DONE (1UL<<7) 2457 #define PCI1_CONFIG_2_EXP_ROM_SIZE (0xffUL<<8) 2458 #define PCI1_CONFIG_2_EXP_ROM_SIZE_DISABLED (0UL<<8) 2459 #define PCI1_CONFIG_2_EXP_ROM_SIZE_2K (1UL<<8) 2460 #define PCI1_CONFIG_2_EXP_ROM_SIZE_4K (2UL<<8) 2461 #define PCI1_CONFIG_2_EXP_ROM_SIZE_8K (3UL<<8) 2462 #define PCI1_CONFIG_2_EXP_ROM_SIZE_16K (4UL<<8) 2463 #define PCI1_CONFIG_2_EXP_ROM_SIZE_32K (5UL<<8) 2464 #define PCI1_CONFIG_2_EXP_ROM_SIZE_64K (6UL<<8) 2465 #define PCI1_CONFIG_2_EXP_ROM_SIZE_128K (7UL<<8) 2466 #define PCI1_CONFIG_2_EXP_ROM_SIZE_256K (8UL<<8) 2467 #define PCI1_CONFIG_2_EXP_ROM_SIZE_512K (9UL<<8) 2468 #define PCI1_CONFIG_2_EXP_ROM_SIZE_1M (10UL<<8) 2469 #define PCI1_CONFIG_2_EXP_ROM_SIZE_2M (11UL<<8) 2470 #define PCI1_CONFIG_2_EXP_ROM_SIZE_4M (12UL<<8) 2471 #define PCI1_CONFIG_2_EXP_ROM_SIZE_8M (13UL<<8) 2472 #define PCI1_CONFIG_2_EXP_ROM_SIZE_16M (14UL<<8) 2473 #define PCI1_CONFIG_2_EXP_ROM_SIZE_32M (15UL<<8) 2474 #define PCI1_CONFIG_2_BAR_PREFETCH (1UL<<16) 2475 #define PCI1_CONFIG_2_RESERVED0 (0x7fffUL<<17) 2476 2477 u32_t pci1_config_3; 2478 #define PCI1_CONFIG_3_STICKY_BYTE (0xffUL<<0) 2479 #define PCI1_CONFIG_3_REG_STICKY_BYTE (0xffUL<<8) 2480 #define PCI1_CONFIG_3_FORCE_PME (1UL<<24) 2481 #define PCI1_CONFIG_3_PME_STATUS (1UL<<25) 2482 #define PCI1_CONFIG_3_PME_ENABLE (1UL<<26) 2483 #define PCI1_CONFIG_3_PM_STATE (0x3UL<<27) 2484 #define PCI1_CONFIG_3_VAUX_PRESET (1UL<<30) 2485 #define PCI1_CONFIG_3_PCI_POWER (1UL<<31) 2486 2487 u32_t pci1_pm_data_a; 2488 #define PCI1_PM_DATA_A_PM_DATA_0_PRG (0xffUL<<0) 2489 #define PCI1_PM_DATA_A_PM_DATA_1_PRG (0xffUL<<8) 2490 #define PCI1_PM_DATA_A_PM_DATA_2_PRG (0xffUL<<16) 2491 #define PCI1_PM_DATA_A_PM_DATA_3_PRG (0xffUL<<24) 2492 2493 u32_t pci1_pm_data_b; 2494 #define PCI1_PM_DATA_B_PM_DATA_4_PRG (0xffUL<<0) 2495 #define PCI1_PM_DATA_B_PM_DATA_5_PRG (0xffUL<<8) 2496 #define PCI1_PM_DATA_B_PM_DATA_6_PRG (0xffUL<<16) 2497 #define PCI1_PM_DATA_B_PM_DATA_7_PRG (0xffUL<<24) 2498 2499 u32_t pci1_swap_diag0; 2500 u32_t pci1_swap_diag1; 2501 u32_t unused_13[2]; 2502 u32_t pci1_vpd_intf; 2503 #define PCI1_VPD_INTF_INTF_REQ (1UL<<0) 2504 2505 u16_t unused_14; 2506 u16_t pci1_vpd_addr_flag; 2507 #define PCI1_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2) 2508 #define PCI1_VPD_ADDR_FLAG_WR (1<<15) 2509 2510 u32_t pci1_vpd_data; 2511 u32_t pci1_id_val1; 2512 #define PCI1_ID_VAL1_DEVICE_ID (0xffffUL<<0) 2513 #define PCI1_ID_VAL1_VENDOR_ID (0xffffUL<<16) 2514 2515 u32_t pci1_id_val2; 2516 #define PCI1_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffUL<<0) 2517 #define PCI1_ID_VAL2_SUBSYSTEM_ID (0xffffUL<<16) 2518 2519 u32_t pci1_id_val3; 2520 #define PCI1_ID_VAL3_CLASS_CODE (0xffffffUL<<0) 2521 #define PCI1_ID_VAL3_REVISION_ID (0xffUL<<24) 2522 2523 u32_t pci1_id_val4; 2524 #define PCI1_ID_VAL4_CAP_ENA (0xfUL<<0) 2525 #define PCI1_ID_VAL4_CAP_ENA_0 (0UL<<0) 2526 #define PCI1_ID_VAL4_CAP_ENA_1 (1UL<<0) 2527 #define PCI1_ID_VAL4_CAP_ENA_2 (2UL<<0) 2528 #define PCI1_ID_VAL4_CAP_ENA_3 (3UL<<0) 2529 #define PCI1_ID_VAL4_CAP_ENA_4 (4UL<<0) 2530 #define PCI1_ID_VAL4_CAP_ENA_5 (5UL<<0) 2531 #define PCI1_ID_VAL4_CAP_ENA_6 (6UL<<0) 2532 #define PCI1_ID_VAL4_CAP_ENA_7 (7UL<<0) 2533 #define PCI1_ID_VAL4_CAP_ENA_8 (8UL<<0) 2534 #define PCI1_ID_VAL4_CAP_ENA_9 (9UL<<0) 2535 #define PCI1_ID_VAL4_CAP_ENA_10 (10UL<<0) 2536 #define PCI1_ID_VAL4_CAP_ENA_11 (11UL<<0) 2537 #define PCI1_ID_VAL4_CAP_ENA_12 (12UL<<0) 2538 #define PCI1_ID_VAL4_CAP_ENA_13 (13UL<<0) 2539 #define PCI1_ID_VAL4_CAP_ENA_14 (14UL<<0) 2540 #define PCI1_ID_VAL4_CAP_ENA_15 (15UL<<0) 2541 #define PCI1_ID_VAL4_PM_SCALE_PRG (0x3UL<<6) 2542 #define PCI1_ID_VAL4_PM_SCALE_PRG_0 (0UL<<6) 2543 #define PCI1_ID_VAL4_PM_SCALE_PRG_1 (1UL<<6) 2544 #define PCI1_ID_VAL4_PM_SCALE_PRG_2 (2UL<<6) 2545 #define PCI1_ID_VAL4_PM_SCALE_PRG_3 (3UL<<6) 2546 #define PCI1_ID_VAL4_MSI_PV_MASK_CAP (1UL<<8) 2547 #define PCI1_ID_VAL4_MSI_LIMIT (0x7UL<<9) 2548 #define PCI1_ID_VAL4_MULTI_MSG_CAP (0x7UL<<12) 2549 #define PCI1_ID_VAL4_MSI_ENABLE (1UL<<15) 2550 #define PCI1_ID_VAL4_RESERVED3 (0xffffUL<<16) 2551 2552 u32_t pci1_id_val5; 2553 #define PCI1_ID_VAL5_D1_SUPPORT (1UL<<0) 2554 #define PCI1_ID_VAL5_D2_SUPPORT (1UL<<1) 2555 #define PCI1_ID_VAL5_PME_IN_D0 (1UL<<2) 2556 #define PCI1_ID_VAL5_PME_IN_D1 (1UL<<3) 2557 #define PCI1_ID_VAL5_PME_IN_D2 (1UL<<4) 2558 #define PCI1_ID_VAL5_PME_IN_D3_HOT (1UL<<5) 2559 #define PCI1_ID_VAL5_PM_VERSION (0x7UL<<6) 2560 #define PCI1_ID_VAL5_NO_SOFT_RESET (1UL<<9) 2561 #define PCI1_ID_VAL5_RESERVED0 (0x3fffffUL<<10) 2562 2563 u32_t unused_15; 2564 u32_t pci1_id_val6; 2565 #define PCI1_ID_VAL6_BIST (0xffUL<<16) 2566 2567 u32_t pci1_msi_data; 2568 #define PCI1_MSI_DATA_MSI_DATA (0xffffUL<<0) 2569 2570 u32_t pci1_msi_addr_h; 2571 u32_t pci1_msi_addr_l; 2572 #define PCI1_MSI_ADDR_L_VAL (0x3fffffffUL<<2) 2573 2574 u32_t unused_16[2]; 2575 u32_t pci1_msi_mask; 2576 #define PCI1_MSI_MASK_MSI_MASK (0xffffffffUL<<0) 2577 2578 u32_t pci1_msi_pend; 2579 #define PCI1_MSI_PEND_MSI_PEND (0xffffffffUL<<0) 2580 2581 u32_t pci1_pm_data_c; 2582 #define PCI1_PM_DATA_C_PM_DATA_8_PRG (0xffUL<<0) 2583 #define PCI1_PM_DATA_C_RESERVED0 (0xffffffUL<<8) 2584 2585 u32_t unused_17[20]; 2586 u32_t pci1_msix_control; 2587 #define PCI1_MSIX_CONTROL_MSIX_TBL_SIZ (0x7ffUL<<0) 2588 #define PCI1_MSIX_CONTROL_RESERVED0 (0x1fffffUL<<11) 2589 2590 u32_t pci1_msix_tbl_off_bir; 2591 #define PCI1_MSIX_TBL_OFF_BIR_MSIX_TBL_BIR (0x7UL<<0) 2592 #define PCI1_MSIX_TBL_OFF_BIR_MSIX_TBL_OFF (0x1fffffffUL<<3) 2593 2594 u32_t pci1_msix_pba_off_bit; 2595 #define PCI1_MSIX_PBA_OFF_BIT_MSIX_PBA_BIR (0x7UL<<0) 2596 #define PCI1_MSIX_PBA_OFF_BIT_MSIX_PBA_OFF (0x1fffffffUL<<3) 2597 2598 u32_t unused_18; 2599 u32_t pci1_pcie_capability; 2600 #define PCI1_PCIE_CAPABILITY_INTERRUPT_MSG_NUM (0x1fUL<<0) 2601 #define PCI1_PCIE_CAPABILITY_COMPLY_PCIE_1_1 (1UL<<5) 2602 2603 u32_t pci1_device_capability; 2604 #define PCI1_DEVICE_CAPABILITY_MAX_PL_SIZ_SUPPORTED (0x7UL<<0) 2605 #define PCI1_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT (1UL<<5) 2606 #define PCI1_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY (0x7UL<<6) 2607 #define PCI1_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY (0x7UL<<9) 2608 #define PCI1_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT (1UL<<15) 2609 2610 u32_t unused_19; 2611 u32_t pci1_link_capability; 2612 #define PCI1_LINK_CAPABILITY_MAX_LINK_SPEED (0xfUL<<0) 2613 #define PCI1_LINK_CAPABILITY_MAX_LINK_SPEED_0001 (1UL<<0) 2614 #define PCI1_LINK_CAPABILITY_MAX_LINK_SPEED_0010 (2UL<<0) 2615 #define PCI1_LINK_CAPABILITY_MAX_LINK_WIDTH (0x1fUL<<4) 2616 #define PCI1_LINK_CAPABILITY_CLK_POWER_MGMT (1UL<<9) 2617 #define PCI1_LINK_CAPABILITY_ASPM_SUPPORT (0x3UL<<10) 2618 #define PCI1_LINK_CAPABILITY_L0S_EXIT_LAT (0x7UL<<12) 2619 #define PCI1_LINK_CAPABILITY_L0S_EXIT_LAT_101 (5UL<<12) 2620 #define PCI1_LINK_CAPABILITY_L0S_EXIT_LAT_110 (6UL<<12) 2621 #define PCI1_LINK_CAPABILITY_L1_EXIT_LAT (0x7UL<<15) 2622 #define PCI1_LINK_CAPABILITY_L1_EXIT_LAT_001 (1UL<<15) 2623 #define PCI1_LINK_CAPABILITY_L1_EXIT_LAT_010 (2UL<<15) 2624 #define PCI1_LINK_CAPABILITY_L0S_EXIT_COMM_LAT (0x7UL<<18) 2625 #define PCI1_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_101 (5UL<<18) 2626 #define PCI1_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_110 (6UL<<18) 2627 #define PCI1_LINK_CAPABILITY_L1_EXIT_COMM_LAT (0x7UL<<21) 2628 #define PCI1_LINK_CAPABILITY_L1_EXIT_COMM_LAT_001 (1UL<<21) 2629 #define PCI1_LINK_CAPABILITY_L1_EXIT_COMM_LAT_010 (2UL<<21) 2630 #define PCI1_LINK_CAPABILITY_PORT_NUM (0xffUL<<24) 2631 2632 u32_t pci1_bar2_config; 2633 #define PCI1_BAR2_CONFIG_BAR2_SIZE (0xfUL<<0) 2634 #define PCI1_BAR2_CONFIG_BAR2_SIZE_DISABLED (0UL<<0) 2635 #define PCI1_BAR2_CONFIG_BAR2_SIZE_64K (1UL<<0) 2636 #define PCI1_BAR2_CONFIG_BAR2_SIZE_128K (2UL<<0) 2637 #define PCI1_BAR2_CONFIG_BAR2_SIZE_256K (3UL<<0) 2638 #define PCI1_BAR2_CONFIG_BAR2_SIZE_512K (4UL<<0) 2639 #define PCI1_BAR2_CONFIG_BAR2_SIZE_1M (5UL<<0) 2640 #define PCI1_BAR2_CONFIG_BAR2_SIZE_2M (6UL<<0) 2641 #define PCI1_BAR2_CONFIG_BAR2_SIZE_4M (7UL<<0) 2642 #define PCI1_BAR2_CONFIG_BAR2_SIZE_8M (8UL<<0) 2643 #define PCI1_BAR2_CONFIG_BAR2_SIZE_16M (9UL<<0) 2644 #define PCI1_BAR2_CONFIG_BAR2_SIZE_32M (10UL<<0) 2645 #define PCI1_BAR2_CONFIG_BAR2_SIZE_64M (11UL<<0) 2646 #define PCI1_BAR2_CONFIG_BAR2_SIZE_128M (12UL<<0) 2647 #define PCI1_BAR2_CONFIG_BAR2_SIZE_256M (13UL<<0) 2648 #define PCI1_BAR2_CONFIG_BAR2_SIZE_512M (14UL<<0) 2649 #define PCI1_BAR2_CONFIG_BAR2_SIZE_1G (15UL<<0) 2650 #define PCI1_BAR2_CONFIG_BAR2_64ENA (1UL<<4) 2651 #define PCI1_BAR2_CONFIG_BAR2_PREFETCH (1UL<<5) 2652 #define PCI1_BAR2_CONFIG_RESERVED (0x3ffffffUL<<6) 2653 2654 u32_t pci1_pcie_device_capability_2; 2655 #define PCI1_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP (0xfUL<<0) 2656 #define PCI1_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP (1UL<<4) 2657 #define PCI1_PCIE_DEVICE_CAPABILITY_2_RESERVED (0x7ffffffUL<<5) 2658 2659 u32_t pci1_pcie_link_capability_2; 2660 #define PCI1_PCIE_LINK_CAPABILITY_2_RESERVED (0xffffffffUL<<0) 2661 2662 u32_t unused_20[5]; 2663 u32_t pci1_dev_ser_num_cap_id; 2664 #define PCI1_DEV_SER_NUM_CAP_ID_CAP_ID (0xffffUL<<0) 2665 #define PCI1_DEV_SER_NUM_CAP_ID_CAP_VER (0xfUL<<16) 2666 #define PCI1_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA (0xfUL<<20) 2667 #define PCI1_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_8 (8UL<<20) 2668 #define PCI1_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_9 (9UL<<20) 2669 #define PCI1_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_10 (10UL<<20) 2670 #define PCI1_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_11 (11UL<<20) 2671 #define PCI1_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_12 (12UL<<20) 2672 #define PCI1_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_13 (13UL<<20) 2673 #define PCI1_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_14 (14UL<<20) 2674 #define PCI1_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_15 (15UL<<20) 2675 2676 u32_t pci1_lower_ser_num; 2677 #define PCI1_LOWER_SER_NUM_LOWER_SER_NUM (0xffffffffUL<<0) 2678 2679 u32_t pci1_upper_ser_num; 2680 #define PCI1_UPPER_SER_NUM_UPPER_SER_NUM (0xffffffffUL<<0) 2681 2682 u32_t pci1_adv_err_cap; 2683 #define PCI1_ADV_ERR_CAP_ECRC_CHK_CAP (1UL<<0) 2684 #define PCI1_ADV_ERR_CAP_ECRC_GEN_CAP (1UL<<1) 2685 2686 u32_t pci1_pwr_bdgt_data_0; 2687 #define PCI1_PWR_BDGT_DATA_0_PWR_BDGT_DATA_0 (0x1fffffUL<<0) 2688 #define PCI1_PWR_BDGT_DATA_0_RESERVED (0x7ffUL<<21) 2689 2690 u32_t pci1_pwr_bdgt_data_1; 2691 #define PCI1_PWR_BDGT_DATA_1_PWR_BDGT_DATA_1 (0x1fffffUL<<0) 2692 #define PCI1_PWR_BDGT_DATA_1_RW (0x7ffUL<<21) 2693 2694 u32_t pci1_pwr_bdgt_data_2; 2695 #define PCI1_PWR_BDGT_DATA_2_PWR_BDGT_DATA_2 (0x1fffffUL<<0) 2696 #define PCI1_PWR_BDGT_DATA_2_RW (0x7ffUL<<21) 2697 2698 u32_t pci1_pwd_bdgt_data_3; 2699 #define PCI1_PWD_BDGT_DATA_3_PWR_BDGT_DATA_3 (0x1fffffUL<<0) 2700 #define PCI1_PWD_BDGT_DATA_3_RW (0x7ffUL<<21) 2701 2702 u32_t pci1_pwr_bdgt_data_4; 2703 #define PCI1_PWR_BDGT_DATA_4_PWR_BDGT_DATA_4 (0x1fffffUL<<0) 2704 #define PCI1_PWR_BDGT_DATA_4_RW (0x7ffUL<<21) 2705 2706 u32_t pci1_pwr_bdgt_data_5; 2707 #define PCI1_PWR_BDGT_DATA_5_PWR_BDGT_DATA_5 (0x1fffffUL<<0) 2708 #define PCI1_PWR_BDGT_DATA_5_RW (0x7ffUL<<21) 2709 2710 u32_t pci1_pwr_bdgt_data_6; 2711 #define PCI1_PWR_BDGT_DATA_6_PWR_BDGT_DATA_6 (0x1fffffUL<<0) 2712 #define PCI1_PWR_BDGT_DATA_6_RW (0x7ffUL<<21) 2713 2714 u32_t pci1_pwr_bdgt_data_7; 2715 #define PCI1_PWR_BDGT_DATA_7_PWR_BDGT_DATA_7 (0x1fffffUL<<0) 2716 #define PCI1_PWR_BDGT_DATA_7_RW (0x7ffUL<<21) 2717 2718 u32_t unused_21[8]; 2719 u32_t pci1_pwr_bdgt_capability_ctl; 2720 #define PCI1_PWR_BDGT_CAPABILITY_CTL_PWR_SYSTEM_ALLOC (1UL<<0) 2721 #define PCI1_PWR_BDGT_CAPABILITY_CTL_RESERVED (0x7fffffffUL<<1) 2722 2723 u32_t unused_22[47]; 2724 u32_t pci1_grc_window1_addr; 2725 #define PCI1_GRC_WINDOW1_ADDR_VALUE (0x1ffUL<<13) 2726 2727 u32_t pci1_grc_window2_addr; 2728 #define PCI1_GRC_WINDOW2_ADDR_VALUE (0x1ffUL<<13) 2729 2730 u32_t pci1_grc_window3_addr; 2731 #define PCI1_GRC_WINDOW3_ADDR_VALUE (0x1ffUL<<13) 2732 2733 u32_t unused_23[9]; 2734 u32_t pci1_exp_rom_adr; 2735 #define PCI1_EXP_ROM_ADR_ADDRESS (0x3fffffUL<<2) 2736 #define PCI1_EXP_ROM_ADR_ADDR_SIZE (0x3UL<<24) 2737 #define PCI1_EXP_ROM_ADR_REQ (1UL<<31) 2738 2739 u32_t pci1_exp_rom_data0; 2740 u32_t pci1_exp_rom_data1; 2741 u32_t pci1_exp_rom_data2; 2742 u32_t pci1_exp_rom_ctrl; 2743 #define PCI1_EXP_ROM_CTRL_ENA (1UL<<0) 2744 #define PCI1_EXP_ROM_CTRL_BFRD (1UL<<1) 2745 #define PCI1_EXP_ROM_CTRL_ARB_NUM (0x3UL<<4) 2746 #define PCI1_EXP_ROM_CTRL_STATE (0xfUL<<16) 2747 #define PCI1_EXP_ROM_CTRL_CACHE_VALID (1UL<<28) 2748 #define PCI1_EXP_ROM_CTRL_ARB_TIMEOUT (1UL<<29) 2749 #define PCI1_EXP_ROM_CTRL_READ_TIMEOUT (1UL<<30) 2750 #define PCI1_EXP_ROM_CTRL_ACTIVE (1UL<<31) 2751 2752 u32_t pci1_exp_rom_baddr; 2753 #define PCI1_EXP_ROM_BADDR_VALUE (0x3fffffUL<<2) 2754 2755 u32_t pci1_exp_rom_cfg; 2756 #define PCI1_EXP_ROM_CFG_ARB_TIMEOUT_SHFT (0xfUL<<0) 2757 #define PCI1_EXP_ROM_CFG_READ_TIMEOUT_SHFT (0xfUL<<4) 2758 2759 u32_t unused_24[41]; 2760 u32_t pci1_debug_vect_peek; 2761 #define PCI1_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) 2762 #define PCI1_DEBUG_VECT_PEEK_1_EN (1UL<<11) 2763 #define PCI1_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) 2764 #define PCI1_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) 2765 #define PCI1_DEBUG_VECT_PEEK_2_EN (1UL<<27) 2766 #define PCI1_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) 2767 2768 u32_t unused_25[63]; 2769 u32_t pci1_tl_control_0; 2770 #define PCI1_TL_CONTROL_0_PM_TL_IGNORE_REQS (1UL<<0) 2771 #define PCI1_TL_CONTROL_0_TIMEOUT (0x3fUL<<1) 2772 #define PCI1_TL_CONTROL_0_FUNC0_HIDDEN (1UL<<16) 2773 #define PCI1_TL_CONTROL_0_FUNC1_HIDDEN (1UL<<17) 2774 #define PCI1_TL_CONTROL_0_BEACON_MULTI_LN_EN (1UL<<19) 2775 #define PCI1_TL_CONTROL_0_BEACON_DIS (1UL<<20) 2776 #define PCI1_TL_CONTROL_0_WAKE_L0_L1_EN (1UL<<21) 2777 #define PCI1_TL_CONTROL_0_OOB_EN (1UL<<22) 2778 #define PCI1_TL_CONTROL_0_RST_IGNORE_DLPDOWN (1UL<<23) 2779 #define PCI1_TL_CONTROL_0_DISABL_L1_REENTRY (1UL<<24) 2780 #define PCI1_TL_CONTROL_0_TX_MARGIN_SEL (1UL<<25) 2781 #define PCI1_TL_CONTROL_0_TX_MARGIN_SEL_0 (0UL<<25) 2782 #define PCI1_TL_CONTROL_0_TX_MARGIN_SEL_1 (1UL<<25) 2783 2784 u32_t pci1_tl_control_1; 2785 #define PCI1_TL_CONTROL_1_EN_4G_CHK (1UL<<0) 2786 #define PCI1_TL_CONTROL_1_EN_4K_CHK (1UL<<1) 2787 #define PCI1_TL_CONTROL_1_EN_BC_CHK (1UL<<2) 2788 #define PCI1_TL_CONTROL_1_EN_BE_CHK (1UL<<3) 2789 #define PCI1_TL_CONTROL_1_EN_EP_CHK (1UL<<4) 2790 #define PCI1_TL_CONTROL_1_EN_MPS_CHECK (1UL<<5) 2791 #define PCI1_TL_CONTROL_1_EN_RCB_CHK (1UL<<6) 2792 #define PCI1_TL_CONTROL_1_EN_RTE_CHK (1UL<<7) 2793 #define PCI1_TL_CONTROL_1_EN_TAC_CHK (1UL<<8) 2794 #define PCI1_TL_CONTROL_1_EN_FC_CHK (1UL<<9) 2795 #define PCI1_TL_CONTROL_1_EN_TO_CHK (1UL<<10) 2796 #define PCI1_TL_CONTROL_1_RESERVED (0x1fffffUL<<11) 2797 2798 u32_t pci1_tl_control_2; 2799 #define PCI1_TL_CONTROL_2_PES0 (1UL<<0) 2800 #define PCI1_TL_CONTROL_2_FCPES0 (1UL<<1) 2801 #define PCI1_TL_CONTROL_2_CTS0 (1UL<<2) 2802 #define PCI1_TL_CONTROL_2_CAS0 (1UL<<3) 2803 #define PCI1_TL_CONTROL_2_UCS0 (1UL<<4) 2804 #define PCI1_TL_CONTROL_2_ROS0 (1UL<<5) 2805 #define PCI1_TL_CONTROL_2_MTLPS0 (1UL<<6) 2806 #define PCI1_TL_CONTROL_2_ECRCS0 (1UL<<7) 2807 #define PCI1_TL_CONTROL_2_URES0 (1UL<<8) 2808 #define PCI1_TL_CONTROL_2_RXTABRT0 (1UL<<9) 2809 #define PCI1_TL_CONTROL_2_PES1 (1UL<<10) 2810 #define PCI1_TL_CONTROL_2_FCPES1 (1UL<<11) 2811 #define PCI1_TL_CONTROL_2_CTS1 (1UL<<12) 2812 #define PCI1_TL_CONTROL_2_CAS1 (1UL<<13) 2813 #define PCI1_TL_CONTROL_2_UCS1 (1UL<<14) 2814 #define PCI1_TL_CONTROL_2_ROS1 (1UL<<15) 2815 #define PCI1_TL_CONTROL_2_MTLPS1 (1UL<<16) 2816 #define PCI1_TL_CONTROL_2_ECRCS1 (1UL<<17) 2817 #define PCI1_TL_CONTROL_2_URES1 (1UL<<18) 2818 #define PCI1_TL_CONTROL_2_RXTABRT1 (1UL<<19) 2819 #define PCI1_TL_CONTROL_2_DLPES (1UL<<20) 2820 #define PCI1_TL_CONTROL_2_PHYES (1UL<<21) 2821 2822 u32_t pci1_tl_control_3; 2823 #define PCI1_TL_CONTROL_3_EN_CMPL_RETRY (1UL<<0) 2824 #define PCI1_TL_CONTROL_3_EN_PSND_RETRY (1UL<<1) 2825 #define PCI1_TL_CONTROL_3_EN_HOLD_PHCRDT (1UL<<2) 2826 #define PCI1_TL_CONTROL_3_MAX_INTER_L1_GAP (0xffffUL<<16) 2827 2828 u32_t pci1_tl_control_4; 2829 #define PCI1_TL_CONTROL_4_RESERVED2 (0xffffUL<<0) 2830 #define PCI1_TL_CONTROL_4_RESERVED1 (0xffffUL<<16) 2831 2832 u32_t pci1_tl_control_5; 2833 #define PCI1_TL_CONTROL_5_PES0 (1UL<<0) 2834 #define PCI1_TL_CONTROL_5_FCPES0 (1UL<<1) 2835 #define PCI1_TL_CONTROL_5_CTS0 (1UL<<2) 2836 #define PCI1_TL_CONTROL_5_CAS0 (1UL<<3) 2837 #define PCI1_TL_CONTROL_5_UCS0 (1UL<<4) 2838 #define PCI1_TL_CONTROL_5_ROS0 (1UL<<5) 2839 #define PCI1_TL_CONTROL_5_MTLPS0 (1UL<<6) 2840 #define PCI1_TL_CONTROL_5_ECRCS0 (1UL<<7) 2841 #define PCI1_TL_CONTROL_5_URES0 (1UL<<8) 2842 #define PCI1_TL_CONTROL_5_RXTABRT0 (1UL<<9) 2843 #define PCI1_TL_CONTROL_5_PES1 (1UL<<10) 2844 #define PCI1_TL_CONTROL_5_FCPES1 (1UL<<11) 2845 #define PCI1_TL_CONTROL_5_CTS1 (1UL<<12) 2846 #define PCI1_TL_CONTROL_5_CAS1 (1UL<<13) 2847 #define PCI1_TL_CONTROL_5_UCS1 (1UL<<14) 2848 #define PCI1_TL_CONTROL_5_ROS1 (1UL<<15) 2849 #define PCI1_TL_CONTROL_5_MTLPS1 (1UL<<16) 2850 #define PCI1_TL_CONTROL_5_ECRCS1 (1UL<<17) 2851 #define PCI1_TL_CONTROL_5_URES1 (1UL<<18) 2852 #define PCI1_TL_CONTROL_5_RXTABRT1 (1UL<<19) 2853 #define PCI1_TL_CONTROL_5_DLPES (1UL<<20) 2854 #define PCI1_TL_CONTROL_5_PHYES (1UL<<21) 2855 2856 u32_t unused_26[23]; 2857 u32_t pci1_TL_CTLSTAT_0; 2858 #define PCI1_TL_CTLSTAT_0_PCIE_FUNC_1_HIDDEN (1UL<<0) 2859 #define PCI1_TL_CTLSTAT_0_RESERVED (0x7fffffffUL<<1) 2860 2861 u32_t pci1_pm_status_0; 2862 #define PCI1_PM_STATUS_0_PME_SENT_SM0 (0x1fUL<<0) 2863 #define PCI1_PM_STATUS_0_PME_SENT_SM1 (0x1fUL<<8) 2864 #define PCI1_PM_STATUS_0_PM_LINK_STATE_SM (0x7fUL<<25) 2865 2866 u32_t pci1_pm_status_1; 2867 #define PCI1_PM_STATUS_1_CFG_PME_ENABLE0B (1UL<<0) 2868 #define PCI1_PM_STATUS_1_CFG_PME_STATUS0 (1UL<<1) 2869 #define PCI1_PM_STATUS_1_CFG_AUX_PWR_PM_EN0 (1UL<<2) 2870 #define PCI1_PM_STATUS_1_CFG_PME_ENABLE1 (1UL<<3) 2871 #define PCI1_PM_STATUS_1_CFG_PME_STATUS1 (1UL<<4) 2872 #define PCI1_PM_STATUS_1_CFG_AUX_PWR_PM_EN1 (1UL<<5) 2873 2874 u32_t unused_27[32]; 2875 u32_t pci1_tl_status_0; 2876 #define PCI1_TL_STATUS_0_DEVICE_NO (0xfUL<<0) 2877 #define PCI1_TL_STATUS_0_FUNC_NO (0x7UL<<4) 2878 #define PCI1_TL_STATUS_0_TC (0x7UL<<7) 2879 #define PCI1_TL_STATUS_0_ATTR (0x3UL<<10) 2880 #define PCI1_TL_STATUS_0_BYTE_COUNT (0x1fffUL<<12) 2881 #define PCI1_TL_STATUS_0_LWR_ADDR (0x7fUL<<25) 2882 2883 u32_t pci1_tl_status_1; 2884 u32_t pci1_tl_status_2; 2885 u32_t pci1_tl_status_3; 2886 u32_t pci1_tl_status_4; 2887 u32_t pci1_tl_status_5; 2888 u32_t pci1_tl_status_6; 2889 u32_t pci1_tl_status_7; 2890 u32_t pci1_tl_status_8; 2891 u32_t pci1_tl_status_9; 2892 u32_t pci1_tl_status_10; 2893 u32_t pci1_tl_status_11; 2894 u32_t pci1_tl_status_12; 2895 u32_t pci1_tl_status_13; 2896 u32_t pci1_tl_status_14; 2897 u32_t pci1_tl_status_15; 2898 u32_t pci1_tl_status_16; 2899 u32_t pci1_tl_status_17; 2900 u32_t pci1_tl_status_18; 2901 u32_t pci1_tl_status_19; 2902 u32_t pci1_tl_status_20; 2903 u32_t pci1_tl_status_21; 2904 u32_t pci1_tl_status_22; 2905 u32_t pci1_tl_status_23; 2906 u32_t pci1_tl_status_24; 2907 u32_t pci1_tl_status_25; 2908 u32_t pci1_tl_status_26; 2909 u32_t pci1_tl_status_27; 2910 u32_t pci1_tl_status_28; 2911 u32_t pci1_tl_status_29; 2912 u32_t pci1_tl_status_30; 2913 u32_t pci1_tl_status_31; 2914 u32_t pci1_tl_hdr_fc_st; 2915 #define PCI1_TL_HDR_FC_ST_NPH_AVAIL (0xffUL<<0) 2916 #define PCI1_TL_HDR_FC_ST_PH_AVAIL (0xffUL<<8) 2917 #define PCI1_TL_HDR_FC_ST_CPLH_AVAIL (0xffUL<<16) 2918 2919 u32_t pci1_tl_dat_fc_st; 2920 #define PCI1_TL_DAT_FC_ST_PD_AVAIL (0xfffUL<<0) 2921 #define PCI1_TL_DAT_FC_ST_CPLD_AVAIL (0xfffUL<<16) 2922 2923 u32_t pci1_tl_hdr_fccon_st; 2924 #define PCI1_TL_HDR_FCCON_ST_NPH_CC (0xffUL<<0) 2925 #define PCI1_TL_HDR_FCCON_ST_PH_CC (0xffUL<<8) 2926 #define PCI1_TL_HDR_FCCON_ST_CPLH_CC (0xffUL<<16) 2927 2928 u32_t pci1_tl_dat_fccon_st; 2929 #define PCI1_TL_DAT_FCCON_ST_PD_CC (0xfffUL<<0) 2930 #define PCI1_TL_DAT_FCCON_ST_CPLD_CC (0xfffUL<<16) 2931 2932 u32_t pci1_tl_tgt_crdt_st; 2933 #define PCI1_TL_TGT_CRDT_ST_PH_CRDT_CNTR (0x7fUL<<0) 2934 #define PCI1_TL_TGT_CRDT_ST_PD_CRDT_CNTR (0x7fUL<<8) 2935 #define PCI1_TL_TGT_CRDT_ST_NP_CRDT_CNTR (1UL<<16) 2936 2937 u32_t pci1_tl_crdt_alloc_st; 2938 #define PCI1_TL_CRDT_ALLOC_ST_NPH_ALLOC (0xffUL<<0) 2939 #define PCI1_TL_CRDT_ALLOC_ST_NPD_ALLOC (0xffUL<<8) 2940 #define PCI1_TL_CRDT_ALLOC_ST_PH_ALLOC (0xffUL<<16) 2941 #define PCI1_TL_CRDT_ALLOC_ST_PD_ALLOC (0xffUL<<24) 2942 2943 u32_t pci1_tl_smlogic_st; 2944 #define PCI1_TL_SMLOGIC_ST_NP_CURR_STATE (0xfUL<<0) 2945 #define PCI1_TL_SMLOGIC_ST_PH_CURR_STATE (0xfUL<<4) 2946 #define PCI1_TL_SMLOGIC_ST_CPL_CURR_STATE (0x3UL<<8) 2947 #define PCI1_TL_SMLOGIC_ST_TX_SM (0x7UL<<16) 2948 2949 u32_t unused_28[409]; 2950 u32_t pci1_pdl_control_0; 2951 #define PCI1_PDL_CONTROL_0_ENABLE_SCRAMB (1UL<<0) 2952 #define PCI1_PDL_CONTROL_0_DISABLE_REVERSE (1UL<<1) 2953 #define PCI1_PDL_CONTROL_0_DISABLE_REPLAY_TIMER (1UL<<2) 2954 #define PCI1_PDL_CONTROL_0_DISABLE_FRAM_CHECK (1UL<<3) 2955 #define PCI1_PDL_CONTROL_0_DISABLE_CRC_DLL (1UL<<4) 2956 #define PCI1_PDL_CONTROL_0_DISABLE_CRC_DLP (1UL<<5) 2957 #define PCI1_PDL_CONTROL_0_DISABLE_REPLAY_BUFF (1UL<<6) 2958 #define PCI1_PDL_CONTROL_0_DISABLE_SKEW_RET (1UL<<7) 2959 #define PCI1_PDL_CONTROL_0_ENABLE_COMPLIANCE (1UL<<8) 2960 #define PCI1_PDL_CONTROL_0_DISABLE_8B10_BYPAS (1UL<<9) 2961 #define PCI1_PDL_CONTROL_0_DISABLE_LOST_SYNCH (1UL<<10) 2962 #define PCI1_PDL_CONTROL_0_DISABLE_AUTO_CRDUPD (1UL<<11) 2963 #define PCI1_PDL_CONTROL_0_DISABLE_RETRAIN_REQ (1UL<<12) 2964 #define PCI1_PDL_CONTROL_0_FORCE_L0TOL1 (1UL<<13) 2965 #define PCI1_PDL_CONTROL_0_RESERVED (1UL<<14) 2966 #define PCI1_PDL_CONTROL_0_DISABLE_REV_LANE (1UL<<15) 2967 #define PCI1_PDL_CONTROL_0_ENABLE_TX_ERR_MUX (1UL<<16) 2968 #define PCI1_PDL_CONTROL_0_ENABLE_RX_ERR_MUX (1UL<<17) 2969 #define PCI1_PDL_CONTROL_0_ENABLE_ERR_FRAMING (1UL<<18) 2970 #define PCI1_PDL_CONTROL_0_ENABLE_SINGLE_ERR (1UL<<19) 2971 #define PCI1_PDL_CONTROL_0_ENCOMFORSIG (1UL<<20) 2972 #define PCI1_PDL_CONTROL_0_DISABLE_TLPRDNXT (1UL<<21) 2973 #define PCI1_PDL_CONTROL_0_DISABLE_GENE_TIMER (1UL<<22) 2974 #define PCI1_PDL_CONTROL_0_DISABLETXDETECT (1UL<<23) 2975 #define PCI1_PDL_CONTROL_0_LOOPBACK_CNTL_REG (0x7UL<<24) 2976 #define PCI1_PDL_CONTROL_0_FORCE_L0TOL2 (1UL<<27) 2977 #define PCI1_PDL_CONTROL_0_DISABLE_HOT_SERDES (1UL<<28) 2978 #define PCI1_PDL_CONTROL_0_DISSKEWCHECK (1UL<<29) 2979 #define PCI1_PDL_CONTROL_0_DISABLERXSKIP (1UL<<30) 2980 #define PCI1_PDL_CONTROL_0_FORCE_RECTOCONF (1UL<<31) 2981 2982 u32_t pci1_pdl_control_1; 2983 #define PCI1_PDL_CONTROL_1_MAX_DLP_IDLE_CNT (0x7fUL<<0) 2984 #define PCI1_PDL_CONTROL_1_DISABLE_CC_DESKEW (1UL<<8) 2985 #define PCI1_PDL_CONTROL_1_DISABLE_DLPTX_BB (1UL<<10) 2986 #define PCI1_PDL_CONTROL_1_FORCE_L0TOL0S (1UL<<11) 2987 #define PCI1_PDL_CONTROL_1_MAX_REPLAY_NUM (0x3UL<<12) 2988 #define PCI1_PDL_CONTROL_1_RETRAIN_REQ (1UL<<14) 2989 #define PCI1_PDL_CONTROL_1_PHYRX_DETECT_ERROR_DIS (1UL<<15) 2990 #define PCI1_PDL_CONTROL_1_MAX_DLP_L1_ENTRANCE (0x7fUL<<16) 2991 #define PCI1_PDL_CONTROL_1_REPLAY_INTDEL_GEN2 (0x1ffUL<<23) 2992 2993 u32_t pci1_pdl_control_2; 2994 #define PCI1_PDL_CONTROL_2_MAX_SYMB_SKIP_OS (0x7UL<<0) 2995 #define PCI1_PDL_CONTROL_2_ENABLE_ACK_LAT_TIMER (1UL<<3) 2996 #define PCI1_PDL_CONTROL_2_SW_ACK_LAT_SEL (1UL<<4) 2997 #define PCI1_PDL_CONTROL_2_SW_REPLAY_TIMER_SEL (1UL<<5) 2998 #define PCI1_PDL_CONTROL_2_SELDETECT_DELAY (0x3UL<<6) 2999 #define PCI1_PDL_CONTROL_2_MAX_WAIT_RX_L0S_ENTRY (0xfUL<<8) 3000 #define PCI1_PDL_CONTROL_2_MAX_WAIT_TX_L0S_ENTRY (0xfUL<<12) 3001 #define PCI1_PDL_CONTROL_2_ENABLE_CRD_LAT_P (1UL<<16) 3002 #define PCI1_PDL_CONTROL_2_ENABLE_CRD_LAT_N (1UL<<17) 3003 #define PCI1_PDL_CONTROL_2_CORR_ERR_REG_MAX (0x3ffUL<<18) 3004 #define PCI1_PDL_CONTROL_2_DISABLE_DESKEW_ERR (1UL<<28) 3005 #define PCI1_PDL_CONTROL_2_ENABLE_SKIP_RST_ERR (1UL<<29) 3006 #define PCI1_PDL_CONTROL_2_DISABLE_FASTACQ (1UL<<30) 3007 #define PCI1_PDL_CONTROL_2_DISABLE_RX_ELEC (1UL<<31) 3008 3009 u32_t pci1_pdl_control_3; 3010 #define PCI1_PDL_CONTROL_3_MAX_TX_FTS_LIMIT (0xffUL<<0) 3011 #define PCI1_PDL_CONTROL_3_MAX_TX_FTS_LIMIT_LONG (0xffUL<<8) 3012 #define PCI1_PDL_CONTROL_3_MAX_TX_FTS_LIMIT_GEN2 (0xffUL<<16) 3013 #define PCI1_PDL_CONTROL_3_MAX_TX_FTS_LIMIT_LONG_GEN2 (0xffUL<<24) 3014 3015 u32_t pci1_pdl_control_4; 3016 #define PCI1_PDL_CONTROL_4_NPD_FC_INIT (0xfffUL<<0) 3017 #define PCI1_PDL_CONTROL_4_PD_FC_INIT (0xfffUL<<12) 3018 #define PCI1_PDL_CONTROL_4_NPH_FC_INIT (0xffUL<<24) 3019 3020 u32_t pci1_pdl_control_5; 3021 #define PCI1_PDL_CONTROL_5_PH_FC_INIT (0xffUL<<0) 3022 #define PCI1_PDL_CONTROL_5_LINK_UPSTREAM (1UL<<8) 3023 #define PCI1_PDL_CONTROL_5_GLOOPBACK (1UL<<9) 3024 #define PCI1_PDL_CONTROL_5_RESERVED (0x3fUL<<10) 3025 #define PCI1_PDL_CONTROL_5_LOOPBACK_REG (0xffffUL<<16) 3026 3027 u32_t pci1_pdl_control_6; 3028 #define PCI1_PDL_CONTROL_6_LOOPBACK_REG (0xffffffffUL<<0) 3029 3030 u32_t pci1_pdl_control_7; 3031 #define PCI1_PDL_CONTROL_7_LOOPBACK_REG (0xffffffffUL<<0) 3032 3033 u32_t pci1_pdl_control_8; 3034 #define PCI1_PDL_CONTROL_8_LOOPBACK_REG (0xffffffffUL<<0) 3035 3036 u32_t pci1_pdl_control_9; 3037 #define PCI1_PDL_CONTROL_9_LOOPBACK_REG (0xffffffffUL<<0) 3038 3039 u32_t pci1_pdl_control_10; 3040 #define PCI1_PDL_CONTROL_10_DL_HI_WATERMARK (0x1fUL<<0) 3041 #define PCI1_PDL_CONTROL_10_DL_CS_RXENABLE (1UL<<8) 3042 #define PCI1_PDL_CONTROL_10_DL_CS_ENABLE (1UL<<9) 3043 #define PCI1_PDL_CONTROL_10_DL_CS_WRITE_NULLIFY (1UL<<10) 3044 #define PCI1_PDL_CONTROL_10_DL_CS_NULLIFY (1UL<<11) 3045 3046 u32_t pci1_pdl_control_11; 3047 #define PCI1_PDL_CONTROL_11_REPLAY_TIMER_LIMIT_GEN1 (0xfffUL<<0) 3048 #define PCI1_PDL_CONTROL_11_REPLAY_TIMER_LIMIT_GEN2 (0xfffUL<<12) 3049 #define PCI1_PDL_CONTROL_11_RESERVED (0xffUL<<24) 3050 3051 u32_t pci1_pdl_control_12; 3052 #define PCI1_PDL_CONTROL_12_UPDATE_FREQ_GEN1 (0xffUL<<0) 3053 #define PCI1_PDL_CONTROL_12_UPDATE_FREQ_GEN2 (0xffUL<<8) 3054 #define PCI1_PDL_CONTROL_12_RESERVED (0xffffUL<<16) 3055 3056 u32_t pci1_pdl_control_13; 3057 #define PCI1_PDL_CONTROL_13_ACK_LATENCY_TIMER_GEN1 (0x3ffUL<<0) 3058 #define PCI1_PDL_CONTROL_13_ACK_LATENCY_TIMER_GEN2 (0x3ffUL<<10) 3059 #define PCI1_PDL_CONTROL_13_ACK_INTDEL_GEN2 (0xffUL<<20) 3060 #define PCI1_PDL_CONTROL_13_RESERVED (0xfUL<<28) 3061 3062 u32_t pci1_pdl_control_14; 3063 #define PCI1_PDL_CONTROL_14_DEBUG_EXT_SEL_0 (0x1fffUL<<0) 3064 #define PCI1_PDL_CONTROL_14_DEBUG_EXT_SEL_1 (0x1fffUL<<13) 3065 #define PCI1_PDL_CONTROL_14_DEBUG_GRC_SEL_0 (0x3UL<<27) 3066 #define PCI1_PDL_CONTROL_14_DEBUG_GRC_SEL_0_00 (0UL<<27) 3067 #define PCI1_PDL_CONTROL_14_DEBUG_GRC_SEL_0_01 (1UL<<27) 3068 #define PCI1_PDL_CONTROL_14_DEBUG_GRC_SEL_0_10 (2UL<<27) 3069 #define PCI1_PDL_CONTROL_14_DEBUG_GRC_SEL_0_11 (2UL<<27) 3070 #define PCI1_PDL_CONTROL_14_DEBUG_GRC_SEL_1 (0x3UL<<29) 3071 #define PCI1_PDL_CONTROL_14_DEBUG_GRC_SEL_1_00 (0UL<<29) 3072 #define PCI1_PDL_CONTROL_14_DEBUG_GRC_SEL_1_01 (1UL<<29) 3073 #define PCI1_PDL_CONTROL_14_DEBUG_GRC_SEL_1_10 (2UL<<29) 3074 #define PCI1_PDL_CONTROL_14_DEBUG_GRC_SEL_1_11 (2UL<<29) 3075 #define PCI1_PDL_CONTROL_14_DEBUG_GRC_ENA (1UL<<31) 3076 3077 u32_t pci1_pdl_control_15; 3078 #define PCI1_PDL_CONTROL_15_FORCE_UPDATE_GEN2 (0x7fffUL<<0) 3079 #define PCI1_PDL_CONTROL_15_FORCE_UPDATE_EXTENDED_SYNC_GEN2 (0x7fffUL<<15) 3080 3081 u32_t pci1_DL_ATTN_VECTOR; 3082 #define PCI1_DL_ATTN_VECTOR_DL_CKSUM_ERR_AT (1UL<<0) 3083 #define PCI1_DL_ATTN_VECTOR_DL_D2TBUF_OFLOW_ERR (1UL<<1) 3084 #define PCI1_DL_ATTN_VECTOR_DLP2TLP_PARITY_ERROR (1UL<<2) 3085 #define PCI1_DL_ATTN_VECTOR_REPLAY_ADDRESS_PARITY_ERROR (1UL<<3) 3086 #define PCI1_DL_ATTN_VECTOR_REPLAY_WRAPPER_PARITY_ERROR (1UL<<4) 3087 #define PCI1_DL_ATTN_VECTOR_DL_CORRECTABLE_ERROR (1UL<<5) 3088 #define PCI1_DL_ATTN_VECTOR_DE_FRAMING_ERROR (1UL<<6) 3089 #define PCI1_DL_ATTN_VECTOR_DLP_ERROR_STATUS (1UL<<7) 3090 #define PCI1_DL_ATTN_VECTOR_DLP_INCORRECT (1UL<<8) 3091 #define PCI1_DL_ATTN_VECTOR_TLPBUFRDERR (1UL<<9) 3092 #define PCI1_DL_ATTN_VECTOR_REPLAY_SEQUENCE_OVERRUN (1UL<<10) 3093 #define PCI1_DL_ATTN_VECTOR_DLL_ERROR_ACK (1UL<<11) 3094 #define PCI1_DL_ATTN_VECTOR_REPLAY_BUFFER_OVERRUN (1UL<<12) 3095 #define PCI1_DL_ATTN_VECTOR_REPLAY_NUMBER_ROLL_OVER (1UL<<13) 3096 #define PCI1_DL_ATTN_VECTOR_REPLAY_TIMEOUT (1UL<<14) 3097 #define PCI1_DL_ATTN_VECTOR_FCPE_ERROR_STATUS (1UL<<15) 3098 #define PCI1_DL_ATTN_VECTOR_DLL_ERROR_STATUS (1UL<<16) 3099 #define PCI1_DL_ATTN_VECTOR_DLL_PE_INIT_STATUS (1UL<<17) 3100 #define PCI1_DL_ATTN_VECTOR_COL_FULL (1UL<<18) 3101 #define PCI1_DL_ATTN_VECTOR_TLP_INCORRECT (1UL<<19) 3102 #define PCI1_DL_ATTN_VECTOR_TLP_SYNC_ERROR (1UL<<20) 3103 3104 u32_t pci1_DL_ATTN_MASK; 3105 #define PCI1_DL_ATTN_MASK_MASK_FOR_DL_ATTENTIONS (0x1fffffUL<<0) 3106 #define PCI1_DL_ATTN_MASK_RESERVED1 (0x7ffUL<<21) 3107 3108 u32_t pci1_DL_STATUS; 3109 #define PCI1_DL_STATUS_CORR_ERR_REG (0x3ffUL<<0) 3110 #define PCI1_DL_STATUS_REPLAY_ALM_FULL (1UL<<10) 3111 #define PCI1_DL_STATUS_PHYLINKUP (1UL<<13) 3112 #define PCI1_DL_STATUS_DL_ACTIVE (1UL<<14) 3113 #define PCI1_DL_STATUS_DL_INIT (1UL<<15) 3114 #define PCI1_DL_STATUS_RESERVED (0xffffUL<<16) 3115 3116 u32_t pci1_DL_TX_Checksum; 3117 #define PCI1_DL_TX_CHECKSUM_EXPECTED_TX_CHECKSUM (0xffffUL<<0) 3118 #define PCI1_DL_TX_CHECKSUM_ACTUAL_TX_CHECKSUM (0xffffUL<<16) 3119 3120 u32_t pci1_dl_forced_update_gen1; 3121 #define PCI1_DL_FORCED_UPDATE_GEN1_FORCE_UPDATE_GEN1 (0x7fffUL<<0) 3122 #define PCI1_DL_FORCED_UPDATE_GEN1_FORCE_UPDATE_EXTENDED_SYNC_GEN1 (0x7fffUL<<15) 3123 3124 u32_t unused_29[43]; 3125 u32_t pci1_mdio_addr; 3126 #define PCI1_MDIO_ADDR_ADR (0xffffUL<<0) 3127 #define PCI1_MDIO_ADDR_PORT (0xfUL<<16) 3128 #define PCI1_MDIO_ADDR_CMD (0xfffUL<<20) 3129 3130 u32_t pci1_mdio_wr_data; 3131 #define PCI1_MDIO_WR_DATA_DATA (0xffffUL<<0) 3132 #define PCI1_MDIO_WR_DATA_CMD (1UL<<31) 3133 3134 u32_t pci1_mdio_rd_data; 3135 #define PCI1_MDIO_RD_DATA_DATA (0xffffUL<<0) 3136 #define PCI1_MDIO_RD_DATA_CMD (1UL<<31) 3137 3138 u32_t unused_30[189]; 3139 u32_t pci1_dl_rx_pn_credit_limit; 3140 #define PCI1_DL_RX_PN_CREDIT_LIMIT_DL_RX_PN_CREDIT_LIMIT (0xffffffffUL<<0) 3141 3142 u32_t pci1_dl_rx_c_credit_limit; 3143 #define PCI1_DL_RX_C_CREDIT_LIMIT_DL_RX_C_CREDIT_LIMIT (0xffffffffUL<<0) 3144 3145 u32_t pci1_dl_rx_ack_nack; 3146 #define PCI1_DL_RX_ACK_NACK_DL_RX_ACK_NACK (0xffffffffUL<<0) 3147 3148 u32_t pci1_dl_coldat_lsb; 3149 #define PCI1_DL_COLDAT_LSB_DL_COLDAT_LSB (0xffffffffUL<<0) 3150 3151 u32_t pci1_dl_coldat_msb; 3152 #define PCI1_DL_COLDAT_MSB_DL_COLDAT_MSB (0xffffffffUL<<0) 3153 3154 u32_t pci1_dl_colcntl; 3155 #define PCI1_DL_COLCNTL_DL_COLCNTL (0xffffffffUL<<0) 3156 3157 u32_t pci1_dl_coldeb; 3158 #define PCI1_DL_COLDEB_DL_COLDEB (0xffffffffUL<<0) 3159 3160 u32_t pci1_dl_pwr_mgmt; 3161 #define PCI1_DL_PWR_MGMT_DL_PWR_MGMT (0xffffffffUL<<0) 3162 3163 u32_t pci1_dl_t2d_rxcksum; 3164 #define PCI1_DL_T2D_RXCKSUM_DL_T2D_RXCKSUM (0xffffffffUL<<0) 3165 3166 u32_t pci1_dl_resend0_dlptx0; 3167 #define PCI1_DL_RESEND0_DLPTX0_DL_RESEND0_DLPTX0 (0xffffffffUL<<0) 3168 3169 u32_t pci1_dl_resend1_dlptx1; 3170 #define PCI1_DL_RESEND1_DLPTX1_DL_RESEND1_DLPTX1 (0xffffffffUL<<0) 3171 3172 u32_t pci1_dl_resend2_dlptx2; 3173 #define PCI1_DL_RESEND2_DLPTX2_DL_RESEND2_DLPTX2 (0xffffffffUL<<0) 3174 3175 u32_t pci1_dl_resend2_dlptx3; 3176 #define PCI1_DL_RESEND2_DLPTX3_DL_RESEND2_DLPTX3 (0xffffffffUL<<0) 3177 3178 u32_t pci1_dl_phyrx0_d2trx0; 3179 #define PCI1_DL_PHYRX0_D2TRX0_DL_PHYRX0_D2TRX0 (0xffffffffUL<<0) 3180 3181 u32_t pci1_dl_phyrx1_d2trx1; 3182 #define PCI1_DL_PHYRX1_D2TRX1_DL_PHYRX1_D2TRX1 (0xffffffffUL<<0) 3183 3184 u32_t pci1_dl_phyrx2_d2trx1; 3185 #define PCI1_DL_PHYRX2_D2TRX1_DL_PHYRX2_D2TRX1 (0xffffffffUL<<0) 3186 3187 u32_t pci1_dl_coldeb_vec1; 3188 #define PCI1_DL_COLDEB_VEC1_DL_COLDEB_VEC1 (0xffffffffUL<<0) 3189 3190 u32_t pci1_dl_d2tbuf_0; 3191 #define PCI1_DL_D2TBUF_0_DL_D2TBUF_0 (0xffffffffUL<<0) 3192 3193 u32_t pci1_dl_d2trx1; 3194 #define PCI1_DL_D2TRX1_DL_D2TRX1 (0xffffffffUL<<0) 3195 3196 u32_t pci1_dl_tx_nullify; 3197 #define PCI1_DL_TX_NULLIFY_DL_TX_NULLIFY (0xffffffffUL<<0) 3198 3199 u32_t pci1_dl_datapathtx0; 3200 #define PCI1_DL_DATAPATHTX0_DL_DATAPATHTX0 (0xffffffffUL<<0) 3201 3202 u32_t pci1_dl_datapathtx1; 3203 #define PCI1_DL_DATAPATHTX1_DL_DATAPATHTX1 (0xffffffffUL<<0) 3204 3205 u32_t pci1_dl_datapathtx2; 3206 #define PCI1_DL_DATAPATHTX2_DL_DATAPATHTX2 (0xffffffffUL<<0) 3207 3208 u32_t pci1_dl_dllrx0; 3209 #define PCI1_DL_DLLRX0_DL_DLLRX0 (0xffffffffUL<<0) 3210 3211 u32_t pci1_dl_dllrx1; 3212 #define PCI1_DL_DLLRX1_DL_DLLRX1 (0xffffffffUL<<0) 3213 3214 u32_t pci1_dl_dllrx2; 3215 #define PCI1_DL_DLLRX2_DL_DLLRX2 (0xffffffffUL<<0) 3216 3217 u32_t pci1_dl_rx_tx; 3218 #define PCI1_DL_RX_TX_DL_RX_TX (0xffffffffUL<<0) 3219 3220 u32_t pci1_dbg_dl_ctrl_status0; 3221 #define PCI1_DBG_DL_CTRL_STATUS0_MAX_FORCE_UPDATE (0x7fffUL<<0) 3222 #define PCI1_DBG_DL_CTRL_STATUS0_EXTENDED_SYNC (1UL<<15) 3223 #define PCI1_DBG_DL_CTRL_STATUS0_FORCE_UPD_VAL_FOR_GEN1 (0x7fffUL<<16) 3224 #define PCI1_DBG_DL_CTRL_STATUS0_PCIE_PHY_RATE (1UL<<31) 3225 3226 u32_t pci1_dbg_dl_ctrl_status1; 3227 #define PCI1_DBG_DL_CTRL_STATUS1_MAX_FORCE_UPDATE (0x7fffUL<<0) 3228 #define PCI1_DBG_DL_CTRL_STATUS1_MAX_UPDATE_FREQUENCY (0x1ffUL<<15) 3229 #define PCI1_DBG_DL_CTRL_STATUS1_MAX_REPLAY_TIMER (0xffUL<<24) 3230 3231 u32_t pci1_dbg_dl_ctrl_status2; 3232 #define PCI1_DBG_DL_CTRL_STATUS2_DBG_MAX_REPLAY_TIMER (0x1fffUL<<0) 3233 #define PCI1_DBG_DL_CTRL_STATUS2_RX_L0S_ADJUSTMENT_R (0x3ffUL<<13) 3234 #define PCI1_DBG_DL_CTRL_STATUS2_DBG_MAX_REPLAY_TIMER_LIMIT (0x1ffUL<<23) 3235 3236 u32_t pci1_dbg_dl_ctrl_status3; 3237 #define PCI1_DBG_DL_CTRL_STATUS3_MAX_REPLAY_TIMER_LIMIT (0xfffUL<<0) 3238 #define PCI1_DBG_DL_CTRL_STATUS3_REPLAYLIMIT_WO_INTDEL (0xfffUL<<12) 3239 #define PCI1_DBG_DL_CTRL_STATUS3_REPLAY_INTDEL (0xffUL<<24) 3240 3241 u32_t unused_31[225]; 3242 u32_t pci1_phy_ctl_0; 3243 #define PCI1_PHY_CTL_0_SPEED_CHANGE_REQ (1UL<<1) 3244 #define PCI1_PHY_CTL_0_WIDTH_CHANGE_REQ (1UL<<1) 3245 #define PCI1_PHY_CTL_0_DIS_X2_LINK_WIDTH (1UL<<2) 3246 #define PCI1_PHY_CTL_0_LINK_LOOPBACK (1UL<<3) 3247 #define PCI1_PHY_CTL_0_LINK_DISABLE (1UL<<4) 3248 #define PCI1_PHY_CTL_0_IDL_TO_RLOCK_ENA (1UL<<5) 3249 #define PCI1_PHY_CTL_0_UPCONFIG_ENA (1UL<<6) 3250 #define PCI1_PHY_CTL_0_HI_AVAIL_COMPLI_EN (1UL<<7) 3251 #define PCI1_PHY_CTL_0_RESERVED (0xffffffUL<<8) 3252 3253 u32_t pci1_phy_ctl_1; 3254 #define PCI1_PHY_CTL_1_FORCE_16BIT (1UL<<0) 3255 #define PCI1_PHY_CTL_1_AUTO_TRAIN_ENA (1UL<<1) 3256 #define PCI1_PHY_CTL_1_LANE_PWRDN_ENA (1UL<<2) 3257 #define PCI1_PHY_CTL_1_P2_PWRDWN_ENA (1UL<<3) 3258 #define PCI1_PHY_CTL_1_FAREND_LPBK_REQ (1UL<<4) 3259 #define PCI1_PHY_CTL_1_DIS_SKIP_IN_SPEED (1UL<<5) 3260 #define PCI1_PHY_CTL_1_RESERVED1 (1UL<<6) 3261 #define PCI1_PHY_CTL_1_EIDL_DLY (0x1fUL<<7) 3262 #define PCI1_PHY_CTL_1_RESERVED (0xfffffUL<<12) 3263 3264 u32_t pci1_phy_ctl_2; 3265 u32_t pci1_phy_ctl_3; 3266 u32_t pci1_phy_ctl_4; 3267 #define PCI1_PHY_CTL_4_PRESCALE (0x7ffUL<<0) 3268 #define PCI1_PHY_CTL_4_RESERVED_B (0x1fUL<<11) 3269 #define PCI1_PHY_CTL_4_EIDL_RX_MAX (0x7ffUL<<16) 3270 #define PCI1_PHY_CTL_4_EIDL_RX_PRESCALE (1UL<<27) 3271 #define PCI1_PHY_CTL_4_RESERVED (0xfUL<<28) 3272 3273 u32_t pci1_phy_ctl_5; 3274 #define PCI1_PHY_CTL_5_EIDL_TX_GOOD_MAX (0x7ffUL<<0) 3275 #define PCI1_PHY_CTL_5_RESERVED_2 (0x1fUL<<11) 3276 #define PCI1_PHY_CTL_5_EIDL_TX_BAD_MAX (0x7ffUL<<16) 3277 #define PCI1_PHY_CTL_5_RESERVED (0x1fUL<<27) 3278 3279 u32_t pci1_phy_ctl_6; 3280 #define PCI1_PHY_CTL_6_EIDL_INF_COM_MAX (0x7ffUL<<0) 3281 #define PCI1_PHY_CTL_6_EIDL_INF_COM_PRESCALE (1UL<<11) 3282 #define PCI1_PHY_CTL_6_RESERVED (0x7UL<<12) 3283 #define PCI1_PHY_CTL_6_EIDL_INF_EIES_PRESCALE (1UL<<15) 3284 #define PCI1_PHY_CTL_6_EIDL_INF_EIES_MAX (0xffffUL<<16) 3285 3286 u32_t pci1_phy_ctl_7; 3287 #define PCI1_PHY_CTL_7_L1_MIN_WAIT_MAX (0x3fUL<<0) 3288 #define PCI1_PHY_CTL_7_RESERVED1 (0x3ffUL<<6) 3289 #define PCI1_PHY_CTL_7_DETECT_MIN_WAIT_MAX (0x3fffUL<<16) 3290 #define PCI1_PHY_CTL_7_RESERVED (0x3UL<<30) 3291 3292 u32_t pci1_phy_err_attn_vec; 3293 #define PCI1_PHY_ERR_ATTN_VEC_ELASTIC_ERR (1UL<<0) 3294 #define PCI1_PHY_ERR_ATTN_VEC_DISPARITY_ERR (1UL<<1) 3295 #define PCI1_PHY_ERR_ATTN_VEC_DECODE_ERR (1UL<<2) 3296 #define PCI1_PHY_ERR_ATTN_VEC_LINK_IS_SKEW (1UL<<3) 3297 #define PCI1_PHY_ERR_ATTN_VEC_TRAIN_ERR (1UL<<4) 3298 #define PCI1_PHY_ERR_ATTN_VEC_L0S_MAIN_ERR (1UL<<5) 3299 #define PCI1_PHY_ERR_ATTN_VEC_RETRAIN_REQ (1UL<<6) 3300 #define PCI1_PHY_ERR_ATTN_VEC_CC_ERR_STATUS (1UL<<7) 3301 #define PCI1_PHY_ERR_ATTN_VEC_RESERVED (0xffffffUL<<8) 3302 3303 u32_t pci1_phy_err_attn_mask; 3304 #define PCI1_PHY_ERR_ATTN_MASK_MASK_ELASTIC_ERR (1UL<<0) 3305 #define PCI1_PHY_ERR_ATTN_MASK_MASK_DISPARITY_ERR (1UL<<1) 3306 #define PCI1_PHY_ERR_ATTN_MASK_MASK_DECODE_ERR (1UL<<2) 3307 #define PCI1_PHY_ERR_ATTN_MASK_MASK_LINK_IS_SKEW (1UL<<3) 3308 #define PCI1_PHY_ERR_ATTN_MASK_MASK_TRAIN_ERR (1UL<<4) 3309 #define PCI1_PHY_ERR_ATTN_MASK_MASK_L0S_MAIN_ERR (1UL<<5) 3310 #define PCI1_PHY_ERR_ATTN_MASK_MASK_RETRAIN_REQ (1UL<<6) 3311 #define PCI1_PHY_ERR_ATTN_MASK_MASK_CC_ERR_STATUS (1UL<<7) 3312 #define PCI1_PHY_ERR_ATTN_MASK_RESERVED (0xffffffUL<<8) 3313 3314 u32_t unused_32[307]; 3315 u32_t pci1_phy_ltssm_hist_0; 3316 #define PCI1_PHY_LTSSM_HIST_0_LTSSM_HIST_0 (0xffffffffUL<<0) 3317 3318 u32_t pci1_phy_ltssm_hist_1; 3319 #define PCI1_PHY_LTSSM_HIST_1_LTSSM_HIST_1 (0xffffffffUL<<0) 3320 3321 u32_t pci1_phy_ltssm_hist_2; 3322 #define PCI1_PHY_LTSSM_HIST_2_LTSSM_HIST_2 (0xffffffffUL<<0) 3323 3324 u32_t pci1_phy_dbg_0; 3325 #define PCI1_PHY_DBG_0_PHY_DBG_0 (0xffffffffUL<<0) 3326 3327 u32_t pci1_phy_dbg_1; 3328 #define PCI1_PHY_DBG_1_PHY_DBG_1 (0xffffffffUL<<0) 3329 3330 u32_t pci1_phy_dbg_2; 3331 #define PCI1_PHY_DBG_2_PHY_DBG_2 (0xffffffffUL<<0) 3332 3333 u32_t pci1_phy_dbg_3; 3334 #define PCI1_PHY_DBG_3_PHY_DBG_3 (0xffffffffUL<<0) 3335 3336 u32_t pci1_phy_dbg_4; 3337 #define PCI1_PHY_DBG_4_PHY_DBG_4 (0xffffffffUL<<0) 3338 3339 u32_t pci1_phy_dbg_5; 3340 #define PCI1_PHY_DBG_5_PHY_DBG_5 (0xffffffffUL<<0) 3341 3342 u32_t pci1_phy_dbg_6; 3343 #define PCI1_PHY_DBG_6_PHY_DBG_6 (0xffffffffUL<<0) 3344 3345 u32_t pci1_phy_dbg_7; 3346 #define PCI1_PHY_DBG_7_PHY_DBG_7 (0xffffffffUL<<0) 3347 3348 u32_t pci1_phy_dbg_8; 3349 #define PCI1_PHY_DBG_8_PHY_DBG_8 (0xffffffffUL<<0) 3350 3351 u32_t pci1_phy_dbg_9; 3352 #define PCI1_PHY_DBG_9_PHY_DBG_9 (0xffffffffUL<<0) 3353 3354 u32_t pci1_phy_dbg_10; 3355 #define PCI1_PHY_DBG_10_PHY_DBG_10 (0xffffffffUL<<0) 3356 3357 u32_t pci1_phy_dbg_11; 3358 #define PCI1_PHY_DBG_11_PHY_DBG_11 (0xffffffffUL<<0) 3359 3360 u32_t unused_33[180]; 3361 u32_t pci1_function1[1536]; 3362 u32_t unused_34[12800]; 3363 } pcie_reg_t; 3364 3365 3366 /* 3367 * misc_reg definition 3368 * offset: 0x800 3369 */ 3370 typedef struct misc_reg 3371 { 3372 u32_t misc_command; 3373 #define MISC_COMMAND_ENABLE_ALL (1UL<<0) 3374 #define MISC_COMMAND_DISABLE_ALL (1UL<<1) 3375 #define MISC_COMMAND_SW_RESET (1UL<<4) 3376 #define MISC_COMMAND_POR_RESET (1UL<<5) 3377 #define MISC_COMMAND_HD_RESET (1UL<<6) 3378 #define MISC_COMMAND_CMN_SW_RESET (1UL<<7) 3379 #define MISC_COMMAND_PAR_ERROR (1UL<<8) 3380 #define MISC_COMMAND_CS16_ERR (1UL<<9) 3381 #define MISC_COMMAND_CS16_ERR_LOC (0xfUL<<12) 3382 #define MISC_COMMAND_PAR_ERR_RAM (0x7fUL<<16) 3383 #define MISC_COMMAND_POWERDOWN_EVENT (1UL<<23) 3384 #define MISC_COMMAND_SW_SHUTDOWN (1UL<<24) 3385 #define MISC_COMMAND_SHUTDOWN_EN (1UL<<25) 3386 #define MISC_COMMAND_DINTEG_ATTN_EN (1UL<<26) 3387 #define MISC_COMMAND_PCIE_LINK_IN_L23 (1UL<<27) 3388 #define MISC_COMMAND_PCIE_DIS (1UL<<28) 3389 3390 u32_t misc_cfg; 3391 #define MISC_CFG_GRC_TMOUT (1UL<<0) 3392 #define MISC_CFG_NVM_WR_EN (0x3UL<<1) 3393 #define MISC_CFG_NVM_WR_EN_PROTECT (0UL<<1) 3394 #define MISC_CFG_NVM_WR_EN_PCI (1UL<<1) 3395 #define MISC_CFG_NVM_WR_EN_ALLOW (2UL<<1) 3396 #define MISC_CFG_NVM_WR_EN_ALLOW2 (3UL<<1) 3397 #define MISC_CFG_BIST_EN (1UL<<3) 3398 #define MISC_CFG_CK25_OUT_ALT_SRC (1UL<<4) 3399 #define MISC_CFG_RESERVED5_TE (1UL<<5) 3400 #define MISC_CFG_RESERVED6_TE (1UL<<6) 3401 #define MISC_CFG_CLK_CTL_OVERRIDE_TE (1UL<<7) 3402 #define MISC_CFG_LEDMODE_TE (0x7UL<<8) 3403 #define MISC_CFG_LEDMODE_MAC_TE (0UL<<8) 3404 #define MISC_CFG_LEDMODE_PHY1_TE (1UL<<8) 3405 #define MISC_CFG_LEDMODE_PHY2_TE (2UL<<8) 3406 #define MISC_CFG_LEDMODE_PHY3_TE (3UL<<8) 3407 #define MISC_CFG_LEDMODE_PHY4_TE (4UL<<8) 3408 #define MISC_CFG_LEDMODE_PHY5_TE (5UL<<8) 3409 #define MISC_CFG_LEDMODE_PHY6_TE (6UL<<8) 3410 #define MISC_CFG_LEDMODE_PHY7_TE (7UL<<8) 3411 #define MISC_CFG_MCP_GRC_TMOUT_TE (1UL<<11) 3412 #define MISC_CFG_DBU_GRC_TMOUT_TE (1UL<<12) 3413 #define MISC_CFG_LEDMODE_XI (0xfUL<<8) 3414 #define MISC_CFG_LEDMODE_MAC_XI (0UL<<8) 3415 #define MISC_CFG_LEDMODE_PHY1_XI (1UL<<8) 3416 #define MISC_CFG_LEDMODE_PHY2_XI (2UL<<8) 3417 #define MISC_CFG_LEDMODE_PHY3_XI (3UL<<8) 3418 #define MISC_CFG_LEDMODE_MAC2_XI (4UL<<8) 3419 #define MISC_CFG_LEDMODE_PHY4_XI (5UL<<8) 3420 #define MISC_CFG_LEDMODE_PHY5_XI (6UL<<8) 3421 #define MISC_CFG_LEDMODE_PHY6_XI (7UL<<8) 3422 #define MISC_CFG_LEDMODE_MAC3_XI (8UL<<8) 3423 #define MISC_CFG_LEDMODE_PHY7_XI (9UL<<8) 3424 #define MISC_CFG_LEDMODE_PHY8_XI (10UL<<8) 3425 #define MISC_CFG_LEDMODE_PHY9_XI (11UL<<8) 3426 #define MISC_CFG_LEDMODE_MAC4_XI (12UL<<8) 3427 #define MISC_CFG_LEDMODE_PHY10_XI (13UL<<8) 3428 #define MISC_CFG_LEDMODE_PHY11_XI (14UL<<8) 3429 #define MISC_CFG_LEDMODE_UNUSED_XI (15UL<<8) 3430 #define MISC_CFG_PORT_SELECT_XI (1UL<<13) 3431 #define MISC_CFG_PARITY_MODE_XI (1UL<<14) 3432 3433 u32_t misc_id; 3434 #define MISC_ID_BOND_ID (0xfUL<<0) 3435 #define MISC_ID_BOND_ID_X (0UL<<0) 3436 #define MISC_ID_BOND_ID_C (3UL<<0) 3437 #define MISC_ID_BOND_ID_S (12UL<<0) 3438 #define MISC_ID_CHIP_METAL (0xffUL<<4) 3439 #define MISC_ID_CHIP_REV (0xfUL<<12) 3440 #define MISC_ID_CHIP_NUM (0xffffUL<<16) 3441 3442 u32_t misc_enable_status_bits; 3443 #define MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1UL<<0) 3444 #define MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1UL<<1) 3445 #define MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1UL<<2) 3446 #define MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1UL<<3) 3447 #define MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1UL<<4) 3448 #define MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1UL<<5) 3449 #define MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1UL<<6) 3450 #define MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1UL<<7) 3451 #define MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1UL<<8) 3452 #define MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1UL<<9) 3453 #define MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1UL<<10) 3454 #define MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1UL<<11) 3455 #define MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1UL<<12) 3456 #define MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1UL<<13) 3457 #define MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1UL<<14) 3458 #define MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1UL<<15) 3459 #define MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1UL<<16) 3460 #define MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1UL<<17) 3461 #define MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1UL<<18) 3462 #define MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1UL<<19) 3463 #define MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1UL<<20) 3464 #define MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1UL<<21) 3465 #define MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1UL<<22) 3466 #define MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1UL<<23) 3467 #define MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1UL<<24) 3468 #define MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1UL<<25) 3469 #define MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1UL<<26) 3470 #define MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1UL<<27) 3471 #define MISC_ENABLE_STATUS_BITS_RV2P_CMD_SCHEDULER_ENABLE (1UL<<28) 3472 #define MISC_ENABLE_STATUS_BITS_RSVD_FUTURE_ENABLE (0x7UL<<29) 3473 3474 u32_t misc_enable_set_bits; 3475 #define MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1UL<<0) 3476 #define MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1UL<<1) 3477 #define MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1UL<<2) 3478 #define MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1UL<<3) 3479 #define MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1UL<<4) 3480 #define MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1UL<<5) 3481 #define MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1UL<<6) 3482 #define MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1UL<<7) 3483 #define MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1UL<<8) 3484 #define MISC_ENABLE_SET_BITS_EMAC_ENABLE (1UL<<9) 3485 #define MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1UL<<10) 3486 #define MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1UL<<11) 3487 #define MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1UL<<12) 3488 #define MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1UL<<13) 3489 #define MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1UL<<14) 3490 #define MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1UL<<15) 3491 #define MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1UL<<16) 3492 #define MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1UL<<17) 3493 #define MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1UL<<18) 3494 #define MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1UL<<19) 3495 #define MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1UL<<20) 3496 #define MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1UL<<21) 3497 #define MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1UL<<22) 3498 #define MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1UL<<23) 3499 #define MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1UL<<24) 3500 #define MISC_ENABLE_SET_BITS_TIMER_ENABLE (1UL<<25) 3501 #define MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1UL<<26) 3502 #define MISC_ENABLE_SET_BITS_UMP_ENABLE (1UL<<27) 3503 #define MISC_ENABLE_SET_BITS_RV2P_CMD_SCHEDULER_ENABLE (1UL<<28) 3504 #define MISC_ENABLE_SET_BITS_RSVD_FUTURE_ENABLE (0x7UL<<29) 3505 3506 u32_t misc_enable_clr_bits; 3507 #define MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1UL<<0) 3508 #define MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1UL<<1) 3509 #define MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1UL<<2) 3510 #define MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1UL<<3) 3511 #define MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1UL<<4) 3512 #define MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1UL<<5) 3513 #define MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1UL<<6) 3514 #define MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1UL<<7) 3515 #define MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1UL<<8) 3516 #define MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1UL<<9) 3517 #define MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1UL<<10) 3518 #define MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1UL<<11) 3519 #define MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1UL<<12) 3520 #define MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1UL<<13) 3521 #define MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1UL<<14) 3522 #define MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1UL<<15) 3523 #define MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1UL<<16) 3524 #define MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1UL<<17) 3525 #define MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1UL<<18) 3526 #define MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1UL<<19) 3527 #define MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1UL<<20) 3528 #define MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1UL<<21) 3529 #define MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1UL<<22) 3530 #define MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1UL<<23) 3531 #define MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1UL<<24) 3532 #define MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1UL<<25) 3533 #define MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1UL<<26) 3534 #define MISC_ENABLE_CLR_BITS_UMP_ENABLE (1UL<<27) 3535 #define MISC_ENABLE_CLR_BITS_RV2P_CMD_SCHEDULER_ENABLE (1UL<<28) 3536 #define MISC_ENABLE_CLR_BITS_RSVD_FUTURE_ENABLE (0x7UL<<29) 3537 3538 u32_t misc_clock_control_bits; 3539 #define MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfUL<<0) 3540 #define MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0UL<<0) 3541 #define MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1UL<<0) 3542 #define MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2UL<<0) 3543 #define MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3UL<<0) 3544 #define MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4UL<<0) 3545 #define MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5UL<<0) 3546 #define MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6UL<<0) 3547 #define MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7UL<<0) 3548 #define MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (15UL<<0) 3549 #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1UL<<6) 3550 #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1UL<<7) 3551 #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_TE (0x7UL<<8) 3552 #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF_TE (0UL<<8) 3553 #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12_TE (1UL<<8) 3554 #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6_TE (2UL<<8) 3555 #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62_TE (4UL<<8) 3556 #define MISC_CLOCK_CONTROL_BITS_RESERVED0_XI (0x7UL<<8) 3557 #define MISC_CLOCK_CONTROL_BITS_MIN_POWER (1UL<<11) 3558 #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_TE (0xfUL<<12) 3559 #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100_TE (0UL<<12) 3560 #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80_TE (1UL<<12) 3561 #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50_TE (2UL<<12) 3562 #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40_TE (4UL<<12) 3563 #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25_TE (8UL<<12) 3564 #define MISC_CLOCK_CONTROL_BITS_RESERVED1_XI (0xfUL<<12) 3565 #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1UL<<16) 3566 #define MISC_CLOCK_CONTROL_BITS_RESERVED_17_TE (1UL<<17) 3567 #define MISC_CLOCK_CONTROL_BITS_RESERVED_18_TE (1UL<<18) 3568 #define MISC_CLOCK_CONTROL_BITS_RESERVED_19_TE (1UL<<19) 3569 #define MISC_CLOCK_CONTROL_BITS_RESERVED_TE (0xfffUL<<20) 3570 #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_MGMT_XI (1UL<<17) 3571 #define MISC_CLOCK_CONTROL_BITS_RESERVED2_XI (0x3fUL<<18) 3572 #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_VCO_XI (0x7UL<<24) 3573 #define MISC_CLOCK_CONTROL_BITS_RESERVED3_XI (1UL<<27) 3574 #define MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_XI (0xfUL<<28) 3575 3576 u32_t misc_spio; 3577 #define MISC_SPIO_VALUE (0xffUL<<0) 3578 #define MISC_SPIO_SET (0xffUL<<8) 3579 #define MISC_SPIO_CLR (0xffUL<<16) 3580 #define MISC_SPIO_FLOAT (0xffUL<<24) 3581 3582 u32_t misc_spio_int; 3583 #define MISC_SPIO_INT_INT_STATE_TE (0xfUL<<0) 3584 #define MISC_SPIO_INT_OLD_VALUE_TE (0xfUL<<8) 3585 #define MISC_SPIO_INT_OLD_SET_TE (0xfUL<<16) 3586 #define MISC_SPIO_INT_OLD_CLR_TE (0xfUL<<24) 3587 #define MISC_SPIO_INT_INT_STATE_XI (0xffUL<<0) 3588 #define MISC_SPIO_INT_OLD_VALUE_XI (0xffUL<<8) 3589 #define MISC_SPIO_INT_OLD_SET_XI (0xffUL<<16) 3590 #define MISC_SPIO_INT_OLD_CLR_XI (0xffUL<<24) 3591 3592 u32_t misc_config_lfsr; 3593 #define MISC_CONFIG_LFSR_DIV (0xffffUL<<0) 3594 3595 u32_t misc_lfsr_mask_bits; 3596 #define MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1UL<<0) 3597 #define MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1UL<<1) 3598 #define MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1UL<<2) 3599 #define MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1UL<<3) 3600 #define MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1UL<<4) 3601 #define MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1UL<<5) 3602 #define MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1UL<<6) 3603 #define MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1UL<<7) 3604 #define MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1UL<<8) 3605 #define MISC_LFSR_MASK_BITS_EMAC_ENABLE (1UL<<9) 3606 #define MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1UL<<10) 3607 #define MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1UL<<11) 3608 #define MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1UL<<12) 3609 #define MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1UL<<13) 3610 #define MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1UL<<14) 3611 #define MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1UL<<15) 3612 #define MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1UL<<16) 3613 #define MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1UL<<17) 3614 #define MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1UL<<18) 3615 #define MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1UL<<19) 3616 #define MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1UL<<20) 3617 #define MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1UL<<21) 3618 #define MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1UL<<22) 3619 #define MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1UL<<23) 3620 #define MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1UL<<24) 3621 #define MISC_LFSR_MASK_BITS_TIMER_ENABLE (1UL<<25) 3622 #define MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1UL<<26) 3623 #define MISC_LFSR_MASK_BITS_UMP_ENABLE (1UL<<27) 3624 #define MISC_LFSR_MASK_BITS_RV2P_CMD_SCHEDULER_ENABLE (1UL<<28) 3625 #define MISC_LFSR_MASK_BITS_RSVD_FUTURE_ENABLE (0x7UL<<29) 3626 3627 u32_t misc_arb_req[5]; 3628 u32_t misc_arb_free[5]; 3629 u32_t misc_arb_req_status[5]; 3630 u32_t misc_arb_gnt0; 3631 #define MISC_ARB_GNT0_0 (0x7UL<<0) 3632 #define MISC_ARB_GNT0_1 (0x7UL<<4) 3633 #define MISC_ARB_GNT0_2 (0x7UL<<8) 3634 #define MISC_ARB_GNT0_3 (0x7UL<<12) 3635 #define MISC_ARB_GNT0_4 (0x7UL<<16) 3636 #define MISC_ARB_GNT0_5 (0x7UL<<20) 3637 #define MISC_ARB_GNT0_6 (0x7UL<<24) 3638 #define MISC_ARB_GNT0_7 (0x7UL<<28) 3639 3640 u32_t misc_arb_gnt1; 3641 #define MISC_ARB_GNT1_8 (0x7UL<<0) 3642 #define MISC_ARB_GNT1_9 (0x7UL<<4) 3643 #define MISC_ARB_GNT1_10 (0x7UL<<8) 3644 #define MISC_ARB_GNT1_11 (0x7UL<<12) 3645 #define MISC_ARB_GNT1_12 (0x7UL<<16) 3646 #define MISC_ARB_GNT1_13 (0x7UL<<20) 3647 #define MISC_ARB_GNT1_14 (0x7UL<<24) 3648 #define MISC_ARB_GNT1_15 (0x7UL<<28) 3649 3650 u32_t misc_arb_gnt2; 3651 #define MISC_ARB_GNT2_16 (0x7UL<<0) 3652 #define MISC_ARB_GNT2_17 (0x7UL<<4) 3653 #define MISC_ARB_GNT2_18 (0x7UL<<8) 3654 #define MISC_ARB_GNT2_19 (0x7UL<<12) 3655 #define MISC_ARB_GNT2_20 (0x7UL<<16) 3656 #define MISC_ARB_GNT2_21 (0x7UL<<20) 3657 #define MISC_ARB_GNT2_22 (0x7UL<<24) 3658 #define MISC_ARB_GNT2_23 (0x7UL<<28) 3659 3660 u32_t misc_arb_gnt3; 3661 #define MISC_ARB_GNT3_24 (0x7UL<<0) 3662 #define MISC_ARB_GNT3_25 (0x7UL<<4) 3663 #define MISC_ARB_GNT3_26 (0x7UL<<8) 3664 #define MISC_ARB_GNT3_27 (0x7UL<<12) 3665 #define MISC_ARB_GNT3_28 (0x7UL<<16) 3666 #define MISC_ARB_GNT3_29 (0x7UL<<20) 3667 #define MISC_ARB_GNT3_30 (0x7UL<<24) 3668 #define MISC_ARB_GNT3_31 (0x7UL<<28) 3669 3670 u32_t misc_reserved1; 3671 #define MISC_RESERVED1_MISC_RESERVED1_VALUE (0x3fUL<<0) 3672 3673 u32_t misc_reserved2; 3674 #define MISC_RESERVED2_PCIE_DIS (1UL<<0) 3675 #define MISC_RESERVED2_LINK_IN_L23 (1UL<<1) 3676 3677 u32_t misc_sm_asf_control; 3678 #define MISC_SM_ASF_CONTROL_ASF_RST (1UL<<0) 3679 #define MISC_SM_ASF_CONTROL_TSC_EN (1UL<<1) 3680 #define MISC_SM_ASF_CONTROL_WG_TO (1UL<<2) 3681 #define MISC_SM_ASF_CONTROL_HB_TO (1UL<<3) 3682 #define MISC_SM_ASF_CONTROL_PA_TO (1UL<<4) 3683 #define MISC_SM_ASF_CONTROL_PL_TO (1UL<<5) 3684 #define MISC_SM_ASF_CONTROL_RT_TO (1UL<<6) 3685 #define MISC_SM_ASF_CONTROL_SMB_EVENT (1UL<<7) 3686 #define MISC_SM_ASF_CONTROL_STRETCH_EN (1UL<<8) 3687 #define MISC_SM_ASF_CONTROL_STRETCH_PULSE (1UL<<9) 3688 #define MISC_SM_ASF_CONTROL_RES (0x3UL<<10) 3689 #define MISC_SM_ASF_CONTROL_SMB_EN (1UL<<12) 3690 #define MISC_SM_ASF_CONTROL_SMB_BB_EN (1UL<<13) 3691 #define MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1UL<<14) 3692 #define MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1UL<<15) 3693 #define MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x7fUL<<16) 3694 #define MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x7fUL<<23) 3695 #define MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1UL<<30) 3696 #define MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1UL<<31) 3697 3698 u32_t misc_smb_in; 3699 #define MISC_SMB_IN_DAT_IN (0xffUL<<0) 3700 #define MISC_SMB_IN_RDY (1UL<<8) 3701 #define MISC_SMB_IN_DONE (1UL<<9) 3702 #define MISC_SMB_IN_FIRSTBYTE (1UL<<10) 3703 #define MISC_SMB_IN_STATUS (0x7UL<<11) 3704 #define MISC_SMB_IN_STATUS_OK (0UL<<11) 3705 #define MISC_SMB_IN_STATUS_PEC (1UL<<11) 3706 #define MISC_SMB_IN_STATUS_OFLOW (2UL<<11) 3707 #define MISC_SMB_IN_STATUS_STOP (3UL<<11) 3708 #define MISC_SMB_IN_STATUS_TIMEOUT (4UL<<11) 3709 3710 u32_t misc_smb_out; 3711 #define MISC_SMB_OUT_DAT_OUT (0xffUL<<0) 3712 #define MISC_SMB_OUT_RDY (1UL<<8) 3713 #define MISC_SMB_OUT_START (1UL<<9) 3714 #define MISC_SMB_OUT_LAST (1UL<<10) 3715 #define MISC_SMB_OUT_ACC_TYPE (1UL<<11) 3716 #define MISC_SMB_OUT_ENB_PEC (1UL<<12) 3717 #define MISC_SMB_OUT_GET_RX_LEN (1UL<<13) 3718 #define MISC_SMB_OUT_SMB_READ_LEN (0x3fUL<<14) 3719 #define MISC_SMB_OUT_SMB_OUT_STATUS (0xfUL<<20) 3720 #define MISC_SMB_OUT_SMB_OUT_STATUS_OK (0UL<<20) 3721 #define MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1UL<<20) 3722 #define MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2UL<<20) 3723 #define MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3UL<<20) 3724 #define MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4UL<<20) 3725 #define MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5UL<<20) 3726 #define MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (6UL<<20) 3727 #define MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9UL<<20) 3728 #define MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (13UL<<20) 3729 #define MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1UL<<24) 3730 #define MISC_SMB_OUT_SMB_OUT_DAT_EN (1UL<<25) 3731 #define MISC_SMB_OUT_SMB_OUT_DAT_IN (1UL<<26) 3732 #define MISC_SMB_OUT_SMB_OUT_CLK_EN (1UL<<27) 3733 #define MISC_SMB_OUT_SMB_OUT_CLK_IN (1UL<<28) 3734 3735 u32_t misc_smb_watchdog; 3736 #define MISC_SMB_WATCHDOG_WATCHDOG (0xffffUL<<0) 3737 3738 u32_t misc_smb_heartbeat; 3739 #define MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffUL<<0) 3740 3741 u32_t misc_smb_poll_asf; 3742 #define MISC_SMB_POLL_ASF_POLL_ASF (0xffffUL<<0) 3743 3744 u32_t misc_smb_poll_legacy; 3745 #define MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffUL<<0) 3746 3747 u32_t misc_smb_retran; 3748 #define MISC_SMB_RETRAN_RETRAN (0xffUL<<0) 3749 3750 u32_t misc_smb_timestamp; 3751 #define MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffUL<<0) 3752 3753 u32_t misc_perr_ena0; 3754 #define MISC_PERR_ENA0_COM_MISC_CTXC_TE (1UL<<0) 3755 #define MISC_PERR_ENA0_COM_MISC_REGF_TE (1UL<<1) 3756 #define MISC_PERR_ENA0_COM_MISC_SCPAD_TE (1UL<<2) 3757 #define MISC_PERR_ENA0_CP_MISC_CTXC_TE (1UL<<3) 3758 #define MISC_PERR_ENA0_CP_MISC_REGF_TE (1UL<<4) 3759 #define MISC_PERR_ENA0_CP_MISC_SCPAD_TE (1UL<<5) 3760 #define MISC_PERR_ENA0_CS_MISC_TMEM_TE (1UL<<6) 3761 #define MISC_PERR_ENA0_CTX_MISC_ACCM0_TE (1UL<<7) 3762 #define MISC_PERR_ENA0_CTX_MISC_ACCM1_TE (1UL<<8) 3763 #define MISC_PERR_ENA0_CTX_MISC_ACCM2_TE (1UL<<9) 3764 #define MISC_PERR_ENA0_CTX_MISC_ACCM3_TE (1UL<<10) 3765 #define MISC_PERR_ENA0_CTX_MISC_ACCM4_TE (1UL<<11) 3766 #define MISC_PERR_ENA0_CTX_MISC_ACCM5_TE (1UL<<12) 3767 #define MISC_PERR_ENA0_CTX_MISC_PGTBL_TE (1UL<<13) 3768 #define MISC_PERR_ENA0_DMAE_MISC_DR0_TE (1UL<<14) 3769 #define MISC_PERR_ENA0_DMAE_MISC_DR1_TE (1UL<<15) 3770 #define MISC_PERR_ENA0_DMAE_MISC_DR2_TE (1UL<<16) 3771 #define MISC_PERR_ENA0_DMAE_MISC_DR3_TE (1UL<<17) 3772 #define MISC_PERR_ENA0_DMAE_MISC_DR4_TE (1UL<<18) 3773 #define MISC_PERR_ENA0_DMAE_MISC_DW0_TE (1UL<<19) 3774 #define MISC_PERR_ENA0_DMAE_MISC_DW1_TE (1UL<<20) 3775 #define MISC_PERR_ENA0_DMAE_MISC_DW2_TE (1UL<<21) 3776 #define MISC_PERR_ENA0_HC_MISC_DMA_TE (1UL<<22) 3777 #define MISC_PERR_ENA0_MCP_MISC_REGF_TE (1UL<<23) 3778 #define MISC_PERR_ENA0_MCP_MISC_SCPAD_TE (1UL<<24) 3779 #define MISC_PERR_ENA0_MQ_MISC_CTX_TE (1UL<<25) 3780 #define MISC_PERR_ENA0_RBDC_MISC_TE (1UL<<26) 3781 #define MISC_PERR_ENA0_RBUF_MISC_MB_TE (1UL<<27) 3782 #define MISC_PERR_ENA0_RBUF_MISC_PTR_TE (1UL<<28) 3783 #define MISC_PERR_ENA0_RDE_MISC_RPC_TE (1UL<<29) 3784 #define MISC_PERR_ENA0_RDE_MISC_RPM_TE (1UL<<30) 3785 #define MISC_PERR_ENA0_RV2P_MISC_CB0REGS_TE (1UL<<31) 3786 #define MISC_PERR_ENA0_COM_DMAE_PERR_EN_XI (1UL<<0) 3787 #define MISC_PERR_ENA0_CP_DMAE_PERR_EN_XI (1UL<<1) 3788 #define MISC_PERR_ENA0_RPM_ACPIBEMEM_PERR_EN_XI (1UL<<2) 3789 #define MISC_PERR_ENA0_CTX_USAGE_CNT_PERR_EN_XI (1UL<<3) 3790 #define MISC_PERR_ENA0_CTX_PGTBL_PERR_EN_XI (1UL<<4) 3791 #define MISC_PERR_ENA0_CTX_CACHE_PERR_EN_XI (1UL<<5) 3792 #define MISC_PERR_ENA0_CTX_MIRROR_PERR_EN_XI (1UL<<6) 3793 #define MISC_PERR_ENA0_COM_CTXC_PERR_EN_XI (1UL<<7) 3794 #define MISC_PERR_ENA0_COM_SCPAD_PERR_EN_XI (1UL<<8) 3795 #define MISC_PERR_ENA0_CP_CTXC_PERR_EN_XI (1UL<<9) 3796 #define MISC_PERR_ENA0_CP_SCPAD_PERR_EN_XI (1UL<<10) 3797 #define MISC_PERR_ENA0_RXP_RBUFC_PERR_EN_XI (1UL<<11) 3798 #define MISC_PERR_ENA0_RXP_CTXC_PERR_EN_XI (1UL<<12) 3799 #define MISC_PERR_ENA0_RXP_SCPAD_PERR_EN_XI (1UL<<13) 3800 #define MISC_PERR_ENA0_TPAT_SCPAD_PERR_EN_XI (1UL<<14) 3801 #define MISC_PERR_ENA0_TXP_CTXC_PERR_EN_XI (1UL<<15) 3802 #define MISC_PERR_ENA0_TXP_SCPAD_PERR_EN_XI (1UL<<16) 3803 #define MISC_PERR_ENA0_CS_TMEM_PERR_EN_XI (1UL<<17) 3804 #define MISC_PERR_ENA0_MQ_CTX_PERR_EN_XI (1UL<<18) 3805 #define MISC_PERR_ENA0_RPM_DFIFOMEM_PERR_EN_XI (1UL<<19) 3806 #define MISC_PERR_ENA0_RPC_DFIFOMEM_PERR_EN_XI (1UL<<20) 3807 #define MISC_PERR_ENA0_RBUF_PTRMEM_PERR_EN_XI (1UL<<21) 3808 #define MISC_PERR_ENA0_RBUF_DATAMEM_PERR_EN_XI (1UL<<22) 3809 #define MISC_PERR_ENA0_RV2P_P2IRAM_PERR_EN_XI (1UL<<23) 3810 #define MISC_PERR_ENA0_RV2P_P1IRAM_PERR_EN_XI (1UL<<24) 3811 #define MISC_PERR_ENA0_RV2P_CB1REGS_PERR_EN_XI (1UL<<25) 3812 #define MISC_PERR_ENA0_RV2P_CB0REGS_PERR_EN_XI (1UL<<26) 3813 #define MISC_PERR_ENA0_TPBUF_PERR_EN_XI (1UL<<27) 3814 #define MISC_PERR_ENA0_THBUF_PERR_EN_XI (1UL<<28) 3815 #define MISC_PERR_ENA0_TDMA_PERR_EN_XI (1UL<<29) 3816 #define MISC_PERR_ENA0_TBDC_PERR_EN_XI (1UL<<30) 3817 #define MISC_PERR_ENA0_TSCH_LR_PERR_EN_XI (1UL<<31) 3818 3819 u32_t misc_perr_ena1; 3820 #define MISC_PERR_ENA1_RV2P_MISC_CB1REGS_TE (1UL<<0) 3821 #define MISC_PERR_ENA1_RV2P_MISC_P1IRAM_TE (1UL<<1) 3822 #define MISC_PERR_ENA1_RV2P_MISC_P2IRAM_TE (1UL<<2) 3823 #define MISC_PERR_ENA1_RXP_MISC_CTXC_TE (1UL<<3) 3824 #define MISC_PERR_ENA1_RXP_MISC_REGF_TE (1UL<<4) 3825 #define MISC_PERR_ENA1_RXP_MISC_SCPAD_TE (1UL<<5) 3826 #define MISC_PERR_ENA1_RXP_MISC_RBUFC_TE (1UL<<6) 3827 #define MISC_PERR_ENA1_TBDC_MISC_TE (1UL<<7) 3828 #define MISC_PERR_ENA1_TDMA_MISC_TE (1UL<<8) 3829 #define MISC_PERR_ENA1_THBUF_MISC_MB0_TE (1UL<<9) 3830 #define MISC_PERR_ENA1_THBUF_MISC_MB1_TE (1UL<<10) 3831 #define MISC_PERR_ENA1_TPAT_MISC_REGF_TE (1UL<<11) 3832 #define MISC_PERR_ENA1_TPAT_MISC_SCPAD_TE (1UL<<12) 3833 #define MISC_PERR_ENA1_TPBUF_MISC_MB_TE (1UL<<13) 3834 #define MISC_PERR_ENA1_TSCH_MISC_LR_TE (1UL<<14) 3835 #define MISC_PERR_ENA1_TXP_MISC_CTXC_TE (1UL<<15) 3836 #define MISC_PERR_ENA1_TXP_MISC_REGF_TE (1UL<<16) 3837 #define MISC_PERR_ENA1_TXP_MISC_SCPAD_TE (1UL<<17) 3838 #define MISC_PERR_ENA1_UMP_MISC_FIORX_TE (1UL<<18) 3839 #define MISC_PERR_ENA1_UMP_MISC_FIOTX_TE (1UL<<19) 3840 #define MISC_PERR_ENA1_UMP_MISC_RX_TE (1UL<<20) 3841 #define MISC_PERR_ENA1_UMP_MISC_TX_TE (1UL<<21) 3842 #define MISC_PERR_ENA1_RDMAQ_MISC_TE (1UL<<22) 3843 #define MISC_PERR_ENA1_CSQ_MISC_TE (1UL<<23) 3844 #define MISC_PERR_ENA1_CPQ_MISC_TE (1UL<<24) 3845 #define MISC_PERR_ENA1_MCPQ_MISC_TE (1UL<<25) 3846 #define MISC_PERR_ENA1_RV2PMQ_MISC_TE (1UL<<26) 3847 #define MISC_PERR_ENA1_RV2PPQ_MISC_TE (1UL<<27) 3848 #define MISC_PERR_ENA1_RV2PTQ_MISC_TE (1UL<<28) 3849 #define MISC_PERR_ENA1_RXPQ_MISC_TE (1UL<<29) 3850 #define MISC_PERR_ENA1_RXPCQ_MISC_TE (1UL<<30) 3851 #define MISC_PERR_ENA1_RLUPQ_MISC_TE (1UL<<31) 3852 #define MISC_PERR_ENA1_RBDC_PERR_EN_XI (1UL<<0) 3853 #define MISC_PERR_ENA1_RDMA_DFIFO_PERR_EN_XI (1UL<<2) 3854 #define MISC_PERR_ENA1_HC_STATS_PERR_EN_XI (1UL<<3) 3855 #define MISC_PERR_ENA1_HC_MSIX_PERR_EN_XI (1UL<<4) 3856 #define MISC_PERR_ENA1_HC_PRODUCSTB_PERR_EN_XI (1UL<<5) 3857 #define MISC_PERR_ENA1_HC_CONSUMSTB_PERR_EN_XI (1UL<<6) 3858 #define MISC_PERR_ENA1_TPATQ_PERR_EN_XI (1UL<<7) 3859 #define MISC_PERR_ENA1_MCPQ_PERR_EN_XI (1UL<<8) 3860 #define MISC_PERR_ENA1_TDMAQ_PERR_EN_XI (1UL<<9) 3861 #define MISC_PERR_ENA1_TXPQ_PERR_EN_XI (1UL<<10) 3862 #define MISC_PERR_ENA1_COMTQ_PERR_EN_XI (1UL<<11) 3863 #define MISC_PERR_ENA1_COMQ_PERR_EN_XI (1UL<<12) 3864 #define MISC_PERR_ENA1_RLUPQ_PERR_EN_XI (1UL<<13) 3865 #define MISC_PERR_ENA1_RXPQ_PERR_EN_XI (1UL<<14) 3866 #define MISC_PERR_ENA1_RV2PPQ_PERR_EN_XI (1UL<<15) 3867 #define MISC_PERR_ENA1_RDMAQ_PERR_EN_XI (1UL<<16) 3868 #define MISC_PERR_ENA1_TASQ_PERR_EN_XI (1UL<<17) 3869 #define MISC_PERR_ENA1_TBDRQ_PERR_EN_XI (1UL<<18) 3870 #define MISC_PERR_ENA1_TSCHQ_PERR_EN_XI (1UL<<19) 3871 #define MISC_PERR_ENA1_COMXQ_PERR_EN_XI (1UL<<20) 3872 #define MISC_PERR_ENA1_RXPCQ_PERR_EN_XI (1UL<<21) 3873 #define MISC_PERR_ENA1_RV2PTQ_PERR_EN_XI (1UL<<22) 3874 #define MISC_PERR_ENA1_RV2PMQ_PERR_EN_XI (1UL<<23) 3875 #define MISC_PERR_ENA1_CPQ_PERR_EN_XI (1UL<<24) 3876 #define MISC_PERR_ENA1_CSQ_PERR_EN_XI (1UL<<25) 3877 #define MISC_PERR_ENA1_RLUP_CID_PERR_EN_XI (1UL<<26) 3878 #define MISC_PERR_ENA1_RV2PCS_TMEM_PERR_EN_XI (1UL<<27) 3879 #define MISC_PERR_ENA1_RV2PCSQ_PERR_EN_XI (1UL<<28) 3880 #define MISC_PERR_ENA1_MQ_IDX_PERR_EN_XI (1UL<<29) 3881 3882 u32_t misc_perr_ena2; 3883 #define MISC_PERR_ENA2_COMQ_MISC_TE (1UL<<0) 3884 #define MISC_PERR_ENA2_COMXQ_MISC_TE (1UL<<1) 3885 #define MISC_PERR_ENA2_COMTQ_MISC_TE (1UL<<2) 3886 #define MISC_PERR_ENA2_TSCHQ_MISC_TE (1UL<<3) 3887 #define MISC_PERR_ENA2_TBDRQ_MISC_TE (1UL<<4) 3888 #define MISC_PERR_ENA2_TXPQ_MISC_TE (1UL<<5) 3889 #define MISC_PERR_ENA2_TDMAQ_MISC_TE (1UL<<6) 3890 #define MISC_PERR_ENA2_TPATQ_MISC_TE (1UL<<7) 3891 #define MISC_PERR_ENA2_TASQ_MISC_TE (1UL<<8) 3892 #define MISC_PERR_ENA2_TGT_FIFO_PERR_EN_XI (1UL<<0) 3893 #define MISC_PERR_ENA2_UMP_TX_PERR_EN_XI (1UL<<1) 3894 #define MISC_PERR_ENA2_UMP_RX_PERR_EN_XI (1UL<<2) 3895 #define MISC_PERR_ENA2_MCP_ROM_PERR_EN_XI (1UL<<3) 3896 #define MISC_PERR_ENA2_MCP_SCPAD_PERR_EN_XI (1UL<<4) 3897 #define MISC_PERR_ENA2_HB_MEM_PERR_EN_XI (1UL<<5) 3898 #define MISC_PERR_ENA2_PCIE_REPLAY_PERR_EN_XI (1UL<<6) 3899 3900 u32_t misc_debug_vector_sel; 3901 #define MISC_DEBUG_VECTOR_SEL_0 (0xfffUL<<0) 3902 #define MISC_DEBUG_VECTOR_SEL_1_TE (0xfffUL<<12) 3903 #define MISC_DEBUG_VECTOR_SEL_1_XI (0xfffUL<<15) 3904 3905 u32_t misc_vreg_control; 3906 #define MISC_VREG_CONTROL_1_2_TE (0xfUL<<0) 3907 #define MISC_VREG_CONTROL_1_0_MAIN_XI (0xfUL<<0) 3908 #define MISC_VREG_CONTROL_1_0_MAIN_PLUS14_XI (0UL<<0) 3909 #define MISC_VREG_CONTROL_1_0_MAIN_PLUS12_XI (1UL<<0) 3910 #define MISC_VREG_CONTROL_1_0_MAIN_PLUS10_XI (2UL<<0) 3911 #define MISC_VREG_CONTROL_1_0_MAIN_PLUS8_XI (3UL<<0) 3912 #define MISC_VREG_CONTROL_1_0_MAIN_PLUS6_XI (4UL<<0) 3913 #define MISC_VREG_CONTROL_1_0_MAIN_PLUS4_XI (5UL<<0) 3914 #define MISC_VREG_CONTROL_1_0_MAIN_PLUS2_XI (6UL<<0) 3915 #define MISC_VREG_CONTROL_1_0_MAIN_NOM_XI (7UL<<0) 3916 #define MISC_VREG_CONTROL_1_0_MAIN_MINUS2_XI (8UL<<0) 3917 #define MISC_VREG_CONTROL_1_0_MAIN_MINUS4_XI (9UL<<0) 3918 #define MISC_VREG_CONTROL_1_0_MAIN_MINUS6_XI (10UL<<0) 3919 #define MISC_VREG_CONTROL_1_0_MAIN_MINUS8_XI (11UL<<0) 3920 #define MISC_VREG_CONTROL_1_0_MAIN_MINUS10_XI (12UL<<0) 3921 #define MISC_VREG_CONTROL_1_0_MAIN_MINUS12_XI (13UL<<0) 3922 #define MISC_VREG_CONTROL_1_0_MAIN_MINUS14_XI (14UL<<0) 3923 #define MISC_VREG_CONTROL_1_0_MAIN_MINUS16_XI (15UL<<0) 3924 #define MISC_VREG_CONTROL_2_5 (0xfUL<<4) 3925 #define MISC_VREG_CONTROL_2_5_PLUS14 (0UL<<4) 3926 #define MISC_VREG_CONTROL_2_5_PLUS12 (1UL<<4) 3927 #define MISC_VREG_CONTROL_2_5_PLUS10 (2UL<<4) 3928 #define MISC_VREG_CONTROL_2_5_PLUS8 (3UL<<4) 3929 #define MISC_VREG_CONTROL_2_5_PLUS6 (4UL<<4) 3930 #define MISC_VREG_CONTROL_2_5_PLUS4 (5UL<<4) 3931 #define MISC_VREG_CONTROL_2_5_PLUS2 (6UL<<4) 3932 #define MISC_VREG_CONTROL_2_5_NOM (7UL<<4) 3933 #define MISC_VREG_CONTROL_2_5_MINUS2 (8UL<<4) 3934 #define MISC_VREG_CONTROL_2_5_MINUS4 (9UL<<4) 3935 #define MISC_VREG_CONTROL_2_5_MINUS6 (10UL<<4) 3936 #define MISC_VREG_CONTROL_2_5_MINUS8 (11UL<<4) 3937 #define MISC_VREG_CONTROL_2_5_MINUS10 (12UL<<4) 3938 #define MISC_VREG_CONTROL_2_5_MINUS12 (13UL<<4) 3939 #define MISC_VREG_CONTROL_2_5_MINUS14 (14UL<<4) 3940 #define MISC_VREG_CONTROL_2_5_MINUS16 (15UL<<4) 3941 #define MISC_VREG_CONTROL_1_0_MGMT (0xfUL<<8) 3942 #define MISC_VREG_CONTROL_1_0_MGMT_PLUS14 (0UL<<8) 3943 #define MISC_VREG_CONTROL_1_0_MGMT_PLUS12 (1UL<<8) 3944 #define MISC_VREG_CONTROL_1_0_MGMT_PLUS10 (2UL<<8) 3945 #define MISC_VREG_CONTROL_1_0_MGMT_PLUS8 (3UL<<8) 3946 #define MISC_VREG_CONTROL_1_0_MGMT_PLUS6 (4UL<<8) 3947 #define MISC_VREG_CONTROL_1_0_MGMT_PLUS4 (5UL<<8) 3948 #define MISC_VREG_CONTROL_1_0_MGMT_PLUS2 (6UL<<8) 3949 #define MISC_VREG_CONTROL_1_0_MGMT_NOM (7UL<<8) 3950 #define MISC_VREG_CONTROL_1_0_MGMT_MINUS2 (8UL<<8) 3951 #define MISC_VREG_CONTROL_1_0_MGMT_MINUS4 (9UL<<8) 3952 #define MISC_VREG_CONTROL_1_0_MGMT_MINUS6 (10UL<<8) 3953 #define MISC_VREG_CONTROL_1_0_MGMT_MINUS8 (11UL<<8) 3954 #define MISC_VREG_CONTROL_1_0_MGMT_MINUS10 (12UL<<8) 3955 #define MISC_VREG_CONTROL_1_0_MGMT_MINUS12 (13UL<<8) 3956 #define MISC_VREG_CONTROL_1_0_MGMT_MINUS14 (14UL<<8) 3957 #define MISC_VREG_CONTROL_1_0_MGMT_MINUS16 (15UL<<8) 3958 3959 u32_t misc_final_clk_ctl_val; 3960 #define MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffUL<<6) 3961 3962 u32_t misc_gp_hw_ctl0; 3963 #define MISC_GP_HW_CTL0_TX_DRIVE (1UL<<0) 3964 #define MISC_GP_HW_CTL0_RMII_MODE (1UL<<1) 3965 #define MISC_GP_HW_CTL0_RMII_CRSDV_SEL (1UL<<2) 3966 #define MISC_GP_HW_CTL0_RVMII_MODE (1UL<<3) 3967 #define MISC_GP_HW_CTL0_FLASH_SAMP_SCLK_NEGEDGE_TE (1UL<<4) 3968 #define MISC_GP_HW_CTL0_HIDDEN_REVISION_ID_TE (1UL<<5) 3969 #define MISC_GP_HW_CTL0_HC_CNTL_TMOUT_CTR_RST_TE (1UL<<6) 3970 #define MISC_GP_HW_CTL0_RESERVED1_XI (0x7UL<<4) 3971 #define MISC_GP_HW_CTL0_ENA_CORE_RST_ON_MAIN_PWR_GOING_AWAY (1UL<<7) 3972 #define MISC_GP_HW_CTL0_ENA_SEL_VAUX_B_IN_L2_TE (1UL<<8) 3973 #define MISC_GP_HW_CTL0_GRC_BNK_FREE_FIX_TE (1UL<<9) 3974 #define MISC_GP_HW_CTL0_LED_ACT_SEL_TE (1UL<<10) 3975 #define MISC_GP_HW_CTL0_RESERVED2_XI (0x7UL<<8) 3976 #define MISC_GP_HW_CTL0_UP1_DEF0 (1UL<<11) 3977 #define MISC_GP_HW_CTL0_FIBER_MODE_DIS_DEF (1UL<<12) 3978 #define MISC_GP_HW_CTL0_FORCE2500_DEF (1UL<<13) 3979 #define MISC_GP_HW_CTL0_AUTODETECT_DIS_DEF (1UL<<14) 3980 #define MISC_GP_HW_CTL0_PARALLEL_DETECT_DEF (1UL<<15) 3981 #define MISC_GP_HW_CTL0_OSCCTRL_DAI (0xfUL<<16) 3982 #define MISC_GP_HW_CTL0_OSCCTRL_DAI_3MA (0UL<<16) 3983 #define MISC_GP_HW_CTL0_OSCCTRL_DAI_2P5MA (1UL<<16) 3984 #define MISC_GP_HW_CTL0_OSCCTRL_DAI_2P0MA (3UL<<16) 3985 #define MISC_GP_HW_CTL0_OSCCTRL_DAI_1P5MA (5UL<<16) 3986 #define MISC_GP_HW_CTL0_OSCCTRL_DAI_1P0MA (7UL<<16) 3987 #define MISC_GP_HW_CTL0_OSCCTRL_DAI_PWRDN (15UL<<16) 3988 #define MISC_GP_HW_CTL0_OSCCTRL_PRE2DIS (1UL<<20) 3989 #define MISC_GP_HW_CTL0_OSCCTRL_PRE1DIS (1UL<<21) 3990 #define MISC_GP_HW_CTL0_OSCCTRL_CTAT (0x3UL<<22) 3991 #define MISC_GP_HW_CTL0_OSCCTRL_CTAT_M6P (0UL<<22) 3992 #define MISC_GP_HW_CTL0_OSCCTRL_CTAT_M0P (1UL<<22) 3993 #define MISC_GP_HW_CTL0_OSCCTRL_CTAT_P0P (2UL<<22) 3994 #define MISC_GP_HW_CTL0_OSCCTRL_CTAT_P6P (3UL<<22) 3995 #define MISC_GP_HW_CTL0_OSCCTRL_PTAT (0x3UL<<24) 3996 #define MISC_GP_HW_CTL0_OSCCTRL_PTAT_M6P (0UL<<24) 3997 #define MISC_GP_HW_CTL0_OSCCTRL_PTAT_M0P (1UL<<24) 3998 #define MISC_GP_HW_CTL0_OSCCTRL_PTAT_P0P (2UL<<24) 3999 #define MISC_GP_HW_CTL0_OSCCTRL_PTAT_P6P (3UL<<24) 4000 #define MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ (0x3UL<<26) 4001 #define MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_240UA (0UL<<26) 4002 #define MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_160UA (1UL<<26) 4003 #define MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_400UA (2UL<<26) 4004 #define MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_320UA (3UL<<26) 4005 #define MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ (0x3UL<<28) 4006 #define MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_240UA (0UL<<28) 4007 #define MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_160UA (1UL<<28) 4008 #define MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_400UA (2UL<<28) 4009 #define MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_320UA (3UL<<28) 4010 #define MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ (0x3UL<<30) 4011 #define MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P57 (0UL<<30) 4012 #define MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P45 (1UL<<30) 4013 #define MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P62 (2UL<<30) 4014 #define MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P66 (3UL<<30) 4015 4016 u32_t misc_gp_hw_ctl1; 4017 #define MISC_GP_HW_CTL1_1_ATTN_BTN_PRSNT_TE (1UL<<0) 4018 #define MISC_GP_HW_CTL1_1_ATTN_IND_PRSNT_TE (1UL<<1) 4019 #define MISC_GP_HW_CTL1_1_PWR_IND_PRSNT_TE (1UL<<2) 4020 #define MISC_GP_HW_CTL1_0_PCIE_LOOPBACK_TE (1UL<<3) 4021 #define MISC_GP_HW_CTL1_RESERVED_SOFT_XI (0xffffUL<<0) 4022 #define MISC_GP_HW_CTL1_RESERVED_HARD_XI (0xffffUL<<16) 4023 4024 u32_t misc_new_hw_ctl; 4025 #define MISC_NEW_HW_CTL_MAIN_POR_BYPASS (1UL<<0) 4026 #define MISC_NEW_HW_CTL_RINGOSC_ENABLE (1UL<<1) 4027 #define MISC_NEW_HW_CTL_RINGOSC_SEL0 (1UL<<2) 4028 #define MISC_NEW_HW_CTL_RINGOSC_SEL1 (1UL<<3) 4029 #define MISC_NEW_HW_CTL_RINGOSC_TAP (0x7UL<<4) 4030 #define MISC_NEW_HW_CTL_SMBUS_FILT_EN (1UL<<7) 4031 #define MISC_NEW_HW_CTL_LED_PHY_SERDES_MODE_0 (1UL<<8) 4032 #define MISC_NEW_HW_CTL_LED_PHY_SERDES_MODE_1 (1UL<<9) 4033 #define MISC_NEW_HW_CTL_SWAP_LED (1UL<<10) 4034 #define MISC_NEW_HW_CTL_SWAP_GPIO (1UL<<11) 4035 #define MISC_NEW_HW_CTL_RESERVED_SHARED (0xfUL<<12) 4036 #define MISC_NEW_HW_CTL_RESERVED_SPLIT (0xffffUL<<16) 4037 4038 u32_t misc_new_core_ctl; 4039 #define MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS (1UL<<0) 4040 #define MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ (1UL<<1) 4041 #define MISC_NEW_CORE_CTL_RESERVED_CMN (0x3fffUL<<2) 4042 #define MISC_NEW_CORE_CTL_DMA_ENABLE (1UL<<16) 4043 #define MISC_NEW_CORE_CTL_RESERVED_TC (0x7fffUL<<17) 4044 4045 u32_t misc_eco_hw_ctl; 4046 #define MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN (1UL<<0) 4047 #define MISC_ECO_HW_CTL_RESERVED_SOFT (0x7fffUL<<1) 4048 #define MISC_ECO_HW_CTL_RESERVED_HARD (0xffffUL<<16) 4049 4050 u32_t misc_eco_core_ctl; 4051 #define MISC_ECO_CORE_CTL_GLOBAL_REG_ATTN_0 (1UL<<0) 4052 #define MISC_ECO_CORE_CTL_GLOBAL_REG_ATTN_1 (1UL<<1) 4053 #define MISC_ECO_CORE_CTL_RESERVED_SOFT (0xffffUL<<0) 4054 #define MISC_ECO_CORE_CTL_RESERVED_HARD (0xffffUL<<16) 4055 4056 u32_t misc_ppio; 4057 #define MISC_PPIO_VALUE (0xfUL<<0) 4058 #define MISC_PPIO_SET (0xfUL<<8) 4059 #define MISC_PPIO_CLR (0xfUL<<16) 4060 #define MISC_PPIO_FLOAT (0xfUL<<24) 4061 4062 u32_t misc_ppio_int; 4063 #define MISC_PPIO_INT_INT_STATE (0xfUL<<0) 4064 #define MISC_PPIO_INT_OLD_VALUE (0xfUL<<8) 4065 #define MISC_PPIO_INT_OLD_SET (0xfUL<<16) 4066 #define MISC_PPIO_INT_OLD_CLR (0xfUL<<24) 4067 4068 u32_t misc_reset_nums; 4069 #define MISC_RESET_NUMS_NUM_HARD_RESETS (0x7UL<<0) 4070 #define MISC_RESET_NUMS_NUM_PCIE_RESETS (0x7UL<<4) 4071 #define MISC_RESET_NUMS_NUM_PERSTB_RESETS (0x7UL<<8) 4072 #define MISC_RESET_NUMS_NUM_CMN_RESETS (0x7UL<<12) 4073 #define MISC_RESET_NUMS_NUM_PORT_RESETS (0x7UL<<16) 4074 4075 u32_t misc_cs16_err; 4076 #define MISC_CS16_ERR_ENA_PCI (1UL<<0) 4077 #define MISC_CS16_ERR_ENA_RDMA (1UL<<1) 4078 #define MISC_CS16_ERR_ENA_TDMA (1UL<<2) 4079 #define MISC_CS16_ERR_ENA_EMAC (1UL<<3) 4080 #define MISC_CS16_ERR_ENA_CTX (1UL<<4) 4081 #define MISC_CS16_ERR_ENA_TBDR (1UL<<5) 4082 #define MISC_CS16_ERR_ENA_RBDC (1UL<<6) 4083 #define MISC_CS16_ERR_ENA_COM (1UL<<7) 4084 #define MISC_CS16_ERR_ENA_CP (1UL<<8) 4085 #define MISC_CS16_ERR_STA_PCI (1UL<<16) 4086 #define MISC_CS16_ERR_STA_RDMA (1UL<<17) 4087 #define MISC_CS16_ERR_STA_TDMA (1UL<<18) 4088 #define MISC_CS16_ERR_STA_EMAC (1UL<<19) 4089 #define MISC_CS16_ERR_STA_CTX (1UL<<20) 4090 #define MISC_CS16_ERR_STA_TBDR (1UL<<21) 4091 #define MISC_CS16_ERR_STA_RBDC (1UL<<22) 4092 #define MISC_CS16_ERR_STA_COM (1UL<<23) 4093 #define MISC_CS16_ERR_STA_CP (1UL<<24) 4094 4095 u32_t misc_spio_event; 4096 #define MISC_SPIO_EVENT_ENABLE (0xffUL<<0) 4097 4098 u32_t misc_ppio_event; 4099 #define MISC_PPIO_EVENT_ENABLE (0xfUL<<0) 4100 4101 u32_t misc_dual_media_ctrl; 4102 #define MISC_DUAL_MEDIA_CTRL_BOND_ID (0xffUL<<0) 4103 #define MISC_DUAL_MEDIA_CTRL_BOND_ID_X (0UL<<0) 4104 #define MISC_DUAL_MEDIA_CTRL_BOND_ID_C (3UL<<0) 4105 #define MISC_DUAL_MEDIA_CTRL_BOND_ID_S (12UL<<0) 4106 #define MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP (0x7UL<<8) 4107 #define MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN (1UL<<11) 4108 #define MISC_DUAL_MEDIA_CTRL_SERDES1_SIGDET (1UL<<12) 4109 #define MISC_DUAL_MEDIA_CTRL_SERDES0_SIGDET (1UL<<13) 4110 #define MISC_DUAL_MEDIA_CTRL_PHY1_SIGDET (1UL<<14) 4111 #define MISC_DUAL_MEDIA_CTRL_PHY0_SIGDET (1UL<<15) 4112 #define MISC_DUAL_MEDIA_CTRL_LCPLL_RST (1UL<<16) 4113 #define MISC_DUAL_MEDIA_CTRL_SERDES1_RST (1UL<<17) 4114 #define MISC_DUAL_MEDIA_CTRL_SERDES0_RST (1UL<<18) 4115 #define MISC_DUAL_MEDIA_CTRL_PHY1_RST (1UL<<19) 4116 #define MISC_DUAL_MEDIA_CTRL_PHY0_RST (1UL<<20) 4117 #define MISC_DUAL_MEDIA_CTRL_PHY_CTRL (0x7UL<<21) 4118 #define MISC_DUAL_MEDIA_CTRL_PORT_SWAP (1UL<<24) 4119 #define MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE (1UL<<25) 4120 #define MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ (0xfUL<<26) 4121 #define MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER1_IDDQ (1UL<<26) 4122 #define MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER0_IDDQ (2UL<<26) 4123 #define MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY1_IDDQ (4UL<<26) 4124 #define MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY0_IDDQ (8UL<<26) 4125 4126 u32_t misc_otp_cmd1; 4127 #define MISC_OTP_CMD1_FMODE (0x7UL<<0) 4128 #define MISC_OTP_CMD1_FMODE_IDLE (0UL<<0) 4129 #define MISC_OTP_CMD1_FMODE_WRITE (1UL<<0) 4130 #define MISC_OTP_CMD1_FMODE_INIT (2UL<<0) 4131 #define MISC_OTP_CMD1_FMODE_SET (3UL<<0) 4132 #define MISC_OTP_CMD1_FMODE_RST (4UL<<0) 4133 #define MISC_OTP_CMD1_FMODE_VERIFY (5UL<<0) 4134 #define MISC_OTP_CMD1_FMODE_RESERVED0 (6UL<<0) 4135 #define MISC_OTP_CMD1_FMODE_RESERVED1 (7UL<<0) 4136 #define MISC_OTP_CMD1_USEPINS (1UL<<8) 4137 #define MISC_OTP_CMD1_PROGSEL (1UL<<9) 4138 #define MISC_OTP_CMD1_PROGSTART (1UL<<10) 4139 #define MISC_OTP_CMD1_PCOUNT (0x7UL<<16) 4140 #define MISC_OTP_CMD1_PBYP (1UL<<19) 4141 #define MISC_OTP_CMD1_VSEL (0xfUL<<20) 4142 #define MISC_OTP_CMD1_TM (0x7UL<<27) 4143 #define MISC_OTP_CMD1_SADBYP (1UL<<30) 4144 #define MISC_OTP_CMD1_DEBUG (1UL<<31) 4145 4146 u32_t misc_otp_cmd2; 4147 #define MISC_OTP_CMD2_OTP_ROM_ADDR (0x3ffUL<<0) 4148 #define MISC_OTP_CMD2_DOSEL (0x7fUL<<16) 4149 #define MISC_OTP_CMD2_DOSEL_0 (0UL<<16) 4150 #define MISC_OTP_CMD2_DOSEL_1 (1UL<<16) 4151 #define MISC_OTP_CMD2_DOSEL_127 (127UL<<16) 4152 4153 u32_t misc_otp_status; 4154 #define MISC_OTP_STATUS_DATA (0xffUL<<0) 4155 #define MISC_OTP_STATUS_VALID (1UL<<8) 4156 #define MISC_OTP_STATUS_BUSY (1UL<<9) 4157 #define MISC_OTP_STATUS_BUSYSM (1UL<<10) 4158 #define MISC_OTP_STATUS_DONE (1UL<<11) 4159 4160 u32_t misc_otp_shift1_cmd; 4161 #define MISC_OTP_SHIFT1_CMD_RESET_MODE_N (1UL<<0) 4162 #define MISC_OTP_SHIFT1_CMD_SHIFT_DONE (1UL<<1) 4163 #define MISC_OTP_SHIFT1_CMD_SHIFT_START (1UL<<2) 4164 #define MISC_OTP_SHIFT1_CMD_LOAD_DATA (1UL<<3) 4165 #define MISC_OTP_SHIFT1_CMD_SHIFT_SELECT (0x1fUL<<8) 4166 4167 u32_t misc_otp_shift1_data; 4168 u32_t misc_otp_shift2_cmd; 4169 #define MISC_OTP_SHIFT2_CMD_RESET_MODE_N (1UL<<0) 4170 #define MISC_OTP_SHIFT2_CMD_SHIFT_DONE (1UL<<1) 4171 #define MISC_OTP_SHIFT2_CMD_SHIFT_START (1UL<<2) 4172 #define MISC_OTP_SHIFT2_CMD_LOAD_DATA (1UL<<3) 4173 #define MISC_OTP_SHIFT2_CMD_SHIFT_SELECT (0x1fUL<<8) 4174 4175 u32_t misc_otp_shift2_data; 4176 u32_t misc_bist_cs0; 4177 #define MISC_BIST_CS0_MBIST_EN (1UL<<0) 4178 #define MISC_BIST_CS0_BIST_SETUP (0x3UL<<1) 4179 #define MISC_BIST_CS0_MBIST_ASYNC_RESET (1UL<<3) 4180 #define MISC_BIST_CS0_MBIST_DONE (1UL<<8) 4181 #define MISC_BIST_CS0_MBIST_GO (1UL<<9) 4182 #define MISC_BIST_CS0_BIST_OVERRIDE (1UL<<31) 4183 4184 u32_t misc_bist_memstatus0; 4185 u32_t misc_bist_cs1; 4186 #define MISC_BIST_CS1_MBIST_EN (1UL<<0) 4187 #define MISC_BIST_CS1_BIST_SETUP (0x3UL<<1) 4188 #define MISC_BIST_CS1_MBIST_ASYNC_RESET (1UL<<3) 4189 #define MISC_BIST_CS1_MBIST_DONE (1UL<<8) 4190 #define MISC_BIST_CS1_MBIST_GO (1UL<<9) 4191 4192 u32_t misc_bist_memstatus1; 4193 u32_t misc_bist_cs2; 4194 #define MISC_BIST_CS2_MBIST_EN (1UL<<0) 4195 #define MISC_BIST_CS2_BIST_SETUP (0x3UL<<1) 4196 #define MISC_BIST_CS2_MBIST_ASYNC_RESET (1UL<<3) 4197 #define MISC_BIST_CS2_MBIST_DONE (1UL<<8) 4198 #define MISC_BIST_CS2_MBIST_GO (1UL<<9) 4199 4200 u32_t misc_bist_memstatus2; 4201 u32_t misc_bist_cs3; 4202 #define MISC_BIST_CS3_MBIST_EN (1UL<<0) 4203 #define MISC_BIST_CS3_BIST_SETUP (0x3UL<<1) 4204 #define MISC_BIST_CS3_MBIST_ASYNC_RESET (1UL<<3) 4205 #define MISC_BIST_CS3_MBIST_DONE (1UL<<8) 4206 #define MISC_BIST_CS3_MBIST_GO (1UL<<9) 4207 4208 u32_t misc_bist_memstatus3; 4209 u32_t misc_bist_cs4; 4210 #define MISC_BIST_CS4_MBIST_EN (1UL<<0) 4211 #define MISC_BIST_CS4_BIST_SETUP (0x3UL<<1) 4212 #define MISC_BIST_CS4_MBIST_ASYNC_RESET (1UL<<3) 4213 #define MISC_BIST_CS4_MBIST_DONE (1UL<<8) 4214 #define MISC_BIST_CS4_MBIST_GO (1UL<<9) 4215 4216 u32_t misc_bist_memstatus4; 4217 u32_t misc_bist_cs5; 4218 #define MISC_BIST_CS5_MBIST_EN (1UL<<0) 4219 #define MISC_BIST_CS5_BIST_SETUP (0x3UL<<1) 4220 #define MISC_BIST_CS5_MBIST_ASYNC_RESET (1UL<<3) 4221 #define MISC_BIST_CS5_MBIST_DONE (1UL<<8) 4222 #define MISC_BIST_CS5_MBIST_GO (1UL<<9) 4223 4224 u32_t misc_bist_memstatus5; 4225 u32_t misc_mem_tm0; 4226 #define MISC_MEM_TM0_PCIE_REPLAY_TM (0xfUL<<0) 4227 #define MISC_MEM_TM0_MCP_SCPAD (0xfUL<<8) 4228 #define MISC_MEM_TM0_UMP_TM (0xffUL<<16) 4229 #define MISC_MEM_TM0_HB_MEM_TM (0xfUL<<24) 4230 4231 u32_t misc_uspll_ctrl; 4232 #define MISC_USPLL_CTRL_PH_DET_DIS (1UL<<0) 4233 #define MISC_USPLL_CTRL_FREQ_DET_DIS (1UL<<1) 4234 #define MISC_USPLL_CTRL_LCPX (0x3fUL<<2) 4235 #define MISC_USPLL_CTRL_RX (0x3UL<<8) 4236 #define MISC_USPLL_CTRL_VC_EN (1UL<<10) 4237 #define MISC_USPLL_CTRL_VCO_MG (0x3UL<<11) 4238 #define MISC_USPLL_CTRL_KVCO_XF (0x7UL<<13) 4239 #define MISC_USPLL_CTRL_KVCO_XS (0x7UL<<16) 4240 #define MISC_USPLL_CTRL_TESTD_EN (1UL<<19) 4241 #define MISC_USPLL_CTRL_TESTD_SEL (0x7UL<<20) 4242 #define MISC_USPLL_CTRL_TESTA_EN (1UL<<23) 4243 #define MISC_USPLL_CTRL_TESTA_SEL (0x3UL<<24) 4244 #define MISC_USPLL_CTRL_ATTEN_FREF (1UL<<26) 4245 #define MISC_USPLL_CTRL_DIGITAL_RST (1UL<<27) 4246 #define MISC_USPLL_CTRL_ANALOG_RST (1UL<<28) 4247 #define MISC_USPLL_CTRL_LOCK (1UL<<29) 4248 4249 u32_t misc_perr_status0; 4250 #define MISC_PERR_STATUS0_COM_DMAE_PERR (1UL<<0) 4251 #define MISC_PERR_STATUS0_CP_DMAE_PERR (1UL<<1) 4252 #define MISC_PERR_STATUS0_RPM_ACPIBEMEM_PERR (1UL<<2) 4253 #define MISC_PERR_STATUS0_CTX_USAGE_CNT_PERR (1UL<<3) 4254 #define MISC_PERR_STATUS0_CTX_PGTBL_PERR (1UL<<4) 4255 #define MISC_PERR_STATUS0_CTX_CACHE_PERR (1UL<<5) 4256 #define MISC_PERR_STATUS0_CTX_MIRROR_PERR (1UL<<6) 4257 #define MISC_PERR_STATUS0_COM_CTXC_PERR (1UL<<7) 4258 #define MISC_PERR_STATUS0_COM_SCPAD_PERR (1UL<<8) 4259 #define MISC_PERR_STATUS0_CP_CTXC_PERR (1UL<<9) 4260 #define MISC_PERR_STATUS0_CP_SCPAD_PERR (1UL<<10) 4261 #define MISC_PERR_STATUS0_RXP_RBUFC_PERR (1UL<<11) 4262 #define MISC_PERR_STATUS0_RXP_CTXC_PERR (1UL<<12) 4263 #define MISC_PERR_STATUS0_RXP_SCPAD_PERR (1UL<<13) 4264 #define MISC_PERR_STATUS0_TPAT_SCPAD_PERR (1UL<<14) 4265 #define MISC_PERR_STATUS0_TXP_CTXC_PERR (1UL<<15) 4266 #define MISC_PERR_STATUS0_TXP_SCPAD_PERR (1UL<<16) 4267 #define MISC_PERR_STATUS0_CS_TMEM_PERR (1UL<<17) 4268 #define MISC_PERR_STATUS0_MQ_CTX_PERR (1UL<<18) 4269 #define MISC_PERR_STATUS0_RPM_DFIFOMEM_PERR (1UL<<19) 4270 #define MISC_PERR_STATUS0_RPC_DFIFOMEM_PERR (1UL<<20) 4271 #define MISC_PERR_STATUS0_RBUF_PTRMEM_PERR (1UL<<21) 4272 #define MISC_PERR_STATUS0_RBUF_DATAMEM_PERR (1UL<<22) 4273 #define MISC_PERR_STATUS0_RV2P_P2IRAM_PERR (1UL<<23) 4274 #define MISC_PERR_STATUS0_RV2P_P1IRAM_PERR (1UL<<24) 4275 #define MISC_PERR_STATUS0_RV2P_CB1REGS_PERR (1UL<<25) 4276 #define MISC_PERR_STATUS0_RV2P_CB0REGS_PERR (1UL<<26) 4277 #define MISC_PERR_STATUS0_TPBUF_PERR (1UL<<27) 4278 #define MISC_PERR_STATUS0_THBUF_PERR (1UL<<28) 4279 #define MISC_PERR_STATUS0_TDMA_PERR (1UL<<29) 4280 #define MISC_PERR_STATUS0_TBDC_PERR (1UL<<30) 4281 #define MISC_PERR_STATUS0_TSCH_LR_PERR (1UL<<31) 4282 4283 u32_t misc_perr_status1; 4284 #define MISC_PERR_STATUS1_RBDC_PERR (1UL<<0) 4285 #define MISC_PERR_STATUS1_RDMA_DFIFO_PERR (1UL<<2) 4286 #define MISC_PERR_STATUS1_HC_STATS_PERR (1UL<<3) 4287 #define MISC_PERR_STATUS1_HC_MSIX_PERR (1UL<<4) 4288 #define MISC_PERR_STATUS1_HC_PRODUCSTB_PERR (1UL<<5) 4289 #define MISC_PERR_STATUS1_HC_CONSUMSTB_PERR (1UL<<6) 4290 #define MISC_PERR_STATUS1_TPATQ_PERR (1UL<<7) 4291 #define MISC_PERR_STATUS1_MCPQ_PERR (1UL<<8) 4292 #define MISC_PERR_STATUS1_TDMAQ_PERR (1UL<<9) 4293 #define MISC_PERR_STATUS1_TXPQ_PERR (1UL<<10) 4294 #define MISC_PERR_STATUS1_COMTQ_PERR (1UL<<11) 4295 #define MISC_PERR_STATUS1_COMQ_PERR (1UL<<12) 4296 #define MISC_PERR_STATUS1_RLUPQ_PERR (1UL<<13) 4297 #define MISC_PERR_STATUS1_RXPQ_PERR (1UL<<14) 4298 #define MISC_PERR_STATUS1_RV2PPQ_PERR (1UL<<15) 4299 #define MISC_PERR_STATUS1_RDMAQ_PERR (1UL<<16) 4300 #define MISC_PERR_STATUS1_TASQ_PERR (1UL<<17) 4301 #define MISC_PERR_STATUS1_TBDRQ_PERR (1UL<<18) 4302 #define MISC_PERR_STATUS1_TSCHQ_PERR (1UL<<19) 4303 #define MISC_PERR_STATUS1_COMXQ_PERR (1UL<<20) 4304 #define MISC_PERR_STATUS1_RXPCQ_PERR (1UL<<21) 4305 #define MISC_PERR_STATUS1_RV2PTQ_PERR (1UL<<22) 4306 #define MISC_PERR_STATUS1_RV2PMQ_PERR (1UL<<23) 4307 #define MISC_PERR_STATUS1_CPQ_PERR (1UL<<24) 4308 #define MISC_PERR_STATUS1_CSQ_PERR (1UL<<25) 4309 #define MISC_PERR_STATUS1_RLUP_CID_PERR (1UL<<26) 4310 #define MISC_PERR_STATUS1_RV2PCS_TMEM_PERR (1UL<<27) 4311 #define MISC_PERR_STATUS1_RV2PCSQ_PERR (1UL<<28) 4312 #define MISC_PERR_STATUS1_MQ_IDX_PERR (1UL<<29) 4313 4314 u32_t misc_perr_status2; 4315 #define MISC_PERR_STATUS2_TGT_FIFO_PERR (1UL<<0) 4316 #define MISC_PERR_STATUS2_UMP_TX_PERR (1UL<<1) 4317 #define MISC_PERR_STATUS2_UMP_RX_PERR (1UL<<2) 4318 #define MISC_PERR_STATUS2_MCP_ROM_PERR (1UL<<3) 4319 #define MISC_PERR_STATUS2_MCP_SCPAD_PERR (1UL<<4) 4320 #define MISC_PERR_STATUS2_HB_MEM_PERR (1UL<<5) 4321 #define MISC_PERR_STATUS2_PCIE_REPLAY_PERR (1UL<<6) 4322 4323 u32_t misc_lcpll_ctrl0; 4324 #define MISC_LCPLL_CTRL0_OAC (0x7UL<<0) 4325 #define MISC_LCPLL_CTRL0_OAC_NEGTWENTY (0UL<<0) 4326 #define MISC_LCPLL_CTRL0_OAC_ZERO (1UL<<0) 4327 #define MISC_LCPLL_CTRL0_OAC_TWENTY (3UL<<0) 4328 #define MISC_LCPLL_CTRL0_OAC_FORTY (7UL<<0) 4329 #define MISC_LCPLL_CTRL0_ICP_CTRL (0x7UL<<3) 4330 #define MISC_LCPLL_CTRL0_ICP_CTRL_360 (0UL<<3) 4331 #define MISC_LCPLL_CTRL0_ICP_CTRL_480 (1UL<<3) 4332 #define MISC_LCPLL_CTRL0_ICP_CTRL_600 (3UL<<3) 4333 #define MISC_LCPLL_CTRL0_ICP_CTRL_720 (7UL<<3) 4334 #define MISC_LCPLL_CTRL0_BIAS_CTRL (0x3UL<<6) 4335 #define MISC_LCPLL_CTRL0_PLL_OBSERVE (0x7UL<<8) 4336 #define MISC_LCPLL_CTRL0_VTH_CTRL (0x3UL<<11) 4337 #define MISC_LCPLL_CTRL0_VTH_CTRL_0 (0UL<<11) 4338 #define MISC_LCPLL_CTRL0_VTH_CTRL_1 (1UL<<11) 4339 #define MISC_LCPLL_CTRL0_VTH_CTRL_2 (2UL<<11) 4340 #define MISC_LCPLL_CTRL0_PLLSEQSTART (1UL<<13) 4341 #define MISC_LCPLL_CTRL0_RESERVED (1UL<<14) 4342 #define MISC_LCPLL_CTRL0_CAPRETRY_EN (1UL<<15) 4343 #define MISC_LCPLL_CTRL0_FREQMONITOR_EN (1UL<<16) 4344 #define MISC_LCPLL_CTRL0_FREQDETRESTART_EN (1UL<<17) 4345 #define MISC_LCPLL_CTRL0_FREQDETRETRY_EN (1UL<<18) 4346 #define MISC_LCPLL_CTRL0_PLLFORCEFDONE_EN (1UL<<19) 4347 #define MISC_LCPLL_CTRL0_PLLFORCEFDONE (1UL<<20) 4348 #define MISC_LCPLL_CTRL0_PLLFORCEFPASS (1UL<<21) 4349 #define MISC_LCPLL_CTRL0_PLLFORCECAPDONE_EN (1UL<<22) 4350 #define MISC_LCPLL_CTRL0_PLLFORCECAPDONE (1UL<<23) 4351 #define MISC_LCPLL_CTRL0_PLLFORCECAPPASS_EN (1UL<<24) 4352 #define MISC_LCPLL_CTRL0_PLLFORCECAPPASS (1UL<<25) 4353 #define MISC_LCPLL_CTRL0_CAPRESTART (1UL<<26) 4354 #define MISC_LCPLL_CTRL0_CAPSELECTM_EN (1UL<<27) 4355 4356 u32_t misc_lcpll_ctrl1; 4357 #define MISC_LCPLL_CTRL1_CAPSELECTM (0x1fUL<<0) 4358 #define MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN_EN (1UL<<5) 4359 #define MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN (1UL<<6) 4360 #define MISC_LCPLL_CTRL1_SLOWDN_XOR (1UL<<7) 4361 4362 u32_t misc_lcpll_status; 4363 #define MISC_LCPLL_STATUS_FREQDONE_SM (1UL<<0) 4364 #define MISC_LCPLL_STATUS_FREQPASS_SM (1UL<<1) 4365 #define MISC_LCPLL_STATUS_PLLSEQDONE (1UL<<2) 4366 #define MISC_LCPLL_STATUS_PLLSEQPASS (1UL<<3) 4367 #define MISC_LCPLL_STATUS_PLLSTATE (0x7UL<<4) 4368 #define MISC_LCPLL_STATUS_CAPSTATE (0x7UL<<7) 4369 #define MISC_LCPLL_STATUS_CAPSELECT (0x1fUL<<10) 4370 #define MISC_LCPLL_STATUS_SLOWDN_INDICATOR (1UL<<15) 4371 #define MISC_LCPLL_STATUS_SLOWDN_INDICATOR_0 (0UL<<15) 4372 #define MISC_LCPLL_STATUS_SLOWDN_INDICATOR_1 (1UL<<15) 4373 4374 u32_t misc_oscfunds_ctrl; 4375 #define MISC_OSCFUNDS_CTRL_FREQ_MON (1UL<<5) 4376 #define MISC_OSCFUNDS_CTRL_FREQ_MON_OFF (0UL<<5) 4377 #define MISC_OSCFUNDS_CTRL_FREQ_MON_ON (1UL<<5) 4378 #define MISC_OSCFUNDS_CTRL_XTAL_ADJCM (0x3UL<<6) 4379 #define MISC_OSCFUNDS_CTRL_XTAL_ADJCM_0 (0UL<<6) 4380 #define MISC_OSCFUNDS_CTRL_XTAL_ADJCM_1 (1UL<<6) 4381 #define MISC_OSCFUNDS_CTRL_XTAL_ADJCM_2 (2UL<<6) 4382 #define MISC_OSCFUNDS_CTRL_XTAL_ADJCM_3 (3UL<<6) 4383 #define MISC_OSCFUNDS_CTRL_ICBUF_ADJ (0x3UL<<8) 4384 #define MISC_OSCFUNDS_CTRL_ICBUF_ADJ_0 (0UL<<8) 4385 #define MISC_OSCFUNDS_CTRL_ICBUF_ADJ_1 (1UL<<8) 4386 #define MISC_OSCFUNDS_CTRL_ICBUF_ADJ_2 (2UL<<8) 4387 #define MISC_OSCFUNDS_CTRL_ICBUF_ADJ_3 (3UL<<8) 4388 #define MISC_OSCFUNDS_CTRL_IAMP_ADJ (0x3UL<<10) 4389 #define MISC_OSCFUNDS_CTRL_IAMP_ADJ_0 (0UL<<10) 4390 #define MISC_OSCFUNDS_CTRL_IAMP_ADJ_1 (1UL<<10) 4391 #define MISC_OSCFUNDS_CTRL_IAMP_ADJ_2 (2UL<<10) 4392 #define MISC_OSCFUNDS_CTRL_IAMP_ADJ_3 (3UL<<10) 4393 4394 u32_t misc_cpu_otp_ctrl1; 4395 #define MISC_CPU_OTP_CTRL1_START (1UL<<0) 4396 #define MISC_CPU_OTP_CTRL1_COMMAND (0xfUL<<1) 4397 #define MISC_CPU_OTP_CTRL1_COMMAND_READ (0UL<<1) 4398 #define MISC_CPU_OTP_CTRL1_COMMAND_PGM_BIT_INT (1UL<<1) 4399 #define MISC_CPU_OTP_CTRL1_COMMAND_PGM_WORD_INT (2UL<<1) 4400 #define MISC_CPU_OTP_CTRL1_COMMAND_VERIFY (3UL<<1) 4401 #define MISC_CPU_OTP_CTRL1_COMMAND_INIT (4UL<<1) 4402 #define MISC_CPU_OTP_CTRL1_COMMAND_SET (5UL<<1) 4403 #define MISC_CPU_OTP_CTRL1_COMMAND_RST (6UL<<1) 4404 #define MISC_CPU_OTP_CTRL1_COMMAND_OCST (7UL<<1) 4405 #define MISC_CPU_OTP_CTRL1_COMMAND_ROW_LOCK (8UL<<1) 4406 #define MISC_CPU_OTP_CTRL1_COMMAND_PRESCREEN_TEST (9UL<<1) 4407 #define MISC_CPU_OTP_CTRL1_COMMAND_PGM_BIT_EXT (10UL<<1) 4408 #define MISC_CPU_OTP_CTRL1_COMMAND_PGM_WORD_EXT (11UL<<1) 4409 #define MISC_CPU_OTP_CTRL1_WRP_PROG_SEL (1UL<<5) 4410 #define MISC_CPU_OTP_CTRL1_WRP_VSEL (0xfUL<<6) 4411 #define MISC_CPU_OTP_CTRL1_WRP_PCOUNT (0x7UL<<10) 4412 #define MISC_CPU_OTP_CTRL1_WRP_PBYP (1UL<<13) 4413 #define MISC_CPU_OTP_CTRL1_WRP_SADBYP (1UL<<15) 4414 #define MISC_CPU_OTP_CTRL1_WRP_TIME_MARGIN (0x7UL<<16) 4415 #define MISC_CPU_OTP_CTRL1_WRP_CONTINUE_ON_FAIL (1UL<<19) 4416 #define MISC_CPU_OTP_CTRL1_OTP_DEBUG_MODE (1UL<<20) 4417 #define MISC_CPU_OTP_CTRL1_OTP_PROG_EN (1UL<<21) 4418 #define MISC_CPU_OTP_CTRL1_ACCESS_MODE (0x3UL<<22) 4419 #define MISC_CPU_OTP_CTRL1_ACCESS_MODE_RAW (0UL<<22) 4420 #define MISC_CPU_OTP_CTRL1_ACCESS_MODE_MFG (1UL<<22) 4421 #define MISC_CPU_OTP_CTRL1_ACCESS_MODE_CFG (2UL<<22) 4422 #define MISC_CPU_OTP_CTRL1_ACCESS_MODE_REP (3UL<<22) 4423 #define MISC_CPU_OTP_CTRL1_BURST_STAT_SEL (1UL<<24) 4424 4425 u32_t misc_cpu_otp_ctrl2; 4426 #define MISC_CPU_OTP_CTRL2_OTP_ROM_ADDR (0x3ffUL<<0) 4427 #define MISC_CPU_OTP_CTRL2_DOSEL (0x7fUL<<16) 4428 #define MISC_CPU_OTP_CTRL2_DOSEL_16 (16UL<<16) 4429 #define MISC_CPU_OTP_CTRL2_DOSEL_17 (17UL<<16) 4430 #define MISC_CPU_OTP_CTRL2_DOSEL_127 (127UL<<16) 4431 #define MISC_CPU_OTP_CTRL2_JTAG_CPU_MODE (1UL<<31) 4432 4433 u32_t misc_cpu_otp_status; 4434 #define MISC_CPU_OTP_STATUS_COMMAND_DONE (1UL<<0) 4435 #define MISC_CPU_OTP_STATUS_WRP_DATA_READY (1UL<<1) 4436 #define MISC_CPU_OTP_STATUS_WRP_DOUT (1UL<<2) 4437 #define MISC_CPU_OTP_STATUS_WRP_BUSY (1UL<<3) 4438 #define MISC_CPU_OTP_STATUS_WRP_FAIL (1UL<<4) 4439 #define MISC_CPU_OTP_STATUS_INVALID_PROG_REQ (1UL<<5) 4440 #define MISC_CPU_OTP_STATUS_PROG_BLOCKED (1UL<<6) 4441 #define MISC_CPU_OTP_STATUS_INIT_WAIT_DONE (1UL<<7) 4442 #define MISC_CPU_OTP_STATUS_DATA (0xffUL<<8) 4443 4444 u32_t misc_cpu_otp_write_data; 4445 u32_t misc_cpu_otp_read_data; 4446 u32_t misc_mem_65_tm0; 4447 #define MISC_MEM_65_TM0_UMP_EGRESS_TM (0xffUL<<0) 4448 #define MISC_MEM_65_TM0_MCP_SCPAD_TM (0xfUL<<8) 4449 #define MISC_MEM_65_TM0_UMP_INGRESS_TM (0xffUL<<16) 4450 #define MISC_MEM_65_TM0_HB_MEM_TM (0xfUL<<24) 4451 4452 u32_t misc_mem_65_tm1; 4453 #define MISC_MEM_65_TM1_MCP_ROM_TM (0x1fUL<<0) 4454 #define MISC_MEM_65_TM1_PCIE_DLP2TLP_BUF_TMA (0x3UL<<8) 4455 #define MISC_MEM_65_TM1_PCIE_DLP2TLP_BUF_TMB (0x3UL<<12) 4456 #define MISC_MEM_65_TM1_PCIE_REPLAY_TM (0xfUL<<16) 4457 #define MISC_MEM_65_TM1_PCIE_REPLAY_ADDR_TM (0x3UL<<24) 4458 #define MISC_MEM_65_TM1_TGT_FIFO_TM (0x3UL<<28) 4459 4460 u32_t misc_weak_wr_cmdstat; 4461 #define MISC_WEAK_WR_CMDSTAT_WW_MODE (1UL<<0) 4462 #define MISC_WEAK_WR_CMDSTAT_WW_START (1UL<<1) 4463 #define MISC_WEAK_WR_CMDSTAT_WW_DONE (1UL<<2) 4464 #define MISC_WEAK_WR_CMDSTAT_HB_MEM_FAIL_FLAG (1UL<<4) 4465 #define MISC_WEAK_WR_CMDSTAT_PCIE_REPLAY_FAIL_FLAG (1UL<<5) 4466 #define MISC_WEAK_WR_CMDSTAT_UMP_INGRESS_FAIL_FLAG (1UL<<6) 4467 #define MISC_WEAK_WR_CMDSTAT_UMP_EGRESS_FAIL_FLAG (1UL<<7) 4468 #define MISC_WEAK_WR_CMDSTAT_MCP_SCPAD_FAIL_FLAG (1UL<<8) 4469 4470 u32_t misc_new_id; 4471 #define MISC_NEW_ID_CHIP_METAL (0xffUL<<0) 4472 #define MISC_NEW_ID_CHIP_REV (0xfUL<<8) 4473 #define MISC_NEW_ID_CHIP_NUM (0xfffffUL<<12) 4474 4475 u32_t misc_add_core_ctl; 4476 #define MISC_ADD_CORE_CTL_RESERVED_SOFT (0xffffUL<<0) 4477 #define MISC_ADD_CORE_CTL_RESERVED_HARD (0xffffUL<<16) 4478 4479 u32_t misc_full_reset_nums0; 4480 #define MISC_FULL_RESET_NUMS0_NUM_HARD_RESETS (0xffUL<<0) 4481 #define MISC_FULL_RESET_NUMS0_NUM_PCIE_RESETS (0xffUL<<8) 4482 #define MISC_FULL_RESET_NUMS0_NUM_PERSTB_RESETS (0xffUL<<16) 4483 #define MISC_FULL_RESET_NUMS0_NUM_CMN_RESETS (0xffUL<<24) 4484 4485 u32_t misc_full_reset_nums1; 4486 #define MISC_FULL_RESET_NUMS1_NUM_PORT_RESETS (0xffUL<<0) 4487 4488 u32_t misc_uspll65_ctrl0; 4489 #define MISC_USPLL65_CTRL0_NUM_PORT_RESETS (0xffffffffUL<<0) 4490 4491 u32_t misc_uspll65_ctrl1; 4492 #define MISC_USPLL65_CTRL1_NUM_PORT_RESETS (0xffffffffUL<<0) 4493 4494 u32_t misc_lcpll65_ctrl0; 4495 #define MISC_LCPLL65_CTRL0_NUM_PORT_RESETS (0xffffffffUL<<0) 4496 4497 u32_t misc_lcpll65_ctrl1; 4498 #define MISC_LCPLL65_CTRL1_NUM_PORT_RESETS (0xffffffffUL<<0) 4499 4500 u32_t misc_lcpll65_status; 4501 #define MISC_LCPLL65_STATUS_NUM_PORT_RESETS (0xffffffffUL<<0) 4502 4503 u32_t misc_lcpll65_ctrl2; 4504 #define MISC_LCPLL65_CTRL2_NUM_PORT_RESETS (0xffffffffUL<<0) 4505 4506 u32_t misc_lcpll65_ctrl3; 4507 #define MISC_LCPLL65_CTRL3_NUM_PORT_RESETS (0xffffffffUL<<0) 4508 4509 u32_t misc_oscfunds65_ctrl1; 4510 #define MISC_OSCFUNDS65_CTRL1_NUM_PORT_RESETS (0xffffffffUL<<0) 4511 4512 u32_t unused_1[148]; 4513 } misc_reg_t; 4514 4515 4516 /* 4517 * p2r_reg definition 4518 * offset: 0x240000 4519 */ 4520 typedef struct p2r_reg 4521 { 4522 u32_t p2r_epb_config[256]; 4523 u32_t p2r_debug[256]; 4524 u32_t p2r_mdio_addr; 4525 #define P2R_MDIO_ADDR_ADR (0xffffUL<<0) 4526 #define P2R_MDIO_ADDR_PORT (0xfUL<<16) 4527 #define P2R_MDIO_ADDR_CMD (0xfffUL<<20) 4528 4529 u32_t p2r_mdio_wr_data; 4530 #define P2R_MDIO_WR_DATA_DATA (0xffffUL<<0) 4531 #define P2R_MDIO_WR_DATA_CMD (1UL<<31) 4532 4533 u32_t p2r_mdio_rd_data; 4534 #define P2R_MDIO_RD_DATA_DATA (0xffffUL<<0) 4535 #define P2R_MDIO_RD_DATA_CMD (1UL<<31) 4536 4537 u32_t unused_0[3581]; 4538 u32_t p2r_command; 4539 #define P2R_COMMAND_P2R_CMD_GRC_TIMEOUT (1UL<<0) 4540 4541 u32_t unused_1[64511]; 4542 } p2r_reg_t; 4543 4544 4545 /* 4546 * nvm_reg definition 4547 * offset: 0x6400 4548 */ 4549 typedef struct nvm_reg 4550 { 4551 u32_t nvm_command; 4552 #define NVM_COMMAND_RST (1UL<<0) 4553 #define NVM_COMMAND_DONE (1UL<<3) 4554 #define NVM_COMMAND_DOIT (1UL<<4) 4555 #define NVM_COMMAND_WR (1UL<<5) 4556 #define NVM_COMMAND_ERASE (1UL<<6) 4557 #define NVM_COMMAND_FIRST (1UL<<7) 4558 #define NVM_COMMAND_LAST (1UL<<8) 4559 #define NVM_COMMAND_WREN (1UL<<16) 4560 #define NVM_COMMAND_WRDI (1UL<<17) 4561 #define NVM_COMMAND_EWSR (1UL<<18) 4562 #define NVM_COMMAND_WRSR (1UL<<19) 4563 #define NVM_COMMAND_RD_ID (1UL<<20) 4564 #define NVM_COMMAND_RD_STATUS (1UL<<21) 4565 #define NVM_COMMAND_MODE_256 (1UL<<22) 4566 4567 u32_t nvm_status; 4568 #define NVM_STATUS_PI_FSM_STATE_TE (0xfUL<<0) 4569 #define NVM_STATUS_EE_FSM_STATE_TE (0xfUL<<4) 4570 #define NVM_STATUS_EQ_FSM_STATE_TE (0xfUL<<8) 4571 #define NVM_STATUS_SPI_FSM_STATE_XI (0x1fUL<<0) 4572 #define NVM_STATUS_SPI_FSM_STATE_SPI_IDLE_XI (0UL<<0) 4573 #define NVM_STATUS_SPI_FSM_STATE_SPI_CMD0_XI (1UL<<0) 4574 #define NVM_STATUS_SPI_FSM_STATE_SPI_CMD1_XI (2UL<<0) 4575 #define NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH0_XI (3UL<<0) 4576 #define NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH1_XI (4UL<<0) 4577 #define NVM_STATUS_SPI_FSM_STATE_SPI_ADDR0_XI (5UL<<0) 4578 #define NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA0_XI (6UL<<0) 4579 #define NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA1_XI (7UL<<0) 4580 #define NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA2_XI (8UL<<0) 4581 #define NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA0_XI (9UL<<0) 4582 #define NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA1_XI (10UL<<0) 4583 #define NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA2_XI (11UL<<0) 4584 #define NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID0_XI (12UL<<0) 4585 #define NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID1_XI (13UL<<0) 4586 #define NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID2_XI (14UL<<0) 4587 #define NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID3_XI (15UL<<0) 4588 #define NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID4_XI (16UL<<0) 4589 #define NVM_STATUS_SPI_FSM_STATE_SPI_CHECK_BUSY0_XI (17UL<<0) 4590 #define NVM_STATUS_SPI_FSM_STATE_SPI_ST_WREN_XI (18UL<<0) 4591 #define NVM_STATUS_SPI_FSM_STATE_SPI_WAIT_XI (19UL<<0) 4592 4593 u32_t nvm_write; 4594 #define NVM_WRITE_NVM_WRITE_VALUE (0xffffffffUL<<0) 4595 #define NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0UL<<0) 4596 #define NVM_WRITE_NVM_WRITE_VALUE_EECLK_TE (1UL<<0) 4597 #define NVM_WRITE_NVM_WRITE_VALUE_EEDATA_TE (2UL<<0) 4598 #define NVM_WRITE_NVM_WRITE_VALUE_SCLK_TE (4UL<<0) 4599 #define NVM_WRITE_NVM_WRITE_VALUE_CS_B_TE (8UL<<0) 4600 #define NVM_WRITE_NVM_WRITE_VALUE_SO_TE (16UL<<0) 4601 #define NVM_WRITE_NVM_WRITE_VALUE_SI_TE (32UL<<0) 4602 #define NVM_WRITE_NVM_WRITE_VALUE_SI_XI (1UL<<0) 4603 #define NVM_WRITE_NVM_WRITE_VALUE_SO_XI (2UL<<0) 4604 #define NVM_WRITE_NVM_WRITE_VALUE_CS_B_XI (4UL<<0) 4605 #define NVM_WRITE_NVM_WRITE_VALUE_SCLK_XI (8UL<<0) 4606 4607 u32_t nvm_addr; 4608 #define NVM_ADDR_NVM_ADDR_VALUE (0xffffffUL<<0) 4609 #define NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0UL<<0) 4610 #define NVM_ADDR_NVM_ADDR_VALUE_EECLK_TE (1UL<<0) 4611 #define NVM_ADDR_NVM_ADDR_VALUE_EEDATA_TE (2UL<<0) 4612 #define NVM_ADDR_NVM_ADDR_VALUE_SCLK_TE (4UL<<0) 4613 #define NVM_ADDR_NVM_ADDR_VALUE_CS_B_TE (8UL<<0) 4614 #define NVM_ADDR_NVM_ADDR_VALUE_SO_TE (16UL<<0) 4615 #define NVM_ADDR_NVM_ADDR_VALUE_SI_TE (32UL<<0) 4616 #define NVM_ADDR_NVM_ADDR_VALUE_SI_XI (1UL<<0) 4617 #define NVM_ADDR_NVM_ADDR_VALUE_SO_XI (2UL<<0) 4618 #define NVM_ADDR_NVM_ADDR_VALUE_CS_B_XI (4UL<<0) 4619 #define NVM_ADDR_NVM_ADDR_VALUE_SCLK_XI (8UL<<0) 4620 4621 u32_t nvm_read; 4622 #define NVM_READ_NVM_READ_VALUE (0xffffffffUL<<0) 4623 #define NVM_READ_NVM_READ_VALUE_BIT_BANG (0UL<<0) 4624 #define NVM_READ_NVM_READ_VALUE_EECLK_TE (1UL<<0) 4625 #define NVM_READ_NVM_READ_VALUE_EEDATA_TE (2UL<<0) 4626 #define NVM_READ_NVM_READ_VALUE_SCLK_TE (4UL<<0) 4627 #define NVM_READ_NVM_READ_VALUE_CS_B_TE (8UL<<0) 4628 #define NVM_READ_NVM_READ_VALUE_SO_TE (16UL<<0) 4629 #define NVM_READ_NVM_READ_VALUE_SI_TE (32UL<<0) 4630 #define NVM_READ_NVM_READ_VALUE_SI_XI (1UL<<0) 4631 #define NVM_READ_NVM_READ_VALUE_SO_XI (2UL<<0) 4632 #define NVM_READ_NVM_READ_VALUE_CS_B_XI (4UL<<0) 4633 #define NVM_READ_NVM_READ_VALUE_SCLK_XI (8UL<<0) 4634 4635 u32_t nvm_cfg1; 4636 #define NVM_CFG1_FLASH_MODE (1UL<<0) 4637 #define NVM_CFG1_BUFFER_MODE (1UL<<1) 4638 #define NVM_CFG1_PASS_MODE (1UL<<2) 4639 #define NVM_CFG1_BITBANG_MODE (1UL<<3) 4640 #define NVM_CFG1_STATUS_BIT (0x7UL<<4) 4641 #define NVM_CFG1_STATUS_BIT_FLASH_RDY (0UL<<4) 4642 #define NVM_CFG1_STATUS_BIT_BUFFER_RDY (7UL<<4) 4643 #define NVM_CFG1_SPI_CLK_DIV (0xfUL<<7) 4644 #define NVM_CFG1_SEE_CLK_DIV (0x7ffUL<<11) 4645 #define NVM_CFG1_STRAP_CONTROL_0 (1UL<<23) 4646 #define NVM_CFG1_PROTECT_MODE (1UL<<24) 4647 #define NVM_CFG1_FLASH_SIZE (1UL<<25) 4648 #define NVM_CFG1_FW_USTRAP_1 (1UL<<26) 4649 #define NVM_CFG1_FW_USTRAP_0 (1UL<<27) 4650 #define NVM_CFG1_FW_USTRAP_2 (1UL<<28) 4651 #define NVM_CFG1_FW_USTRAP_3 (1UL<<29) 4652 #define NVM_CFG1_FW_FLASH_TYPE_EN (1UL<<30) 4653 #define NVM_CFG1_COMPAT_BYPASSS (1UL<<31) 4654 4655 u32_t nvm_cfg2; 4656 #define NVM_CFG2_ERASE_CMD (0xffUL<<0) 4657 #define NVM_CFG2_DUMMY (0xffUL<<8) 4658 #define NVM_CFG2_STATUS_CMD (0xffUL<<16) 4659 #define NVM_CFG2_READ_ID (0xffUL<<24) 4660 4661 u32_t nvm_cfg3; 4662 #define NVM_CFG3_BUFFER_RD_CMD (0xffUL<<0) 4663 #define NVM_CFG3_WRITE_CMD (0xffUL<<8) 4664 #define NVM_CFG3_BUFFER_WRITE_CMD (0xffUL<<16) 4665 #define NVM_CFG3_READ_CMD (0xffUL<<24) 4666 4667 u32_t nvm_sw_arb; 4668 #define NVM_SW_ARB_ARB_REQ_SET0 (1UL<<0) 4669 #define NVM_SW_ARB_ARB_REQ_SET1 (1UL<<1) 4670 #define NVM_SW_ARB_ARB_REQ_SET2 (1UL<<2) 4671 #define NVM_SW_ARB_ARB_REQ_SET3 (1UL<<3) 4672 #define NVM_SW_ARB_ARB_REQ_CLR0 (1UL<<4) 4673 #define NVM_SW_ARB_ARB_REQ_CLR1 (1UL<<5) 4674 #define NVM_SW_ARB_ARB_REQ_CLR2 (1UL<<6) 4675 #define NVM_SW_ARB_ARB_REQ_CLR3 (1UL<<7) 4676 #define NVM_SW_ARB_ARB_ARB0 (1UL<<8) 4677 #define NVM_SW_ARB_ARB_ARB1 (1UL<<9) 4678 #define NVM_SW_ARB_ARB_ARB2 (1UL<<10) 4679 #define NVM_SW_ARB_ARB_ARB3 (1UL<<11) 4680 #define NVM_SW_ARB_REQ0 (1UL<<12) 4681 #define NVM_SW_ARB_REQ1 (1UL<<13) 4682 #define NVM_SW_ARB_REQ2 (1UL<<14) 4683 #define NVM_SW_ARB_REQ3 (1UL<<15) 4684 4685 u32_t nvm_access_enable; 4686 #define NVM_ACCESS_ENABLE_EN (1UL<<0) 4687 #define NVM_ACCESS_ENABLE_WR_EN (1UL<<1) 4688 4689 u32_t nvm_write1; 4690 #define NVM_WRITE1_WREN_CMD (0xffUL<<0) 4691 #define NVM_WRITE1_WRDI_CMD (0xffUL<<8) 4692 #define NVM_WRITE1_SR_DATA (0xffUL<<16) 4693 4694 u32_t nvm_cfg4; 4695 #define NVM_CFG4_FLASH_SIZE (0x7UL<<0) 4696 #define NVM_CFG4_FLASH_SIZE_1MBIT (0UL<<0) 4697 #define NVM_CFG4_FLASH_SIZE_2MBIT (1UL<<0) 4698 #define NVM_CFG4_FLASH_SIZE_4MBIT (2UL<<0) 4699 #define NVM_CFG4_FLASH_SIZE_8MBIT (3UL<<0) 4700 #define NVM_CFG4_FLASH_SIZE_16MBIT (4UL<<0) 4701 #define NVM_CFG4_FLASH_SIZE_32MBIT (5UL<<0) 4702 #define NVM_CFG4_FLASH_SIZE_64MBIT (6UL<<0) 4703 #define NVM_CFG4_FLASH_SIZE_128MBIT (7UL<<0) 4704 #define NVM_CFG4_FLASH_VENDOR (1UL<<3) 4705 #define NVM_CFG4_FLASH_VENDOR_ST (0UL<<3) 4706 #define NVM_CFG4_FLASH_VENDOR_ATMEL (1UL<<3) 4707 #define NVM_CFG4_MODE_256_EMPTY_BIT_LOC (0x3UL<<4) 4708 #define NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT8 (0UL<<4) 4709 #define NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT9 (1UL<<4) 4710 #define NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT10 (2UL<<4) 4711 #define NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT11 (3UL<<4) 4712 #define NVM_CFG4_STATUS_BIT_POLARITY (1UL<<6) 4713 #define NVM_CFG4_RESERVED (0x1ffffffUL<<7) 4714 4715 u32_t nvm_reconfig; 4716 #define NVM_RECONFIG_ORIG_STRAP_VALUE (0xfUL<<0) 4717 #define NVM_RECONFIG_ORIG_STRAP_VALUE_ST (0UL<<0) 4718 #define NVM_RECONFIG_ORIG_STRAP_VALUE_ATMEL (1UL<<0) 4719 #define NVM_RECONFIG_RECONFIG_STRAP_VALUE (0xfUL<<4) 4720 #define NVM_RECONFIG_RESERVED (0x7fffffUL<<8) 4721 #define NVM_RECONFIG_RECONFIG_DONE (1UL<<31) 4722 4723 u32_t unused_0[243]; 4724 } nvm_reg_t; 4725 4726 4727 /* 4728 * dma_reg definition 4729 * offset: 0xc00 4730 */ 4731 typedef struct dma_reg 4732 { 4733 u32_t dma_command; 4734 #define DMA_COMMAND_ENABLE (1UL<<0) 4735 4736 u32_t dma_status; 4737 #define DMA_STATUS_PAR_ERROR_STATE_TE (1UL<<0) 4738 #define DMA_STATUS_READ_TRANSFERS_STAT_TE (1UL<<16) 4739 #define DMA_STATUS_READ_DELAY_PCI_CLKS_STAT_TE (1UL<<17) 4740 #define DMA_STATUS_BIG_READ_TRANSFERS_STAT_TE (1UL<<18) 4741 #define DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT_TE (1UL<<19) 4742 #define DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT_TE (1UL<<20) 4743 #define DMA_STATUS_WRITE_TRANSFERS_STAT_TE (1UL<<21) 4744 #define DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT_TE (1UL<<22) 4745 #define DMA_STATUS_BIG_WRITE_TRANSFERS_STAT_TE (1UL<<23) 4746 #define DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT_TE (1UL<<24) 4747 #define DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT_TE (1UL<<25) 4748 #define DMA_STATUS_GLOBAL_ERR_XI (1UL<<0) 4749 #define DMA_STATUS_BME_XI (1UL<<4) 4750 4751 u32_t dma_config; 4752 #define DMA_CONFIG_DATA_BYTE_SWAP_TE (1UL<<0) 4753 #define DMA_CONFIG_DATA_WORD_SWAP_TE (1UL<<1) 4754 #define DMA_CONFIG_CNTL_BYTE_SWAP_TE (1UL<<4) 4755 #define DMA_CONFIG_CNTL_WORD_SWAP_TE (1UL<<5) 4756 #define DMA_CONFIG_ONE_DMA_TE (1UL<<6) 4757 #define DMA_CONFIG_CNTL_TWO_DMA_TE (1UL<<7) 4758 #define DMA_CONFIG_CNTL_FPGA_MODE_TE (1UL<<8) 4759 #define DMA_CONFIG_CNTL_PING_PONG_DMA_TE (1UL<<10) 4760 #define DMA_CONFIG_CNTL_PCI_COMP_DLY_TE (1UL<<11) 4761 #define DMA_CONFIG_NO_RCHANS_IN_USE_TE (0xfUL<<12) 4762 #define DMA_CONFIG_NO_WCHANS_IN_USE_TE (0xfUL<<16) 4763 #define DMA_CONFIG_PCI_CLK_CMP_BITS_TE (0x7UL<<20) 4764 #define DMA_CONFIG_PCI_FAST_CLK_CMP_TE (1UL<<23) 4765 #define DMA_CONFIG_BIG_SIZE_TE (0xfUL<<24) 4766 #define DMA_CONFIG_BIG_SIZE_NONE_TE (0UL<<24) 4767 #define DMA_CONFIG_BIG_SIZE_64_TE (1UL<<24) 4768 #define DMA_CONFIG_BIG_SIZE_128_TE (2UL<<24) 4769 #define DMA_CONFIG_BIG_SIZE_256_TE (4UL<<24) 4770 #define DMA_CONFIG_BIG_SIZE_512_TE (8UL<<24) 4771 #define DMA_CONFIG_DAT_WBSWAP_MODE_XI (0x3UL<<0) 4772 #define DMA_CONFIG_CTL_WBSWAP_MODE_XI (0x3UL<<4) 4773 #define DMA_CONFIG_MAX_PL_XI (0x7UL<<12) 4774 #define DMA_CONFIG_MAX_PL_128B_XI (0UL<<12) 4775 #define DMA_CONFIG_MAX_PL_256B_XI (1UL<<12) 4776 #define DMA_CONFIG_MAX_PL_512B_XI (2UL<<12) 4777 #define DMA_CONFIG_MAX_PL_EN_XI (1UL<<15) 4778 #define DMA_CONFIG_MAX_RRS_XI (0x7UL<<16) 4779 #define DMA_CONFIG_MAX_RRS_128B_XI (0UL<<16) 4780 #define DMA_CONFIG_MAX_RRS_256B_XI (1UL<<16) 4781 #define DMA_CONFIG_MAX_RRS_512B_XI (2UL<<16) 4782 #define DMA_CONFIG_MAX_RRS_1024B_XI (3UL<<16) 4783 #define DMA_CONFIG_MAX_RRS_2048B_XI (4UL<<16) 4784 #define DMA_CONFIG_MAX_RRS_4096B_XI (5UL<<16) 4785 #define DMA_CONFIG_MAX_RRS_EN_XI (1UL<<19) 4786 #define DMA_CONFIG_NO_64SWAP_EN_XI (1UL<<31) 4787 4788 u32_t dma_blackout; 4789 #define DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffUL<<0) 4790 #define DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffUL<<8) 4791 #define DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffUL<<16) 4792 4793 u32_t dma_read_master_setting_0; 4794 #define DMA_READ_MASTER_SETTING_0_TBDC_NO_SNOOP (1UL<<0) 4795 #define DMA_READ_MASTER_SETTING_0_TBDC_RELAX_ORDER (1UL<<1) 4796 #define DMA_READ_MASTER_SETTING_0_TBDC_PRIORITY (1UL<<2) 4797 #define DMA_READ_MASTER_SETTING_0_TBDC_TRAFFIC_CLASS (0x7UL<<4) 4798 #define DMA_READ_MASTER_SETTING_0_TBDC_PARAM_EN (1UL<<7) 4799 #define DMA_READ_MASTER_SETTING_0_RBDC_NO_SNOOP (1UL<<8) 4800 #define DMA_READ_MASTER_SETTING_0_RBDC_RELAX_ORDER (1UL<<9) 4801 #define DMA_READ_MASTER_SETTING_0_RBDC_PRIORITY (1UL<<10) 4802 #define DMA_READ_MASTER_SETTING_0_RBDC_TRAFFIC_CLASS (0x7UL<<12) 4803 #define DMA_READ_MASTER_SETTING_0_RBDC_PARAM_EN (1UL<<15) 4804 #define DMA_READ_MASTER_SETTING_0_TDMA_NO_SNOOP (1UL<<16) 4805 #define DMA_READ_MASTER_SETTING_0_TDMA_RELAX_ORDER (1UL<<17) 4806 #define DMA_READ_MASTER_SETTING_0_TDMA_PRIORITY (1UL<<18) 4807 #define DMA_READ_MASTER_SETTING_0_TDMA_TRAFFIC_CLASS (0x7UL<<20) 4808 #define DMA_READ_MASTER_SETTING_0_TDMA_PARAM_EN (1UL<<23) 4809 #define DMA_READ_MASTER_SETTING_0_CTX_NO_SNOOP (1UL<<24) 4810 #define DMA_READ_MASTER_SETTING_0_CTX_RELAX_ORDER (1UL<<25) 4811 #define DMA_READ_MASTER_SETTING_0_CTX_PRIORITY (1UL<<26) 4812 #define DMA_READ_MASTER_SETTING_0_CTX_TRAFFIC_CLASS (0x7UL<<28) 4813 #define DMA_READ_MASTER_SETTING_0_CTX_PARAM_EN (1UL<<31) 4814 4815 u32_t dma_read_master_setting_1; 4816 #define DMA_READ_MASTER_SETTING_1_COM_NO_SNOOP (1UL<<0) 4817 #define DMA_READ_MASTER_SETTING_1_COM_RELAX_ORDER (1UL<<1) 4818 #define DMA_READ_MASTER_SETTING_1_COM_PRIORITY (1UL<<2) 4819 #define DMA_READ_MASTER_SETTING_1_COM_TRAFFIC_CLASS (0x7UL<<4) 4820 #define DMA_READ_MASTER_SETTING_1_COM_PARAM_EN (1UL<<7) 4821 #define DMA_READ_MASTER_SETTING_1_CP_NO_SNOOP (1UL<<8) 4822 #define DMA_READ_MASTER_SETTING_1_CP_RELAX_ORDER (1UL<<9) 4823 #define DMA_READ_MASTER_SETTING_1_CP_PRIORITY (1UL<<10) 4824 #define DMA_READ_MASTER_SETTING_1_CP_TRAFFIC_CLASS (0x7UL<<12) 4825 #define DMA_READ_MASTER_SETTING_1_CP_PARAM_EN (1UL<<15) 4826 4827 u32_t dma_write_master_setting_0; 4828 #define DMA_WRITE_MASTER_SETTING_0_HC_NO_SNOOP (1UL<<0) 4829 #define DMA_WRITE_MASTER_SETTING_0_HC_RELAX_ORDER (1UL<<1) 4830 #define DMA_WRITE_MASTER_SETTING_0_HC_PRIORITY (1UL<<2) 4831 #define DMA_WRITE_MASTER_SETTING_0_HC_CS_VLD (1UL<<3) 4832 #define DMA_WRITE_MASTER_SETTING_0_HC_TRAFFIC_CLASS (0x7UL<<4) 4833 #define DMA_WRITE_MASTER_SETTING_0_HC_PARAM_EN (1UL<<7) 4834 #define DMA_WRITE_MASTER_SETTING_0_RDMA_NO_SNOOP (1UL<<8) 4835 #define DMA_WRITE_MASTER_SETTING_0_RDMA_RELAX_ORDER (1UL<<9) 4836 #define DMA_WRITE_MASTER_SETTING_0_RDMA_PRIORITY (1UL<<10) 4837 #define DMA_WRITE_MASTER_SETTING_0_RDMA_CS_VLD (1UL<<11) 4838 #define DMA_WRITE_MASTER_SETTING_0_RDMA_TRAFFIC_CLASS (0x7UL<<12) 4839 #define DMA_WRITE_MASTER_SETTING_0_RDMA_PARAM_EN (1UL<<15) 4840 #define DMA_WRITE_MASTER_SETTING_0_CTX_NO_SNOOP (1UL<<24) 4841 #define DMA_WRITE_MASTER_SETTING_0_CTX_RELAX_ORDER (1UL<<25) 4842 #define DMA_WRITE_MASTER_SETTING_0_CTX_PRIORITY (1UL<<26) 4843 #define DMA_WRITE_MASTER_SETTING_0_CTX_CS_VLD (1UL<<27) 4844 #define DMA_WRITE_MASTER_SETTING_0_CTX_TRAFFIC_CLASS (0x7UL<<28) 4845 #define DMA_WRITE_MASTER_SETTING_0_CTX_PARAM_EN (1UL<<31) 4846 4847 u32_t dma_write_master_setting_1; 4848 #define DMA_WRITE_MASTER_SETTING_1_COM_NO_SNOOP (1UL<<0) 4849 #define DMA_WRITE_MASTER_SETTING_1_COM_RELAX_ORDER (1UL<<1) 4850 #define DMA_WRITE_MASTER_SETTING_1_COM_PRIORITY (1UL<<2) 4851 #define DMA_WRITE_MASTER_SETTING_1_COM_CS_VLD (1UL<<3) 4852 #define DMA_WRITE_MASTER_SETTING_1_COM_TRAFFIC_CLASS (0x7UL<<4) 4853 #define DMA_WRITE_MASTER_SETTING_1_COM_PARAM_EN (1UL<<7) 4854 #define DMA_WRITE_MASTER_SETTING_1_CP_NO_SNOOP (1UL<<8) 4855 #define DMA_WRITE_MASTER_SETTING_1_CP_RELAX_ORDER (1UL<<9) 4856 #define DMA_WRITE_MASTER_SETTING_1_CP_PRIORITY (1UL<<10) 4857 #define DMA_WRITE_MASTER_SETTING_1_CP_CS_VLD (1UL<<11) 4858 #define DMA_WRITE_MASTER_SETTING_1_CP_TRAFFIC_CLASS (0x7UL<<12) 4859 #define DMA_WRITE_MASTER_SETTING_1_CP_PARAM_EN (1UL<<15) 4860 4861 u32_t dma_arbiter; 4862 #define DMA_ARBITER_NUM_READS (0x7UL<<0) 4863 #define DMA_ARBITER_WR_ARB_MODE (1UL<<4) 4864 #define DMA_ARBITER_WR_ARB_MODE_STRICT (0UL<<4) 4865 #define DMA_ARBITER_WR_ARB_MODE_RND_RBN (1UL<<4) 4866 #define DMA_ARBITER_RD_ARB_MODE (0x3UL<<5) 4867 #define DMA_ARBITER_RD_ARB_MODE_STRICT (0UL<<5) 4868 #define DMA_ARBITER_RD_ARB_MODE_RND_RBN (1UL<<5) 4869 #define DMA_ARBITER_RD_ARB_MODE_WGT_RND_RBN (2UL<<5) 4870 #define DMA_ARBITER_ALT_MODE_EN (1UL<<8) 4871 #define DMA_ARBITER_RR_MODE (1UL<<9) 4872 #define DMA_ARBITER_TIMER_MODE (1UL<<10) 4873 #define DMA_ARBITER_OUSTD_READ_REQ (0xfUL<<12) 4874 4875 u32_t dma_arb_timers; 4876 #define DMA_ARB_TIMERS_RD_DRR_WAIT_TIME (0xffUL<<0) 4877 #define DMA_ARB_TIMERS_TM_MIN_TIMEOUT (0xffUL<<12) 4878 #define DMA_ARB_TIMERS_TM_MAX_TIMEOUT (0xfffUL<<20) 4879 4880 u32_t unused_0; 4881 u32_t dma_debug_vect_peek; 4882 #define DMA_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) 4883 #define DMA_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) 4884 #define DMA_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) 4885 #define DMA_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) 4886 #define DMA_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) 4887 #define DMA_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) 4888 4889 u32_t dma_tag_ram_00; 4890 #define DMA_TAG_RAM_00_CHANNEL (0xfUL<<0) 4891 #define DMA_TAG_RAM_00_MASTER (0x7UL<<4) 4892 #define DMA_TAG_RAM_00_MASTER_CTX (0UL<<4) 4893 #define DMA_TAG_RAM_00_MASTER_RBDC (1UL<<4) 4894 #define DMA_TAG_RAM_00_MASTER_TBDC (2UL<<4) 4895 #define DMA_TAG_RAM_00_MASTER_COM (3UL<<4) 4896 #define DMA_TAG_RAM_00_MASTER_CP (4UL<<4) 4897 #define DMA_TAG_RAM_00_MASTER_TDMA (5UL<<4) 4898 #define DMA_TAG_RAM_00_SWAP (0x3UL<<7) 4899 #define DMA_TAG_RAM_00_SWAP_CONFIG (0UL<<7) 4900 #define DMA_TAG_RAM_00_SWAP_DATA (1UL<<7) 4901 #define DMA_TAG_RAM_00_SWAP_CONTROL (2UL<<7) 4902 #define DMA_TAG_RAM_00_FUNCTION (1UL<<9) 4903 #define DMA_TAG_RAM_00_VALID (1UL<<10) 4904 4905 u32_t dma_tag_ram_01; 4906 #define DMA_TAG_RAM_01_CHANNEL (0xfUL<<0) 4907 #define DMA_TAG_RAM_01_MASTER (0x7UL<<4) 4908 #define DMA_TAG_RAM_01_MASTER_CTX (0UL<<4) 4909 #define DMA_TAG_RAM_01_MASTER_RBDC (1UL<<4) 4910 #define DMA_TAG_RAM_01_MASTER_TBDC (2UL<<4) 4911 #define DMA_TAG_RAM_01_MASTER_COM (3UL<<4) 4912 #define DMA_TAG_RAM_01_MASTER_CP (4UL<<4) 4913 #define DMA_TAG_RAM_01_MASTER_TDMA (5UL<<4) 4914 #define DMA_TAG_RAM_01_SWAP (0x3UL<<7) 4915 #define DMA_TAG_RAM_01_SWAP_CONFIG (0UL<<7) 4916 #define DMA_TAG_RAM_01_SWAP_DATA (1UL<<7) 4917 #define DMA_TAG_RAM_01_SWAP_CONTROL (2UL<<7) 4918 #define DMA_TAG_RAM_01_FUNCTION (1UL<<9) 4919 #define DMA_TAG_RAM_01_VALID (1UL<<10) 4920 4921 u32_t dma_tag_ram_02; 4922 #define DMA_TAG_RAM_02_CHANNEL (0xfUL<<0) 4923 #define DMA_TAG_RAM_02_MASTER (0x7UL<<4) 4924 #define DMA_TAG_RAM_02_MASTER_CTX (0UL<<4) 4925 #define DMA_TAG_RAM_02_MASTER_RBDC (1UL<<4) 4926 #define DMA_TAG_RAM_02_MASTER_TBDC (2UL<<4) 4927 #define DMA_TAG_RAM_02_MASTER_COM (3UL<<4) 4928 #define DMA_TAG_RAM_02_MASTER_CP (4UL<<4) 4929 #define DMA_TAG_RAM_02_MASTER_TDMA (5UL<<4) 4930 #define DMA_TAG_RAM_02_SWAP (0x3UL<<7) 4931 #define DMA_TAG_RAM_02_SWAP_CONFIG (0UL<<7) 4932 #define DMA_TAG_RAM_02_SWAP_DATA (1UL<<7) 4933 #define DMA_TAG_RAM_02_SWAP_CONTROL (2UL<<7) 4934 #define DMA_TAG_RAM_02_FUNCTION (1UL<<9) 4935 #define DMA_TAG_RAM_02_VALID (1UL<<10) 4936 4937 u32_t dma_tag_ram_03; 4938 #define DMA_TAG_RAM_03_CHANNEL (0xfUL<<0) 4939 #define DMA_TAG_RAM_03_MASTER (0x7UL<<4) 4940 #define DMA_TAG_RAM_03_MASTER_CTX (0UL<<4) 4941 #define DMA_TAG_RAM_03_MASTER_RBDC (1UL<<4) 4942 #define DMA_TAG_RAM_03_MASTER_TBDC (2UL<<4) 4943 #define DMA_TAG_RAM_03_MASTER_COM (3UL<<4) 4944 #define DMA_TAG_RAM_03_MASTER_CP (4UL<<4) 4945 #define DMA_TAG_RAM_03_MASTER_TDMA (5UL<<4) 4946 #define DMA_TAG_RAM_03_SWAP (0x3UL<<7) 4947 #define DMA_TAG_RAM_03_SWAP_CONFIG (0UL<<7) 4948 #define DMA_TAG_RAM_03_SWAP_DATA (1UL<<7) 4949 #define DMA_TAG_RAM_03_SWAP_CONTROL (2UL<<7) 4950 #define DMA_TAG_RAM_03_FUNCTION (1UL<<9) 4951 #define DMA_TAG_RAM_03_VALID (1UL<<10) 4952 4953 u32_t dma_tag_ram_04; 4954 #define DMA_TAG_RAM_04_CHANNEL (0xfUL<<0) 4955 #define DMA_TAG_RAM_04_MASTER (0x7UL<<4) 4956 #define DMA_TAG_RAM_04_MASTER_CTX (0UL<<4) 4957 #define DMA_TAG_RAM_04_MASTER_RBDC (1UL<<4) 4958 #define DMA_TAG_RAM_04_MASTER_TBDC (2UL<<4) 4959 #define DMA_TAG_RAM_04_MASTER_COM (3UL<<4) 4960 #define DMA_TAG_RAM_04_MASTER_CP (4UL<<4) 4961 #define DMA_TAG_RAM_04_MASTER_TDMA (5UL<<4) 4962 #define DMA_TAG_RAM_04_SWAP (0x3UL<<7) 4963 #define DMA_TAG_RAM_04_SWAP_CONFIG (0UL<<7) 4964 #define DMA_TAG_RAM_04_SWAP_DATA (1UL<<7) 4965 #define DMA_TAG_RAM_04_SWAP_CONTROL (2UL<<7) 4966 #define DMA_TAG_RAM_04_FUNCTION (1UL<<9) 4967 #define DMA_TAG_RAM_04_VALID (1UL<<10) 4968 4969 u32_t dma_tag_ram_05; 4970 #define DMA_TAG_RAM_05_CHANNEL (0xfUL<<0) 4971 #define DMA_TAG_RAM_05_MASTER (0x7UL<<4) 4972 #define DMA_TAG_RAM_05_MASTER_CTX (0UL<<4) 4973 #define DMA_TAG_RAM_05_MASTER_RBDC (1UL<<4) 4974 #define DMA_TAG_RAM_05_MASTER_TBDC (2UL<<4) 4975 #define DMA_TAG_RAM_05_MASTER_COM (3UL<<4) 4976 #define DMA_TAG_RAM_05_MASTER_CP (4UL<<4) 4977 #define DMA_TAG_RAM_05_MASTER_TDMA (5UL<<4) 4978 #define DMA_TAG_RAM_05_SWAP (0x3UL<<7) 4979 #define DMA_TAG_RAM_05_SWAP_CONFIG (0UL<<7) 4980 #define DMA_TAG_RAM_05_SWAP_DATA (1UL<<7) 4981 #define DMA_TAG_RAM_05_SWAP_CONTROL (2UL<<7) 4982 #define DMA_TAG_RAM_05_FUNCTION (1UL<<9) 4983 #define DMA_TAG_RAM_05_VALID (1UL<<10) 4984 4985 u32_t dma_tag_ram_06; 4986 #define DMA_TAG_RAM_06_CHANNEL (0xfUL<<0) 4987 #define DMA_TAG_RAM_06_MASTER (0x7UL<<4) 4988 #define DMA_TAG_RAM_06_MASTER_CTX (0UL<<4) 4989 #define DMA_TAG_RAM_06_MASTER_RBDC (1UL<<4) 4990 #define DMA_TAG_RAM_06_MASTER_TBDC (2UL<<4) 4991 #define DMA_TAG_RAM_06_MASTER_COM (3UL<<4) 4992 #define DMA_TAG_RAM_06_MASTER_CP (4UL<<4) 4993 #define DMA_TAG_RAM_06_MASTER_TDMA (5UL<<4) 4994 #define DMA_TAG_RAM_06_SWAP (0x3UL<<7) 4995 #define DMA_TAG_RAM_06_SWAP_CONFIG (0UL<<7) 4996 #define DMA_TAG_RAM_06_SWAP_DATA (1UL<<7) 4997 #define DMA_TAG_RAM_06_SWAP_CONTROL (2UL<<7) 4998 #define DMA_TAG_RAM_06_FUNCTION (1UL<<9) 4999 #define DMA_TAG_RAM_06_VALID (1UL<<10) 5000 5001 u32_t dma_tag_ram_07; 5002 #define DMA_TAG_RAM_07_CHANNEL (0xfUL<<0) 5003 #define DMA_TAG_RAM_07_MASTER (0x7UL<<4) 5004 #define DMA_TAG_RAM_07_MASTER_CTX (0UL<<4) 5005 #define DMA_TAG_RAM_07_MASTER_RBDC (1UL<<4) 5006 #define DMA_TAG_RAM_07_MASTER_TBDC (2UL<<4) 5007 #define DMA_TAG_RAM_07_MASTER_COM (3UL<<4) 5008 #define DMA_TAG_RAM_07_MASTER_CP (4UL<<4) 5009 #define DMA_TAG_RAM_07_MASTER_TDMA (5UL<<4) 5010 #define DMA_TAG_RAM_07_SWAP (0x3UL<<7) 5011 #define DMA_TAG_RAM_07_SWAP_CONFIG (0UL<<7) 5012 #define DMA_TAG_RAM_07_SWAP_DATA (1UL<<7) 5013 #define DMA_TAG_RAM_07_SWAP_CONTROL (2UL<<7) 5014 #define DMA_TAG_RAM_07_FUNCTION (1UL<<9) 5015 #define DMA_TAG_RAM_07_VALID (1UL<<10) 5016 5017 u32_t dma_tag_ram_08; 5018 #define DMA_TAG_RAM_08_CHANNEL (0xfUL<<0) 5019 #define DMA_TAG_RAM_08_MASTER (0x7UL<<4) 5020 #define DMA_TAG_RAM_08_MASTER_CTX (0UL<<4) 5021 #define DMA_TAG_RAM_08_MASTER_RBDC (1UL<<4) 5022 #define DMA_TAG_RAM_08_MASTER_TBDC (2UL<<4) 5023 #define DMA_TAG_RAM_08_MASTER_COM (3UL<<4) 5024 #define DMA_TAG_RAM_08_MASTER_CP (4UL<<4) 5025 #define DMA_TAG_RAM_08_MASTER_TDMA (5UL<<4) 5026 #define DMA_TAG_RAM_08_SWAP (0x3UL<<7) 5027 #define DMA_TAG_RAM_08_SWAP_CONFIG (0UL<<7) 5028 #define DMA_TAG_RAM_08_SWAP_DATA (1UL<<7) 5029 #define DMA_TAG_RAM_08_SWAP_CONTROL (2UL<<7) 5030 #define DMA_TAG_RAM_08_FUNCTION (1UL<<9) 5031 #define DMA_TAG_RAM_08_VALID (1UL<<10) 5032 5033 u32_t dma_tag_ram_09; 5034 #define DMA_TAG_RAM_09_CHANNEL (0xfUL<<0) 5035 #define DMA_TAG_RAM_09_MASTER (0x7UL<<4) 5036 #define DMA_TAG_RAM_09_MASTER_CTX (0UL<<4) 5037 #define DMA_TAG_RAM_09_MASTER_RBDC (1UL<<4) 5038 #define DMA_TAG_RAM_09_MASTER_TBDC (2UL<<4) 5039 #define DMA_TAG_RAM_09_MASTER_COM (3UL<<4) 5040 #define DMA_TAG_RAM_09_MASTER_CP (4UL<<4) 5041 #define DMA_TAG_RAM_09_MASTER_TDMA (5UL<<4) 5042 #define DMA_TAG_RAM_09_SWAP (0x3UL<<7) 5043 #define DMA_TAG_RAM_09_SWAP_CONFIG (0UL<<7) 5044 #define DMA_TAG_RAM_09_SWAP_DATA (1UL<<7) 5045 #define DMA_TAG_RAM_09_SWAP_CONTROL (2UL<<7) 5046 #define DMA_TAG_RAM_09_FUNCTION (1UL<<9) 5047 #define DMA_TAG_RAM_09_VALID (1UL<<10) 5048 5049 u32_t dma_tag_ram_10; 5050 #define DMA_TAG_RAM_10_CHANNEL (0xfUL<<0) 5051 #define DMA_TAG_RAM_10_MASTER (0x7UL<<4) 5052 #define DMA_TAG_RAM_10_MASTER_CTX (0UL<<4) 5053 #define DMA_TAG_RAM_10_MASTER_RBDC (1UL<<4) 5054 #define DMA_TAG_RAM_10_MASTER_TBDC (2UL<<4) 5055 #define DMA_TAG_RAM_10_MASTER_COM (3UL<<4) 5056 #define DMA_TAG_RAM_10_MASTER_CP (4UL<<4) 5057 #define DMA_TAG_RAM_10_MASTER_TDMA (5UL<<4) 5058 #define DMA_TAG_RAM_10_SWAP (0x3UL<<7) 5059 #define DMA_TAG_RAM_10_SWAP_CONFIG (0UL<<7) 5060 #define DMA_TAG_RAM_10_SWAP_DATA (1UL<<7) 5061 #define DMA_TAG_RAM_10_SWAP_CONTROL (2UL<<7) 5062 #define DMA_TAG_RAM_10_FUNCTION (1UL<<9) 5063 #define DMA_TAG_RAM_10_VALID (1UL<<10) 5064 5065 u32_t dma_tag_ram_11; 5066 #define DMA_TAG_RAM_11_CHANNEL (0xfUL<<0) 5067 #define DMA_TAG_RAM_11_MASTER (0x7UL<<4) 5068 #define DMA_TAG_RAM_11_MASTER_CTX (0UL<<4) 5069 #define DMA_TAG_RAM_11_MASTER_RBDC (1UL<<4) 5070 #define DMA_TAG_RAM_11_MASTER_TBDC (2UL<<4) 5071 #define DMA_TAG_RAM_11_MASTER_COM (3UL<<4) 5072 #define DMA_TAG_RAM_11_MASTER_CP (4UL<<4) 5073 #define DMA_TAG_RAM_11_MASTER_TDMA (5UL<<4) 5074 #define DMA_TAG_RAM_11_SWAP (0x3UL<<7) 5075 #define DMA_TAG_RAM_11_SWAP_CONFIG (0UL<<7) 5076 #define DMA_TAG_RAM_11_SWAP_DATA (1UL<<7) 5077 #define DMA_TAG_RAM_11_SWAP_CONTROL (2UL<<7) 5078 #define DMA_TAG_RAM_11_FUNCTION (1UL<<9) 5079 #define DMA_TAG_RAM_11_VALID (1UL<<10) 5080 5081 u32_t dma_rchan_stat_22; 5082 u32_t dma_rchan_stat_30; 5083 u32_t dma_rchan_stat_31; 5084 u32_t dma_rchan_stat_32; 5085 u32_t dma_rchan_stat_40; 5086 u32_t dma_rchan_stat_41; 5087 u32_t dma_rchan_stat_42; 5088 u32_t dma_rchan_stat_50; 5089 u32_t dma_rchan_stat_51; 5090 u32_t dma_rchan_stat_52; 5091 u32_t dma_rchan_stat_60; 5092 u32_t dma_rchan_stat_61; 5093 u32_t dma_rchan_stat_62; 5094 u32_t dma_rchan_stat_70; 5095 u32_t dma_rchan_stat_71; 5096 u32_t dma_rchan_stat_72; 5097 u32_t dma_wchan_stat_00; 5098 #define DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffUL<<0) 5099 5100 u32_t dma_wchan_stat_01; 5101 #define DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffUL<<0) 5102 5103 u32_t dma_wchan_stat_02; 5104 #define DMA_WCHAN_STAT_02_LENGTH (0xffffUL<<0) 5105 #define DMA_WCHAN_STAT_02_WORD_SWAP (1UL<<16) 5106 #define DMA_WCHAN_STAT_02_BYTE_SWAP (1UL<<17) 5107 #define DMA_WCHAN_STAT_02_PRIORITY_LVL (1UL<<18) 5108 5109 u32_t dma_wchan_stat_10; 5110 u32_t dma_wchan_stat_11; 5111 u32_t dma_wchan_stat_12; 5112 u32_t dma_wchan_stat_20; 5113 u32_t dma_wchan_stat_21; 5114 u32_t dma_wchan_stat_22; 5115 u32_t dma_wchan_stat_30; 5116 u32_t dma_wchan_stat_31; 5117 u32_t dma_wchan_stat_32; 5118 u32_t dma_wchan_stat_40; 5119 u32_t dma_wchan_stat_41; 5120 u32_t dma_wchan_stat_42; 5121 u32_t dma_wchan_stat_50; 5122 u32_t dma_wchan_stat_51; 5123 u32_t dma_wchan_stat_52; 5124 u32_t dma_wchan_stat_60; 5125 u32_t dma_wchan_stat_61; 5126 u32_t dma_wchan_stat_62; 5127 u32_t dma_wchan_stat_70; 5128 u32_t dma_wchan_stat_71; 5129 u32_t dma_wchan_stat_72; 5130 u32_t dma_arb_stat_00; 5131 #define DMA_ARB_STAT_00_MASTER (0xffffUL<<0) 5132 #define DMA_ARB_STAT_00_MASTER_ENC (0xffUL<<16) 5133 #define DMA_ARB_STAT_00_CUR_BINMSTR (0xffUL<<24) 5134 5135 u32_t dma_arb_stat_01; 5136 #define DMA_ARB_STAT_01_LPR_RPTR (0xfUL<<0) 5137 #define DMA_ARB_STAT_01_LPR_WPTR (0xfUL<<4) 5138 #define DMA_ARB_STAT_01_LPB_RPTR (0xfUL<<8) 5139 #define DMA_ARB_STAT_01_LPB_WPTR (0xfUL<<12) 5140 #define DMA_ARB_STAT_01_HPR_RPTR (0xfUL<<16) 5141 #define DMA_ARB_STAT_01_HPR_WPTR (0xfUL<<20) 5142 #define DMA_ARB_STAT_01_HPB_RPTR (0xfUL<<24) 5143 #define DMA_ARB_STAT_01_HPB_WPTR (0xfUL<<28) 5144 5145 u32_t unused_1[126]; 5146 u32_t dma_fuse_ctrl0_cmd; 5147 #define DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1UL<<0) 5148 #define DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1UL<<1) 5149 #define DMA_FUSE_CTRL0_CMD_SHIFT (1UL<<2) 5150 #define DMA_FUSE_CTRL0_CMD_LOAD (1UL<<3) 5151 #define DMA_FUSE_CTRL0_CMD_SEL (0xfUL<<8) 5152 5153 u32_t dma_fuse_ctrl0_data; 5154 u32_t dma_fuse_ctrl1_cmd; 5155 #define DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1UL<<0) 5156 #define DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1UL<<1) 5157 #define DMA_FUSE_CTRL1_CMD_SHIFT (1UL<<2) 5158 #define DMA_FUSE_CTRL1_CMD_LOAD (1UL<<3) 5159 #define DMA_FUSE_CTRL1_CMD_SEL (0xfUL<<8) 5160 5161 u32_t dma_fuse_ctrl1_data; 5162 u32_t dma_fuse_ctrl2_cmd; 5163 #define DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1UL<<0) 5164 #define DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1UL<<1) 5165 #define DMA_FUSE_CTRL2_CMD_SHIFT (1UL<<2) 5166 #define DMA_FUSE_CTRL2_CMD_LOAD (1UL<<3) 5167 #define DMA_FUSE_CTRL2_CMD_SEL (0xfUL<<8) 5168 5169 u32_t dma_fuse_ctrl2_data; 5170 u32_t unused_2[58]; 5171 } dma_reg_t; 5172 5173 5174 /* 5175 * context_reg definition 5176 * offset: 0x1000 5177 */ 5178 typedef struct context_reg 5179 { 5180 u32_t ctx_command; 5181 #define CTX_COMMAND_ENABLED (1UL<<0) 5182 #define CTX_COMMAND_DISABLE_USAGE_CNT (1UL<<1) 5183 #define CTX_COMMAND_DISABLE_PLRU (1UL<<2) 5184 #define CTX_COMMAND_DISABLE_COMBINE_READ (1UL<<3) 5185 #define CTX_COMMAND_FLUSH_AHEAD (0x1fUL<<8) 5186 #define CTX_COMMAND_MEM_INIT (1UL<<13) 5187 #define CTX_COMMAND_PAGE_SIZE (0xfUL<<16) 5188 #define CTX_COMMAND_PAGE_SIZE_256 (0UL<<16) 5189 #define CTX_COMMAND_PAGE_SIZE_512 (1UL<<16) 5190 #define CTX_COMMAND_PAGE_SIZE_1K (2UL<<16) 5191 #define CTX_COMMAND_PAGE_SIZE_2K (3UL<<16) 5192 #define CTX_COMMAND_PAGE_SIZE_4K (4UL<<16) 5193 #define CTX_COMMAND_PAGE_SIZE_8K (5UL<<16) 5194 #define CTX_COMMAND_PAGE_SIZE_16K (6UL<<16) 5195 #define CTX_COMMAND_PAGE_SIZE_32K (7UL<<16) 5196 #define CTX_COMMAND_PAGE_SIZE_64K (8UL<<16) 5197 #define CTX_COMMAND_PAGE_SIZE_128K (9UL<<16) 5198 #define CTX_COMMAND_PAGE_SIZE_256K (10UL<<16) 5199 #define CTX_COMMAND_PAGE_SIZE_512K (11UL<<16) 5200 #define CTX_COMMAND_PAGE_SIZE_1M (12UL<<16) 5201 5202 u32_t ctx_status; 5203 #define CTX_STATUS_LOCK_WAIT (1UL<<0) 5204 #define CTX_STATUS_READ_STAT (1UL<<16) 5205 #define CTX_STATUS_WRITE_STAT (1UL<<17) 5206 #define CTX_STATUS_ACC_STALL_STAT (1UL<<18) 5207 #define CTX_STATUS_LOCK_STALL_STAT (1UL<<19) 5208 #define CTX_STATUS_EXT_READ_STAT (1UL<<20) 5209 #define CTX_STATUS_EXT_WRITE_STAT (1UL<<21) 5210 #define CTX_STATUS_MISS_STAT (1UL<<22) 5211 #define CTX_STATUS_HIT_STAT (1UL<<23) 5212 #define CTX_STATUS_DEAD_LOCK (1UL<<24) 5213 #define CTX_STATUS_USAGE_CNT_ERR (1UL<<25) 5214 #define CTX_STATUS_INVALID_PAGE (1UL<<26) 5215 5216 u32_t ctx_virt_addr; 5217 #define CTX_VIRT_ADDR_VIRT_ADDR (0x7fffUL<<6) 5218 5219 u32_t ctx_page_tbl; 5220 #define CTX_PAGE_TBL_PAGE_TBL (0x3fffUL<<6) 5221 5222 u32_t ctx_data_adr; 5223 #define CTX_DATA_ADR_DATA_ADR (0x7ffffUL<<2) 5224 5225 u32_t ctx_data; 5226 u32_t ctx_lock; 5227 #define CTX_LOCK_TYPE (0x7UL<<0) 5228 #define CTX_LOCK_TYPE_LOCK_TYPE_VOID_TE (0UL<<0) 5229 #define CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL_TE (1UL<<0) 5230 #define CTX_LOCK_TYPE_LOCK_TYPE_TX_TE (2UL<<0) 5231 #define CTX_LOCK_TYPE_LOCK_TYPE_TIMER_TE (4UL<<0) 5232 #define CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE_TE (7UL<<0) 5233 #define CTX_LOCK_TYPE_VOID_XI (0UL<<0) 5234 #define CTX_LOCK_TYPE_PROTOCOL_XI (1UL<<0) 5235 #define CTX_LOCK_TYPE_TX_XI (2UL<<0) 5236 #define CTX_LOCK_TYPE_TIMER_XI (4UL<<0) 5237 #define CTX_LOCK_TYPE_COMPLETE_XI (7UL<<0) 5238 #define CTX_LOCK_CID_VALUE (0x3fffUL<<7) 5239 #define CTX_LOCK_GRANTED (1UL<<26) 5240 #define CTX_LOCK_MODE (0x7UL<<27) 5241 #define CTX_LOCK_MODE_UNLOCK (0UL<<27) 5242 #define CTX_LOCK_MODE_IMMEDIATE (1UL<<27) 5243 #define CTX_LOCK_MODE_SURE (2UL<<27) 5244 #define CTX_LOCK_STATUS (1UL<<30) 5245 #define CTX_LOCK_REQ (1UL<<31) 5246 5247 u32_t ctx_ctx_ctrl; 5248 #define CTX_CTX_CTRL_CTX_ADDR (0x7ffffUL<<2) 5249 #define CTX_CTX_CTRL_MOD_USAGE_CNT (0x3UL<<21) 5250 #define CTX_CTX_CTRL_NO_RAM_ACC (1UL<<23) 5251 #define CTX_CTX_CTRL_PREFETCH_SIZE (0x3UL<<24) 5252 #define CTX_CTX_CTRL_ATTR (1UL<<26) 5253 #define CTX_CTX_CTRL_WRITE_REQ (1UL<<30) 5254 #define CTX_CTX_CTRL_READ_REQ (1UL<<31) 5255 5256 u32_t ctx_ctx_data; 5257 u32_t unused_0[7]; 5258 u32_t ctx_access_status; 5259 #define CTX_ACCESS_STATUS_MASTERENCODED_TE (0xfUL<<0) 5260 #define CTX_ACCESS_STATUS_ACCESSMEMORYSM_TE (0x3UL<<10) 5261 #define CTX_ACCESS_STATUS_PAGETABLEINITSM_TE (0x3UL<<12) 5262 #define CTX_ACCESS_STATUS_ACCESSMEMORYINITSM_TE (0x3UL<<14) 5263 #define CTX_ACCESS_STATUS_QUALIFIED_REQUEST_TE (0x7ffUL<<17) 5264 #define CTX_ACCESS_STATUS_CAMMASTERENCODED_XI (0x1fUL<<0) 5265 #define CTX_ACCESS_STATUS_CACHEMASTERENCODED_XI (0x1fUL<<5) 5266 #define CTX_ACCESS_STATUS_REQUEST_XI (0x3fffffUL<<10) 5267 5268 u32_t ctx_dbg_lock_status; 5269 #define CTX_DBG_LOCK_STATUS_SM (0x3ffUL<<0) 5270 #define CTX_DBG_LOCK_STATUS_MATCH (0x3ffUL<<22) 5271 5272 u32_t ctx_cache_ctrl_status; 5273 #define CTX_CACHE_CTRL_STATUS_RFIFO_OVERFLOW (1UL<<0) 5274 #define CTX_CACHE_CTRL_STATUS_INVALID_READ_COMP (1UL<<1) 5275 #define CTX_CACHE_CTRL_STATUS_FLUSH_START (1UL<<6) 5276 #define CTX_CACHE_CTRL_STATUS_FREE_ENTRY_CNT (0x3fUL<<7) 5277 #define CTX_CACHE_CTRL_STATUS_CACHE_ENTRY_NEEDED (0x3fUL<<13) 5278 #define CTX_CACHE_CTRL_STATUS_RD_CHAN0_ACTIVE (1UL<<19) 5279 #define CTX_CACHE_CTRL_STATUS_RD_CHAN1_ACTIVE (1UL<<20) 5280 #define CTX_CACHE_CTRL_STATUS_RD_CHAN2_ACTIVE (1UL<<21) 5281 #define CTX_CACHE_CTRL_STATUS_RD_CHAN3_ACTIVE (1UL<<22) 5282 #define CTX_CACHE_CTRL_STATUS_RD_CHAN4_ACTIVE (1UL<<23) 5283 #define CTX_CACHE_CTRL_STATUS_RD_CHAN5_ACTIVE (1UL<<24) 5284 #define CTX_CACHE_CTRL_STATUS_RD_CHAN6_ACTIVE (1UL<<25) 5285 #define CTX_CACHE_CTRL_STATUS_RD_CHAN7_ACTIVE (1UL<<26) 5286 #define CTX_CACHE_CTRL_STATUS_RD_CHAN8_ACTIVE (1UL<<27) 5287 #define CTX_CACHE_CTRL_STATUS_RD_CHAN9_ACTIVE (1UL<<28) 5288 #define CTX_CACHE_CTRL_STATUS_RD_CHAN10_ACTIVE (1UL<<29) 5289 5290 u32_t ctx_cache_ctrl_sm_status; 5291 #define CTX_CACHE_CTRL_SM_STATUS_CS_DWC (0x7UL<<0) 5292 #define CTX_CACHE_CTRL_SM_STATUS_CS_WFIFOC (0x7UL<<3) 5293 #define CTX_CACHE_CTRL_SM_STATUS_CS_RTAGC (0x7UL<<6) 5294 #define CTX_CACHE_CTRL_SM_STATUS_CS_RFIFOC (0x7UL<<9) 5295 #define CTX_CACHE_CTRL_SM_STATUS_INVALID_BLK_ADDR (0x7fffUL<<16) 5296 5297 u32_t ctx_cache_status; 5298 #define CTX_CACHE_STATUS_HELD_ENTRIES (0x3ffUL<<0) 5299 #define CTX_CACHE_STATUS_MAX_HELD_ENTRIES (0x3ffUL<<16) 5300 5301 u32_t ctx_dma_status; 5302 #define CTX_DMA_STATUS_RD_CHAN0_STATUS (0x3UL<<0) 5303 #define CTX_DMA_STATUS_RD_CHAN1_STATUS (0x3UL<<2) 5304 #define CTX_DMA_STATUS_RD_CHAN2_STATUS (0x3UL<<4) 5305 #define CTX_DMA_STATUS_RD_CHAN3_STATUS (0x3UL<<6) 5306 #define CTX_DMA_STATUS_RD_CHAN4_STATUS (0x3UL<<8) 5307 #define CTX_DMA_STATUS_RD_CHAN5_STATUS (0x3UL<<10) 5308 #define CTX_DMA_STATUS_RD_CHAN6_STATUS (0x3UL<<12) 5309 #define CTX_DMA_STATUS_RD_CHAN7_STATUS (0x3UL<<14) 5310 #define CTX_DMA_STATUS_RD_CHAN8_STATUS (0x3UL<<16) 5311 #define CTX_DMA_STATUS_RD_CHAN9_STATUS (0x3UL<<18) 5312 #define CTX_DMA_STATUS_RD_CHAN10_STATUS (0x3UL<<20) 5313 5314 u32_t ctx_rep_status; 5315 #define CTX_REP_STATUS_ERROR_ENTRY (0x3ffUL<<0) 5316 #define CTX_REP_STATUS_ERROR_CLIENT_ID (0x1fUL<<10) 5317 #define CTX_REP_STATUS_USAGE_CNT_MAX_ERR (1UL<<16) 5318 #define CTX_REP_STATUS_USAGE_CNT_MIN_ERR (1UL<<17) 5319 #define CTX_REP_STATUS_USAGE_CNT_MISS_ERR (1UL<<18) 5320 5321 u32_t ctx_cksum_error_status; 5322 #define CTX_CKSUM_ERROR_STATUS_CALCULATED (0xffffUL<<0) 5323 #define CTX_CKSUM_ERROR_STATUS_EXPECTED (0xffffUL<<16) 5324 5325 u32_t unused_1[8]; 5326 u32_t ctx_chnl_lock_status_0; 5327 #define CTX_CHNL_LOCK_STATUS_0_CID (0x3fffUL<<0) 5328 #define CTX_CHNL_LOCK_STATUS_0_TYPE_TE (0x3UL<<14) 5329 #define CTX_CHNL_LOCK_STATUS_0_MODE_TE (1UL<<16) 5330 #define CTX_CHNL_LOCK_STATUS_0_MODE_XI (1UL<<14) 5331 #define CTX_CHNL_LOCK_STATUS_0_TYPE_XI (0x7UL<<15) 5332 5333 u32_t ctx_chnl_lock_status_1; 5334 u32_t ctx_chnl_lock_status_2; 5335 u32_t ctx_chnl_lock_status_3; 5336 u32_t ctx_chnl_lock_status_4; 5337 u32_t ctx_chnl_lock_status_5; 5338 u32_t ctx_chnl_lock_status_6; 5339 u32_t ctx_chnl_lock_status_7; 5340 u32_t ctx_chnl_lock_status_8; 5341 u32_t ctx_chnl_lock_status_9; 5342 u32_t ctx_debug_sm; 5343 u32_t unused_2[5]; 5344 u32_t ctx_cache_ctrl; 5345 #define CTX_CACHE_CTRL_CACHE_ADDR (0x3fffUL<<2) 5346 #define CTX_CACHE_CTRL_WRITE_REQ (1UL<<30) 5347 #define CTX_CACHE_CTRL_READ_REQ (1UL<<31) 5348 5349 u32_t ctx_cache_data; 5350 u32_t ctx_host_page_tbl_ctrl; 5351 #define CTX_HOST_PAGE_TBL_CTRL_PAGE_TBL_ADDR (0x1ffUL<<0) 5352 #define CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ (1UL<<30) 5353 #define CTX_HOST_PAGE_TBL_CTRL_READ_REQ (1UL<<31) 5354 5355 u32_t ctx_host_page_tbl_data0; 5356 #define CTX_HOST_PAGE_TBL_DATA0_VALID (1UL<<0) 5357 #define CTX_HOST_PAGE_TBL_DATA0_VALUE (0xffffffUL<<8) 5358 5359 u32_t ctx_host_page_tbl_data1; 5360 u32_t ctx_cam_ctrl; 5361 #define CTX_CAM_CTRL_CAM_ADDR (0x3ffUL<<0) 5362 #define CTX_CAM_CTRL_RESET (1UL<<27) 5363 #define CTX_CAM_CTRL_INVALIDATE (1UL<<28) 5364 #define CTX_CAM_CTRL_SEARCH (1UL<<29) 5365 #define CTX_CAM_CTRL_WRITE_REQ (1UL<<30) 5366 #define CTX_CAM_CTRL_READ_REQ (1UL<<31) 5367 5368 u32_t ctx_cam_data; 5369 #define CTX_CAM_DATA_CAM_DATA (0xffffUL<<0) 5370 5371 u32_t ctx_mirror_ctrl; 5372 #define CTX_MIRROR_CTRL_MIRROR_ADDR (0x3ffUL<<0) 5373 #define CTX_MIRROR_CTRL_WRITE_REQ (1UL<<30) 5374 #define CTX_MIRROR_CTRL_READ_REQ (1UL<<31) 5375 5376 u32_t ctx_mirror_data; 5377 #define CTX_MIRROR_DATA_MIRROR_DATA (0x7fffUL<<0) 5378 5379 u32_t ctx_usage_cnt_ctrl; 5380 #define CTX_USAGE_CNT_CTRL_USAGE_CNT_ADDR (0x3ffUL<<0) 5381 #define CTX_USAGE_CNT_CTRL_WRITE_REQ (1UL<<30) 5382 #define CTX_USAGE_CNT_CTRL_READ_REQ (1UL<<31) 5383 5384 u32_t ctx_usage_cnt_data; 5385 #define CTX_USAGE_CNT_DATA_USAGE_CNT_DATA (0x7fUL<<0) 5386 #define CTX_USAGE_CNT_DATA_USAGE_CNT_ZERO (1UL<<7) 5387 5388 u32_t unused_3[191]; 5389 u32_t ctx_cam_bist_command; 5390 #define CTX_CAM_BIST_COMMAND_BIST_RST_B (1UL<<0) 5391 #define CTX_CAM_BIST_COMMAND_BIST_EN (1UL<<1) 5392 #define CTX_CAM_BIST_COMMAND_BIST_DONE (1UL<<2) 5393 #define CTX_CAM_BIST_COMMAND_BIST_PASSED (1UL<<3) 5394 5395 u32_t ctx_cam_bist_status0; 5396 #define CTX_CAM_BIST_STATUS0_MATCH_STATUS (1UL<<0) 5397 #define CTX_CAM_BIST_STATUS0_ACTUAL_BITPOS (0xfUL<<1) 5398 #define CTX_CAM_BIST_STATUS0_ACTUAL_ADDROUT (0x3ffUL<<5) 5399 5400 u32_t ctx_cam_bist_status1; 5401 #define CTX_CAM_BIST_STATUS1_MATCH_STATUS (1UL<<0) 5402 #define CTX_CAM_BIST_STATUS1_ADDROUT_STATUS (1UL<<1) 5403 #define CTX_CAM_BIST_STATUS1_ACTUAL_ADDROUT (0x3ffUL<<2) 5404 #define CTX_CAM_BIST_STATUS1_EXPECTED_ADDROUT (0x3ffUL<<12) 5405 5406 u32_t ctx_cam_bist_status2; 5407 #define CTX_CAM_BIST_STATUS2_MATCH_STATUS (1UL<<0) 5408 #define CTX_CAM_BIST_STATUS2_ACTUAL_BITPOS (0xfUL<<1) 5409 #define CTX_CAM_BIST_STATUS2_ACTUAL_ADDROUT (0x3ffUL<<5) 5410 5411 u32_t ctx_cam_bist_status3; 5412 #define CTX_CAM_BIST_STATUS3_MATCH_STATUS (1UL<<0) 5413 #define CTX_CAM_BIST_STATUS3_ADDROUT_STATUS (1UL<<1) 5414 #define CTX_CAM_BIST_STATUS3_ACTUAL_ADDROUT (0x3ffUL<<2) 5415 #define CTX_CAM_BIST_STATUS3_EXPECTED_ADDROUT (0x3ffUL<<12) 5416 5417 u32_t ctx_cam_bist_status4; 5418 #define CTX_CAM_BIST_STATUS4_MATCH_STATUS (1UL<<0) 5419 #define CTX_CAM_BIST_STATUS4_ACTUAL_ADDROUT (0x3ffUL<<1) 5420 5421 } context_reg_t; 5422 5423 5424 /* 5425 * emac_reg definition 5426 * offset: 0x1400 5427 */ 5428 typedef struct emac_reg 5429 { 5430 u32_t emac_mode; 5431 #define EMAC_MODE_RESET (1UL<<0) 5432 #define EMAC_MODE_HALF_DUPLEX (1UL<<1) 5433 #define EMAC_MODE_PORT (0x3UL<<2) 5434 #define EMAC_MODE_PORT_NONE (0UL<<2) 5435 #define EMAC_MODE_PORT_MII (1UL<<2) 5436 #define EMAC_MODE_PORT_GMII (2UL<<2) 5437 #define EMAC_MODE_PORT_MII_10M (3UL<<2) 5438 #define EMAC_MODE_MAC_LOOP (1UL<<4) 5439 #define EMAC_MODE_25G_MODE (1UL<<5) 5440 #define EMAC_MODE_TAGGED_MAC_CTL (1UL<<7) 5441 #define EMAC_MODE_TX_BURST (1UL<<8) 5442 #define EMAC_MODE_MAX_DEFER_DROP_ENA (1UL<<9) 5443 #define EMAC_MODE_EXT_LINK_POL (1UL<<10) 5444 #define EMAC_MODE_FORCE_LINK (1UL<<11) 5445 #define EMAC_MODE_SERDES_MODE (1UL<<12) 5446 #define EMAC_MODE_BOND_OVRD (1UL<<13) 5447 #define EMAC_MODE_MPKT (1UL<<18) 5448 #define EMAC_MODE_MPKT_RCVD (1UL<<19) 5449 #define EMAC_MODE_ACPI_RCVD (1UL<<20) 5450 5451 u32_t emac_status; 5452 #define EMAC_STATUS_LINK (1UL<<11) 5453 #define EMAC_STATUS_LINK_CHANGE (1UL<<12) 5454 #define EMAC_STATUS_SERDES_AUTONEG_COMPLETE (1UL<<13) 5455 #define EMAC_STATUS_SERDES_AUTONEG_CHANGE (1UL<<14) 5456 #define EMAC_STATUS_SERDES_NXT_PG_CHANGE (1UL<<16) 5457 #define EMAC_STATUS_SERDES_RX_CONFIG_IS_0 (1UL<<17) 5458 #define EMAC_STATUS_SERDES_RX_CONFIG_IS_0_CHANGE (1UL<<18) 5459 #define EMAC_STATUS_MI_COMPLETE (1UL<<22) 5460 #define EMAC_STATUS_MI_INT (1UL<<23) 5461 #define EMAC_STATUS_AP_ERROR (1UL<<24) 5462 #define EMAC_STATUS_PARITY_ERROR_STATE (1UL<<31) 5463 5464 u32_t emac_attention_ena; 5465 #define EMAC_ATTENTION_ENA_LINK (1UL<<11) 5466 #define EMAC_ATTENTION_ENA_AUTONEG_CHANGE (1UL<<14) 5467 #define EMAC_ATTENTION_ENA_NXT_PG_CHANGE (1UL<<16) 5468 #define EMAC_ATTENTION_ENA_SERDES_RX_CONFIG_IS_0_CHANGE (1UL<<18) 5469 #define EMAC_ATTENTION_ENA_MI_COMPLETE (1UL<<22) 5470 #define EMAC_ATTENTION_ENA_MI_INT (1UL<<23) 5471 #define EMAC_ATTENTION_ENA_AP_ERROR (1UL<<24) 5472 5473 u32_t emac_led; 5474 #define EMAC_LED_OVERRIDE (1UL<<0) 5475 #define EMAC_LED_1000MB_OVERRIDE (1UL<<1) 5476 #define EMAC_LED_100MB_OVERRIDE (1UL<<2) 5477 #define EMAC_LED_10MB_OVERRIDE (1UL<<3) 5478 #define EMAC_LED_TRAFFIC_OVERRIDE (1UL<<4) 5479 #define EMAC_LED_BLNK_TRAFFIC (1UL<<5) 5480 #define EMAC_LED_TRAFFIC (1UL<<6) 5481 #define EMAC_LED_1000MB (1UL<<7) 5482 #define EMAC_LED_100MB (1UL<<8) 5483 #define EMAC_LED_10MB (1UL<<9) 5484 #define EMAC_LED_TRAFFIC_STAT (1UL<<10) 5485 #define EMAC_LED_2500MB (1UL<<11) 5486 #define EMAC_LED_2500MB_OVERRIDE (1UL<<12) 5487 #define EMAC_LED_ACTIVITY_SEL (0x3UL<<17) 5488 #define EMAC_LED_ACTIVITY_SEL_0 (0UL<<17) 5489 #define EMAC_LED_ACTIVITY_SEL_1 (1UL<<17) 5490 #define EMAC_LED_ACTIVITY_SEL_2 (2UL<<17) 5491 #define EMAC_LED_ACTIVITY_SEL_3 (3UL<<17) 5492 #define EMAC_LED_BLNK_RATE (0xfffUL<<19) 5493 #define EMAC_LED_BLNK_RATE_ENA (1UL<<31) 5494 5495 u32_t emac_mac_match[32]; 5496 u32_t unused_0[2]; 5497 u32_t emac_backoff_seed; 5498 #define EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffUL<<0) 5499 5500 u32_t emac_rx_mtu_size; 5501 #define EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffUL<<0) 5502 #define EMAC_RX_MTU_SIZE_JUMBO_ENA (1UL<<31) 5503 5504 u32_t unused_1[3]; 5505 u32_t emac_mdio_comm; 5506 #define EMAC_MDIO_COMM_DATA (0xffffUL<<0) 5507 #define EMAC_MDIO_COMM_REG_ADDR (0x1fUL<<16) 5508 #define EMAC_MDIO_COMM_PHY_ADDR (0x1fUL<<21) 5509 #define EMAC_MDIO_COMM_COMMAND (0x3UL<<26) 5510 #define EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0UL<<26) 5511 #define EMAC_MDIO_COMM_COMMAND_ADDRESS (0UL<<26) 5512 #define EMAC_MDIO_COMM_COMMAND_WRITE_TE (1UL<<26) 5513 #define EMAC_MDIO_COMM_COMMAND_READ_TE (2UL<<26) 5514 #define EMAC_MDIO_COMM_COMMAND_WRITE_22_XI (1UL<<26) 5515 #define EMAC_MDIO_COMM_COMMAND_WRITE_45_XI (1UL<<26) 5516 #define EMAC_MDIO_COMM_COMMAND_READ_22_XI (2UL<<26) 5517 #define EMAC_MDIO_COMM_COMMAND_READ_INC_45_XI (2UL<<26) 5518 #define EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3UL<<26) 5519 #define EMAC_MDIO_COMM_COMMAND_READ_45 (3UL<<26) 5520 #define EMAC_MDIO_COMM_FAIL (1UL<<28) 5521 #define EMAC_MDIO_COMM_START_BUSY (1UL<<29) 5522 #define EMAC_MDIO_COMM_DISEXT (1UL<<30) 5523 5524 u32_t emac_mdio_status; 5525 #define EMAC_MDIO_STATUS_LINK (1UL<<0) 5526 #define EMAC_MDIO_STATUS_10MB (1UL<<1) 5527 5528 u32_t emac_mdio_mode; 5529 #define EMAC_MDIO_MODE_SHORT_PREAMBLE (1UL<<1) 5530 #define EMAC_MDIO_MODE_AUTO_POLL (1UL<<4) 5531 #define EMAC_MDIO_MODE_BIT_BANG (1UL<<8) 5532 #define EMAC_MDIO_MODE_MDIO (1UL<<9) 5533 #define EMAC_MDIO_MODE_MDIO_OE (1UL<<10) 5534 #define EMAC_MDIO_MODE_MDC (1UL<<11) 5535 #define EMAC_MDIO_MODE_MDINT (1UL<<12) 5536 #define EMAC_MDIO_MODE_EXT_MDINT (1UL<<13) 5537 #define EMAC_MDIO_MODE_CLOCK_CNT_TE (0x1fUL<<16) 5538 #define EMAC_MDIO_MODE_CLOCK_CNT_XI (0x3fUL<<16) 5539 #define EMAC_MDIO_MODE_CLAUSE_45_XI (1UL<<31) 5540 5541 u32_t emac_mdio_auto_status; 5542 #define EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1UL<<0) 5543 5544 u32_t emac_tx_mode; 5545 #define EMAC_TX_MODE_RESET (1UL<<0) 5546 #define EMAC_TX_MODE_CS16_TEST (1UL<<2) 5547 #define EMAC_TX_MODE_EXT_PAUSE_EN (1UL<<3) 5548 #define EMAC_TX_MODE_FLOW_EN (1UL<<4) 5549 #define EMAC_TX_MODE_BIG_BACKOFF (1UL<<5) 5550 #define EMAC_TX_MODE_LONG_PAUSE (1UL<<6) 5551 #define EMAC_TX_MODE_LINK_AWARE (1UL<<7) 5552 5553 u32_t emac_tx_status; 5554 #define EMAC_TX_STATUS_XOFFED (1UL<<0) 5555 #define EMAC_TX_STATUS_XOFF_SENT (1UL<<1) 5556 #define EMAC_TX_STATUS_XON_SENT (1UL<<2) 5557 #define EMAC_TX_STATUS_LINK_UP (1UL<<3) 5558 #define EMAC_TX_STATUS_UNDERRUN (1UL<<4) 5559 #define EMAC_TX_STATUS_CS16_ERROR (1UL<<5) 5560 5561 u32_t emac_tx_lengths; 5562 #define EMAC_TX_LENGTHS_SLOT (0xffUL<<0) 5563 #define EMAC_TX_LENGTHS_IPG (0xfUL<<8) 5564 #define EMAC_TX_LENGTHS_IPG_CRS (0x3UL<<12) 5565 5566 u32_t emac_rx_mode; 5567 #define EMAC_RX_MODE_RESET (1UL<<0) 5568 #define EMAC_RX_MODE_FLOW_EN (1UL<<2) 5569 #define EMAC_RX_MODE_KEEP_MAC_CONTROL (1UL<<3) 5570 #define EMAC_RX_MODE_KEEP_PAUSE (1UL<<4) 5571 #define EMAC_RX_MODE_ACCEPT_OVERSIZE (1UL<<5) 5572 #define EMAC_RX_MODE_ACCEPT_RUNTS (1UL<<6) 5573 #define EMAC_RX_MODE_LLC_CHK (1UL<<7) 5574 #define EMAC_RX_MODE_PROMISCUOUS (1UL<<8) 5575 #define EMAC_RX_MODE_NO_CRC_CHK (1UL<<9) 5576 #define EMAC_RX_MODE_KEEP_VLAN_TAG (1UL<<10) 5577 #define EMAC_RX_MODE_FILT_BROADCAST (1UL<<11) 5578 #define EMAC_RX_MODE_SORT_MODE (1UL<<12) 5579 5580 u32_t emac_rx_status; 5581 #define EMAC_RX_STATUS_FFED (1UL<<0) 5582 #define EMAC_RX_STATUS_FF_RECEIVED (1UL<<1) 5583 #define EMAC_RX_STATUS_N_RECEIVED (1UL<<2) 5584 5585 u32_t emac_multicast_hash[8]; 5586 u32_t emac_cksum_error_status; 5587 #define EMAC_CKSUM_ERROR_STATUS_CALCULATED (0xffffUL<<0) 5588 #define EMAC_CKSUM_ERROR_STATUS_EXPECTED (0xffffUL<<16) 5589 5590 u32_t unused_2[3]; 5591 u32_t emac_rx_stat_ifhcinoctets; 5592 u32_t emac_rx_stat_ifhcinbadoctets; 5593 u32_t emac_rx_stat_etherstatsfragments; 5594 u32_t emac_rx_stat_ifhcinucastpkts; 5595 u32_t emac_rx_stat_ifhcinmulticastpkts; 5596 u32_t emac_rx_stat_ifhcinbroadcastpkts; 5597 u32_t emac_rx_stat_dot3statsfcserrors; 5598 u32_t emac_rx_stat_dot3statsalignmenterrors; 5599 u32_t emac_rx_stat_dot3statscarriersenseerrors; 5600 u32_t emac_rx_stat_xonpauseframesreceived; 5601 u32_t emac_rx_stat_xoffpauseframesreceived; 5602 u32_t emac_rx_stat_maccontrolframesreceived; 5603 u32_t emac_rx_stat_xoffstateentered; 5604 u32_t emac_rx_stat_dot3statsframestoolong; 5605 u32_t emac_rx_stat_etherstatsjabbers; 5606 u32_t emac_rx_stat_etherstatsundersizepkts; 5607 u32_t emac_rx_stat_etherstatspkts64octets; 5608 u32_t emac_rx_stat_etherstatspkts65octetsto127octets; 5609 u32_t emac_rx_stat_etherstatspkts128octetsto255octets; 5610 u32_t emac_rx_stat_etherstatspkts256octetsto511octets; 5611 u32_t emac_rx_stat_etherstatspkts512octetsto1023octets; 5612 u32_t emac_rx_stat_etherstatspkts1024octetsto1522octets; 5613 u32_t emac_rx_stat_etherstatspktsover1522octets; 5614 u32_t emac_rxmac_debug0; 5615 u32_t emac_rxmac_debug1; 5616 #define EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1UL<<0) 5617 #define EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1UL<<1) 5618 #define EMAC_RXMAC_DEBUG1_BAD_CRC (1UL<<2) 5619 #define EMAC_RXMAC_DEBUG1_RX_ERROR (1UL<<3) 5620 #define EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1UL<<4) 5621 #define EMAC_RXMAC_DEBUG1_LAST_DATA (1UL<<5) 5622 #define EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1UL<<6) 5623 #define EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffUL<<7) 5624 #define EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffUL<<23) 5625 5626 u32_t emac_rxmac_debug2; 5627 #define EMAC_RXMAC_DEBUG2_SM_STATE (0x7UL<<0) 5628 #define EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0UL<<0) 5629 #define EMAC_RXMAC_DEBUG2_SM_STATE_SFD (1UL<<0) 5630 #define EMAC_RXMAC_DEBUG2_SM_STATE_DATA (2UL<<0) 5631 #define EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (3UL<<0) 5632 #define EMAC_RXMAC_DEBUG2_SM_STATE_EXT (4UL<<0) 5633 #define EMAC_RXMAC_DEBUG2_SM_STATE_DROP (5UL<<0) 5634 #define EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (6UL<<0) 5635 #define EMAC_RXMAC_DEBUG2_SM_STATE_FC (7UL<<0) 5636 #define EMAC_RXMAC_DEBUG2_IDI_STATE (0xfUL<<3) 5637 #define EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0UL<<3) 5638 #define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (1UL<<3) 5639 #define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (2UL<<3) 5640 #define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (3UL<<3) 5641 #define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (4UL<<3) 5642 #define EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (5UL<<3) 5643 #define EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (6UL<<3) 5644 #define EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (7UL<<3) 5645 #define EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (8UL<<3) 5646 #define EMAC_RXMAC_DEBUG2_BYTE_IN (0xffUL<<7) 5647 #define EMAC_RXMAC_DEBUG2_FALSEC (1UL<<15) 5648 #define EMAC_RXMAC_DEBUG2_TAGGED (1UL<<16) 5649 #define EMAC_RXMAC_DEBUG2_PAUSE_STATE (1UL<<18) 5650 #define EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0UL<<18) 5651 #define EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1UL<<18) 5652 #define EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfUL<<19) 5653 #define EMAC_RXMAC_DEBUG2_QUANTA (0x1fUL<<23) 5654 5655 u32_t emac_rxmac_debug3; 5656 #define EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffUL<<0) 5657 #define EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffUL<<16) 5658 5659 u32_t emac_rxmac_debug4; 5660 #define EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffUL<<0) 5661 #define EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fUL<<16) 5662 #define EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0UL<<16) 5663 #define EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (1UL<<16) 5664 #define EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (2UL<<16) 5665 #define EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (3UL<<16) 5666 #define EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (5UL<<16) 5667 #define EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (6UL<<16) 5668 #define EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (7UL<<16) 5669 #define EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (7UL<<16) 5670 #define EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (8UL<<16) 5671 #define EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (9UL<<16) 5672 #define EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (10UL<<16) 5673 #define EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (14UL<<16) 5674 #define EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (15UL<<16) 5675 #define EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (16UL<<16) 5676 #define EMAC_RXMAC_DEBUG4_FILT_STATE_MC (17UL<<16) 5677 #define EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (18UL<<16) 5678 #define EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (19UL<<16) 5679 #define EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (20UL<<16) 5680 #define EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (21UL<<16) 5681 #define EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (22UL<<16) 5682 #define EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (23UL<<16) 5683 #define EMAC_RXMAC_DEBUG4_FILT_STATE_BC (24UL<<16) 5684 #define EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (25UL<<16) 5685 #define EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (26UL<<16) 5686 #define EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (27UL<<16) 5687 #define EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (28UL<<16) 5688 #define EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (29UL<<16) 5689 #define EMAC_RXMAC_DEBUG4_FILT_STATE_XON (30UL<<16) 5690 #define EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (31UL<<16) 5691 #define EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (32UL<<16) 5692 #define EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (33UL<<16) 5693 #define EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (34UL<<16) 5694 #define EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (35UL<<16) 5695 #define EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (36UL<<16) 5696 #define EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (37UL<<16) 5697 #define EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (38UL<<16) 5698 #define EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (39UL<<16) 5699 #define EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (40UL<<16) 5700 #define EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (41UL<<16) 5701 #define EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (42UL<<16) 5702 #define EMAC_RXMAC_DEBUG4_DROP_PKT (1UL<<22) 5703 #define EMAC_RXMAC_DEBUG4_SLOT_FILLED (1UL<<23) 5704 #define EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1UL<<24) 5705 #define EMAC_RXMAC_DEBUG4_LAST_DATA (1UL<<25) 5706 #define EMAC_RXMAC_DEBUG4_SFD_FOUND (1UL<<26) 5707 #define EMAC_RXMAC_DEBUG4_ADVANCE (1UL<<27) 5708 #define EMAC_RXMAC_DEBUG4_START (1UL<<28) 5709 5710 u32_t emac_rxmac_debug5; 5711 #define EMAC_RXMAC_DEBUG5_PS_IDISM (0x7UL<<0) 5712 #define EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0UL<<0) 5713 #define EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1UL<<0) 5714 #define EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2UL<<0) 5715 #define EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3UL<<0) 5716 #define EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4UL<<0) 5717 #define EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5UL<<0) 5718 #define EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6UL<<0) 5719 #define EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7UL<<4) 5720 #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0UL<<4) 5721 #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (1UL<<4) 5722 #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (2UL<<4) 5723 #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (3UL<<4) 5724 #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (4UL<<4) 5725 #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (6UL<<4) 5726 #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (7UL<<4) 5727 #define EMAC_RXMAC_DEBUG5_EOF_DETECTED (1UL<<7) 5728 #define EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7UL<<8) 5729 #define EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1UL<<11) 5730 #define EMAC_RXMAC_DEBUG5_LOAD_CCODE (1UL<<12) 5731 #define EMAC_RXMAC_DEBUG5_LOAD_DATA (1UL<<13) 5732 #define EMAC_RXMAC_DEBUG5_LOAD_STAT (1UL<<14) 5733 #define EMAC_RXMAC_DEBUG5_CLR_STAT (1UL<<15) 5734 #define EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3UL<<16) 5735 #define EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1UL<<19) 5736 #define EMAC_RXMAC_DEBUG5_FMLEN (0xfffUL<<20) 5737 5738 u32_t emac_rx_stat_falsecarriererrors; 5739 u32_t unused_3[2]; 5740 u32_t emac_rx_stat_ac[23]; 5741 u32_t emac_rxmac_suc_dbg_overrunvec; 5742 u32_t unused_4[5]; 5743 u32_t emac_rx_stat_ac_28; 5744 u32_t unused_5[2]; 5745 u32_t emac_tx_stat_ifhcoutoctets; 5746 u32_t emac_tx_stat_ifhcoutbadoctets; 5747 u32_t emac_tx_stat_etherstatscollisions; 5748 u32_t emac_tx_stat_outxonsent; 5749 u32_t emac_tx_stat_outxoffsent; 5750 u32_t emac_tx_stat_flowcontroldone; 5751 u32_t emac_tx_stat_dot3statssinglecollisionframes; 5752 u32_t emac_tx_stat_dot3statsmultiplecollisionframes; 5753 u32_t emac_tx_stat_dot3statsdeferredtransmissions; 5754 u32_t emac_tx_stat_dot3statsexcessivecollisions; 5755 u32_t emac_tx_stat_dot3statslatecollisions; 5756 u32_t emac_tx_stat_ifhcoutucastpkts; 5757 u32_t emac_tx_stat_ifhcoutmulticastpkts; 5758 u32_t emac_tx_stat_ifhcoutbroadcastpkts; 5759 u32_t emac_tx_stat_etherstatspkts64octets; 5760 u32_t emac_tx_stat_etherstatspkts65octetsto127octets; 5761 u32_t emac_tx_stat_etherstatspkts128octetsto255octets; 5762 u32_t emac_tx_stat_etherstatspkts256octetsto511octets; 5763 u32_t emac_tx_stat_etherstatspkts512octetsto1023octets; 5764 u32_t emac_tx_stat_etherstatspkts1024octetsto1522octets; 5765 u32_t emac_tx_stat_etherstatspktsover1522octets; 5766 u32_t emac_tx_stat_dot3statsinternalmactransmiterrors; 5767 u32_t emac_txmac_debug0; 5768 u32_t emac_txmac_debug1; 5769 #define EMAC_TXMAC_DEBUG1_ODI_STATE (0xfUL<<0) 5770 #define EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0UL<<0) 5771 #define EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (1UL<<0) 5772 #define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (4UL<<0) 5773 #define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (5UL<<0) 5774 #define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (6UL<<0) 5775 #define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (7UL<<0) 5776 #define EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (8UL<<0) 5777 #define EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (9UL<<0) 5778 #define EMAC_TXMAC_DEBUG1_CRS_ENABLE (1UL<<4) 5779 #define EMAC_TXMAC_DEBUG1_BAD_CRC (1UL<<5) 5780 #define EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfUL<<6) 5781 #define EMAC_TXMAC_DEBUG1_SEND_PAUSE (1UL<<10) 5782 #define EMAC_TXMAC_DEBUG1_LATE_COLLISION (1UL<<11) 5783 #define EMAC_TXMAC_DEBUG1_MAX_DEFER (1UL<<12) 5784 #define EMAC_TXMAC_DEBUG1_DEFERRED (1UL<<13) 5785 #define EMAC_TXMAC_DEBUG1_ONE_BYTE (1UL<<14) 5786 #define EMAC_TXMAC_DEBUG1_IPG_TIME (0xfUL<<15) 5787 #define EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffUL<<19) 5788 5789 u32_t emac_txmac_debug2; 5790 #define EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffUL<<0) 5791 #define EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffUL<<10) 5792 #define EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fUL<<26) 5793 #define EMAC_TXMAC_DEBUG2_COL_BIT (1UL<<31) 5794 5795 u32_t emac_txmac_debug3; 5796 #define EMAC_TXMAC_DEBUG3_SM_STATE (0xfUL<<0) 5797 #define EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0UL<<0) 5798 #define EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (1UL<<0) 5799 #define EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (2UL<<0) 5800 #define EMAC_TXMAC_DEBUG3_SM_STATE_SFD (3UL<<0) 5801 #define EMAC_TXMAC_DEBUG3_SM_STATE_DATA (4UL<<0) 5802 #define EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (5UL<<0) 5803 #define EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (6UL<<0) 5804 #define EMAC_TXMAC_DEBUG3_SM_STATE_EXT (7UL<<0) 5805 #define EMAC_TXMAC_DEBUG3_SM_STATE_STATB (8UL<<0) 5806 #define EMAC_TXMAC_DEBUG3_SM_STATE_STATG (9UL<<0) 5807 #define EMAC_TXMAC_DEBUG3_SM_STATE_JAM (10UL<<0) 5808 #define EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (11UL<<0) 5809 #define EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (12UL<<0) 5810 #define EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (13UL<<0) 5811 #define EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (14UL<<0) 5812 #define EMAC_TXMAC_DEBUG3_FILT_STATE (0x7UL<<4) 5813 #define EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0UL<<4) 5814 #define EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (1UL<<4) 5815 #define EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (2UL<<4) 5816 #define EMAC_TXMAC_DEBUG3_FILT_STATE_MC (3UL<<4) 5817 #define EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (4UL<<4) 5818 #define EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (5UL<<4) 5819 #define EMAC_TXMAC_DEBUG3_FILT_STATE_BC (6UL<<4) 5820 #define EMAC_TXMAC_DEBUG3_CRS_DONE (1UL<<7) 5821 #define EMAC_TXMAC_DEBUG3_XOFF (1UL<<8) 5822 #define EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfUL<<9) 5823 #define EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fUL<<13) 5824 5825 u32_t emac_txmac_debug4; 5826 #define EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffUL<<0) 5827 #define EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfUL<<16) 5828 #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0UL<<16) 5829 #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (2UL<<16) 5830 #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (3UL<<16) 5831 #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (4UL<<16) 5832 #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (5UL<<16) 5833 #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (6UL<<16) 5834 #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (7UL<<16) 5835 #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (8UL<<16) 5836 #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (9UL<<16) 5837 #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (10UL<<16) 5838 #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (12UL<<16) 5839 #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (13UL<<16) 5840 #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (14UL<<16) 5841 #define EMAC_TXMAC_DEBUG4_STATS0_VALID (1UL<<20) 5842 #define EMAC_TXMAC_DEBUG4_APPEND_CRC (1UL<<21) 5843 #define EMAC_TXMAC_DEBUG4_SLOT_FILLED (1UL<<22) 5844 #define EMAC_TXMAC_DEBUG4_MAX_DEFER (1UL<<23) 5845 #define EMAC_TXMAC_DEBUG4_SEND_EXTEND (1UL<<24) 5846 #define EMAC_TXMAC_DEBUG4_SEND_PADDING (1UL<<25) 5847 #define EMAC_TXMAC_DEBUG4_EOF_LOC (1UL<<26) 5848 #define EMAC_TXMAC_DEBUG4_COLLIDING (1UL<<27) 5849 #define EMAC_TXMAC_DEBUG4_COL_IN (1UL<<28) 5850 #define EMAC_TXMAC_DEBUG4_BURSTING (1UL<<29) 5851 #define EMAC_TXMAC_DEBUG4_ADVANCE (1UL<<30) 5852 #define EMAC_TXMAC_DEBUG4_GO (1UL<<31) 5853 5854 u32_t unused_6[5]; 5855 u32_t emac_tx_stat_ac[22]; 5856 u32_t emac_txmac_suc_dbg_overrunvec; 5857 u32_t unused_7[8]; 5858 u32_t emac_tx_rate_limit_ctrl; 5859 #define EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_INC (0x7fUL<<0) 5860 #define EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_NUM (0x7fUL<<16) 5861 #define EMAC_TX_RATE_LIMIT_CTRL_RATE_LIMITER_EN (1UL<<31) 5862 5863 u32_t unused_8[64]; 5864 } emac_reg_t; 5865 5866 5867 /* 5868 * rpm_reg definition 5869 * offset: 0x1800 5870 */ 5871 typedef struct rpm_reg 5872 { 5873 u32_t rpm_command; 5874 #define RPM_COMMAND_ENABLED (1UL<<0) 5875 #define RPM_COMMAND_OVERRUN_ABORT (1UL<<4) 5876 5877 u32_t rpm_status; 5878 #define RPM_STATUS_MBUF_WAIT (1UL<<0) 5879 #define RPM_STATUS_FREE_WAIT (1UL<<1) 5880 5881 u32_t rpm_config; 5882 #define RPM_CONFIG_NO_PSD_HDR_CKSUM (1UL<<0) 5883 #define RPM_CONFIG_ACPI_ENA (1UL<<1) 5884 #define RPM_CONFIG_ACPI_KEEP (1UL<<2) 5885 #define RPM_CONFIG_MP_KEEP (1UL<<3) 5886 #define RPM_CONFIG_SORT_VECT_VAL (0xfUL<<4) 5887 #define RPM_CONFIG_DISABLE_WOL_ASSERT (1UL<<30) 5888 #define RPM_CONFIG_IGNORE_VLAN (1UL<<31) 5889 5890 u32_t rpm_mgmt_pkt_ctrl; 5891 #define RPM_MGMT_PKT_CTRL_MGMT_SORT (0xfUL<<0) 5892 #define RPM_MGMT_PKT_CTRL_MGMT_RULE (0xfUL<<4) 5893 #define RPM_MGMT_PKT_CTRL_MGMT_DISCARD_EN (1UL<<30) 5894 #define RPM_MGMT_PKT_CTRL_MGMT_EN (1UL<<31) 5895 5896 u32_t rpm_vlan_match0; 5897 #define RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffUL<<0) 5898 5899 u32_t rpm_vlan_match1; 5900 #define RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffUL<<0) 5901 5902 u32_t rpm_vlan_match2; 5903 #define RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffUL<<0) 5904 5905 u32_t rpm_vlan_match3; 5906 #define RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffUL<<0) 5907 5908 u32_t rpm_sort_user0; 5909 #define RPM_SORT_USER0_PM_EN (0xffffUL<<0) 5910 #define RPM_SORT_USER0_BC_EN (1UL<<16) 5911 #define RPM_SORT_USER0_MC_EN (1UL<<17) 5912 #define RPM_SORT_USER0_MC_HSH_EN (1UL<<18) 5913 #define RPM_SORT_USER0_PROM_EN (1UL<<19) 5914 #define RPM_SORT_USER0_VLAN_EN (0xfUL<<20) 5915 #define RPM_SORT_USER0_PROM_VLAN (1UL<<24) 5916 #define RPM_SORT_USER0_VLAN_NOTMATCH (1UL<<25) 5917 #define RPM_SORT_USER0_ENA (1UL<<31) 5918 5919 u32_t rpm_sort_user1; 5920 #define RPM_SORT_USER1_PM_EN (0xffffUL<<0) 5921 #define RPM_SORT_USER1_BC_EN (1UL<<16) 5922 #define RPM_SORT_USER1_MC_EN (1UL<<17) 5923 #define RPM_SORT_USER1_MC_HSH_EN (1UL<<18) 5924 #define RPM_SORT_USER1_PROM_EN (1UL<<19) 5925 #define RPM_SORT_USER1_VLAN_EN (0xfUL<<20) 5926 #define RPM_SORT_USER1_PROM_VLAN (1UL<<24) 5927 #define RPM_SORT_USER1_ENA (1UL<<31) 5928 5929 u32_t rpm_sort_user2; 5930 #define RPM_SORT_USER2_PM_EN (0xffffUL<<0) 5931 #define RPM_SORT_USER2_BC_EN (1UL<<16) 5932 #define RPM_SORT_USER2_MC_EN (1UL<<17) 5933 #define RPM_SORT_USER2_MC_HSH_EN (1UL<<18) 5934 #define RPM_SORT_USER2_PROM_EN (1UL<<19) 5935 #define RPM_SORT_USER2_VLAN_EN (0xfUL<<20) 5936 #define RPM_SORT_USER2_PROM_VLAN (1UL<<24) 5937 #define RPM_SORT_USER2_ENA (1UL<<31) 5938 5939 u32_t rpm_sort_user3; 5940 #define RPM_SORT_USER3_PM_EN (0xffffUL<<0) 5941 #define RPM_SORT_USER3_BC_EN (1UL<<16) 5942 #define RPM_SORT_USER3_MC_EN (1UL<<17) 5943 #define RPM_SORT_USER3_MC_HSH_EN (1UL<<18) 5944 #define RPM_SORT_USER3_PROM_EN (1UL<<19) 5945 #define RPM_SORT_USER3_VLAN_EN (0xfUL<<20) 5946 #define RPM_SORT_USER3_PROM_VLAN (1UL<<24) 5947 #define RPM_SORT_USER3_ENA (1UL<<31) 5948 5949 u32_t unused_0[4]; 5950 u32_t rpm_stat_l2_filter_discards; 5951 u32_t rpm_stat_rule_checker_discards; 5952 u32_t rpm_stat_ifinftqdiscards; 5953 u32_t rpm_stat_ifinmbufdiscard; 5954 u32_t rpm_stat_rule_checker_p4_hit; 5955 u32_t rpm_ipv6_programmable_extension0; 5956 #define RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN (0xffUL<<0) 5957 #define RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER (0xffUL<<16) 5958 #define RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN_TYPE (1UL<<30) 5959 #define RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_EN (1UL<<31) 5960 5961 u32_t rpm_ipv6_programmable_extension1; 5962 #define RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN (0xffUL<<0) 5963 #define RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER (0xffUL<<16) 5964 #define RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN_TYPE (1UL<<30) 5965 #define RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_EN (1UL<<31) 5966 5967 u32_t rpm_ipv6_programmable_extension2; 5968 #define RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN (0xffUL<<0) 5969 #define RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER (0xffUL<<16) 5970 #define RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN_TYPE (1UL<<30) 5971 #define RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_EN (1UL<<31) 5972 5973 u32_t rpm_ipv6_programmable_extension3; 5974 #define RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN (0xffUL<<0) 5975 #define RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER (0xffUL<<16) 5976 #define RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN_TYPE (1UL<<30) 5977 #define RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_EN (1UL<<31) 5978 5979 u32_t rpm_ipv6_programmable_extension4; 5980 #define RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN (0xffUL<<0) 5981 #define RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER (0xffUL<<16) 5982 #define RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN_TYPE (1UL<<30) 5983 #define RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_EN (1UL<<31) 5984 5985 u32_t rpm_ipv6_programmable_extension5; 5986 #define RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN (0xffUL<<0) 5987 #define RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER (0xffUL<<16) 5988 #define RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN_TYPE (1UL<<30) 5989 #define RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_EN (1UL<<31) 5990 5991 u32_t rpm_ipv6_programmable_extension6; 5992 #define RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN (0xffUL<<0) 5993 #define RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER (0xffUL<<16) 5994 #define RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN_TYPE (1UL<<30) 5995 #define RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_EN (1UL<<31) 5996 5997 u32_t rpm_ipv6_programmable_extension7; 5998 #define RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN (0xffUL<<0) 5999 #define RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER (0xffUL<<16) 6000 #define RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN_TYPE (1UL<<30) 6001 #define RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_EN (1UL<<31) 6002 6003 u32_t unused_1[3]; 6004 u32_t rpm_stat_ac[5]; 6005 u32_t unused_2[19]; 6006 u32_t rpm_rc_cntl_16; 6007 #define RPM_RC_CNTL_16_OFFSET (0xffUL<<0) 6008 #define RPM_RC_CNTL_16_CLASS (0x7UL<<8) 6009 #define RPM_RC_CNTL_16_PRIORITY (1UL<<11) 6010 #define RPM_RC_CNTL_16_P4 (1UL<<12) 6011 #define RPM_RC_CNTL_16_HDR_TYPE (0x7UL<<13) 6012 #define RPM_RC_CNTL_16_HDR_TYPE_START (0UL<<13) 6013 #define RPM_RC_CNTL_16_HDR_TYPE_IP (1UL<<13) 6014 #define RPM_RC_CNTL_16_HDR_TYPE_TCP (2UL<<13) 6015 #define RPM_RC_CNTL_16_HDR_TYPE_UDP (3UL<<13) 6016 #define RPM_RC_CNTL_16_HDR_TYPE_DATA (4UL<<13) 6017 #define RPM_RC_CNTL_16_HDR_TYPE_TCP_UDP (5UL<<13) 6018 #define RPM_RC_CNTL_16_HDR_TYPE_ICMPV6 (6UL<<13) 6019 #define RPM_RC_CNTL_16_COMP (0x3UL<<16) 6020 #define RPM_RC_CNTL_16_COMP_EQUAL (0UL<<16) 6021 #define RPM_RC_CNTL_16_COMP_NEQUAL (1UL<<16) 6022 #define RPM_RC_CNTL_16_COMP_GREATER (2UL<<16) 6023 #define RPM_RC_CNTL_16_COMP_LESS (3UL<<16) 6024 #define RPM_RC_CNTL_16_MAP (1UL<<18) 6025 #define RPM_RC_CNTL_16_SBIT (1UL<<19) 6026 #define RPM_RC_CNTL_16_CMDSEL (0x1fUL<<20) 6027 #define RPM_RC_CNTL_16_DISCARD (1UL<<25) 6028 #define RPM_RC_CNTL_16_MASK (1UL<<26) 6029 #define RPM_RC_CNTL_16_P1 (1UL<<27) 6030 #define RPM_RC_CNTL_16_P2 (1UL<<28) 6031 #define RPM_RC_CNTL_16_P3 (1UL<<29) 6032 #define RPM_RC_CNTL_16_NBIT (1UL<<30) 6033 6034 u32_t rpm_rc_value_mask_16; 6035 #define RPM_RC_VALUE_MASK_16_VALUE (0xffffUL<<0) 6036 #define RPM_RC_VALUE_MASK_16_MASK (0xffffUL<<16) 6037 6038 u32_t rpm_rc_cntl_17; 6039 #define RPM_RC_CNTL_17_OFFSET (0xffUL<<0) 6040 #define RPM_RC_CNTL_17_CLASS (0x7UL<<8) 6041 #define RPM_RC_CNTL_17_PRIORITY (1UL<<11) 6042 #define RPM_RC_CNTL_17_P4 (1UL<<12) 6043 #define RPM_RC_CNTL_17_HDR_TYPE (0x7UL<<13) 6044 #define RPM_RC_CNTL_17_HDR_TYPE_START (0UL<<13) 6045 #define RPM_RC_CNTL_17_HDR_TYPE_IP (1UL<<13) 6046 #define RPM_RC_CNTL_17_HDR_TYPE_TCP (2UL<<13) 6047 #define RPM_RC_CNTL_17_HDR_TYPE_UDP (3UL<<13) 6048 #define RPM_RC_CNTL_17_HDR_TYPE_DATA (4UL<<13) 6049 #define RPM_RC_CNTL_17_HDR_TYPE_TCP_UDP (5UL<<13) 6050 #define RPM_RC_CNTL_17_HDR_TYPE_ICMPV6 (6UL<<13) 6051 #define RPM_RC_CNTL_17_COMP (0x3UL<<16) 6052 #define RPM_RC_CNTL_17_COMP_EQUAL (0UL<<16) 6053 #define RPM_RC_CNTL_17_COMP_NEQUAL (1UL<<16) 6054 #define RPM_RC_CNTL_17_COMP_GREATER (2UL<<16) 6055 #define RPM_RC_CNTL_17_COMP_LESS (3UL<<16) 6056 #define RPM_RC_CNTL_17_MAP (1UL<<18) 6057 #define RPM_RC_CNTL_17_SBIT (1UL<<19) 6058 #define RPM_RC_CNTL_17_CMDSEL (0x1fUL<<20) 6059 #define RPM_RC_CNTL_17_DISCARD (1UL<<25) 6060 #define RPM_RC_CNTL_17_MASK (1UL<<26) 6061 #define RPM_RC_CNTL_17_P1 (1UL<<27) 6062 #define RPM_RC_CNTL_17_P2 (1UL<<28) 6063 #define RPM_RC_CNTL_17_P3 (1UL<<29) 6064 #define RPM_RC_CNTL_17_NBIT (1UL<<30) 6065 6066 u32_t rpm_rc_value_mask_17; 6067 #define RPM_RC_VALUE_MASK_17_VALUE (0xffffUL<<0) 6068 #define RPM_RC_VALUE_MASK_17_MASK (0xffffUL<<16) 6069 6070 u32_t rpm_rc_cntl_18; 6071 #define RPM_RC_CNTL_18_OFFSET (0xffUL<<0) 6072 #define RPM_RC_CNTL_18_CLASS (0x7UL<<8) 6073 #define RPM_RC_CNTL_18_PRIORITY (1UL<<11) 6074 #define RPM_RC_CNTL_18_P4 (1UL<<12) 6075 #define RPM_RC_CNTL_18_HDR_TYPE (0x7UL<<13) 6076 #define RPM_RC_CNTL_18_HDR_TYPE_START (0UL<<13) 6077 #define RPM_RC_CNTL_18_HDR_TYPE_IP (1UL<<13) 6078 #define RPM_RC_CNTL_18_HDR_TYPE_TCP (2UL<<13) 6079 #define RPM_RC_CNTL_18_HDR_TYPE_UDP (3UL<<13) 6080 #define RPM_RC_CNTL_18_HDR_TYPE_DATA (4UL<<13) 6081 #define RPM_RC_CNTL_18_HDR_TYPE_TCP_UDP (5UL<<13) 6082 #define RPM_RC_CNTL_18_HDR_TYPE_ICMPV6 (6UL<<13) 6083 #define RPM_RC_CNTL_18_COMP (0x3UL<<16) 6084 #define RPM_RC_CNTL_18_COMP_EQUAL (0UL<<16) 6085 #define RPM_RC_CNTL_18_COMP_NEQUAL (1UL<<16) 6086 #define RPM_RC_CNTL_18_COMP_GREATER (2UL<<16) 6087 #define RPM_RC_CNTL_18_COMP_LESS (3UL<<16) 6088 #define RPM_RC_CNTL_18_MAP (1UL<<18) 6089 #define RPM_RC_CNTL_18_SBIT (1UL<<19) 6090 #define RPM_RC_CNTL_18_CMDSEL (0x1fUL<<20) 6091 #define RPM_RC_CNTL_18_DISCARD (1UL<<25) 6092 #define RPM_RC_CNTL_18_MASK (1UL<<26) 6093 #define RPM_RC_CNTL_18_P1 (1UL<<27) 6094 #define RPM_RC_CNTL_18_P2 (1UL<<28) 6095 #define RPM_RC_CNTL_18_P3 (1UL<<29) 6096 #define RPM_RC_CNTL_18_NBIT (1UL<<30) 6097 6098 u32_t rpm_rc_value_mask_18; 6099 #define RPM_RC_VALUE_MASK_18_VALUE (0xffffUL<<0) 6100 #define RPM_RC_VALUE_MASK_18_MASK (0xffffUL<<16) 6101 6102 u32_t rpm_rc_cntl_19; 6103 #define RPM_RC_CNTL_19_OFFSET (0xffUL<<0) 6104 #define RPM_RC_CNTL_19_CLASS (0x7UL<<8) 6105 #define RPM_RC_CNTL_19_PRIORITY (1UL<<11) 6106 #define RPM_RC_CNTL_19_P4 (1UL<<12) 6107 #define RPM_RC_CNTL_19_HDR_TYPE (0x7UL<<13) 6108 #define RPM_RC_CNTL_19_HDR_TYPE_START (0UL<<13) 6109 #define RPM_RC_CNTL_19_HDR_TYPE_IP (1UL<<13) 6110 #define RPM_RC_CNTL_19_HDR_TYPE_TCP (2UL<<13) 6111 #define RPM_RC_CNTL_19_HDR_TYPE_UDP (3UL<<13) 6112 #define RPM_RC_CNTL_19_HDR_TYPE_DATA (4UL<<13) 6113 #define RPM_RC_CNTL_19_HDR_TYPE_TCP_UDP (5UL<<13) 6114 #define RPM_RC_CNTL_19_HDR_TYPE_ICMPV6 (6UL<<13) 6115 #define RPM_RC_CNTL_19_COMP (0x3UL<<16) 6116 #define RPM_RC_CNTL_19_COMP_EQUAL (0UL<<16) 6117 #define RPM_RC_CNTL_19_COMP_NEQUAL (1UL<<16) 6118 #define RPM_RC_CNTL_19_COMP_GREATER (2UL<<16) 6119 #define RPM_RC_CNTL_19_COMP_LESS (3UL<<16) 6120 #define RPM_RC_CNTL_19_MAP (1UL<<18) 6121 #define RPM_RC_CNTL_19_SBIT (1UL<<19) 6122 #define RPM_RC_CNTL_19_CMDSEL (0x1fUL<<20) 6123 #define RPM_RC_CNTL_19_DISCARD (1UL<<25) 6124 #define RPM_RC_CNTL_19_MASK (1UL<<26) 6125 #define RPM_RC_CNTL_19_P1 (1UL<<27) 6126 #define RPM_RC_CNTL_19_P2 (1UL<<28) 6127 #define RPM_RC_CNTL_19_P3 (1UL<<29) 6128 #define RPM_RC_CNTL_19_NBIT (1UL<<30) 6129 6130 u32_t rpm_rc_value_mask_19; 6131 #define RPM_RC_VALUE_MASK_19_VALUE (0xffffUL<<0) 6132 #define RPM_RC_VALUE_MASK_19_MASK (0xffffUL<<16) 6133 6134 u32_t rpm_rc_cntl_0; 6135 #define RPM_RC_CNTL_0_OFFSET (0xffUL<<0) 6136 #define RPM_RC_CNTL_0_CLASS (0x7UL<<8) 6137 #define RPM_RC_CNTL_0_PRIORITY (1UL<<11) 6138 #define RPM_RC_CNTL_0_P4 (1UL<<12) 6139 #define RPM_RC_CNTL_0_HDR_TYPE (0x7UL<<13) 6140 #define RPM_RC_CNTL_0_HDR_TYPE_START (0UL<<13) 6141 #define RPM_RC_CNTL_0_HDR_TYPE_IP (1UL<<13) 6142 #define RPM_RC_CNTL_0_HDR_TYPE_TCP (2UL<<13) 6143 #define RPM_RC_CNTL_0_HDR_TYPE_UDP (3UL<<13) 6144 #define RPM_RC_CNTL_0_HDR_TYPE_DATA (4UL<<13) 6145 #define RPM_RC_CNTL_0_HDR_TYPE_TCP_UDP (5UL<<13) 6146 #define RPM_RC_CNTL_0_HDR_TYPE_ICMPV6 (6UL<<13) 6147 #define RPM_RC_CNTL_0_COMP (0x3UL<<16) 6148 #define RPM_RC_CNTL_0_COMP_EQUAL (0UL<<16) 6149 #define RPM_RC_CNTL_0_COMP_NEQUAL (1UL<<16) 6150 #define RPM_RC_CNTL_0_COMP_GREATER (2UL<<16) 6151 #define RPM_RC_CNTL_0_COMP_LESS (3UL<<16) 6152 #define RPM_RC_CNTL_0_MAP_XI (1UL<<18) 6153 #define RPM_RC_CNTL_0_SBIT (1UL<<19) 6154 #define RPM_RC_CNTL_0_CMDSEL_TE (0xfUL<<20) 6155 #define RPM_RC_CNTL_0_MAP_TE (1UL<<24) 6156 #define RPM_RC_CNTL_0_CMDSEL_XI (0x1fUL<<20) 6157 #define RPM_RC_CNTL_0_DISCARD (1UL<<25) 6158 #define RPM_RC_CNTL_0_MASK (1UL<<26) 6159 #define RPM_RC_CNTL_0_P1 (1UL<<27) 6160 #define RPM_RC_CNTL_0_P2 (1UL<<28) 6161 #define RPM_RC_CNTL_0_P3 (1UL<<29) 6162 #define RPM_RC_CNTL_0_NBIT (1UL<<30) 6163 6164 u32_t rpm_rc_value_mask_0; 6165 #define RPM_RC_VALUE_MASK_0_VALUE (0xffffUL<<0) 6166 #define RPM_RC_VALUE_MASK_0_MASK (0xffffUL<<16) 6167 6168 u32_t rpm_rc_cntl_1; 6169 #define RPM_RC_CNTL_1_A_TE (0x3ffffUL<<0) 6170 #define RPM_RC_CNTL_1_B_TE (0xfffUL<<19) 6171 #define RPM_RC_CNTL_1_OFFSET_XI (0xffUL<<0) 6172 #define RPM_RC_CNTL_1_CLASS_XI (0x7UL<<8) 6173 #define RPM_RC_CNTL_1_PRIORITY_XI (1UL<<11) 6174 #define RPM_RC_CNTL_1_P4_XI (1UL<<12) 6175 #define RPM_RC_CNTL_1_HDR_TYPE_XI (0x7UL<<13) 6176 #define RPM_RC_CNTL_1_HDR_TYPE_START_XI (0UL<<13) 6177 #define RPM_RC_CNTL_1_HDR_TYPE_IP_XI (1UL<<13) 6178 #define RPM_RC_CNTL_1_HDR_TYPE_TCP_XI (2UL<<13) 6179 #define RPM_RC_CNTL_1_HDR_TYPE_UDP_XI (3UL<<13) 6180 #define RPM_RC_CNTL_1_HDR_TYPE_DATA_XI (4UL<<13) 6181 #define RPM_RC_CNTL_1_HDR_TYPE_TCP_UDP_XI (5UL<<13) 6182 #define RPM_RC_CNTL_1_HDR_TYPE_ICMPV6_XI (6UL<<13) 6183 #define RPM_RC_CNTL_1_COMP_XI (0x3UL<<16) 6184 #define RPM_RC_CNTL_1_COMP_EQUAL_XI (0UL<<16) 6185 #define RPM_RC_CNTL_1_COMP_NEQUAL_XI (1UL<<16) 6186 #define RPM_RC_CNTL_1_COMP_GREATER_XI (2UL<<16) 6187 #define RPM_RC_CNTL_1_COMP_LESS_XI (3UL<<16) 6188 #define RPM_RC_CNTL_1_MAP_XI (1UL<<18) 6189 #define RPM_RC_CNTL_1_SBIT_XI (1UL<<19) 6190 #define RPM_RC_CNTL_1_CMDSEL_XI (0x1fUL<<20) 6191 #define RPM_RC_CNTL_1_DISCARD_XI (1UL<<25) 6192 #define RPM_RC_CNTL_1_MASK_XI (1UL<<26) 6193 #define RPM_RC_CNTL_1_P1_XI (1UL<<27) 6194 #define RPM_RC_CNTL_1_P2_XI (1UL<<28) 6195 #define RPM_RC_CNTL_1_P3_XI (1UL<<29) 6196 #define RPM_RC_CNTL_1_NBIT_XI (1UL<<30) 6197 6198 u32_t rpm_rc_value_mask_1; 6199 #define RPM_RC_VALUE_MASK_1_VALUE (0xffffUL<<0) 6200 #define RPM_RC_VALUE_MASK_1_MASK (0xffffUL<<16) 6201 6202 u32_t rpm_rc_cntl_2; 6203 #define RPM_RC_CNTL_2_A_TE (0x3ffffUL<<0) 6204 #define RPM_RC_CNTL_2_B_TE (0xfffUL<<19) 6205 #define RPM_RC_CNTL_2_OFFSET_XI (0xffUL<<0) 6206 #define RPM_RC_CNTL_2_CLASS_XI (0x7UL<<8) 6207 #define RPM_RC_CNTL_2_PRIORITY_XI (1UL<<11) 6208 #define RPM_RC_CNTL_2_P4_XI (1UL<<12) 6209 #define RPM_RC_CNTL_2_HDR_TYPE_XI (0x7UL<<13) 6210 #define RPM_RC_CNTL_2_HDR_TYPE_START_XI (0UL<<13) 6211 #define RPM_RC_CNTL_2_HDR_TYPE_IP_XI (1UL<<13) 6212 #define RPM_RC_CNTL_2_HDR_TYPE_TCP_XI (2UL<<13) 6213 #define RPM_RC_CNTL_2_HDR_TYPE_UDP_XI (3UL<<13) 6214 #define RPM_RC_CNTL_2_HDR_TYPE_DATA_XI (4UL<<13) 6215 #define RPM_RC_CNTL_2_HDR_TYPE_TCP_UDP_XI (5UL<<13) 6216 #define RPM_RC_CNTL_2_HDR_TYPE_ICMPV6_XI (6UL<<13) 6217 #define RPM_RC_CNTL_2_COMP_XI (0x3UL<<16) 6218 #define RPM_RC_CNTL_2_COMP_EQUAL_XI (0UL<<16) 6219 #define RPM_RC_CNTL_2_COMP_NEQUAL_XI (1UL<<16) 6220 #define RPM_RC_CNTL_2_COMP_GREATER_XI (2UL<<16) 6221 #define RPM_RC_CNTL_2_COMP_LESS_XI (3UL<<16) 6222 #define RPM_RC_CNTL_2_MAP_XI (1UL<<18) 6223 #define RPM_RC_CNTL_2_SBIT_XI (1UL<<19) 6224 #define RPM_RC_CNTL_2_CMDSEL_XI (0x1fUL<<20) 6225 #define RPM_RC_CNTL_2_DISCARD_XI (1UL<<25) 6226 #define RPM_RC_CNTL_2_MASK_XI (1UL<<26) 6227 #define RPM_RC_CNTL_2_P1_XI (1UL<<27) 6228 #define RPM_RC_CNTL_2_P2_XI (1UL<<28) 6229 #define RPM_RC_CNTL_2_P3_XI (1UL<<29) 6230 #define RPM_RC_CNTL_2_NBIT_XI (1UL<<30) 6231 6232 u32_t rpm_rc_value_mask_2; 6233 #define RPM_RC_VALUE_MASK_2_VALUE (0xffffUL<<0) 6234 #define RPM_RC_VALUE_MASK_2_MASK (0xffffUL<<16) 6235 6236 u32_t rpm_rc_cntl_3; 6237 #define RPM_RC_CNTL_3_A_TE (0x3ffffUL<<0) 6238 #define RPM_RC_CNTL_3_B_TE (0xfffUL<<19) 6239 #define RPM_RC_CNTL_3_OFFSET_XI (0xffUL<<0) 6240 #define RPM_RC_CNTL_3_CLASS_XI (0x7UL<<8) 6241 #define RPM_RC_CNTL_3_PRIORITY_XI (1UL<<11) 6242 #define RPM_RC_CNTL_3_P4_XI (1UL<<12) 6243 #define RPM_RC_CNTL_3_HDR_TYPE_XI (0x7UL<<13) 6244 #define RPM_RC_CNTL_3_HDR_TYPE_START_XI (0UL<<13) 6245 #define RPM_RC_CNTL_3_HDR_TYPE_IP_XI (1UL<<13) 6246 #define RPM_RC_CNTL_3_HDR_TYPE_TCP_XI (2UL<<13) 6247 #define RPM_RC_CNTL_3_HDR_TYPE_UDP_XI (3UL<<13) 6248 #define RPM_RC_CNTL_3_HDR_TYPE_DATA_XI (4UL<<13) 6249 #define RPM_RC_CNTL_3_HDR_TYPE_TCP_UDP_XI (5UL<<13) 6250 #define RPM_RC_CNTL_3_HDR_TYPE_ICMPV6_XI (6UL<<13) 6251 #define RPM_RC_CNTL_3_COMP_XI (0x3UL<<16) 6252 #define RPM_RC_CNTL_3_COMP_EQUAL_XI (0UL<<16) 6253 #define RPM_RC_CNTL_3_COMP_NEQUAL_XI (1UL<<16) 6254 #define RPM_RC_CNTL_3_COMP_GREATER_XI (2UL<<16) 6255 #define RPM_RC_CNTL_3_COMP_LESS_XI (3UL<<16) 6256 #define RPM_RC_CNTL_3_MAP_XI (1UL<<18) 6257 #define RPM_RC_CNTL_3_SBIT_XI (1UL<<19) 6258 #define RPM_RC_CNTL_3_CMDSEL_XI (0x1fUL<<20) 6259 #define RPM_RC_CNTL_3_DISCARD_XI (1UL<<25) 6260 #define RPM_RC_CNTL_3_MASK_XI (1UL<<26) 6261 #define RPM_RC_CNTL_3_P1_XI (1UL<<27) 6262 #define RPM_RC_CNTL_3_P2_XI (1UL<<28) 6263 #define RPM_RC_CNTL_3_P3_XI (1UL<<29) 6264 #define RPM_RC_CNTL_3_NBIT_XI (1UL<<30) 6265 6266 u32_t rpm_rc_value_mask_3; 6267 #define RPM_RC_VALUE_MASK_3_VALUE (0xffffUL<<0) 6268 #define RPM_RC_VALUE_MASK_3_MASK (0xffffUL<<16) 6269 6270 u32_t rpm_rc_cntl_4; 6271 #define RPM_RC_CNTL_4_A_TE (0x3ffffUL<<0) 6272 #define RPM_RC_CNTL_4_B_TE (0xfffUL<<19) 6273 #define RPM_RC_CNTL_4_OFFSET_XI (0xffUL<<0) 6274 #define RPM_RC_CNTL_4_CLASS_XI (0x7UL<<8) 6275 #define RPM_RC_CNTL_4_PRIORITY_XI (1UL<<11) 6276 #define RPM_RC_CNTL_4_P4_XI (1UL<<12) 6277 #define RPM_RC_CNTL_4_HDR_TYPE_XI (0x7UL<<13) 6278 #define RPM_RC_CNTL_4_HDR_TYPE_START_XI (0UL<<13) 6279 #define RPM_RC_CNTL_4_HDR_TYPE_IP_XI (1UL<<13) 6280 #define RPM_RC_CNTL_4_HDR_TYPE_TCP_XI (2UL<<13) 6281 #define RPM_RC_CNTL_4_HDR_TYPE_UDP_XI (3UL<<13) 6282 #define RPM_RC_CNTL_4_HDR_TYPE_DATA_XI (4UL<<13) 6283 #define RPM_RC_CNTL_4_HDR_TYPE_TCP_UDP_XI (5UL<<13) 6284 #define RPM_RC_CNTL_4_HDR_TYPE_ICMPV6_XI (6UL<<13) 6285 #define RPM_RC_CNTL_4_COMP_XI (0x3UL<<16) 6286 #define RPM_RC_CNTL_4_COMP_EQUAL_XI (0UL<<16) 6287 #define RPM_RC_CNTL_4_COMP_NEQUAL_XI (1UL<<16) 6288 #define RPM_RC_CNTL_4_COMP_GREATER_XI (2UL<<16) 6289 #define RPM_RC_CNTL_4_COMP_LESS_XI (3UL<<16) 6290 #define RPM_RC_CNTL_4_MAP_XI (1UL<<18) 6291 #define RPM_RC_CNTL_4_SBIT_XI (1UL<<19) 6292 #define RPM_RC_CNTL_4_CMDSEL_XI (0x1fUL<<20) 6293 #define RPM_RC_CNTL_4_DISCARD_XI (1UL<<25) 6294 #define RPM_RC_CNTL_4_MASK_XI (1UL<<26) 6295 #define RPM_RC_CNTL_4_P1_XI (1UL<<27) 6296 #define RPM_RC_CNTL_4_P2_XI (1UL<<28) 6297 #define RPM_RC_CNTL_4_P3_XI (1UL<<29) 6298 #define RPM_RC_CNTL_4_NBIT_XI (1UL<<30) 6299 6300 u32_t rpm_rc_value_mask_4; 6301 #define RPM_RC_VALUE_MASK_4_VALUE (0xffffUL<<0) 6302 #define RPM_RC_VALUE_MASK_4_MASK (0xffffUL<<16) 6303 6304 u32_t rpm_rc_cntl_5; 6305 #define RPM_RC_CNTL_5_A_TE (0x3ffffUL<<0) 6306 #define RPM_RC_CNTL_5_B_TE (0xfffUL<<19) 6307 #define RPM_RC_CNTL_5_OFFSET_XI (0xffUL<<0) 6308 #define RPM_RC_CNTL_5_CLASS_XI (0x7UL<<8) 6309 #define RPM_RC_CNTL_5_PRIORITY_XI (1UL<<11) 6310 #define RPM_RC_CNTL_5_P4_XI (1UL<<12) 6311 #define RPM_RC_CNTL_5_HDR_TYPE_XI (0x7UL<<13) 6312 #define RPM_RC_CNTL_5_HDR_TYPE_START_XI (0UL<<13) 6313 #define RPM_RC_CNTL_5_HDR_TYPE_IP_XI (1UL<<13) 6314 #define RPM_RC_CNTL_5_HDR_TYPE_TCP_XI (2UL<<13) 6315 #define RPM_RC_CNTL_5_HDR_TYPE_UDP_XI (3UL<<13) 6316 #define RPM_RC_CNTL_5_HDR_TYPE_DATA_XI (4UL<<13) 6317 #define RPM_RC_CNTL_5_HDR_TYPE_TCP_UDP_XI (5UL<<13) 6318 #define RPM_RC_CNTL_5_HDR_TYPE_ICMPV6_XI (6UL<<13) 6319 #define RPM_RC_CNTL_5_COMP_XI (0x3UL<<16) 6320 #define RPM_RC_CNTL_5_COMP_EQUAL_XI (0UL<<16) 6321 #define RPM_RC_CNTL_5_COMP_NEQUAL_XI (1UL<<16) 6322 #define RPM_RC_CNTL_5_COMP_GREATER_XI (2UL<<16) 6323 #define RPM_RC_CNTL_5_COMP_LESS_XI (3UL<<16) 6324 #define RPM_RC_CNTL_5_MAP_XI (1UL<<18) 6325 #define RPM_RC_CNTL_5_SBIT_XI (1UL<<19) 6326 #define RPM_RC_CNTL_5_CMDSEL_XI (0x1fUL<<20) 6327 #define RPM_RC_CNTL_5_DISCARD_XI (1UL<<25) 6328 #define RPM_RC_CNTL_5_MASK_XI (1UL<<26) 6329 #define RPM_RC_CNTL_5_P1_XI (1UL<<27) 6330 #define RPM_RC_CNTL_5_P2_XI (1UL<<28) 6331 #define RPM_RC_CNTL_5_P3_XI (1UL<<29) 6332 #define RPM_RC_CNTL_5_NBIT_XI (1UL<<30) 6333 6334 u32_t rpm_rc_value_mask_5; 6335 #define RPM_RC_VALUE_MASK_5_VALUE (0xffffUL<<0) 6336 #define RPM_RC_VALUE_MASK_5_MASK (0xffffUL<<16) 6337 6338 u32_t rpm_rc_cntl_6; 6339 #define RPM_RC_CNTL_6_A_TE (0x3ffffUL<<0) 6340 #define RPM_RC_CNTL_6_B_TE (0xfffUL<<19) 6341 #define RPM_RC_CNTL_6_OFFSET_XI (0xffUL<<0) 6342 #define RPM_RC_CNTL_6_CLASS_XI (0x7UL<<8) 6343 #define RPM_RC_CNTL_6_PRIORITY_XI (1UL<<11) 6344 #define RPM_RC_CNTL_6_P4_XI (1UL<<12) 6345 #define RPM_RC_CNTL_6_HDR_TYPE_XI (0x7UL<<13) 6346 #define RPM_RC_CNTL_6_HDR_TYPE_START_XI (0UL<<13) 6347 #define RPM_RC_CNTL_6_HDR_TYPE_IP_XI (1UL<<13) 6348 #define RPM_RC_CNTL_6_HDR_TYPE_TCP_XI (2UL<<13) 6349 #define RPM_RC_CNTL_6_HDR_TYPE_UDP_XI (3UL<<13) 6350 #define RPM_RC_CNTL_6_HDR_TYPE_DATA_XI (4UL<<13) 6351 #define RPM_RC_CNTL_6_HDR_TYPE_TCP_UDP_XI (5UL<<13) 6352 #define RPM_RC_CNTL_6_HDR_TYPE_ICMPV6_XI (6UL<<13) 6353 #define RPM_RC_CNTL_6_COMP_XI (0x3UL<<16) 6354 #define RPM_RC_CNTL_6_COMP_EQUAL_XI (0UL<<16) 6355 #define RPM_RC_CNTL_6_COMP_NEQUAL_XI (1UL<<16) 6356 #define RPM_RC_CNTL_6_COMP_GREATER_XI (2UL<<16) 6357 #define RPM_RC_CNTL_6_COMP_LESS_XI (3UL<<16) 6358 #define RPM_RC_CNTL_6_MAP_XI (1UL<<18) 6359 #define RPM_RC_CNTL_6_SBIT_XI (1UL<<19) 6360 #define RPM_RC_CNTL_6_CMDSEL_XI (0x1fUL<<20) 6361 #define RPM_RC_CNTL_6_DISCARD_XI (1UL<<25) 6362 #define RPM_RC_CNTL_6_MASK_XI (1UL<<26) 6363 #define RPM_RC_CNTL_6_P1_XI (1UL<<27) 6364 #define RPM_RC_CNTL_6_P2_XI (1UL<<28) 6365 #define RPM_RC_CNTL_6_P3_XI (1UL<<29) 6366 #define RPM_RC_CNTL_6_NBIT_XI (1UL<<30) 6367 6368 u32_t rpm_rc_value_mask_6; 6369 #define RPM_RC_VALUE_MASK_6_VALUE (0xffffUL<<0) 6370 #define RPM_RC_VALUE_MASK_6_MASK (0xffffUL<<16) 6371 6372 u32_t rpm_rc_cntl_7; 6373 #define RPM_RC_CNTL_7_A_TE (0x3ffffUL<<0) 6374 #define RPM_RC_CNTL_7_B_TE (0xfffUL<<19) 6375 #define RPM_RC_CNTL_7_OFFSET_XI (0xffUL<<0) 6376 #define RPM_RC_CNTL_7_CLASS_XI (0x7UL<<8) 6377 #define RPM_RC_CNTL_7_PRIORITY_XI (1UL<<11) 6378 #define RPM_RC_CNTL_7_P4_XI (1UL<<12) 6379 #define RPM_RC_CNTL_7_HDR_TYPE_XI (0x7UL<<13) 6380 #define RPM_RC_CNTL_7_HDR_TYPE_START_XI (0UL<<13) 6381 #define RPM_RC_CNTL_7_HDR_TYPE_IP_XI (1UL<<13) 6382 #define RPM_RC_CNTL_7_HDR_TYPE_TCP_XI (2UL<<13) 6383 #define RPM_RC_CNTL_7_HDR_TYPE_UDP_XI (3UL<<13) 6384 #define RPM_RC_CNTL_7_HDR_TYPE_DATA_XI (4UL<<13) 6385 #define RPM_RC_CNTL_7_HDR_TYPE_TCP_UDP_XI (5UL<<13) 6386 #define RPM_RC_CNTL_7_HDR_TYPE_ICMPV6_XI (6UL<<13) 6387 #define RPM_RC_CNTL_7_COMP_XI (0x3UL<<16) 6388 #define RPM_RC_CNTL_7_COMP_EQUAL_XI (0UL<<16) 6389 #define RPM_RC_CNTL_7_COMP_NEQUAL_XI (1UL<<16) 6390 #define RPM_RC_CNTL_7_COMP_GREATER_XI (2UL<<16) 6391 #define RPM_RC_CNTL_7_COMP_LESS_XI (3UL<<16) 6392 #define RPM_RC_CNTL_7_MAP_XI (1UL<<18) 6393 #define RPM_RC_CNTL_7_SBIT_XI (1UL<<19) 6394 #define RPM_RC_CNTL_7_CMDSEL_XI (0x1fUL<<20) 6395 #define RPM_RC_CNTL_7_DISCARD_XI (1UL<<25) 6396 #define RPM_RC_CNTL_7_MASK_XI (1UL<<26) 6397 #define RPM_RC_CNTL_7_P1_XI (1UL<<27) 6398 #define RPM_RC_CNTL_7_P2_XI (1UL<<28) 6399 #define RPM_RC_CNTL_7_P3_XI (1UL<<29) 6400 #define RPM_RC_CNTL_7_NBIT_XI (1UL<<30) 6401 6402 u32_t rpm_rc_value_mask_7; 6403 #define RPM_RC_VALUE_MASK_7_VALUE (0xffffUL<<0) 6404 #define RPM_RC_VALUE_MASK_7_MASK (0xffffUL<<16) 6405 6406 u32_t rpm_rc_cntl_8; 6407 #define RPM_RC_CNTL_8_A_TE (0x3ffffUL<<0) 6408 #define RPM_RC_CNTL_8_B_TE (0xfffUL<<19) 6409 #define RPM_RC_CNTL_8_OFFSET_XI (0xffUL<<0) 6410 #define RPM_RC_CNTL_8_CLASS_XI (0x7UL<<8) 6411 #define RPM_RC_CNTL_8_PRIORITY_XI (1UL<<11) 6412 #define RPM_RC_CNTL_8_P4_XI (1UL<<12) 6413 #define RPM_RC_CNTL_8_HDR_TYPE_XI (0x7UL<<13) 6414 #define RPM_RC_CNTL_8_HDR_TYPE_START_XI (0UL<<13) 6415 #define RPM_RC_CNTL_8_HDR_TYPE_IP_XI (1UL<<13) 6416 #define RPM_RC_CNTL_8_HDR_TYPE_TCP_XI (2UL<<13) 6417 #define RPM_RC_CNTL_8_HDR_TYPE_UDP_XI (3UL<<13) 6418 #define RPM_RC_CNTL_8_HDR_TYPE_DATA_XI (4UL<<13) 6419 #define RPM_RC_CNTL_8_HDR_TYPE_TCP_UDP_XI (5UL<<13) 6420 #define RPM_RC_CNTL_8_HDR_TYPE_ICMPV6_XI (6UL<<13) 6421 #define RPM_RC_CNTL_8_COMP_XI (0x3UL<<16) 6422 #define RPM_RC_CNTL_8_COMP_EQUAL_XI (0UL<<16) 6423 #define RPM_RC_CNTL_8_COMP_NEQUAL_XI (1UL<<16) 6424 #define RPM_RC_CNTL_8_COMP_GREATER_XI (2UL<<16) 6425 #define RPM_RC_CNTL_8_COMP_LESS_XI (3UL<<16) 6426 #define RPM_RC_CNTL_8_MAP_XI (1UL<<18) 6427 #define RPM_RC_CNTL_8_SBIT_XI (1UL<<19) 6428 #define RPM_RC_CNTL_8_CMDSEL_XI (0x1fUL<<20) 6429 #define RPM_RC_CNTL_8_DISCARD_XI (1UL<<25) 6430 #define RPM_RC_CNTL_8_MASK_XI (1UL<<26) 6431 #define RPM_RC_CNTL_8_P1_XI (1UL<<27) 6432 #define RPM_RC_CNTL_8_P2_XI (1UL<<28) 6433 #define RPM_RC_CNTL_8_P3_XI (1UL<<29) 6434 #define RPM_RC_CNTL_8_NBIT_XI (1UL<<30) 6435 6436 u32_t rpm_rc_value_mask_8; 6437 #define RPM_RC_VALUE_MASK_8_VALUE (0xffffUL<<0) 6438 #define RPM_RC_VALUE_MASK_8_MASK (0xffffUL<<16) 6439 6440 u32_t rpm_rc_cntl_9; 6441 #define RPM_RC_CNTL_9_A_TE (0x3ffffUL<<0) 6442 #define RPM_RC_CNTL_9_B_TE (0xfffUL<<19) 6443 #define RPM_RC_CNTL_9_OFFSET_XI (0xffUL<<0) 6444 #define RPM_RC_CNTL_9_CLASS_XI (0x7UL<<8) 6445 #define RPM_RC_CNTL_9_PRIORITY_XI (1UL<<11) 6446 #define RPM_RC_CNTL_9_P4_XI (1UL<<12) 6447 #define RPM_RC_CNTL_9_HDR_TYPE_XI (0x7UL<<13) 6448 #define RPM_RC_CNTL_9_HDR_TYPE_START_XI (0UL<<13) 6449 #define RPM_RC_CNTL_9_HDR_TYPE_IP_XI (1UL<<13) 6450 #define RPM_RC_CNTL_9_HDR_TYPE_TCP_XI (2UL<<13) 6451 #define RPM_RC_CNTL_9_HDR_TYPE_UDP_XI (3UL<<13) 6452 #define RPM_RC_CNTL_9_HDR_TYPE_DATA_XI (4UL<<13) 6453 #define RPM_RC_CNTL_9_HDR_TYPE_TCP_UDP_XI (5UL<<13) 6454 #define RPM_RC_CNTL_9_HDR_TYPE_ICMPV6_XI (6UL<<13) 6455 #define RPM_RC_CNTL_9_COMP_XI (0x3UL<<16) 6456 #define RPM_RC_CNTL_9_COMP_EQUAL_XI (0UL<<16) 6457 #define RPM_RC_CNTL_9_COMP_NEQUAL_XI (1UL<<16) 6458 #define RPM_RC_CNTL_9_COMP_GREATER_XI (2UL<<16) 6459 #define RPM_RC_CNTL_9_COMP_LESS_XI (3UL<<16) 6460 #define RPM_RC_CNTL_9_MAP_XI (1UL<<18) 6461 #define RPM_RC_CNTL_9_SBIT_XI (1UL<<19) 6462 #define RPM_RC_CNTL_9_CMDSEL_XI (0x1fUL<<20) 6463 #define RPM_RC_CNTL_9_DISCARD_XI (1UL<<25) 6464 #define RPM_RC_CNTL_9_MASK_XI (1UL<<26) 6465 #define RPM_RC_CNTL_9_P1_XI (1UL<<27) 6466 #define RPM_RC_CNTL_9_P2_XI (1UL<<28) 6467 #define RPM_RC_CNTL_9_P3_XI (1UL<<29) 6468 #define RPM_RC_CNTL_9_NBIT_XI (1UL<<30) 6469 6470 u32_t rpm_rc_value_mask_9; 6471 #define RPM_RC_VALUE_MASK_9_VALUE (0xffffUL<<0) 6472 #define RPM_RC_VALUE_MASK_9_MASK (0xffffUL<<16) 6473 6474 u32_t rpm_rc_cntl_10; 6475 #define RPM_RC_CNTL_10_A_TE (0x3ffffUL<<0) 6476 #define RPM_RC_CNTL_10_B_TE (0xfffUL<<19) 6477 #define RPM_RC_CNTL_10_OFFSET_XI (0xffUL<<0) 6478 #define RPM_RC_CNTL_10_CLASS_XI (0x7UL<<8) 6479 #define RPM_RC_CNTL_10_PRIORITY_XI (1UL<<11) 6480 #define RPM_RC_CNTL_10_P4_XI (1UL<<12) 6481 #define RPM_RC_CNTL_10_HDR_TYPE_XI (0x7UL<<13) 6482 #define RPM_RC_CNTL_10_HDR_TYPE_START_XI (0UL<<13) 6483 #define RPM_RC_CNTL_10_HDR_TYPE_IP_XI (1UL<<13) 6484 #define RPM_RC_CNTL_10_HDR_TYPE_TCP_XI (2UL<<13) 6485 #define RPM_RC_CNTL_10_HDR_TYPE_UDP_XI (3UL<<13) 6486 #define RPM_RC_CNTL_10_HDR_TYPE_DATA_XI (4UL<<13) 6487 #define RPM_RC_CNTL_10_HDR_TYPE_TCP_UDP_XI (5UL<<13) 6488 #define RPM_RC_CNTL_10_HDR_TYPE_ICMPV6_XI (6UL<<13) 6489 #define RPM_RC_CNTL_10_COMP_XI (0x3UL<<16) 6490 #define RPM_RC_CNTL_10_COMP_EQUAL_XI (0UL<<16) 6491 #define RPM_RC_CNTL_10_COMP_NEQUAL_XI (1UL<<16) 6492 #define RPM_RC_CNTL_10_COMP_GREATER_XI (2UL<<16) 6493 #define RPM_RC_CNTL_10_COMP_LESS_XI (3UL<<16) 6494 #define RPM_RC_CNTL_10_MAP_XI (1UL<<18) 6495 #define RPM_RC_CNTL_10_SBIT_XI (1UL<<19) 6496 #define RPM_RC_CNTL_10_CMDSEL_XI (0x1fUL<<20) 6497 #define RPM_RC_CNTL_10_DISCARD_XI (1UL<<25) 6498 #define RPM_RC_CNTL_10_MASK_XI (1UL<<26) 6499 #define RPM_RC_CNTL_10_P1_XI (1UL<<27) 6500 #define RPM_RC_CNTL_10_P2_XI (1UL<<28) 6501 #define RPM_RC_CNTL_10_P3_XI (1UL<<29) 6502 #define RPM_RC_CNTL_10_NBIT_XI (1UL<<30) 6503 6504 u32_t rpm_rc_value_mask_10; 6505 #define RPM_RC_VALUE_MASK_10_VALUE (0xffffUL<<0) 6506 #define RPM_RC_VALUE_MASK_10_MASK (0xffffUL<<16) 6507 6508 u32_t rpm_rc_cntl_11; 6509 #define RPM_RC_CNTL_11_A_TE (0x3ffffUL<<0) 6510 #define RPM_RC_CNTL_11_B_TE (0xfffUL<<19) 6511 #define RPM_RC_CNTL_11_OFFSET_XI (0xffUL<<0) 6512 #define RPM_RC_CNTL_11_CLASS_XI (0x7UL<<8) 6513 #define RPM_RC_CNTL_11_PRIORITY_XI (1UL<<11) 6514 #define RPM_RC_CNTL_11_P4_XI (1UL<<12) 6515 #define RPM_RC_CNTL_11_HDR_TYPE_XI (0x7UL<<13) 6516 #define RPM_RC_CNTL_11_HDR_TYPE_START_XI (0UL<<13) 6517 #define RPM_RC_CNTL_11_HDR_TYPE_IP_XI (1UL<<13) 6518 #define RPM_RC_CNTL_11_HDR_TYPE_TCP_XI (2UL<<13) 6519 #define RPM_RC_CNTL_11_HDR_TYPE_UDP_XI (3UL<<13) 6520 #define RPM_RC_CNTL_11_HDR_TYPE_DATA_XI (4UL<<13) 6521 #define RPM_RC_CNTL_11_HDR_TYPE_TCP_UDP_XI (5UL<<13) 6522 #define RPM_RC_CNTL_11_HDR_TYPE_ICMPV6_XI (6UL<<13) 6523 #define RPM_RC_CNTL_11_COMP_XI (0x3UL<<16) 6524 #define RPM_RC_CNTL_11_COMP_EQUAL_XI (0UL<<16) 6525 #define RPM_RC_CNTL_11_COMP_NEQUAL_XI (1UL<<16) 6526 #define RPM_RC_CNTL_11_COMP_GREATER_XI (2UL<<16) 6527 #define RPM_RC_CNTL_11_COMP_LESS_XI (3UL<<16) 6528 #define RPM_RC_CNTL_11_MAP_XI (1UL<<18) 6529 #define RPM_RC_CNTL_11_SBIT_XI (1UL<<19) 6530 #define RPM_RC_CNTL_11_CMDSEL_XI (0x1fUL<<20) 6531 #define RPM_RC_CNTL_11_DISCARD_XI (1UL<<25) 6532 #define RPM_RC_CNTL_11_MASK_XI (1UL<<26) 6533 #define RPM_RC_CNTL_11_P1_XI (1UL<<27) 6534 #define RPM_RC_CNTL_11_P2_XI (1UL<<28) 6535 #define RPM_RC_CNTL_11_P3_XI (1UL<<29) 6536 #define RPM_RC_CNTL_11_NBIT_XI (1UL<<30) 6537 6538 u32_t rpm_rc_value_mask_11; 6539 #define RPM_RC_VALUE_MASK_11_VALUE (0xffffUL<<0) 6540 #define RPM_RC_VALUE_MASK_11_MASK (0xffffUL<<16) 6541 6542 u32_t rpm_rc_cntl_12; 6543 #define RPM_RC_CNTL_12_A_TE (0x3ffffUL<<0) 6544 #define RPM_RC_CNTL_12_B_TE (0xfffUL<<19) 6545 #define RPM_RC_CNTL_12_OFFSET_XI (0xffUL<<0) 6546 #define RPM_RC_CNTL_12_CLASS_XI (0x7UL<<8) 6547 #define RPM_RC_CNTL_12_PRIORITY_XI (1UL<<11) 6548 #define RPM_RC_CNTL_12_P4_XI (1UL<<12) 6549 #define RPM_RC_CNTL_12_HDR_TYPE_XI (0x7UL<<13) 6550 #define RPM_RC_CNTL_12_HDR_TYPE_START_XI (0UL<<13) 6551 #define RPM_RC_CNTL_12_HDR_TYPE_IP_XI (1UL<<13) 6552 #define RPM_RC_CNTL_12_HDR_TYPE_TCP_XI (2UL<<13) 6553 #define RPM_RC_CNTL_12_HDR_TYPE_UDP_XI (3UL<<13) 6554 #define RPM_RC_CNTL_12_HDR_TYPE_DATA_XI (4UL<<13) 6555 #define RPM_RC_CNTL_12_HDR_TYPE_TCP_UDP_XI (5UL<<13) 6556 #define RPM_RC_CNTL_12_HDR_TYPE_ICMPV6_XI (6UL<<13) 6557 #define RPM_RC_CNTL_12_COMP_XI (0x3UL<<16) 6558 #define RPM_RC_CNTL_12_COMP_EQUAL_XI (0UL<<16) 6559 #define RPM_RC_CNTL_12_COMP_NEQUAL_XI (1UL<<16) 6560 #define RPM_RC_CNTL_12_COMP_GREATER_XI (2UL<<16) 6561 #define RPM_RC_CNTL_12_COMP_LESS_XI (3UL<<16) 6562 #define RPM_RC_CNTL_12_MAP_XI (1UL<<18) 6563 #define RPM_RC_CNTL_12_SBIT_XI (1UL<<19) 6564 #define RPM_RC_CNTL_12_CMDSEL_XI (0x1fUL<<20) 6565 #define RPM_RC_CNTL_12_DISCARD_XI (1UL<<25) 6566 #define RPM_RC_CNTL_12_MASK_XI (1UL<<26) 6567 #define RPM_RC_CNTL_12_P1_XI (1UL<<27) 6568 #define RPM_RC_CNTL_12_P2_XI (1UL<<28) 6569 #define RPM_RC_CNTL_12_P3_XI (1UL<<29) 6570 #define RPM_RC_CNTL_12_NBIT_XI (1UL<<30) 6571 6572 u32_t rpm_rc_value_mask_12; 6573 #define RPM_RC_VALUE_MASK_12_VALUE (0xffffUL<<0) 6574 #define RPM_RC_VALUE_MASK_12_MASK (0xffffUL<<16) 6575 6576 u32_t rpm_rc_cntl_13; 6577 #define RPM_RC_CNTL_13_A_TE (0x3ffffUL<<0) 6578 #define RPM_RC_CNTL_13_B_TE (0xfffUL<<19) 6579 #define RPM_RC_CNTL_13_OFFSET_XI (0xffUL<<0) 6580 #define RPM_RC_CNTL_13_CLASS_XI (0x7UL<<8) 6581 #define RPM_RC_CNTL_13_PRIORITY_XI (1UL<<11) 6582 #define RPM_RC_CNTL_13_P4_XI (1UL<<12) 6583 #define RPM_RC_CNTL_13_HDR_TYPE_XI (0x7UL<<13) 6584 #define RPM_RC_CNTL_13_HDR_TYPE_START_XI (0UL<<13) 6585 #define RPM_RC_CNTL_13_HDR_TYPE_IP_XI (1UL<<13) 6586 #define RPM_RC_CNTL_13_HDR_TYPE_TCP_XI (2UL<<13) 6587 #define RPM_RC_CNTL_13_HDR_TYPE_UDP_XI (3UL<<13) 6588 #define RPM_RC_CNTL_13_HDR_TYPE_DATA_XI (4UL<<13) 6589 #define RPM_RC_CNTL_13_HDR_TYPE_TCP_UDP_XI (5UL<<13) 6590 #define RPM_RC_CNTL_13_HDR_TYPE_ICMPV6_XI (6UL<<13) 6591 #define RPM_RC_CNTL_13_COMP_XI (0x3UL<<16) 6592 #define RPM_RC_CNTL_13_COMP_EQUAL_XI (0UL<<16) 6593 #define RPM_RC_CNTL_13_COMP_NEQUAL_XI (1UL<<16) 6594 #define RPM_RC_CNTL_13_COMP_GREATER_XI (2UL<<16) 6595 #define RPM_RC_CNTL_13_COMP_LESS_XI (3UL<<16) 6596 #define RPM_RC_CNTL_13_MAP_XI (1UL<<18) 6597 #define RPM_RC_CNTL_13_SBIT_XI (1UL<<19) 6598 #define RPM_RC_CNTL_13_CMDSEL_XI (0x1fUL<<20) 6599 #define RPM_RC_CNTL_13_DISCARD_XI (1UL<<25) 6600 #define RPM_RC_CNTL_13_MASK_XI (1UL<<26) 6601 #define RPM_RC_CNTL_13_P1_XI (1UL<<27) 6602 #define RPM_RC_CNTL_13_P2_XI (1UL<<28) 6603 #define RPM_RC_CNTL_13_P3_XI (1UL<<29) 6604 #define RPM_RC_CNTL_13_NBIT_XI (1UL<<30) 6605 6606 u32_t rpm_rc_value_mask_13; 6607 #define RPM_RC_VALUE_MASK_13_VALUE (0xffffUL<<0) 6608 #define RPM_RC_VALUE_MASK_13_MASK (0xffffUL<<16) 6609 6610 u32_t rpm_rc_cntl_14; 6611 #define RPM_RC_CNTL_14_A_TE (0x3ffffUL<<0) 6612 #define RPM_RC_CNTL_14_B_TE (0xfffUL<<19) 6613 #define RPM_RC_CNTL_14_OFFSET_XI (0xffUL<<0) 6614 #define RPM_RC_CNTL_14_CLASS_XI (0x7UL<<8) 6615 #define RPM_RC_CNTL_14_PRIORITY_XI (1UL<<11) 6616 #define RPM_RC_CNTL_14_P4_XI (1UL<<12) 6617 #define RPM_RC_CNTL_14_HDR_TYPE_XI (0x7UL<<13) 6618 #define RPM_RC_CNTL_14_HDR_TYPE_START_XI (0UL<<13) 6619 #define RPM_RC_CNTL_14_HDR_TYPE_IP_XI (1UL<<13) 6620 #define RPM_RC_CNTL_14_HDR_TYPE_TCP_XI (2UL<<13) 6621 #define RPM_RC_CNTL_14_HDR_TYPE_UDP_XI (3UL<<13) 6622 #define RPM_RC_CNTL_14_HDR_TYPE_DATA_XI (4UL<<13) 6623 #define RPM_RC_CNTL_14_HDR_TYPE_TCP_UDP_XI (5UL<<13) 6624 #define RPM_RC_CNTL_14_HDR_TYPE_ICMPV6_XI (6UL<<13) 6625 #define RPM_RC_CNTL_14_COMP_XI (0x3UL<<16) 6626 #define RPM_RC_CNTL_14_COMP_EQUAL_XI (0UL<<16) 6627 #define RPM_RC_CNTL_14_COMP_NEQUAL_XI (1UL<<16) 6628 #define RPM_RC_CNTL_14_COMP_GREATER_XI (2UL<<16) 6629 #define RPM_RC_CNTL_14_COMP_LESS_XI (3UL<<16) 6630 #define RPM_RC_CNTL_14_MAP_XI (1UL<<18) 6631 #define RPM_RC_CNTL_14_SBIT_XI (1UL<<19) 6632 #define RPM_RC_CNTL_14_CMDSEL_XI (0x1fUL<<20) 6633 #define RPM_RC_CNTL_14_DISCARD_XI (1UL<<25) 6634 #define RPM_RC_CNTL_14_MASK_XI (1UL<<26) 6635 #define RPM_RC_CNTL_14_P1_XI (1UL<<27) 6636 #define RPM_RC_CNTL_14_P2_XI (1UL<<28) 6637 #define RPM_RC_CNTL_14_P3_XI (1UL<<29) 6638 #define RPM_RC_CNTL_14_NBIT_XI (1UL<<30) 6639 6640 u32_t rpm_rc_value_mask_14; 6641 #define RPM_RC_VALUE_MASK_14_VALUE (0xffffUL<<0) 6642 #define RPM_RC_VALUE_MASK_14_MASK (0xffffUL<<16) 6643 6644 u32_t rpm_rc_cntl_15; 6645 #define RPM_RC_CNTL_15_A_TE (0x3ffffUL<<0) 6646 #define RPM_RC_CNTL_15_B_TE (0xfffUL<<19) 6647 #define RPM_RC_CNTL_15_OFFSET_XI (0xffUL<<0) 6648 #define RPM_RC_CNTL_15_CLASS_XI (0x7UL<<8) 6649 #define RPM_RC_CNTL_15_PRIORITY_XI (1UL<<11) 6650 #define RPM_RC_CNTL_15_P4_XI (1UL<<12) 6651 #define RPM_RC_CNTL_15_HDR_TYPE_XI (0x7UL<<13) 6652 #define RPM_RC_CNTL_15_HDR_TYPE_START_XI (0UL<<13) 6653 #define RPM_RC_CNTL_15_HDR_TYPE_IP_XI (1UL<<13) 6654 #define RPM_RC_CNTL_15_HDR_TYPE_TCP_XI (2UL<<13) 6655 #define RPM_RC_CNTL_15_HDR_TYPE_UDP_XI (3UL<<13) 6656 #define RPM_RC_CNTL_15_HDR_TYPE_DATA_XI (4UL<<13) 6657 #define RPM_RC_CNTL_15_HDR_TYPE_TCP_UDP_XI (5UL<<13) 6658 #define RPM_RC_CNTL_15_HDR_TYPE_ICMPV6_XI (6UL<<13) 6659 #define RPM_RC_CNTL_15_COMP_XI (0x3UL<<16) 6660 #define RPM_RC_CNTL_15_COMP_EQUAL_XI (0UL<<16) 6661 #define RPM_RC_CNTL_15_COMP_NEQUAL_XI (1UL<<16) 6662 #define RPM_RC_CNTL_15_COMP_GREATER_XI (2UL<<16) 6663 #define RPM_RC_CNTL_15_COMP_LESS_XI (3UL<<16) 6664 #define RPM_RC_CNTL_15_MAP_XI (1UL<<18) 6665 #define RPM_RC_CNTL_15_SBIT_XI (1UL<<19) 6666 #define RPM_RC_CNTL_15_CMDSEL_XI (0x1fUL<<20) 6667 #define RPM_RC_CNTL_15_DISCARD_XI (1UL<<25) 6668 #define RPM_RC_CNTL_15_MASK_XI (1UL<<26) 6669 #define RPM_RC_CNTL_15_P1_XI (1UL<<27) 6670 #define RPM_RC_CNTL_15_P2_XI (1UL<<28) 6671 #define RPM_RC_CNTL_15_P3_XI (1UL<<29) 6672 #define RPM_RC_CNTL_15_NBIT_XI (1UL<<30) 6673 6674 u32_t rpm_rc_value_mask_15; 6675 #define RPM_RC_VALUE_MASK_15_VALUE (0xffffUL<<0) 6676 #define RPM_RC_VALUE_MASK_15_MASK (0xffffUL<<16) 6677 6678 u32_t rpm_rc_config; 6679 #define RPM_RC_CONFIG_RULE_ENABLE_TE (0xffffUL<<0) 6680 #define RPM_RC_CONFIG_RULE_ENABLE_XI (0xfffffUL<<0) 6681 #define RPM_RC_CONFIG_DEF_CLASS (0x7UL<<24) 6682 #define RPM_RC_CONFIG_KNUM_OVERWRITE (1UL<<31) 6683 6684 u32_t rpm_debug0; 6685 #define RPM_DEBUG0_FM_BCNT (0xffffUL<<0) 6686 #define RPM_DEBUG0_T_DATA_OFST_VLD (1UL<<16) 6687 #define RPM_DEBUG0_T_UDP_OFST_VLD (1UL<<17) 6688 #define RPM_DEBUG0_T_TCP_OFST_VLD (1UL<<18) 6689 #define RPM_DEBUG0_T_IP_OFST_VLD (1UL<<19) 6690 #define RPM_DEBUG0_IP_MORE_FRGMT (1UL<<20) 6691 #define RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1UL<<21) 6692 #define RPM_DEBUG0_LLC_SNAP (1UL<<22) 6693 #define RPM_DEBUG0_FM_STARTED (1UL<<23) 6694 #define RPM_DEBUG0_DONE (1UL<<24) 6695 #define RPM_DEBUG0_WAIT_4_DONE (1UL<<25) 6696 #define RPM_DEBUG0_USE_TPBUF_CKSUM (1UL<<26) 6697 #define RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1UL<<27) 6698 #define RPM_DEBUG0_IGNORE_VLAN (1UL<<28) 6699 #define RPM_DEBUG0_RP_ENA_ACTIVE (1UL<<31) 6700 6701 u32_t rpm_debug1; 6702 #define RPM_DEBUG1_FSM_CUR_ST (0xffffUL<<0) 6703 #define RPM_DEBUG1_FSM_CUR_ST_IDLE (0UL<<0) 6704 #define RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1UL<<0) 6705 #define RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2UL<<0) 6706 #define RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4UL<<0) 6707 #define RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8UL<<0) 6708 #define RPM_DEBUG1_FSM_CUR_ST_IP_START (16UL<<0) 6709 #define RPM_DEBUG1_FSM_CUR_ST_IP (32UL<<0) 6710 #define RPM_DEBUG1_FSM_CUR_ST_TCP (64UL<<0) 6711 #define RPM_DEBUG1_FSM_CUR_ST_UDP (128UL<<0) 6712 #define RPM_DEBUG1_FSM_CUR_ST_AH (256UL<<0) 6713 #define RPM_DEBUG1_FSM_CUR_ST_ESP (512UL<<0) 6714 #define RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024UL<<0) 6715 #define RPM_DEBUG1_FSM_CUR_ST_DATA (2048UL<<0) 6716 #define RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY (8192UL<<0) 6717 #define RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (16384UL<<0) 6718 #define RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT (32768UL<<0) 6719 #define RPM_DEBUG1_HDR_BCNT (0x7ffUL<<16) 6720 #define RPM_DEBUG1_UNKNOWN_ETYPE_D (1UL<<28) 6721 #define RPM_DEBUG1_VLAN_REMOVED_D2 (1UL<<29) 6722 #define RPM_DEBUG1_VLAN_REMOVED_D1 (1UL<<30) 6723 #define RPM_DEBUG1_EOF_0XTRA_WD (1UL<<31) 6724 6725 u32_t rpm_debug2; 6726 #define RPM_DEBUG2_CMD_HIT_VEC (0xffffUL<<0) 6727 #define RPM_DEBUG2_IP_BCNT (0xffUL<<16) 6728 #define RPM_DEBUG2_THIS_CMD_M4 (1UL<<24) 6729 #define RPM_DEBUG2_THIS_CMD_M3 (1UL<<25) 6730 #define RPM_DEBUG2_THIS_CMD_M2 (1UL<<26) 6731 #define RPM_DEBUG2_THIS_CMD_M1 (1UL<<27) 6732 #define RPM_DEBUG2_IPIPE_EMPTY (1UL<<28) 6733 #define RPM_DEBUG2_FM_DISCARD (1UL<<29) 6734 #define RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1UL<<30) 6735 #define RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1UL<<31) 6736 6737 u32_t rpm_debug3; 6738 #define RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffUL<<0) 6739 #define RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1UL<<9) 6740 #define RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1UL<<10) 6741 #define RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1UL<<11) 6742 #define RPM_DEBUG3_RDE_RBUF_FREE_REQ (1UL<<12) 6743 #define RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1UL<<13) 6744 #define RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1UL<<14) 6745 #define RPM_DEBUG3_RBUF_RDE_SOF_DROP (1UL<<15) 6746 #define RPM_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfUL<<16) 6747 #define RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1UL<<21) 6748 #define RPM_DEBUG3_DROP_NXT_VLD (1UL<<22) 6749 #define RPM_DEBUG3_DROP_NXT (1UL<<23) 6750 #define RPM_DEBUG3_FTQ_FSM (0x3UL<<24) 6751 #define RPM_DEBUG3_FTQ_FSM_IDLE (0UL<<24) 6752 #define RPM_DEBUG3_FTQ_FSM_WAIT_ACK (1UL<<24) 6753 #define RPM_DEBUG3_FTQ_FSM_WAIT_FREE (2UL<<24) 6754 #define RPM_DEBUG3_MBWRITE_FSM (0x3UL<<26) 6755 #define RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF (0UL<<26) 6756 #define RPM_DEBUG3_MBWRITE_FSM_GET_MBUF (1UL<<26) 6757 #define RPM_DEBUG3_MBWRITE_FSM_DMA_DATA (2UL<<26) 6758 #define RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA (3UL<<26) 6759 #define RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF (4UL<<26) 6760 #define RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (5UL<<26) 6761 #define RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (6UL<<26) 6762 #define RPM_DEBUG3_MBWRITE_FSM_DONE (7UL<<26) 6763 #define RPM_DEBUG3_MBFREE_FSM (1UL<<29) 6764 #define RPM_DEBUG3_MBFREE_FSM_IDLE (0UL<<29) 6765 #define RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1UL<<29) 6766 #define RPM_DEBUG3_MBALLOC_FSM (1UL<<30) 6767 #define RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0UL<<30) 6768 #define RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (1UL<<30) 6769 #define RPM_DEBUG3_CCODE_EOF_ERROR (1UL<<31) 6770 6771 u32_t rpm_debug4; 6772 #define RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffUL<<0) 6773 #define RPM_DEBUG4_DFIFO_CUR_CCODE (0x7UL<<25) 6774 #define RPM_DEBUG4_MBWRITE_FSM (0x7UL<<28) 6775 #define RPM_DEBUG4_DFIFO_EMPTY (1UL<<31) 6776 6777 u32_t rpm_debug5; 6778 #define RPM_DEBUG5_RDROP_WPTR (0x1fUL<<0) 6779 #define RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fUL<<5) 6780 #define RPM_DEBUG5_RDROP_MC_RPTR (0x1fUL<<10) 6781 #define RPM_DEBUG5_RDROP_RC_RPTR (0x1fUL<<15) 6782 #define RPM_DEBUG5_RDROP_ACPI_EMPTY (1UL<<20) 6783 #define RPM_DEBUG5_RDROP_MC_EMPTY (1UL<<21) 6784 #define RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1UL<<22) 6785 #define RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1UL<<23) 6786 #define RPM_DEBUG5_HOLDREG_DISCARD (1UL<<24) 6787 #define RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1UL<<25) 6788 #define RPM_DEBUG5_HOLDREG_MC_EMPTY (1UL<<26) 6789 #define RPM_DEBUG5_HOLDREG_RC_EMPTY (1UL<<27) 6790 #define RPM_DEBUG5_HOLDREG_FC_EMPTY (1UL<<28) 6791 #define RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1UL<<29) 6792 #define RPM_DEBUG5_HOLDREG_FULL_T (1UL<<30) 6793 #define RPM_DEBUG5_HOLDREG_RD (1UL<<31) 6794 6795 u32_t rpm_debug6; 6796 #define RPM_DEBUG6_ACPI_VEC (0xffffUL<<0) 6797 #define RPM_DEBUG6_VEC (0xffffUL<<16) 6798 6799 u32_t rpm_debug7; 6800 #define RPM_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffUL<<0) 6801 6802 u32_t rpm_debug8; 6803 #define RPM_DEBUG8_PS_ACPI_FSM (0xfUL<<0) 6804 #define RPM_DEBUG8_PS_ACPI_FSM_IDLE (0UL<<0) 6805 #define RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1UL<<0) 6806 #define RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2UL<<0) 6807 #define RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3UL<<0) 6808 #define RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4UL<<0) 6809 #define RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5UL<<0) 6810 #define RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6UL<<0) 6811 #define RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7UL<<0) 6812 #define RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8UL<<0) 6813 #define RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9UL<<0) 6814 #define RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10UL<<0) 6815 #define RPM_DEBUG8_COMPARE_AT_W0 (1UL<<4) 6816 #define RPM_DEBUG8_COMPARE_AT_W3_DATA (1UL<<5) 6817 #define RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1UL<<6) 6818 #define RPM_DEBUG8_COMPARE_AT_SOF_W3 (1UL<<7) 6819 #define RPM_DEBUG8_COMPARE_AT_SOF_W2 (1UL<<8) 6820 #define RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1UL<<9) 6821 #define RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1UL<<10) 6822 #define RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1UL<<11) 6823 #define RPM_DEBUG8_EOF_DET (1UL<<12) 6824 #define RPM_DEBUG8_SOF_DET (1UL<<13) 6825 #define RPM_DEBUG8_WAIT_4_SOF (1UL<<14) 6826 #define RPM_DEBUG8_ALL_DONE (1UL<<15) 6827 #define RPM_DEBUG8_THBUF_ADDR (0x7fUL<<16) 6828 #define RPM_DEBUG8_BYTE_CTR (0xffUL<<24) 6829 6830 u32_t rpm_debug9; 6831 #define RPM_DEBUG9_OUTFIFO_COUNT_TE (0x7UL<<0) 6832 #define RPM_DEBUG9_RDE_ACPI_RDY_TE (1UL<<3) 6833 #define RPM_DEBUG9_VLD_RD_ENTRY_CT_TE (0x7UL<<4) 6834 #define RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED_TE (1UL<<28) 6835 #define RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED_TE (1UL<<29) 6836 #define RPM_DEBUG9_ACPI_MATCH_INT_TE (1UL<<30) 6837 #define RPM_DEBUG9_ACPI_ENABLE_SYN_TE (1UL<<31) 6838 #define RPM_DEBUG9_BEMEM_R_XI (0x1fUL<<0) 6839 #define RPM_DEBUG9_EO_XI (1UL<<5) 6840 #define RPM_DEBUG9_AEOF_DE_XI (1UL<<6) 6841 #define RPM_DEBUG9_SO_XI (1UL<<7) 6842 #define RPM_DEBUG9_WD64_CT_XI (0x1fUL<<8) 6843 #define RPM_DEBUG9_EOF_VLDBYTE_XI (0x7UL<<13) 6844 #define RPM_DEBUG9_ACPI_RDE_PAT_ID_XI (0xfUL<<16) 6845 #define RPM_DEBUG9_CALCRC_RESULT_XI (0x3ffUL<<20) 6846 #define RPM_DEBUG9_DATA_IN_VL_XI (1UL<<30) 6847 #define RPM_DEBUG9_CALCRC_BUFFER_VLD_XI (1UL<<31) 6848 6849 u32_t unused_3[5]; 6850 u32_t rpm_acpi_dbg_buf_w0[4]; 6851 u32_t rpm_acpi_dbg_buf_w1[4]; 6852 u32_t rpm_acpi_dbg_buf_w2[4]; 6853 u32_t rpm_acpi_dbg_buf_w3[4]; 6854 u32_t rpm_acpi_byte_enable_ctrl; 6855 #define RPM_ACPI_BYTE_ENABLE_CTRL_BYTE_ADDRESS (0xffffUL<<0) 6856 #define RPM_ACPI_BYTE_ENABLE_CTRL_DEBUGRD (1UL<<28) 6857 #define RPM_ACPI_BYTE_ENABLE_CTRL_MODE (1UL<<29) 6858 #define RPM_ACPI_BYTE_ENABLE_CTRL_INIT (1UL<<30) 6859 #define RPM_ACPI_BYTE_ENABLE_CTRL_WR (1UL<<31) 6860 6861 u32_t rpm_acpi_pattern_ctrl; 6862 #define RPM_ACPI_PATTERN_CTRL_PATTERN_ID (0xfUL<<0) 6863 #define RPM_ACPI_PATTERN_CTRL_CRC_SM_CLR (1UL<<30) 6864 #define RPM_ACPI_PATTERN_CTRL_WR (1UL<<31) 6865 6866 u32_t rpm_acpi_data; 6867 #define RPM_ACPI_DATA_PATTERN_BE (0xffffffffUL<<0) 6868 6869 u32_t rpm_acpi_pattern_len0; 6870 #define RPM_ACPI_PATTERN_LEN0_PATTERN_LEN3 (0xffUL<<0) 6871 #define RPM_ACPI_PATTERN_LEN0_PATTERN_LEN2 (0xffUL<<8) 6872 #define RPM_ACPI_PATTERN_LEN0_PATTERN_LEN1 (0xffUL<<16) 6873 #define RPM_ACPI_PATTERN_LEN0_PATTERN_LEN0 (0xffUL<<24) 6874 6875 u32_t rpm_acpi_pattern_len1; 6876 #define RPM_ACPI_PATTERN_LEN1_PATTERN_LEN7 (0xffUL<<0) 6877 #define RPM_ACPI_PATTERN_LEN1_PATTERN_LEN6 (0xffUL<<8) 6878 #define RPM_ACPI_PATTERN_LEN1_PATTERN_LEN5 (0xffUL<<16) 6879 #define RPM_ACPI_PATTERN_LEN1_PATTERN_LEN4 (0xffUL<<24) 6880 6881 u32_t unused_4; 6882 u32_t rpm_acpi_pattern_crc0; 6883 #define RPM_ACPI_PATTERN_CRC0_PATTERN_CRC0 (0xffffffffUL<<0) 6884 6885 u32_t rpm_acpi_pattern_crc1; 6886 #define RPM_ACPI_PATTERN_CRC1_PATTERN_CRC1 (0xffffffffUL<<0) 6887 6888 u32_t rpm_acpi_pattern_crc2; 6889 #define RPM_ACPI_PATTERN_CRC2_PATTERN_CRC2 (0xffffffffUL<<0) 6890 6891 u32_t rpm_acpi_pattern_crc3; 6892 #define RPM_ACPI_PATTERN_CRC3_PATTERN_CRC3 (0xffffffffUL<<0) 6893 6894 u32_t rpm_acpi_pattern_crc4; 6895 #define RPM_ACPI_PATTERN_CRC4_PATTERN_CRC4 (0xffffffffUL<<0) 6896 6897 u32_t rpm_acpi_pattern_crc5; 6898 #define RPM_ACPI_PATTERN_CRC5_PATTERN_CRC5 (0xffffffffUL<<0) 6899 6900 u32_t rpm_acpi_pattern_crc6; 6901 #define RPM_ACPI_PATTERN_CRC6_PATTERN_CRC6 (0xffffffffUL<<0) 6902 6903 u32_t rpm_acpi_pattern_crc7; 6904 #define RPM_ACPI_PATTERN_CRC7_PATTERN_CRC7 (0xffffffffUL<<0) 6905 6906 u32_t unused_5[114]; 6907 } rpm_reg_t; 6908 6909 typedef rpm_reg_t rx_parser_reg_t; 6910 6911 /* 6912 * rpc_reg definition 6913 * offset: 0x1c00 6914 */ 6915 typedef struct rpc_reg 6916 { 6917 u32_t rpc_command; 6918 #define RPC_COMMAND_ENABLED (1UL<<0) 6919 #define RPC_COMMAND_OVERRUN_ABORT (1UL<<4) 6920 6921 u32_t rpc_status; 6922 #define RPC_STATUS_MBUF_WAIT (1UL<<0) 6923 #define RPC_STATUS_FREE_WAIT (1UL<<1) 6924 6925 u32_t rpc_config; 6926 #define RPC_CONFIG_NO_PSD_HDR_CKSUM (1UL<<0) 6927 #define RPC_CONFIG_SORT_VECT_VAL (0xfUL<<4) 6928 #define RPC_CONFIG_IGNORE_VLAN (1UL<<31) 6929 6930 u32_t unused_0[13]; 6931 u32_t rpc_stat_l2_filter_discards; 6932 u32_t rpc_stat_rule_checker_discards; 6933 u32_t rpc_stat_ifinftqdiscards; 6934 u32_t rpc_stat_ifinmbufdiscard; 6935 u32_t rpc_stat_rule_checker_p4_hit; 6936 u32_t rpc_ipv6_programmable_extension0; 6937 #define RPC_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN (0xffUL<<0) 6938 #define RPC_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER (0xffUL<<16) 6939 #define RPC_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN_TYPE (1UL<<30) 6940 #define RPC_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_EN (1UL<<31) 6941 6942 u32_t rpc_ipv6_programmable_extension1; 6943 #define RPC_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN (0xffUL<<0) 6944 #define RPC_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER (0xffUL<<16) 6945 #define RPC_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN_TYPE (1UL<<30) 6946 #define RPC_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_EN (1UL<<31) 6947 6948 u32_t rpc_ipv6_programmable_extension2; 6949 #define RPC_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN (0xffUL<<0) 6950 #define RPC_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER (0xffUL<<16) 6951 #define RPC_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN_TYPE (1UL<<30) 6952 #define RPC_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_EN (1UL<<31) 6953 6954 u32_t rpc_ipv6_programmable_extension3; 6955 #define RPC_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN (0xffUL<<0) 6956 #define RPC_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER (0xffUL<<16) 6957 #define RPC_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN_TYPE (1UL<<30) 6958 #define RPC_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_EN (1UL<<31) 6959 6960 u32_t rpc_ipv6_programmable_extension4; 6961 #define RPC_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN (0xffUL<<0) 6962 #define RPC_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER (0xffUL<<16) 6963 #define RPC_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN_TYPE (1UL<<30) 6964 #define RPC_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_EN (1UL<<31) 6965 6966 u32_t rpc_ipv6_programmable_extension5; 6967 #define RPC_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN (0xffUL<<0) 6968 #define RPC_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER (0xffUL<<16) 6969 #define RPC_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN_TYPE (1UL<<30) 6970 #define RPC_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_EN (1UL<<31) 6971 6972 u32_t rpc_ipv6_programmable_extension6; 6973 #define RPC_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN (0xffUL<<0) 6974 #define RPC_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER (0xffUL<<16) 6975 #define RPC_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN_TYPE (1UL<<30) 6976 #define RPC_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_EN (1UL<<31) 6977 6978 u32_t rpc_ipv6_programmable_extension7; 6979 #define RPC_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN (0xffUL<<0) 6980 #define RPC_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER (0xffUL<<16) 6981 #define RPC_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN_TYPE (1UL<<30) 6982 #define RPC_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_EN (1UL<<31) 6983 6984 u32_t unused_1[3]; 6985 u32_t rpc_stat_ac[5]; 6986 u32_t unused_2[27]; 6987 u32_t rpc_rc_cntl_0; 6988 #define RPC_RC_CNTL_0_OFFSET (0xffUL<<0) 6989 #define RPC_RC_CNTL_0_CLASS (0x7UL<<8) 6990 #define RPC_RC_CNTL_0_PRIORITY (1UL<<11) 6991 #define RPC_RC_CNTL_0_P4 (1UL<<12) 6992 #define RPC_RC_CNTL_0_HDR_TYPE (0x7UL<<13) 6993 #define RPC_RC_CNTL_0_HDR_TYPE_START (0UL<<13) 6994 #define RPC_RC_CNTL_0_HDR_TYPE_IP (1UL<<13) 6995 #define RPC_RC_CNTL_0_HDR_TYPE_TCP (2UL<<13) 6996 #define RPC_RC_CNTL_0_HDR_TYPE_UDP (3UL<<13) 6997 #define RPC_RC_CNTL_0_HDR_TYPE_DATA (4UL<<13) 6998 #define RPC_RC_CNTL_0_COMP (0x3UL<<16) 6999 #define RPC_RC_CNTL_0_COMP_EQUAL (0UL<<16) 7000 #define RPC_RC_CNTL_0_COMP_NEQUAL (1UL<<16) 7001 #define RPC_RC_CNTL_0_COMP_GREATER (2UL<<16) 7002 #define RPC_RC_CNTL_0_COMP_LESS (3UL<<16) 7003 #define RPC_RC_CNTL_0_MAP_XI (1UL<<18) 7004 #define RPC_RC_CNTL_0_SBIT (1UL<<19) 7005 #define RPC_RC_CNTL_0_CMDSEL_TE (0xfUL<<20) 7006 #define RPC_RC_CNTL_0_MAP_TE (1UL<<24) 7007 #define RPC_RC_CNTL_0_CMDSEL_XI (0x1fUL<<20) 7008 #define RPC_RC_CNTL_0_DISCARD (1UL<<25) 7009 #define RPC_RC_CNTL_0_MASK (1UL<<26) 7010 #define RPC_RC_CNTL_0_P1 (1UL<<27) 7011 #define RPC_RC_CNTL_0_P2 (1UL<<28) 7012 #define RPC_RC_CNTL_0_P3 (1UL<<29) 7013 #define RPC_RC_CNTL_0_NBIT (1UL<<30) 7014 7015 u32_t rpc_rc_value_mask_0; 7016 #define RPC_RC_VALUE_MASK_0_VALUE (0xffffUL<<0) 7017 #define RPC_RC_VALUE_MASK_0_MASK (0xffffUL<<16) 7018 7019 u32_t rpc_rc_cntl_1; 7020 #define RPC_RC_CNTL_1_A_TE (0x3ffffUL<<0) 7021 #define RPC_RC_CNTL_1_B_TE (0xfffUL<<19) 7022 #define RPC_RC_CNTL_1_OFFSET_XI (0xffUL<<0) 7023 #define RPC_RC_CNTL_1_CLASS_XI (0x7UL<<8) 7024 #define RPC_RC_CNTL_1_PRIORITY_XI (1UL<<11) 7025 #define RPC_RC_CNTL_1_P4_XI (1UL<<12) 7026 #define RPC_RC_CNTL_1_HDR_TYPE_XI (0x7UL<<13) 7027 #define RPC_RC_CNTL_1_HDR_TYPE_START_XI (0UL<<13) 7028 #define RPC_RC_CNTL_1_HDR_TYPE_IP_XI (1UL<<13) 7029 #define RPC_RC_CNTL_1_HDR_TYPE_TCP_XI (2UL<<13) 7030 #define RPC_RC_CNTL_1_HDR_TYPE_UDP_XI (3UL<<13) 7031 #define RPC_RC_CNTL_1_HDR_TYPE_DATA_XI (4UL<<13) 7032 #define RPC_RC_CNTL_1_COMP_XI (0x3UL<<16) 7033 #define RPC_RC_CNTL_1_COMP_EQUAL_XI (0UL<<16) 7034 #define RPC_RC_CNTL_1_COMP_NEQUAL_XI (1UL<<16) 7035 #define RPC_RC_CNTL_1_COMP_GREATER_XI (2UL<<16) 7036 #define RPC_RC_CNTL_1_COMP_LESS_XI (3UL<<16) 7037 #define RPC_RC_CNTL_1_MAP_XI (1UL<<18) 7038 #define RPC_RC_CNTL_1_SBIT_XI (1UL<<19) 7039 #define RPC_RC_CNTL_1_CMDSEL_XI (0x1fUL<<20) 7040 #define RPC_RC_CNTL_1_DISCARD_XI (1UL<<25) 7041 #define RPC_RC_CNTL_1_MASK_XI (1UL<<26) 7042 #define RPC_RC_CNTL_1_P1_XI (1UL<<27) 7043 #define RPC_RC_CNTL_1_P2_XI (1UL<<28) 7044 #define RPC_RC_CNTL_1_P3_XI (1UL<<29) 7045 #define RPC_RC_CNTL_1_NBIT_XI (1UL<<30) 7046 7047 u32_t rpc_rc_value_mask_1; 7048 #define RPC_RC_VALUE_MASK_1_VALUE (0xffffUL<<0) 7049 #define RPC_RC_VALUE_MASK_1_MASK (0xffffUL<<16) 7050 7051 u32_t rpc_rc_cntl_2; 7052 #define RPC_RC_CNTL_2_A_TE (0x3ffffUL<<0) 7053 #define RPC_RC_CNTL_2_B_TE (0xfffUL<<19) 7054 #define RPC_RC_CNTL_2_OFFSET_XI (0xffUL<<0) 7055 #define RPC_RC_CNTL_2_CLASS_XI (0x7UL<<8) 7056 #define RPC_RC_CNTL_2_PRIORITY_XI (1UL<<11) 7057 #define RPC_RC_CNTL_2_P4_XI (1UL<<12) 7058 #define RPC_RC_CNTL_2_HDR_TYPE_XI (0x7UL<<13) 7059 #define RPC_RC_CNTL_2_HDR_TYPE_START_XI (0UL<<13) 7060 #define RPC_RC_CNTL_2_HDR_TYPE_IP_XI (1UL<<13) 7061 #define RPC_RC_CNTL_2_HDR_TYPE_TCP_XI (2UL<<13) 7062 #define RPC_RC_CNTL_2_HDR_TYPE_UDP_XI (3UL<<13) 7063 #define RPC_RC_CNTL_2_HDR_TYPE_DATA_XI (4UL<<13) 7064 #define RPC_RC_CNTL_2_COMP_XI (0x3UL<<16) 7065 #define RPC_RC_CNTL_2_COMP_EQUAL_XI (0UL<<16) 7066 #define RPC_RC_CNTL_2_COMP_NEQUAL_XI (1UL<<16) 7067 #define RPC_RC_CNTL_2_COMP_GREATER_XI (2UL<<16) 7068 #define RPC_RC_CNTL_2_COMP_LESS_XI (3UL<<16) 7069 #define RPC_RC_CNTL_2_MAP_XI (1UL<<18) 7070 #define RPC_RC_CNTL_2_SBIT_XI (1UL<<19) 7071 #define RPC_RC_CNTL_2_CMDSEL_XI (0x1fUL<<20) 7072 #define RPC_RC_CNTL_2_DISCARD_XI (1UL<<25) 7073 #define RPC_RC_CNTL_2_MASK_XI (1UL<<26) 7074 #define RPC_RC_CNTL_2_P1_XI (1UL<<27) 7075 #define RPC_RC_CNTL_2_P2_XI (1UL<<28) 7076 #define RPC_RC_CNTL_2_P3_XI (1UL<<29) 7077 #define RPC_RC_CNTL_2_NBIT_XI (1UL<<30) 7078 7079 u32_t rpc_rc_value_mask_2; 7080 #define RPC_RC_VALUE_MASK_2_VALUE (0xffffUL<<0) 7081 #define RPC_RC_VALUE_MASK_2_MASK (0xffffUL<<16) 7082 7083 u32_t rpc_rc_cntl_3; 7084 #define RPC_RC_CNTL_3_A_TE (0x3ffffUL<<0) 7085 #define RPC_RC_CNTL_3_B_TE (0xfffUL<<19) 7086 #define RPC_RC_CNTL_3_OFFSET_XI (0xffUL<<0) 7087 #define RPC_RC_CNTL_3_CLASS_XI (0x7UL<<8) 7088 #define RPC_RC_CNTL_3_PRIORITY_XI (1UL<<11) 7089 #define RPC_RC_CNTL_3_P4_XI (1UL<<12) 7090 #define RPC_RC_CNTL_3_HDR_TYPE_XI (0x7UL<<13) 7091 #define RPC_RC_CNTL_3_HDR_TYPE_START_XI (0UL<<13) 7092 #define RPC_RC_CNTL_3_HDR_TYPE_IP_XI (1UL<<13) 7093 #define RPC_RC_CNTL_3_HDR_TYPE_TCP_XI (2UL<<13) 7094 #define RPC_RC_CNTL_3_HDR_TYPE_UDP_XI (3UL<<13) 7095 #define RPC_RC_CNTL_3_HDR_TYPE_DATA_XI (4UL<<13) 7096 #define RPC_RC_CNTL_3_COMP_XI (0x3UL<<16) 7097 #define RPC_RC_CNTL_3_COMP_EQUAL_XI (0UL<<16) 7098 #define RPC_RC_CNTL_3_COMP_NEQUAL_XI (1UL<<16) 7099 #define RPC_RC_CNTL_3_COMP_GREATER_XI (2UL<<16) 7100 #define RPC_RC_CNTL_3_COMP_LESS_XI (3UL<<16) 7101 #define RPC_RC_CNTL_3_MAP_XI (1UL<<18) 7102 #define RPC_RC_CNTL_3_SBIT_XI (1UL<<19) 7103 #define RPC_RC_CNTL_3_CMDSEL_XI (0x1fUL<<20) 7104 #define RPC_RC_CNTL_3_DISCARD_XI (1UL<<25) 7105 #define RPC_RC_CNTL_3_MASK_XI (1UL<<26) 7106 #define RPC_RC_CNTL_3_P1_XI (1UL<<27) 7107 #define RPC_RC_CNTL_3_P2_XI (1UL<<28) 7108 #define RPC_RC_CNTL_3_P3_XI (1UL<<29) 7109 #define RPC_RC_CNTL_3_NBIT_XI (1UL<<30) 7110 7111 u32_t rpc_rc_value_mask_3; 7112 #define RPC_RC_VALUE_MASK_3_VALUE (0xffffUL<<0) 7113 #define RPC_RC_VALUE_MASK_3_MASK (0xffffUL<<16) 7114 7115 u32_t rpc_rc_cntl_4; 7116 #define RPC_RC_CNTL_4_A (0x3ffffUL<<0) 7117 #define RPC_RC_CNTL_4_B (0xfffUL<<19) 7118 7119 u32_t rpc_rc_value_mask_4; 7120 u32_t rpc_rc_cntl_5; 7121 #define RPC_RC_CNTL_5_A (0x3ffffUL<<0) 7122 #define RPC_RC_CNTL_5_B (0xfffUL<<19) 7123 7124 u32_t rpc_rc_value_mask_5; 7125 u32_t rpc_rc_cntl_6; 7126 #define RPC_RC_CNTL_6_A (0x3ffffUL<<0) 7127 #define RPC_RC_CNTL_6_B (0xfffUL<<19) 7128 7129 u32_t rpc_rc_value_mask_6; 7130 u32_t rpc_rc_cntl_7; 7131 #define RPC_RC_CNTL_7_A (0x3ffffUL<<0) 7132 #define RPC_RC_CNTL_7_B (0xfffUL<<19) 7133 7134 u32_t rpc_rc_value_mask_7; 7135 u32_t rpc_rc_cntl_8; 7136 #define RPC_RC_CNTL_8_A (0x3ffffUL<<0) 7137 #define RPC_RC_CNTL_8_B (0xfffUL<<19) 7138 7139 u32_t rpc_rc_value_mask_8; 7140 u32_t rpc_rc_cntl_9; 7141 #define RPC_RC_CNTL_9_A (0x3ffffUL<<0) 7142 #define RPC_RC_CNTL_9_B (0xfffUL<<19) 7143 7144 u32_t rpc_rc_value_mask_9; 7145 u32_t rpc_rc_cntl_10; 7146 #define RPC_RC_CNTL_10_A (0x3ffffUL<<0) 7147 #define RPC_RC_CNTL_10_B (0xfffUL<<19) 7148 7149 u32_t rpc_rc_value_mask_10; 7150 u32_t rpc_rc_cntl_11; 7151 #define RPC_RC_CNTL_11_A (0x3ffffUL<<0) 7152 #define RPC_RC_CNTL_11_B (0xfffUL<<19) 7153 7154 u32_t rpc_rc_value_mask_11; 7155 u32_t rpc_rc_cntl_12; 7156 #define RPC_RC_CNTL_12_A (0x3ffffUL<<0) 7157 #define RPC_RC_CNTL_12_B (0xfffUL<<19) 7158 7159 u32_t rpc_rc_value_mask_12; 7160 u32_t rpc_rc_cntl_13; 7161 #define RPC_RC_CNTL_13_A (0x3ffffUL<<0) 7162 #define RPC_RC_CNTL_13_B (0xfffUL<<19) 7163 7164 u32_t rpc_rc_value_mask_13; 7165 u32_t rpc_rc_cntl_14; 7166 #define RPC_RC_CNTL_14_A (0x3ffffUL<<0) 7167 #define RPC_RC_CNTL_14_B (0xfffUL<<19) 7168 7169 u32_t rpc_rc_value_mask_14; 7170 u32_t rpc_rc_cntl_15; 7171 #define RPC_RC_CNTL_15_A (0x3ffffUL<<0) 7172 #define RPC_RC_CNTL_15_B (0xfffUL<<19) 7173 7174 u32_t rpc_rc_value_mask_15; 7175 u32_t rpc_rc_config; 7176 #define RPC_RC_CONFIG_RULE_ENABLE_TE (0xffffUL<<0) 7177 #define RPC_RC_CONFIG_RULE_ENABLE_XI (0xfUL<<0) 7178 #define RPC_RC_CONFIG_DEF_CLASS (0x7UL<<24) 7179 7180 u32_t rpc_debug0; 7181 #define RPC_DEBUG0_FM_BCNT (0xffffUL<<0) 7182 #define RPC_DEBUG0_T_DATA_OFST_VLD (1UL<<16) 7183 #define RPC_DEBUG0_T_UDP_OFST_VLD (1UL<<17) 7184 #define RPC_DEBUG0_T_TCP_OFST_VLD (1UL<<18) 7185 #define RPC_DEBUG0_T_IP_OFST_VLD (1UL<<19) 7186 #define RPC_DEBUG0_IP_MORE_FRGMT (1UL<<20) 7187 #define RPC_DEBUG0_T_IP_NO_TCP_UDP_HDR (1UL<<21) 7188 #define RPC_DEBUG0_LLC_SNAP (1UL<<22) 7189 #define RPC_DEBUG0_FM_STARTED (1UL<<23) 7190 #define RPC_DEBUG0_DONE (1UL<<24) 7191 #define RPC_DEBUG0_WAIT_4_DONE (1UL<<25) 7192 #define RPC_DEBUG0_USE_TPBUF_CKSUM (1UL<<26) 7193 #define RPC_DEBUG0_RX_NO_PSD_HDR_CKSUM (1UL<<27) 7194 #define RPC_DEBUG0_IGNORE_VLAN (1UL<<28) 7195 #define RPC_DEBUG0_RP_ENA_ACTIVE (1UL<<31) 7196 7197 u32_t rpc_debug1; 7198 #define RPC_DEBUG1_FSM_CUR_ST (0xffffUL<<0) 7199 #define RPC_DEBUG1_FSM_CUR_ST_IDLE (0UL<<0) 7200 #define RPC_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1UL<<0) 7201 #define RPC_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2UL<<0) 7202 #define RPC_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4UL<<0) 7203 #define RPC_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8UL<<0) 7204 #define RPC_DEBUG1_FSM_CUR_ST_IP_START (16UL<<0) 7205 #define RPC_DEBUG1_FSM_CUR_ST_IP (32UL<<0) 7206 #define RPC_DEBUG1_FSM_CUR_ST_TCP (64UL<<0) 7207 #define RPC_DEBUG1_FSM_CUR_ST_UDP (128UL<<0) 7208 #define RPC_DEBUG1_FSM_CUR_ST_AH (256UL<<0) 7209 #define RPC_DEBUG1_FSM_CUR_ST_ESP (512UL<<0) 7210 #define RPC_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024UL<<0) 7211 #define RPC_DEBUG1_FSM_CUR_ST_DATA (2048UL<<0) 7212 #define RPC_DEBUG1_FSM_CUR_ST_ADD_CARRY (8192UL<<0) 7213 #define RPC_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (16384UL<<0) 7214 #define RPC_DEBUG1_FSM_CUR_ST_LATCH_RESULT (32768UL<<0) 7215 #define RPC_DEBUG1_HDR_BCNT (0x7ffUL<<16) 7216 #define RPC_DEBUG1_UNKNOWN_ETYPE_D (1UL<<28) 7217 #define RPC_DEBUG1_VLAN_REMOVED_D2 (1UL<<29) 7218 #define RPC_DEBUG1_VLAN_REMOVED_D1 (1UL<<30) 7219 #define RPC_DEBUG1_EOF_0XTRA_WD (1UL<<31) 7220 7221 u32_t rpc_debug2; 7222 #define RPC_DEBUG2_CMD_HIT_VEC (0xffffUL<<0) 7223 #define RPC_DEBUG2_IP_BCNT (0xffUL<<16) 7224 #define RPC_DEBUG2_THIS_CMD_M4 (1UL<<24) 7225 #define RPC_DEBUG2_THIS_CMD_M3 (1UL<<25) 7226 #define RPC_DEBUG2_THIS_CMD_M2 (1UL<<26) 7227 #define RPC_DEBUG2_THIS_CMD_M1 (1UL<<27) 7228 #define RPC_DEBUG2_IPIPE_EMPTY (1UL<<28) 7229 #define RPC_DEBUG2_FM_DISCARD (1UL<<29) 7230 #define RPC_DEBUG2_LAST_RULE_IN_FM_D2 (1UL<<30) 7231 #define RPC_DEBUG2_LAST_RULE_IN_FM_D1 (1UL<<31) 7232 7233 u32_t rpc_debug3; 7234 #define RPC_DEBUG3_AVAIL_MBUF_PTR (0x1ffUL<<0) 7235 #define RPC_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1UL<<9) 7236 #define RPC_DEBUG3_RDE_RBUF_WR_LAST_INT (1UL<<10) 7237 #define RPC_DEBUG3_RDE_RBUF_WR_REQ_INT (1UL<<11) 7238 #define RPC_DEBUG3_RDE_RBUF_FREE_REQ (1UL<<12) 7239 #define RPC_DEBUG3_RDE_RBUF_ALLOC_REQ (1UL<<13) 7240 #define RPC_DEBUG3_DFSM_MBUF_NOTAVAIL (1UL<<14) 7241 #define RPC_DEBUG3_RBUF_RDE_SOF_DROP (1UL<<15) 7242 #define RPC_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfUL<<16) 7243 #define RPC_DEBUG3_RDE_SRC_FIFO_ALMFULL (1UL<<21) 7244 #define RPC_DEBUG3_DROP_NXT_VLD (1UL<<22) 7245 #define RPC_DEBUG3_DROP_NXT (1UL<<23) 7246 #define RPC_DEBUG3_FTQ_FSM (0x3UL<<24) 7247 #define RPC_DEBUG3_FTQ_FSM_IDLE (0UL<<24) 7248 #define RPC_DEBUG3_FTQ_FSM_WAIT_ACK (1UL<<24) 7249 #define RPC_DEBUG3_FTQ_FSM_WAIT_FREE (2UL<<24) 7250 #define RPC_DEBUG3_MBWRITE_FSM (0x3UL<<26) 7251 #define RPC_DEBUG3_MBWRITE_FSM_WAIT_SOF (0UL<<26) 7252 #define RPC_DEBUG3_MBWRITE_FSM_GET_MBUF (1UL<<26) 7253 #define RPC_DEBUG3_MBWRITE_FSM_DMA_DATA (2UL<<26) 7254 #define RPC_DEBUG3_MBWRITE_FSM_WAIT_DATA (3UL<<26) 7255 #define RPC_DEBUG3_MBWRITE_FSM_WAIT_EOF (4UL<<26) 7256 #define RPC_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (5UL<<26) 7257 #define RPC_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (6UL<<26) 7258 #define RPC_DEBUG3_MBWRITE_FSM_DONE (7UL<<26) 7259 #define RPC_DEBUG3_MBFREE_FSM (1UL<<29) 7260 #define RPC_DEBUG3_MBFREE_FSM_IDLE (0UL<<29) 7261 #define RPC_DEBUG3_MBFREE_FSM_WAIT_ACK (1UL<<29) 7262 #define RPC_DEBUG3_MBALLOC_FSM (1UL<<30) 7263 #define RPC_DEBUG3_MBALLOC_FSM_ET_MBUF (0UL<<30) 7264 #define RPC_DEBUG3_MBALLOC_FSM_IVE_MBUF (1UL<<30) 7265 #define RPC_DEBUG3_CCODE_EOF_ERROR (1UL<<31) 7266 7267 u32_t rpc_debug4; 7268 #define RPC_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffUL<<0) 7269 #define RPC_DEBUG4_DFIFO_CUR_CCODE (0x7UL<<25) 7270 #define RPC_DEBUG4_MBWRITE_FSM (0x7UL<<28) 7271 #define RPC_DEBUG4_DFIFO_EMPTY (1UL<<31) 7272 7273 u32_t rpc_debug5; 7274 #define RPC_DEBUG5_RDROP_WPTR (0x1fUL<<0) 7275 #define RPC_DEBUG5_RDROP_ACPI_RPTR (0x1fUL<<5) 7276 #define RPC_DEBUG5_RDROP_MC_RPTR (0x1fUL<<10) 7277 #define RPC_DEBUG5_RDROP_RC_RPTR (0x1fUL<<15) 7278 #define RPC_DEBUG5_RDROP_ACPI_EMPTY (1UL<<20) 7279 #define RPC_DEBUG5_RDROP_MC_EMPTY (1UL<<21) 7280 #define RPC_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1UL<<22) 7281 #define RPC_DEBUG5_HOLDREG_WOL_DROP_INT (1UL<<23) 7282 #define RPC_DEBUG5_HOLDREG_DISCARD (1UL<<24) 7283 #define RPC_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1UL<<25) 7284 #define RPC_DEBUG5_HOLDREG_MC_EMPTY (1UL<<26) 7285 #define RPC_DEBUG5_HOLDREG_RC_EMPTY (1UL<<27) 7286 #define RPC_DEBUG5_HOLDREG_FC_EMPTY (1UL<<28) 7287 #define RPC_DEBUG5_HOLDREG_ACPI_EMPTY (1UL<<29) 7288 #define RPC_DEBUG5_HOLDREG_FULL_T (1UL<<30) 7289 #define RPC_DEBUG5_HOLDREG_RD (1UL<<31) 7290 7291 u32_t rpc_debug6; 7292 #define RPC_DEBUG6_ACPI_VEC (0xffffUL<<0) 7293 #define RPC_DEBUG6_VEC (0xffffUL<<16) 7294 7295 u32_t rpc_debug7; 7296 #define RPC_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffUL<<0) 7297 7298 u32_t rpc_debug8; 7299 #define RPC_DEBUG8_PS_ACPI_FSM (0xfUL<<0) 7300 #define RPC_DEBUG8_PS_ACPI_FSM_IDLE (0UL<<0) 7301 #define RPC_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1UL<<0) 7302 #define RPC_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2UL<<0) 7303 #define RPC_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3UL<<0) 7304 #define RPC_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4UL<<0) 7305 #define RPC_DEBUG8_PS_ACPI_FSM_W3_DATA (5UL<<0) 7306 #define RPC_DEBUG8_PS_ACPI_FSM_W0_ADDR (6UL<<0) 7307 #define RPC_DEBUG8_PS_ACPI_FSM_W1_ADDR (7UL<<0) 7308 #define RPC_DEBUG8_PS_ACPI_FSM_W2_ADDR (8UL<<0) 7309 #define RPC_DEBUG8_PS_ACPI_FSM_W3_ADDR (9UL<<0) 7310 #define RPC_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10UL<<0) 7311 #define RPC_DEBUG8_COMPARE_AT_W0 (1UL<<4) 7312 #define RPC_DEBUG8_COMPARE_AT_W3_DATA (1UL<<5) 7313 #define RPC_DEBUG8_COMPARE_AT_SOF_WAIT (1UL<<6) 7314 #define RPC_DEBUG8_COMPARE_AT_SOF_W3 (1UL<<7) 7315 #define RPC_DEBUG8_COMPARE_AT_SOF_W2 (1UL<<8) 7316 #define RPC_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1UL<<9) 7317 #define RPC_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1UL<<10) 7318 #define RPC_DEBUG8_NXT_EOF_W_12_VLDBYTES (1UL<<11) 7319 #define RPC_DEBUG8_EOF_DET (1UL<<12) 7320 #define RPC_DEBUG8_SOF_DET (1UL<<13) 7321 #define RPC_DEBUG8_WAIT_4_SOF (1UL<<14) 7322 #define RPC_DEBUG8_ALL_DONE (1UL<<15) 7323 #define RPC_DEBUG8_THBUF_ADDR (0x7fUL<<16) 7324 #define RPC_DEBUG8_BYTE_CTR (0xffUL<<24) 7325 7326 u32_t rpc_debug9; 7327 #define RPC_DEBUG9_OUTFIFO_COUNT (0x7UL<<0) 7328 #define RPC_DEBUG9_RDE_ACPI_RDY (1UL<<3) 7329 #define RPC_DEBUG9_VLD_RD_ENTRY_CT (0x7UL<<4) 7330 #define RPC_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1UL<<28) 7331 #define RPC_DEBUG9_INFIFO_OVERRUN_OCCURRED (1UL<<29) 7332 #define RPC_DEBUG9_ACPI_MATCH_INT (1UL<<30) 7333 #define RPC_DEBUG9_ACPI_ENABLE_SYN (1UL<<31) 7334 7335 u32_t unused_3[149]; 7336 } rpc_reg_t; 7337 7338 typedef rpc_reg_t rx_cu_parser_reg_t; 7339 7340 /* 7341 * rlupq definition 7342 * offset: 0000 7343 */ 7344 typedef struct rlupq 7345 { 7346 u32_t rlupq_ip_destadd0; 7347 u32_t rlupq_ip_destadd1; 7348 u32_t rlupq_ip_destadd2; 7349 u32_t rlupq_ip_destadd3; 7350 u32_t rlupq_wd4; 7351 #define RLUPQ_TCP_SRCPORT (0xffff<<16) 7352 #define RLUPQ_TCP_DSTPORT (0xffff<<0) 7353 7354 u32_t rlupq_wd5; 7355 #define RLUPQ_CS16 (0xffff<<16) 7356 7357 u32_t rlupq_wd6; 7358 #define RLUPQ_EXT_STATUS_TCP_SYNC_PRESENT (1<<16) 7359 #define RLUPQ_EXT_STATUS_RLUP_HIT2 (1<<17) 7360 #define RLUPQ_EXT_STATUS_TCP_UDP_XSUM_IS_0 (1<<18) 7361 #define RLUPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT (0x3<<19) 7362 #define RLUPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT_00 (0<<19) 7363 #define RLUPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT_01 (1<<19) 7364 #define RLUPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT_10 (2<<19) 7365 #define RLUPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT_11 (3<<19) 7366 #define RLUPQ_EXT_STATUS_ACPI_MATCH (1<<21) 7367 7368 u32_t unused_0[9]; 7369 u32_t rlupq_bits_errors; 7370 #define RLUPQ_BITS_ERRORS_L2_BAD_CRC (1UL<<1) 7371 #define RLUPQ_BITS_ERRORS_L2_PHY_DECODE (1UL<<2) 7372 #define RLUPQ_BITS_ERRORS_L2_ALIGNMENT (1UL<<3) 7373 #define RLUPQ_BITS_ERRORS_L2_TOO_SHORT (1UL<<4) 7374 #define RLUPQ_BITS_ERRORS_L2_GIANT_FRAME (1UL<<5) 7375 #define RLUPQ_BITS_ERRORS_IP_BAD_LEN (1UL<<6) 7376 #define RLUPQ_BITS_ERRORS_IP_TOO_SHORT (1UL<<7) 7377 #define RLUPQ_BITS_ERRORS_IP_BAD_VERSION (1UL<<8) 7378 #define RLUPQ_BITS_ERRORS_IP_BAD_HLEN (1UL<<9) 7379 #define RLUPQ_BITS_ERRORS_IP_BAD_XSUM (1UL<<10) 7380 #define RLUPQ_BITS_ERRORS_TCP_TOO_SHORT (1UL<<11) 7381 #define RLUPQ_BITS_ERRORS_TCP_BAD_XSUM (1UL<<12) 7382 #define RLUPQ_BITS_ERRORS_TCP_BAD_OFFSET (1UL<<13) 7383 #define RLUPQ_BITS_ERRORS_UDP_BAD_XSUM (1UL<<15) 7384 #define RLUPQ_BITS_ERRORS_IP_BAD_ORDER (1UL<<16) 7385 #define RLUPQ_BITS_ERRORS_IP_HDR_MISMATCH (1UL<<18) 7386 7387 u32_t rlupq_bits_status; 7388 #define RLUPQ_BITS_STATUS_RULE_CLASS (0x7UL<<0) 7389 #define RLUPQ_BITS_STATUS_RULE_P2 (1UL<<3) 7390 #define RLUPQ_BITS_STATUS_RULE_P3 (1UL<<4) 7391 #define RLUPQ_BITS_STATUS_RULE_P4 (1UL<<5) 7392 #define RLUPQ_BITS_STATUS_L2_VLAN_TAG (1UL<<6) 7393 #define RLUPQ_BITS_STATUS_L2_LLC_SNAP (1UL<<7) 7394 #define RLUPQ_BITS_STATUS_RSS_HASH (1UL<<8) 7395 #define RLUPQ_BITS_STATUS_SORT_VECT (0xfUL<<9) 7396 #define RLUPQ_BITS_STATUS_IP_DATAGRAM (1UL<<13) 7397 #define RLUPQ_BITS_STATUS_TCP_SEGMENT (1UL<<14) 7398 #define RLUPQ_BITS_STATUS_UDP_DATAGRAM (1UL<<15) 7399 #define RLUPQ_BITS_STATUS_CU_FRAME (1UL<<16) 7400 #define RLUPQ_BITS_STATUS_IP_PROG_EXT (1UL<<17) 7401 #define RLUPQ_BITS_STATUS_IP_TYPE (1UL<<18) 7402 #define RLUPQ_BITS_STATUS_RULE_P1 (1UL<<19) 7403 #define RLUPQ_BITS_STATUS_RLUP_HIT4 (1UL<<20) 7404 #define RLUPQ_BITS_STATUS_IP_FRAGMENT (1UL<<21) 7405 #define RLUPQ_BITS_STATUS_IP_OPTIONS_PRESENT (1UL<<22) 7406 #define RLUPQ_BITS_STATUS_TCP_OPTIONS_PRESENT (1UL<<23) 7407 #define RLUPQ_BITS_STATUS_L2_PM_IDX (0xfUL<<24) 7408 #define RLUPQ_BITS_STATUS_L2_PM_HIT (1UL<<28) 7409 #define RLUPQ_BITS_STATUS_L2_MC_HASH_HIT (1UL<<29) 7410 #define RLUPQ_BITS_STATUS_RDMAC_CRC_PASS (1UL<<30) 7411 #define RLUPQ_BITS_STATUS_MP_HIT (1UL<<31) 7412 7413 u32_t rlupq_wd18; 7414 #define RLUPQ_BITS_MULTICAST_HASH_IDX (0xff<<24) 7415 #define RLUPQ_BITS_ACPI_PAT_ACPI_PAT (0xf<<16) 7416 #define RLUPQ_BITS_ACPI_PAT_ACPI_PAT_0 (0<<16) 7417 #define RLUPQ_BITS_ACPI_PAT_ACPI_PAT_1 (1<<16) 7418 #define RLUPQ_BITS_ACPI_PAT_ACPI_PAT_2 (2<<16) 7419 #define RLUPQ_BITS_ACPI_PAT_ACPI_PAT_3 (3<<16) 7420 #define RLUPQ_BITS_ACPI_PAT_ACPI_PAT_4 (4<<16) 7421 #define RLUPQ_BITS_ACPI_PAT_ACPI_PAT_5 (5<<16) 7422 #define RLUPQ_BITS_ACPI_PAT_ACPI_PAT_6 (6<<16) 7423 #define RLUPQ_BITS_ACPI_PAT_ACPI_PAT_NONE (7<<16) 7424 #define RLUPQ_BITS_ACPI_PAT_ACPI_PAT_8 (8<<16) 7425 #define RLUPQ_KNUM (0xff<<8) 7426 7427 u32_t rlupq_wd19; 7428 #define RLUPQ_RULE_TAG (0xffff<<16) 7429 #define RLUPQ_PKT_LEN_VALUE (0x3fff<<0) 7430 7431 u32_t rlupq_wd20; 7432 #define RLUPQ_VLAN_TAG (0xffff<<16) 7433 #define RLUPQ_IP_HDR_OFFSET (0xff<<8) 7434 7435 u32_t rlupq_wd21; 7436 #define RLUPQ_IP_XSUM (0xffff<<16) 7437 #define RLUPQ_TCP_UDP_HDR_OFFSET (0xffff<<0) 7438 7439 u32_t rlupq_wd22; 7440 #define RLUPQ_TCP_UDP_XSUM (0xffff<<16) 7441 #define RLUPQ_TCP_PAYLOAD_LEN (0xffff<<0) 7442 7443 u32_t rlupq_wd23; 7444 #define RLUPQ_PSEUD_XSUM (0xffff<<16) 7445 #define RLUPQ_L2_PAYLOAD_RAW_XSUM (0xffff<<0) 7446 7447 u32_t rlupq_wd24; 7448 #define RLUPQ_DATA_OFFSET (0xffff<<16) 7449 #define RLUPQ_L3_PAYLOAD_RAW_XSUM (0xffff<<0) 7450 7451 u32_t rlupq_mbuf_cluster; 7452 #define RLUPQ_MBUF_CLUSTER_VALUE (0x1ffffffUL<<0) 7453 7454 u32_t rlupq_ip_srcadd0; 7455 u32_t rlupq_ip_srcadd1; 7456 u32_t rlupq_ip_srcadd2; 7457 u32_t rlupq_ip_srcadd3; 7458 } rlupq_t; 7459 7460 7461 /* 7462 * rlup_reg definition 7463 * offset: 0x2000 7464 */ 7465 typedef struct rlup_reg 7466 { 7467 u32_t rlup_command; 7468 #define RLUP_COMMAND_ENABLED (1UL<<0) 7469 #define RLUP_COMMAND_ADD (1UL<<1) 7470 #define RLUP_COMMAND_INVALIDATE (1UL<<2) 7471 #define RLUP_COMMAND_LOOKUP (1UL<<3) 7472 #define RLUP_COMMAND_READ_TE (1UL<<4) 7473 #define RLUP_COMMAND_WRITE_TE (1UL<<5) 7474 #define RLUP_COMMAND_READ_CAM_XI (1UL<<4) 7475 #define RLUP_COMMAND_WRITE_CAM_XI (1UL<<5) 7476 #define RLUP_COMMAND_CAM_RESET (1UL<<6) 7477 #define RLUP_COMMAND_READ_RAM (1UL<<7) 7478 #define RLUP_COMMAND_WRITE_RAM (1UL<<8) 7479 #define RLUP_COMMAND_ENTRY_TYPE (0x3UL<<9) 7480 #define RLUP_COMMAND_ENTRY_TYPE_IPV4 (0UL<<9) 7481 #define RLUP_COMMAND_ENTRY_TYPE_IPV6_4_TUPLE (1UL<<9) 7482 #define RLUP_COMMAND_ENTRY_TYPE_IPV6_2_TUPLE (2UL<<9) 7483 #define RLUP_COMMAND_ENTRY_TYPE_RES (3UL<<9) 7484 #define RLUP_COMMAND_2ND_TUPLE_LOOKUP_EN (1UL<<11) 7485 #define RLUP_COMMAND_MAINTENANCE_MODE (1UL<<12) 7486 7487 u32_t rlup_status; 7488 #define RLUP_STATUS_FTQ (1UL<<0) 7489 #define RLUP_STATUS_SUCCESS (1UL<<1) 7490 #define RLUP_STATUS_WORD_MATCH_TE (1UL<<2) 7491 #define RLUP_STATUS_LOOKUP_MATCH_STAT_TE (1UL<<3) 7492 #define RLUP_STATUS_LOOKUP_SM_TE (0x7UL<<16) 7493 #define RLUP_STATUS_LOOKUP_SM_IDLE_TE (0UL<<16) 7494 #define RLUP_STATUS_LOOKUP_SM_INPUT_TE (1UL<<16) 7495 #define RLUP_STATUS_LOOKUP_SM_CAM_GRC_TE (2UL<<16) 7496 #define RLUP_STATUS_LOOKUP_SM_CAM_STROBE_TE (3UL<<16) 7497 #define RLUP_STATUS_LOOKUP_SM_CAM_WAIT_TE (4UL<<16) 7498 #define RLUP_STATUS_LOOKUP_SM_RSS_WAIT_TE (5UL<<16) 7499 #define RLUP_STATUS_LOOKUP_SM_FTQ_WR_TE (6UL<<16) 7500 #define RLUP_STATUS_LOOKUP_SM_FTQ_POP_TE (7UL<<16) 7501 #define RLUP_STATUS_REGCAM_SM_TE (0x3UL<<20) 7502 #define RLUP_STATUS_REGCAM_SM_IDLE_TE (0UL<<20) 7503 #define RLUP_STATUS_REGCAM_SM_STROBE_TE (1UL<<20) 7504 #define RLUP_STATUS_REGCAM_SM_WAIT_TE (2UL<<20) 7505 #define RLUP_STATUS_ACK_SM_TE (0x3UL<<24) 7506 #define RLUP_STATUS_ACK_SM_IDLE_TE (0UL<<24) 7507 #define RLUP_STATUS_ACK_SM_WAIT_TE (1UL<<24) 7508 #define RLUP_STATUS_ACK_SM_STROBE_TE (2UL<<24) 7509 #define RLUP_STATUS_LOOKUP_MATCH_STAT_XI (1UL<<2) 7510 #define RLUP_STATUS_2TUPLE_LOOKUP_MATCH_STAT_XI (1UL<<3) 7511 #define RLUP_STATUS_CAM_FULL_XI (1UL<<4) 7512 #define RLUP_STATUS_DUPLICATE_ENTRY_XI (1UL<<5) 7513 #define RLUP_STATUS_ZERO_CNT_ERR_XI (1UL<<6) 7514 7515 u32_t rlup_ipsrc; 7516 u32_t rlup_ipdest; 7517 u32_t rlup_tcpport; 7518 #define RLUP_TCPPORT_DESTPORT (0xffffUL<<0) 7519 #define RLUP_TCPPORT_SRCPORT (0xffffUL<<16) 7520 7521 u32_t rlup_cid; 7522 #define RLUP_CID_VALUE (0x3fffUL<<7) 7523 #define RLUP_CID_VALID (1UL<<31) 7524 7525 u32_t rlup_idx; 7526 #define RLUP_IDX_IDX_VALUE (0x3ffUL<<0) 7527 7528 u32_t rlup_rss_config; 7529 #define RLUP_RSS_CONFIG_RSS_TE (0x3UL<<0) 7530 #define RLUP_RSS_CONFIG_RSS_OFF_TE (0UL<<0) 7531 #define RLUP_RSS_CONFIG_RSS_ALL_TE (1UL<<0) 7532 #define RLUP_RSS_CONFIG_RSS_IP_ONLY_TE (2UL<<0) 7533 #define RLUP_RSS_CONFIG_RSS_RES_TE (3UL<<0) 7534 #define RLUP_RSS_CONFIG_IPV4_RSS_TYPE_XI (0x3UL<<0) 7535 #define RLUP_RSS_CONFIG_IPV4_RSS_TYPE_OFF_XI (0UL<<0) 7536 #define RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI (1UL<<0) 7537 #define RLUP_RSS_CONFIG_IPV4_RSS_TYPE_IP_ONLY_XI (2UL<<0) 7538 #define RLUP_RSS_CONFIG_IPV4_RSS_TYPE_RES_XI (3UL<<0) 7539 #define RLUP_RSS_CONFIG_IPV6_RSS_TYPE_XI (0x3UL<<2) 7540 #define RLUP_RSS_CONFIG_IPV6_RSS_TYPE_OFF_XI (0UL<<2) 7541 #define RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI (1UL<<2) 7542 #define RLUP_RSS_CONFIG_IPV6_RSS_TYPE_IP_ONLY_XI (2UL<<2) 7543 #define RLUP_RSS_CONFIG_IPV6_RSS_TYPE_RES_XI (3UL<<2) 7544 7545 u32_t rlup_rss_key1; 7546 u32_t rlup_rss_key2; 7547 u32_t rlup_rss_key3; 7548 u32_t rlup_rss_key4; 7549 u32_t rlup_ipv6_rss_key5; 7550 u32_t rlup_ipv6_rss_key6; 7551 u32_t rlup_ipv6_rss_key7; 7552 u32_t rlup_ipv6_rss_key8; 7553 u32_t rlup_ipv6_rss_key9; 7554 u32_t rlup_ipv6_rss_key10; 7555 u32_t rlup_rss_command; 7556 #define RLUP_RSS_COMMAND_RSS_IND_TABLE_ADDR (0xfUL<<0) 7557 #define RLUP_RSS_COMMAND_RSS_WRITE_MASK (0xffUL<<4) 7558 #define RLUP_RSS_COMMAND_WRITE (1UL<<12) 7559 #define RLUP_RSS_COMMAND_READ (1UL<<13) 7560 #define RLUP_RSS_COMMAND_HASH_MASK (0x7UL<<14) 7561 7562 u32_t rlup_rss_data; 7563 #define RLUP_RSS_DATA_RSS_D0 (0xfUL<<0) 7564 #define RLUP_RSS_DATA_RSS_D1 (0xfUL<<4) 7565 #define RLUP_RSS_DATA_RSS_D2 (0xfUL<<8) 7566 #define RLUP_RSS_DATA_RSS_D3 (0xfUL<<12) 7567 #define RLUP_RSS_DATA_RSS_D4 (0xfUL<<16) 7568 #define RLUP_RSS_DATA_RSS_D5 (0xfUL<<20) 7569 #define RLUP_RSS_DATA_RSS_D6 (0xfUL<<24) 7570 #define RLUP_RSS_DATA_RSS_D7 (0xfUL<<28) 7571 7572 u32_t unused_0[9]; 7573 u32_t rlup_free_count; 7574 #define RLUP_FREE_COUNT_FREE_COUNT (0x7ffUL<<0) 7575 7576 u32_t rlup_ipv6_src1; 7577 u32_t rlup_ipv6_src2; 7578 u32_t rlup_ipv6_src3; 7579 u32_t rlup_ipv6_src4; 7580 u32_t rlup_ipv6_dest1; 7581 u32_t rlup_ipv6_dest2; 7582 u32_t rlup_ipv6_dest3; 7583 u32_t rlup_ipv6_dest4; 7584 u32_t unused_1[154]; 7585 u32_t rlup_cam_bist_command; 7586 #define RLUP_CAM_BIST_COMMAND_BIST_RST_B (1UL<<0) 7587 #define RLUP_CAM_BIST_COMMAND_BIST_EN (1UL<<1) 7588 #define RLUP_CAM_BIST_COMMAND_BIST_DONE (1UL<<2) 7589 #define RLUP_CAM_BIST_COMMAND_BIST_PASSED (1UL<<3) 7590 7591 u32_t rlup_cam_bist_status0; 7592 #define RLUP_CAM_BIST_STATUS0_MATCH_STATUS (1UL<<0) 7593 #define RLUP_CAM_BIST_STATUS0_ACTUAL_BITPOS (0x7fUL<<1) 7594 #define RLUP_CAM_BIST_STATUS0_ACTUAL_ADDROUT (0x3ffUL<<8) 7595 7596 u32_t rlup_cam_bist_status1; 7597 #define RLUP_CAM_BIST_STATUS1_MATCH_STATUS (1UL<<0) 7598 #define RLUP_CAM_BIST_STATUS1_ADDROUT_STATUS (1UL<<1) 7599 #define RLUP_CAM_BIST_STATUS1_ACTUAL_ADDROUT (0x3ffUL<<2) 7600 #define RLUP_CAM_BIST_STATUS1_EXPECTED_ADDROUT (0x3ffUL<<12) 7601 7602 u32_t rlup_cam_bist_status2; 7603 #define RLUP_CAM_BIST_STATUS2_MATCH_STATUS (1UL<<0) 7604 #define RLUP_CAM_BIST_STATUS2_ACTUAL_BITPOS (0x7fUL<<1) 7605 #define RLUP_CAM_BIST_STATUS2_ACTUAL_ADDROUT (0x3ffUL<<8) 7606 7607 u32_t rlup_cam_bist_status3; 7608 #define RLUP_CAM_BIST_STATUS3_MATCH_STATUS (1UL<<0) 7609 #define RLUP_CAM_BIST_STATUS3_ADDROUT_STATUS (1UL<<1) 7610 #define RLUP_CAM_BIST_STATUS3_ACTUAL_ADDROUT (0x3ffUL<<2) 7611 #define RLUP_CAM_BIST_STATUS3_EXPECTED_ADDROUT (0x3ffUL<<12) 7612 7613 u32_t rlup_cam_bist_status4; 7614 #define RLUP_CAM_BIST_STATUS4_MATCH_STATUS (1UL<<0) 7615 #define RLUP_CAM_BIST_STATUS4_ACTUAL_ADDROUT (0x3ffUL<<1) 7616 7617 u32_t unused_2[10]; 7618 u32_t rlup_debug_vect_peek; 7619 #define RLUP_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) 7620 #define RLUP_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) 7621 #define RLUP_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) 7622 #define RLUP_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) 7623 #define RLUP_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) 7624 #define RLUP_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) 7625 7626 u32_t unused_3[15]; 7627 rlupq_t rlup_rlupq; 7628 u32_t rlup_ftq_cmd; 7629 #define RLUP_FTQ_CMD_OFFSET (0x3ffUL<<0) 7630 #define RLUP_FTQ_CMD_WR_TOP (1UL<<10) 7631 #define RLUP_FTQ_CMD_WR_TOP_0 (0UL<<10) 7632 #define RLUP_FTQ_CMD_WR_TOP_1 (1UL<<10) 7633 #define RLUP_FTQ_CMD_SFT_RESET (1UL<<25) 7634 #define RLUP_FTQ_CMD_RD_DATA (1UL<<26) 7635 #define RLUP_FTQ_CMD_ADD_INTERVEN (1UL<<27) 7636 #define RLUP_FTQ_CMD_ADD_DATA (1UL<<28) 7637 #define RLUP_FTQ_CMD_INTERVENE_CLR (1UL<<29) 7638 #define RLUP_FTQ_CMD_POP (1UL<<30) 7639 #define RLUP_FTQ_CMD_BUSY (1UL<<31) 7640 7641 u32_t rlup_ftq_ctl; 7642 #define RLUP_FTQ_CTL_INTERVENE (1UL<<0) 7643 #define RLUP_FTQ_CTL_OVERFLOW (1UL<<1) 7644 #define RLUP_FTQ_CTL_FORCE_INTERVENE (1UL<<2) 7645 #define RLUP_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) 7646 #define RLUP_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) 7647 7648 } rlup_reg_t; 7649 7650 typedef rlup_reg_t rx_lookup_reg_t; 7651 7652 /* 7653 * rx_v2p_mailbox_enqueue definition 7654 * offset: 0000 7655 */ 7656 typedef struct rx_v2p_mailbox_enqueue 7657 { 7658 u32_t rx_v2p_mailbox_enqueue_cid; 7659 #define RX_V2P_MAILBOX_ENQUEUE_CID_VALUE (0x3fffUL<<7) 7660 7661 } rx_v2p_mailbox_enqueue_t; 7662 7663 7664 /* 7665 * rx_v2p_timeout_enqueue definition 7666 * offset: 0000 7667 */ 7668 typedef struct rx_v2p_timeout_enqueue 7669 { 7670 u32_t rx_v2p_timeout_enqueue_cid; 7671 #define RX_V2P_TIMEOUT_ENQUEUE_CID_VALUE (0x3fffUL<<7) 7672 7673 } rx_v2p_timeout_enqueue_t; 7674 7675 7676 /* 7677 * rx_v2p_enqueue definition 7678 * offset: 0000 7679 */ 7680 typedef struct rx_v2p_enqueue 7681 { 7682 u32_t rx_v2p_enqueue_cid; 7683 #define RX_V2P_ENQUEUE_CID_VALUE (0x3fffUL<<7) 7684 7685 u32_t rx_v2p_enqueue_mbuf_cluster; 7686 #define RX_V2P_ENQUEUE_MBUF_CLUSTER_VALUE (0x1ffffffUL<<0) 7687 7688 u32_t rx_v2p_enqueue_wd2; 7689 #define RX_V2P_ENQUEUE_OPERAND_FLAGS (0xffff<<16) 7690 #define RX_V2P_ENQUEUE_KNUM (0xff<<8) 7691 #define RX_V2P_ENQUEUE_OPCODE (0xff<<0) 7692 7693 u32_t rx_v2p_enqueue_wd3; 7694 #define RX_V2P_ENQUEUE_OPERAND16_0 (0xffff<<16) 7695 #define RX_V2P_ENQUEUE_OPERAND16_1 (0xffff<<0) 7696 7697 u32_t rx_v2p_enqueue_wd4; 7698 #define RX_V2P_ENQUEUE_OPERAND16_2 (0xffff<<16) 7699 #define RX_V2P_ENQUEUE_OPERAND16_3 (0xffff<<0) 7700 7701 u32_t rx_v2p_enqueue_wd5; 7702 #define RX_V2P_ENQUEUE_OPERAND16_4 (0xffff<<16) 7703 #define RX_V2P_ENQUEUE_OPERAND16_5 (0xffff<<0) 7704 7705 u32_t rx_v2p_enqueue_wd6; 7706 #define RX_V2P_ENQUEUE_OPERAND16_6 (0xffff<<16) 7707 #define RX_V2P_ENQUEUE_OPERAND16_7 (0xffff<<0) 7708 7709 u32_t rx_v2p_enqueue_operand32_0; 7710 u32_t rx_v2p_enqueue_operand32_1; 7711 u32_t rx_v2p_enqueue_operand32_2; 7712 u32_t rx_v2p_enqueue_operand32_3; 7713 u32_t rx_v2p_enqueue_operand32_4; 7714 u32_t rx_v2p_enqueue_wd12; 7715 #define RX_V2P_ENQUEUE_RDMA_ACTION_CS16_VLD (1<<30) 7716 #define RX_V2P_ENQUEUE_RDMA_ACTION_NO_SNOOP (1<<31) 7717 #define RX_V2P_ENQUEUE_CS16_PKT_LEN_VALUE (0x7f<<16) 7718 #define RX_V2P_ENQUEUE_CS16 (0xffff<<0) 7719 7720 } rx_v2p_enqueue_t; 7721 7722 7723 /* 7724 * rv2p_reg definition 7725 * offset: 0x2800 7726 */ 7727 typedef struct rv2p_reg 7728 { 7729 u32_t rv2p_command; 7730 #define RV2P_COMMAND_ENABLED (1UL<<0) 7731 #define RV2P_COMMAND_PROC1_INTRPT (1UL<<1) 7732 #define RV2P_COMMAND_PROC2_INTRPT (1UL<<2) 7733 #define RV2P_COMMAND_ABORT0 (1UL<<4) 7734 #define RV2P_COMMAND_ABORT1 (1UL<<5) 7735 #define RV2P_COMMAND_ABORT2 (1UL<<6) 7736 #define RV2P_COMMAND_ABORT3 (1UL<<7) 7737 #define RV2P_COMMAND_ABORT4 (1UL<<8) 7738 #define RV2P_COMMAND_ABORT5 (1UL<<9) 7739 #define RV2P_COMMAND_PROC1_RESET (1UL<<16) 7740 #define RV2P_COMMAND_PROC2_RESET (1UL<<17) 7741 #define RV2P_COMMAND_CTXIF_RESET (1UL<<18) 7742 7743 u32_t rv2p_status; 7744 #define RV2P_STATUS_ALWAYS_0 (1UL<<0) 7745 #define RV2P_STATUS_RV2P_GEN_STAT0_CNT (1UL<<8) 7746 #define RV2P_STATUS_RV2P_GEN_STAT1_CNT (1UL<<9) 7747 #define RV2P_STATUS_RV2P_GEN_STAT2_CNT (1UL<<10) 7748 #define RV2P_STATUS_RV2P_GEN_STAT3_CNT (1UL<<11) 7749 #define RV2P_STATUS_RV2P_GEN_STAT4_CNT (1UL<<12) 7750 #define RV2P_STATUS_RV2P_GEN_STAT5_CNT (1UL<<13) 7751 7752 u32_t rv2p_config; 7753 #define RV2P_CONFIG_STALL_PROC1 (1UL<<0) 7754 #define RV2P_CONFIG_STALL_PROC2 (1UL<<1) 7755 #define RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1UL<<8) 7756 #define RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1UL<<9) 7757 #define RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1UL<<10) 7758 #define RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1UL<<11) 7759 #define RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1UL<<12) 7760 #define RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1UL<<13) 7761 #define RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1UL<<16) 7762 #define RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1UL<<17) 7763 #define RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1UL<<18) 7764 #define RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1UL<<19) 7765 #define RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1UL<<20) 7766 #define RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1UL<<21) 7767 #define RV2P_CONFIG_PAGE_SIZE (0xfUL<<24) 7768 #define RV2P_CONFIG_PAGE_SIZE_256 (0UL<<24) 7769 #define RV2P_CONFIG_PAGE_SIZE_512 (1UL<<24) 7770 #define RV2P_CONFIG_PAGE_SIZE_1K (2UL<<24) 7771 #define RV2P_CONFIG_PAGE_SIZE_2K (3UL<<24) 7772 #define RV2P_CONFIG_PAGE_SIZE_4K (4UL<<24) 7773 #define RV2P_CONFIG_PAGE_SIZE_8K (5UL<<24) 7774 #define RV2P_CONFIG_PAGE_SIZE_16K (6UL<<24) 7775 #define RV2P_CONFIG_PAGE_SIZE_32K (7UL<<24) 7776 #define RV2P_CONFIG_PAGE_SIZE_64K (8UL<<24) 7777 #define RV2P_CONFIG_PAGE_SIZE_128K (9UL<<24) 7778 #define RV2P_CONFIG_PAGE_SIZE_256K (10UL<<24) 7779 #define RV2P_CONFIG_PAGE_SIZE_512K (11UL<<24) 7780 #define RV2P_CONFIG_PAGE_SIZE_1M (12UL<<24) 7781 7782 u32_t unused_0; 7783 u32_t rv2p_gen_bfr_addr_0; 7784 #define RV2P_GEN_BFR_ADDR_0_VALUE (0xffffUL<<16) 7785 7786 u32_t rv2p_gen_bfr_addr_1; 7787 #define RV2P_GEN_BFR_ADDR_1_VALUE (0xffffUL<<16) 7788 7789 u32_t rv2p_gen_bfr_addr_2; 7790 #define RV2P_GEN_BFR_ADDR_2_VALUE (0xffffUL<<16) 7791 7792 u32_t rv2p_gen_bfr_addr_3; 7793 #define RV2P_GEN_BFR_ADDR_3_VALUE (0xffffUL<<16) 7794 7795 u32_t unused_1[4]; 7796 u32_t rv2p_instr_high; 7797 #define RV2P_INSTR_HIGH_HIGH (0x1fUL<<0) 7798 7799 u32_t rv2p_instr_low; 7800 #define RV2P_INSTR_LOW_LOW (0xffffffffUL<<0) 7801 7802 u32_t rv2p_proc1_addr_cmd; 7803 #define RV2P_PROC1_ADDR_CMD_ADD (0x3ffUL<<0) 7804 #define RV2P_PROC1_ADDR_CMD_RDWR (1UL<<31) 7805 7806 u32_t rv2p_proc2_addr_cmd; 7807 #define RV2P_PROC2_ADDR_CMD_ADD (0x3ffUL<<0) 7808 #define RV2P_PROC2_ADDR_CMD_RDWR (1UL<<31) 7809 7810 u32_t rv2p_proc1_grc_debug; 7811 u32_t rv2p_proc2_grc_debug; 7812 u32_t rv2p_grc_proc_debug; 7813 u32_t rv2p_debug_vect_peek; 7814 #define RV2P_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) 7815 #define RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) 7816 #define RV2P_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) 7817 #define RV2P_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) 7818 #define RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) 7819 #define RV2P_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) 7820 7821 u32_t unused_2[171]; 7822 u32_t rv2p_mpfe_pfe_ctl; 7823 #define RV2P_MPFE_PFE_CTL_INC_USAGE_CNT (1UL<<0) 7824 #define RV2P_MPFE_PFE_CTL_PFE_SIZE (0xfUL<<4) 7825 #define RV2P_MPFE_PFE_CTL_PFE_SIZE_0 (0UL<<4) 7826 #define RV2P_MPFE_PFE_CTL_PFE_SIZE_1 (1UL<<4) 7827 #define RV2P_MPFE_PFE_CTL_PFE_SIZE_2 (2UL<<4) 7828 #define RV2P_MPFE_PFE_CTL_PFE_SIZE_3 (3UL<<4) 7829 #define RV2P_MPFE_PFE_CTL_PFE_SIZE_4 (4UL<<4) 7830 #define RV2P_MPFE_PFE_CTL_PFE_SIZE_5 (5UL<<4) 7831 #define RV2P_MPFE_PFE_CTL_PFE_SIZE_6 (6UL<<4) 7832 #define RV2P_MPFE_PFE_CTL_PFE_SIZE_7 (7UL<<4) 7833 #define RV2P_MPFE_PFE_CTL_PFE_SIZE_8 (8UL<<4) 7834 #define RV2P_MPFE_PFE_CTL_PFE_SIZE_9 (9UL<<4) 7835 #define RV2P_MPFE_PFE_CTL_PFE_SIZE_10 (10UL<<4) 7836 #define RV2P_MPFE_PFE_CTL_PFE_SIZE_11 (11UL<<4) 7837 #define RV2P_MPFE_PFE_CTL_PFE_SIZE_12 (12UL<<4) 7838 #define RV2P_MPFE_PFE_CTL_PFE_SIZE_13 (13UL<<4) 7839 #define RV2P_MPFE_PFE_CTL_PFE_SIZE_14 (14UL<<4) 7840 #define RV2P_MPFE_PFE_CTL_PFE_SIZE_15 (15UL<<4) 7841 #define RV2P_MPFE_PFE_CTL_PFE_COUNT (0xfUL<<12) 7842 #define RV2P_MPFE_PFE_CTL_OFFSET (0x1ffUL<<16) 7843 7844 u32_t unused_3[16]; 7845 rx_v2p_enqueue_t rv2p_rv2ppq; 7846 u32_t unused_4; 7847 u32_t rv2p_pftq_cmd; 7848 #define RV2P_PFTQ_CMD_OFFSET (0x3ffUL<<0) 7849 #define RV2P_PFTQ_CMD_WR_TOP (1UL<<10) 7850 #define RV2P_PFTQ_CMD_WR_TOP_0 (0UL<<10) 7851 #define RV2P_PFTQ_CMD_WR_TOP_1 (1UL<<10) 7852 #define RV2P_PFTQ_CMD_SFT_RESET (1UL<<25) 7853 #define RV2P_PFTQ_CMD_RD_DATA (1UL<<26) 7854 #define RV2P_PFTQ_CMD_ADD_INTERVEN (1UL<<27) 7855 #define RV2P_PFTQ_CMD_ADD_DATA (1UL<<28) 7856 #define RV2P_PFTQ_CMD_INTERVENE_CLR (1UL<<29) 7857 #define RV2P_PFTQ_CMD_POP (1UL<<30) 7858 #define RV2P_PFTQ_CMD_BUSY (1UL<<31) 7859 7860 u32_t rv2p_pftq_ctl; 7861 #define RV2P_PFTQ_CTL_INTERVENE (1UL<<0) 7862 #define RV2P_PFTQ_CTL_OVERFLOW (1UL<<1) 7863 #define RV2P_PFTQ_CTL_FORCE_INTERVENE (1UL<<2) 7864 #define RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffUL<<12) 7865 #define RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffUL<<22) 7866 7867 rx_v2p_timeout_enqueue_t rv2p_rv2ptq; 7868 u32_t unused_5[13]; 7869 u32_t rv2p_tftq_cmd; 7870 #define RV2P_TFTQ_CMD_OFFSET (0x3ffUL<<0) 7871 #define RV2P_TFTQ_CMD_WR_TOP (1UL<<10) 7872 #define RV2P_TFTQ_CMD_WR_TOP_0 (0UL<<10) 7873 #define RV2P_TFTQ_CMD_WR_TOP_1 (1UL<<10) 7874 #define RV2P_TFTQ_CMD_SFT_RESET (1UL<<25) 7875 #define RV2P_TFTQ_CMD_RD_DATA (1UL<<26) 7876 #define RV2P_TFTQ_CMD_ADD_INTERVEN (1UL<<27) 7877 #define RV2P_TFTQ_CMD_ADD_DATA (1UL<<28) 7878 #define RV2P_TFTQ_CMD_INTERVENE_CLR (1UL<<29) 7879 #define RV2P_TFTQ_CMD_POP (1UL<<30) 7880 #define RV2P_TFTQ_CMD_BUSY (1UL<<31) 7881 7882 u32_t rv2p_tftq_ctl; 7883 #define RV2P_TFTQ_CTL_INTERVENE (1UL<<0) 7884 #define RV2P_TFTQ_CTL_OVERFLOW (1UL<<1) 7885 #define RV2P_TFTQ_CTL_FORCE_INTERVENE (1UL<<2) 7886 #define RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffUL<<12) 7887 #define RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffUL<<22) 7888 7889 rx_v2p_mailbox_enqueue_t rv2p_rv2pmq; 7890 u32_t unused_6[13]; 7891 u32_t rv2p_mftq_cmd; 7892 #define RV2P_MFTQ_CMD_OFFSET (0x3ffUL<<0) 7893 #define RV2P_MFTQ_CMD_WR_TOP (1UL<<10) 7894 #define RV2P_MFTQ_CMD_WR_TOP_0 (0UL<<10) 7895 #define RV2P_MFTQ_CMD_WR_TOP_1 (1UL<<10) 7896 #define RV2P_MFTQ_CMD_SFT_RESET (1UL<<25) 7897 #define RV2P_MFTQ_CMD_RD_DATA (1UL<<26) 7898 #define RV2P_MFTQ_CMD_ADD_INTERVEN (1UL<<27) 7899 #define RV2P_MFTQ_CMD_ADD_DATA (1UL<<28) 7900 #define RV2P_MFTQ_CMD_INTERVENE_CLR (1UL<<29) 7901 #define RV2P_MFTQ_CMD_POP (1UL<<30) 7902 #define RV2P_MFTQ_CMD_BUSY (1UL<<31) 7903 7904 u32_t rv2p_mftq_ctl; 7905 #define RV2P_MFTQ_CTL_INTERVENE (1UL<<0) 7906 #define RV2P_MFTQ_CTL_OVERFLOW (1UL<<1) 7907 #define RV2P_MFTQ_CTL_FORCE_INTERVENE (1UL<<2) 7908 #define RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffUL<<12) 7909 #define RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffUL<<22) 7910 7911 } rv2p_reg_t; 7912 7913 typedef rv2p_reg_t rx_v2p_reg_t; 7914 7915 /* 7916 * rx_dma_enqueue definition 7917 * offset: 0000 7918 */ 7919 typedef struct rx_dma_enqueue 7920 { 7921 u32_t rx_dma_enqueue_cid; 7922 #define RX_DMA_ENQUEUE_CID_VALUE (0x3fffUL<<7) 7923 7924 u32_t rx_dma_enqueue_mbuf_cluster; 7925 #define RX_DMA_ENQUEUE_MBUF_CLUSTER_VALUE (0x1ffffffUL<<0) 7926 7927 u32_t rx_dma_enqueue_wd2; 7928 #define RX_DMA_ENQUEUE_OPERAND_FLAGS (0xffff<<16) 7929 #define RX_DMA_ENQUEUE_KNUM (0xff<<8) 7930 #define RX_DMA_ENQUEUE_OPCODE (0xff<<0) 7931 7932 u32_t rx_dma_enqueue_wd3; 7933 #define RX_DMA_ENQUEUE_OPERAND16_0 (0xffff<<16) 7934 #define RX_DMA_ENQUEUE_OPERAND16_1 (0xffff<<0) 7935 7936 u32_t rx_dma_enqueue_wd4; 7937 #define RX_DMA_ENQUEUE_OPERAND16_2 (0xffff<<16) 7938 #define RX_DMA_ENQUEUE_OPERAND16_3 (0xffff<<0) 7939 7940 u32_t rx_dma_enqueue_wd5; 7941 #define RX_DMA_ENQUEUE_OPERAND16_4 (0xffff<<16) 7942 #define RX_DMA_ENQUEUE_OPERAND16_5 (0xffff<<0) 7943 7944 u32_t rx_dma_enqueue_wd6; 7945 #define RX_DMA_ENQUEUE_OPERAND16_6 (0xffff<<16) 7946 #define RX_DMA_ENQUEUE_OPERAND16_7 (0xffff<<0) 7947 7948 u32_t rx_dma_enqueue_operand32_0; 7949 u32_t rx_dma_enqueue_operand32_1; 7950 u32_t rx_dma_enqueue_operand32_2; 7951 u32_t rx_dma_enqueue_operand32_3; 7952 u32_t rx_dma_enqueue_operand32_4; 7953 u32_t rx_dma_enqueue_wd12; 7954 #define RX_DMA_ENQUEUE_RDMA_ACTION_DO_DMA (1<<24) 7955 #define RX_DMA_ENQUEUE_RDMA_ACTION_PREPEND_L2_FRAME_HDR (1<<25) 7956 #define RX_DMA_ENQUEUE_RDMA_ACTION_CRC_ENABLE (1<<26) 7957 #define RX_DMA_ENQUEUE_RDMA_ACTION_CRC_USE_CTX_SEED (1<<27) 7958 #define RX_DMA_ENQUEUE_RDMA_ACTION_CS16_FIRST (1<<28) 7959 #define RX_DMA_ENQUEUE_RDMA_ACTION_CS16_LAST (1<<29) 7960 #define RX_DMA_ENQUEUE_RDMA_ACTION_CS16_VLD (1<<30) 7961 #define RX_DMA_ENQUEUE_RDMA_ACTION_NO_SNOOP (1<<31) 7962 #define RX_DMA_ENQUEUE_CS16_PKT_LEN_VALUE (0x7f<<16) 7963 #define RX_DMA_ENQUEUE_CS16 (0xffff<<0) 7964 7965 } rx_dma_enqueue_t; 7966 7967 7968 /* 7969 * rdma_reg definition 7970 * offset: 0x2c00 7971 */ 7972 typedef struct rdma_reg 7973 { 7974 u32_t rdma_command; 7975 #define RDMA_COMMAND_ENABLED (1UL<<0) 7976 #define RDMA_COMMAND_MASTER_ABORT (1UL<<4) 7977 7978 u32_t rdma_status; 7979 #define RDMA_STATUS_DMA_WAIT (1UL<<0) 7980 #define RDMA_STATUS_MBUF_WAIT (1UL<<1) 7981 #define RDMA_STATUS_CMP_FTQ_WAIT (1UL<<2) 7982 #define RDMA_STATUS_DMA_CNT_STAT (1UL<<16) 7983 #define RDMA_STATUS_BURST_CNT_STAT (1UL<<17) 7984 #define RDMA_STATUS_ERR (0xffUL<<20) 7985 #define RDMA_STATUS_CS16_ERR (1UL<<31) 7986 7987 u32_t rdma_config; 7988 #define RDMA_CONFIG_MAX_DMAS (0x3UL<<0) 7989 #define RDMA_CONFIG_ONE_RECORD (1UL<<2) 7990 #define RDMA_CONFIG_CACHE_ALIGN_EN (1UL<<3) 7991 #define RDMA_CONFIG_LIMIT_SZ (0x7UL<<4) 7992 #define RDMA_CONFIG_LIMIT_SZ_8 (0UL<<4) 7993 #define RDMA_CONFIG_LIMIT_SZ_16 (1UL<<4) 7994 #define RDMA_CONFIG_LIMIT_SZ_32 (2UL<<4) 7995 #define RDMA_CONFIG_LIMIT_SZ_64 (3UL<<4) 7996 #define RDMA_CONFIG_LIMIT_SZ_128 (4UL<<4) 7997 #define RDMA_CONFIG_LIMIT_SZ_256 (5UL<<4) 7998 #define RDMA_CONFIG_LIMIT_SZ_512 (6UL<<4) 7999 #define RDMA_CONFIG_LINE_SZ (0x7UL<<8) 8000 #define RDMA_CONFIG_LINE_SZ_8 (0UL<<8) 8001 #define RDMA_CONFIG_LINE_SZ_16 (1UL<<8) 8002 #define RDMA_CONFIG_LINE_SZ_32 (2UL<<8) 8003 #define RDMA_CONFIG_LINE_SZ_64 (3UL<<8) 8004 #define RDMA_CONFIG_LINE_SZ_128 (4UL<<8) 8005 #define RDMA_CONFIG_LINE_SZ_256 (5UL<<8) 8006 #define RDMA_CONFIG_LINE_SZ_512 (6UL<<8) 8007 #define RDMA_CONFIG_DI_DISABLE (1UL<<12) 8008 #define RDMA_CONFIG_CTXCACHE_DISABLE (1UL<<16) 8009 #define RDMA_CONFIG_CRC_OFFSET (0x3ffUL<<18) 8010 #define RDMA_CONFIG_DMA_BREAKUP (0x3UL<<28) 8011 #define RDMA_CONFIG_DMA_BREAKUP_00 (0UL<<28) 8012 #define RDMA_CONFIG_DMA_BREAKUP_01 (1UL<<28) 8013 #define RDMA_CONFIG_DMA_BREAKUP_10 (2UL<<28) 8014 #define RDMA_CONFIG_DMA_BREAKUP_11 (3UL<<28) 8015 #define RDMA_CONFIG_DMA_BREAK_OVERRIDE (1UL<<31) 8016 8017 u32_t rdma_debug_vect_peek; 8018 #define RDMA_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) 8019 #define RDMA_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) 8020 #define RDMA_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) 8021 #define RDMA_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) 8022 #define RDMA_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) 8023 #define RDMA_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) 8024 8025 u32_t rdma_cksum_error_status; 8026 #define RDMA_CKSUM_ERROR_STATUS_CALCULATED (0xffffUL<<0) 8027 #define RDMA_CKSUM_ERROR_STATUS_EXPECTED (0xffffUL<<16) 8028 8029 u32_t unused_0[235]; 8030 rx_dma_enqueue_t rdma_rdmaq; 8031 u32_t unused_1; 8032 u32_t rdma_ftq_cmd; 8033 #define RDMA_FTQ_CMD_OFFSET (0x3ffUL<<0) 8034 #define RDMA_FTQ_CMD_WR_TOP (1UL<<10) 8035 #define RDMA_FTQ_CMD_WR_TOP_0 (0UL<<10) 8036 #define RDMA_FTQ_CMD_WR_TOP_1 (1UL<<10) 8037 #define RDMA_FTQ_CMD_SFT_RESET (1UL<<25) 8038 #define RDMA_FTQ_CMD_RD_DATA (1UL<<26) 8039 #define RDMA_FTQ_CMD_ADD_INTERVEN (1UL<<27) 8040 #define RDMA_FTQ_CMD_ADD_DATA (1UL<<28) 8041 #define RDMA_FTQ_CMD_INTERVENE_CLR (1UL<<29) 8042 #define RDMA_FTQ_CMD_POP (1UL<<30) 8043 #define RDMA_FTQ_CMD_BUSY (1UL<<31) 8044 8045 u32_t rdma_ftq_ctl; 8046 #define RDMA_FTQ_CTL_INTERVENE (1UL<<0) 8047 #define RDMA_FTQ_CTL_OVERFLOW (1UL<<1) 8048 #define RDMA_FTQ_CTL_FORCE_INTERVENE (1UL<<2) 8049 #define RDMA_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) 8050 #define RDMA_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) 8051 8052 } rdma_reg_t; 8053 8054 typedef rdma_reg_t rx_dma_reg_t; 8055 8056 /* 8057 * rbdc_reg definition 8058 * offset: 0x3000 8059 */ 8060 typedef struct rbdc_reg 8061 { 8062 u32_t rbdc_command; 8063 #define RBDC_COMMAND_ENABLED (1UL<<0) 8064 #define RBDC_COMMAND_FLUSH (1UL<<1) 8065 #define RBDC_COMMAND_SOFT_RST (1UL<<2) 8066 #define RBDC_COMMAND_REG_ARB (1UL<<3) 8067 #define RBDC_COMMAND_MASTER_ABORT (1UL<<4) 8068 8069 u32_t rbdc_status; 8070 #define RBDC_STATUS_LOCKED_CNT (0xffUL<<0) 8071 #define RBDC_STATUS_DMA_WAIT_COMP (1UL<<8) 8072 #define RBDC_STATUS_DMA_WAIT_ALLOC (1UL<<9) 8073 #define RBDC_STATUS_DMA_WAIT_FREE (1UL<<10) 8074 #define RBDC_STATUS_ZLD1 (1UL<<11) 8075 #define RBDC_STATUS_ZLD2 (1UL<<12) 8076 #define RBDC_STATUS_BURST_CNT (1UL<<20) 8077 #define RBDC_STATUS_PROC1_MISS_CNT (1UL<<21) 8078 #define RBDC_STATUS_PROC2_MISS_CNT (1UL<<22) 8079 8080 u32_t rbdc_control; 8081 #define RBDC_CONTROL_SWAP_MODE (1UL<<0) 8082 #define RBDC_CONTROL_PRIORITY (1UL<<1) 8083 // This bit forces RBDC to run in a single channel mode, in other words 8084 // it will only have outstanding DMA read request. This bit is 8085 // available starting from Xinan 65nm. 8086 #define RBDC_CONTROL_ONE_CHNL (1UL<<4) 8087 // The bit forces RBDC to limit the DMA requests to 64bytes at a time. 8088 // This bit is available starting from Xinan 65nm. 8089 #define REQ64_MODE (1UL<<5) 8090 u32_t rbdc_bd_haddr_hi; 8091 u32_t rbdc_bd_haddr_lo; 8092 u32_t rbdc_bd_len; 8093 #define RBDC_BD_UNUSED_UNUSED (0xffffUL<<0) 8094 8095 u32_t unused_0; 8096 u32_t rbdc_bd_flags; 8097 #define RBDC_BD_FLAGS_FLAGS (0xffffUL<<0) 8098 8099 u32_t rbdc_add; 8100 #define RBDC_ADD_ADD (0x1ffUL<<0) 8101 8102 u32_t rbdc_bdidx; 8103 #define RBDC_BDIDX_BDIDX (0xffffUL<<0) 8104 8105 u32_t rbdc_cid; 8106 #define RBDC_CID_CID (0x3fffUL<<7) 8107 8108 u32_t rbdc_flength; 8109 #define RBDC_FLENGTH_FLENGTH (0x1fUL<<0) 8110 8111 u32_t rbdc_opcode; 8112 #define RBDC_OPCODE_OPCODE (0xfUL<<0) 8113 #define RBDC_OPCODE_BDPT_B (1UL<<4) 8114 8115 u32_t rbdc_haddr_hi; 8116 u32_t rbdc_haddr_lo; 8117 u32_t rbdc_fillhi; 8118 #define RBDC_FILLHI_FILLHI (0xfUL<<0) 8119 8120 u32_t rbdc_filllo; 8121 #define RBDC_FILLLO_FILLLO (0xfUL<<0) 8122 8123 u32_t rbdc_validhi; 8124 #define RBDC_VALIDHI_VALIDHI (0xfUL<<0) 8125 8126 u32_t rbdc_validlo; 8127 #define RBDC_VALIDLO_VALIDLO (0xfUL<<0) 8128 8129 u32_t rbdc_lockcount; 8130 #define RBDC_LOCKCOUNT_LOCKCOUNT (0x3UL<<0) 8131 8132 u32_t rbdc_valid; 8133 #define RBDC_VALID_VALID (1UL<<0) 8134 8135 u32_t rbdc_debug_vect_peek; 8136 #define RBDC_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) 8137 #define RBDC_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) 8138 #define RBDC_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) 8139 #define RBDC_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) 8140 #define RBDC_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) 8141 #define RBDC_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) 8142 8143 u32_t rbdc_cksum_error_status; 8144 #define RBDC_CKSUM_ERROR_STATUS_CALCULATED (0xffffUL<<0) 8145 #define RBDC_CKSUM_ERROR_STATUS_EXPECTED (0xffffUL<<16) 8146 8147 u32_t unused_1[233]; 8148 } rbdc_reg_t; 8149 8150 typedef rbdc_reg_t rx_bd_cache_reg_t; 8151 8152 /* 8153 * rbuf_reg definition 8154 * offset: 0x200000 8155 */ 8156 typedef struct rbuf_reg 8157 { 8158 u32_t rbuf_command; 8159 #define RBUF_COMMAND_ENABLED (1UL<<0) 8160 #define RBUF_COMMAND_FREE_INIT (1UL<<1) 8161 #define RBUF_COMMAND_RAM_INIT (1UL<<2) 8162 #define RBUF_COMMAND_PKT_OFFSET_OVFL (1UL<<3) 8163 #define RBUF_COMMAND_OVER_FREE (1UL<<4) 8164 #define RBUF_COMMAND_ALLOC_REQ_TE (1UL<<5) 8165 #define RBUF_COMMAND_EN_PRI_CHNGE_TE (1UL<<6) 8166 #define RBUF_COMMAND_CU_ISOLATE_XI (1UL<<5) 8167 #define RBUF_COMMAND_EN_PRI_CHANGE_XI (1UL<<6) 8168 #define RBUF_COMMAND_GRC_ENDIAN_CONV_DIS_XI (1UL<<7) 8169 8170 u32_t rbuf_status1; 8171 #define RBUF_STATUS1_FREE_COUNT (0x3ffUL<<0) 8172 8173 u32_t rbuf_status2; 8174 #define RBUF_STATUS2_FREE_TAIL (0x1ffUL<<0) 8175 #define RBUF_STATUS2_FREE_HEAD (0x1ffUL<<16) 8176 8177 u32_t rbuf_config; 8178 #define RBUF_CONFIG_XOFF_TRIP (0x3ffUL<<0) 8179 #define RBUF_CONFIG_XON_TRIP (0x3ffUL<<16) 8180 8181 u32_t rbuf_fw_buf_alloc; 8182 #define RBUF_FW_BUF_ALLOC_VALUE (0x1ffUL<<7) 8183 #define RBUF_FW_BUF_ALLOC_TYPE (1UL<<16) 8184 #define RBUF_FW_BUF_ALLOC_ALLOC_REQ (1UL<<31) 8185 8186 u32_t rbuf_fw_buf_free; 8187 #define RBUF_FW_BUF_FREE_COUNT (0x7fUL<<0) 8188 #define RBUF_FW_BUF_FREE_TAIL (0x1ffUL<<7) 8189 #define RBUF_FW_BUF_FREE_HEAD (0x1ffUL<<16) 8190 #define RBUF_FW_BUF_FREE_TYPE (1UL<<25) 8191 #define RBUF_FW_BUF_FREE_FREE_REQ (1UL<<31) 8192 8193 u32_t rbuf_fw_buf_sel; 8194 #define RBUF_FW_BUF_SEL_COUNT (0x7fUL<<0) 8195 #define RBUF_FW_BUF_SEL_TAIL (0x1ffUL<<7) 8196 #define RBUF_FW_BUF_SEL_HEAD (0x1ffUL<<16) 8197 #define RBUF_FW_BUF_SEL_SEL_REQ (1UL<<31) 8198 8199 u32_t rbuf_config2; 8200 #define RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffUL<<0) 8201 #define RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffUL<<16) 8202 8203 u32_t rbuf_config3; 8204 #define RBUF_CONFIG3_CU_DROP_TRIP (0x3ffUL<<0) 8205 #define RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffUL<<16) 8206 8207 u32_t rbuf_mbuf_count; 8208 #define RBUF_MBUF_COUNT_OCCUPIED_COUNT (0x3ffUL<<0) 8209 #define RBUF_MBUF_COUNT_MAX_COUNT (0x3ffUL<<16) 8210 #define RBUF_MBUF_COUNT_CLR (1UL<<31) 8211 8212 u32_t rbuf_cu_mbuf_count; 8213 #define RBUF_CU_MBUF_COUNT_OCCUPIED_COUNT (0x3ffUL<<0) 8214 #define RBUF_CU_MBUF_COUNT_MAX_COUNT (0x3ffUL<<16) 8215 #define RBUF_CU_MBUF_COUNT_CLR (1UL<<31) 8216 8217 u32_t rbuf_cu_buffer_size; 8218 #define RBUF_CU_BUFFER_SIZE_CU_BUFFER_SIZE (0x3ffUL<<0) 8219 8220 u32_t rbuf_cu_free_count; 8221 #define RBUF_CU_FREE_COUNT_CU_FREE_COUNT (0x3ffUL<<0) 8222 8223 u32_t unused_0[243]; 8224 u32_t rbuf_bist_cs0; 8225 #define RBUF_BIST_CS0_MBIST_EN (1UL<<0) 8226 #define RBUF_BIST_CS0_BIST_SETUP (0x3UL<<1) 8227 #define RBUF_BIST_CS0_MBIST_ASYNC_RESET (1UL<<3) 8228 #define RBUF_BIST_CS0_MBIST_DONE (1UL<<8) 8229 #define RBUF_BIST_CS0_MBIST_GO (1UL<<9) 8230 8231 u32_t rbuf_bist_memstatus0; 8232 u32_t rbuf_bist_cs1; 8233 #define RBUF_BIST_CS1_MBIST_EN (1UL<<0) 8234 #define RBUF_BIST_CS1_BIST_SETUP (0x3UL<<1) 8235 #define RBUF_BIST_CS1_MBIST_ASYNC_RESET (1UL<<3) 8236 #define RBUF_BIST_CS1_MBIST_DONE (1UL<<8) 8237 #define RBUF_BIST_CS1_MBIST_GO (1UL<<9) 8238 8239 u32_t rbuf_bist_memstatus1; 8240 u32_t rbuf_bist_cs2; 8241 #define RBUF_BIST_CS2_MBIST_EN (1UL<<0) 8242 #define RBUF_BIST_CS2_BIST_SETUP (0x3UL<<1) 8243 #define RBUF_BIST_CS2_MBIST_ASYNC_RESET (1UL<<3) 8244 #define RBUF_BIST_CS2_MBIST_DONE (1UL<<8) 8245 #define RBUF_BIST_CS2_MBIST_GO (1UL<<9) 8246 8247 u32_t rbuf_bist_memstatus2; 8248 u32_t rbuf_bist_cs3; 8249 #define RBUF_BIST_CS3_MBIST_EN (1UL<<0) 8250 #define RBUF_BIST_CS3_BIST_SETUP (0x3UL<<1) 8251 #define RBUF_BIST_CS3_MBIST_ASYNC_RESET (1UL<<3) 8252 #define RBUF_BIST_CS3_MBIST_DONE (1UL<<8) 8253 #define RBUF_BIST_CS3_MBIST_GO (1UL<<9) 8254 8255 u32_t rbuf_bist_memstatus3; 8256 u32_t rbuf_bist_cs4; 8257 #define RBUF_BIST_CS4_MBIST_EN (1UL<<0) 8258 #define RBUF_BIST_CS4_BIST_SETUP (0x3UL<<1) 8259 #define RBUF_BIST_CS4_MBIST_ASYNC_RESET (1UL<<3) 8260 #define RBUF_BIST_CS4_MBIST_DONE (1UL<<8) 8261 #define RBUF_BIST_CS4_MBIST_GO (1UL<<9) 8262 8263 u32_t rbuf_bist_memstatus4; 8264 u32_t rbuf_bist_cs5; 8265 #define RBUF_BIST_CS5_MBIST_EN (1UL<<0) 8266 #define RBUF_BIST_CS5_BIST_SETUP (0x3UL<<1) 8267 #define RBUF_BIST_CS5_MBIST_ASYNC_RESET (1UL<<3) 8268 #define RBUF_BIST_CS5_MBIST_DONE (1UL<<8) 8269 #define RBUF_BIST_CS5_MBIST_GO (1UL<<9) 8270 8271 u32_t rbuf_bist_memstatus5; 8272 u32_t rbuf_bist_cs6; 8273 #define RBUF_BIST_CS6_MBIST_EN (1UL<<0) 8274 #define RBUF_BIST_CS6_BIST_SETUP (0x3UL<<1) 8275 #define RBUF_BIST_CS6_MBIST_ASYNC_RESET (1UL<<3) 8276 #define RBUF_BIST_CS6_MBIST_DONE (1UL<<8) 8277 #define RBUF_BIST_CS6_MBIST_GO (1UL<<9) 8278 8279 u32_t rbuf_bist_memstatus6; 8280 u32_t rbuf_bist_cs7; 8281 #define RBUF_BIST_CS7_MBIST_EN (1UL<<0) 8282 #define RBUF_BIST_CS7_BIST_SETUP (0x3UL<<1) 8283 #define RBUF_BIST_CS7_MBIST_ASYNC_RESET (1UL<<3) 8284 #define RBUF_BIST_CS7_MBIST_DONE (1UL<<8) 8285 #define RBUF_BIST_CS7_MBIST_GO (1UL<<9) 8286 8287 u32_t rbuf_bist_memstatus7; 8288 u32_t rbuf_mem_tm0; 8289 #define RBUF_MEM_TM0_CTX_USAGE_CNT_TMB (0x3UL<<0) 8290 #define RBUF_MEM_TM0_CTX_USAGE_CNT_TMA (0x3UL<<2) 8291 #define RBUF_MEM_TM0_CTX_PAGE_TABLE_TM (0xfUL<<4) 8292 #define RBUF_MEM_TM0_CTX_CACHE_TM (0xfUL<<8) 8293 #define RBUF_MEM_TM0_CTX_CAM_TM (0x7ffUL<<12) 8294 8295 u32_t rbuf_mem_tm1; 8296 #define RBUF_MEM_TM1_CTX_CAM_MIRROR_TM (0xfUL<<0) 8297 #define RBUF_MEM_TM1_RXPQ_TM (0xffUL<<8) 8298 #define RBUF_MEM_TM1_THBUF_DATAMEM_TM (0xffUL<<16) 8299 #define RBUF_MEM_TM1_TSCH_CONN_LIST_TM (0xfUL<<24) 8300 #define RBUF_MEM_TM1_MQ_IDX_STOR_TM (0xfUL<<28) 8301 8302 u32_t rbuf_mem_tm2; 8303 #define RBUF_MEM_TM2_RV2P_PROC2_TM (0xfUL<<0) 8304 #define RBUF_MEM_TM2_CS_TMEM_TM (0xfUL<<4) 8305 #define RBUF_MEM_TM2_RV2PCS_TMEM_TM (0xfUL<<8) 8306 #define RBUF_MEM_TM2_CP_SCPAD_TM (0xfUL<<12) 8307 #define RBUF_MEM_TM2_RLUP_CAM_TM (0x7ffUL<<16) 8308 8309 u32_t rbuf_mem_tm3; 8310 #define RBUF_MEM_TM3_RX_BDCACHE_TM (0xffUL<<0) 8311 #define RBUF_MEM_TM3_TX_BDCACHE_TM (0xffUL<<8) 8312 #define RBUF_MEM_TM3_RLUP_CID_TM (0xfUL<<16) 8313 #define RBUF_MEM_TM3_RV2P_PROC1_TM (0xfUL<<24) 8314 8315 u32_t rbuf_mem_tm4; 8316 #define RBUF_MEM_TM4_COM_CP_CACHE_TM (0xfUL<<0) 8317 #define RBUF_MEM_TM4_TPAT_SCPAD_TM (0xfUL<<8) 8318 #define RBUF_MEM_TM4_TXP_SCPAD_TM (0xfUL<<16) 8319 #define RBUF_MEM_TM4_RXP_SCPAD_TM (0xfUL<<24) 8320 8321 u32_t rbuf_mem_tm5; 8322 #define RBUF_MEM_TM5_TPBUF_DATAMEM_TM (0xffUL<<0) 8323 #define RBUF_MEM_TM5_RBUF_DATAMEM_TM (0xffUL<<8) 8324 #define RBUF_MEM_TM5_RBUF_PTRMEM_TMA (0x3UL<<16) 8325 #define RBUF_MEM_TM5_RBUF_PTRMEM_TMB (0x3UL<<24) 8326 8327 u32_t rbuf_mem_65_tm0; 8328 #define RBUF_MEM_65_TM0_CTX_USAGE_CNT_TMB (0xfUL<<0) 8329 #define RBUF_MEM_65_TM0_CTX_PAGE_TABLE_TM (0xfUL<<4) 8330 #define RBUF_MEM_65_TM0_CTX_CACHE_TM (0xfUL<<8) 8331 #define RBUF_MEM_65_TM0_CTX_CAM_TM (0x7ffUL<<12) 8332 #define RBUF_MEM_65_TM0_CTX_USAGE_CNT_TMA (0xfUL<<28) 8333 8334 u32_t rbuf_mem_65_tm1; 8335 #define RBUF_MEM_65_TM1_CTX_CAM_MIRROR_TM (0xfUL<<0) 8336 #define RBUF_MEM_65_TM1_RXPQ_TM (0xffUL<<8) 8337 #define RBUF_MEM_65_TM1_THBUF_DATAMEM_TM (0xffUL<<16) 8338 #define RBUF_MEM_65_TM1_TSCH_CONN_LIST_TM (0xfUL<<24) 8339 #define RBUF_MEM_65_TM1_MQ_IDX_STOR_TM (0xfUL<<28) 8340 8341 u32_t rbuf_mem_65_tm2; 8342 #define RBUF_MEM_65_TM2_RV2P_PROC2_TM (0xfUL<<0) 8343 #define RBUF_MEM_65_TM2_CS_TMEM_TM (0xfUL<<4) 8344 #define RBUF_MEM_65_TM2_RV2PCS_TMEM_TM (0xfUL<<8) 8345 #define RBUF_MEM_65_TM2_CP_SCPAD_TM (0xfUL<<12) 8346 #define RBUF_MEM_65_TM2_RLUB_CAM_TM (0x7ffUL<<16) 8347 #define RBUF_MEM_65_TM2_TDMA_IFIFO_TMB (0x3UL<<28) 8348 #define RBUF_MEM_65_TM2_TDMA_IFIFO_TMA (0x3UL<<30) 8349 8350 u32_t rbuf_mem_65_tm3; 8351 #define RBUF_MEM_65_TM3_RX_BDCACHE_TM (0xffUL<<0) 8352 #define RBUF_MEM_65_TM3_TX_BDCACHE_TM (0xffUL<<8) 8353 #define RBUF_MEM_65_TM3_RLUP_CID_TM (0xfUL<<16) 8354 #define RBUF_MEM_65_TM3_RV2P_PROC1_TM (0xfUL<<24) 8355 #define RBUF_MEM_65_TM3_RDMA_DFIFO_TM (0x3UL<<28) 8356 #define RBUF_MEM_65_TM3_MQ_FIFO_TM (0x3UL<<30) 8357 8358 u32_t rbuf_mem_65_tm4; 8359 #define RBUF_MEM_65_TM4_TPAT_SCPAD_TM (0xfUL<<8) 8360 #define RBUF_MEM_65_TM4_COM_SCPAD_TM (0xfUL<<8) 8361 #define RBUF_MEM_65_TM4_CTX_CP_BURST_BUFS_TM (0x3UL<<14) 8362 #define RBUF_MEM_65_TM4_TXP_SCPAD_TM (0xfUL<<16) 8363 #define RBUF_MEM_65_TM4_CTX_TXP_BURST_BUFS_TM (0x3UL<<22) 8364 #define RBUF_MEM_65_TM4_RXP_SCPAD_TM (0xfUL<<24) 8365 #define RBUF_MEM_65_TM4_CTX_RXP_BURST_BUFS_TM (0x3UL<<30) 8366 8367 u32_t rbuf_mem_65_tm5; 8368 #define RBUF_MEM_65_TM5_TPBUF_DATAMEM_TM (0xffUL<<0) 8369 #define RBUF_MEM_65_TM5_RBUF_DATAMEM_TM (0xffUL<<8) 8370 #define RBUF_MEM_65_TM5_RBUF_PTRMEM_TMA (0xfUL<<16) 8371 #define RBUF_MEM_65_TM5_DMAE_COM_CACHE_TM (0x3UL<<22) 8372 #define RBUF_MEM_65_TM5_RBUF_PTRMEM_TMB (0xfUL<<24) 8373 #define RBUF_MEM_65_TM5_DMAE_CP_CACHE_TM (0x3UL<<30) 8374 8375 u32_t rbuf_weak_wr_cmdstat; 8376 #define RBUF_WEAK_WR_CMDSTAT_WW_MODE (1UL<<0) 8377 #define RBUF_WEAK_WR_CMDSTAT_WW_START (1UL<<1) 8378 #define RBUF_WEAK_WR_CMDSTAT_WW_DONE (1UL<<2) 8379 #define RBUF_WEAK_WR_CMDSTAT_RBUF_DATAMEM_FAIL_FLAG (1UL<<4) 8380 #define RBUF_WEAK_WR_CMDSTAT_TPBUF_DATAMEM_FAIL_FLAG (1UL<<5) 8381 #define RBUF_WEAK_WR_CMDSTAT_RBUF_PTMEM_FAIL_FLAG (1UL<<6) 8382 #define RBUF_WEAK_WR_CMDSTAT_RXP_SCPAD_FAIL_FLAG (1UL<<7) 8383 #define RBUF_WEAK_WR_CMDSTAT_TPAT_SCPAD_FAIL_FLAG (1UL<<8) 8384 #define RBUF_WEAK_WR_CMDSTAT_CTX_USAGE_CNT_FAIL_FLAG (1UL<<9) 8385 #define RBUF_WEAK_WR_CMDSTAT_CTX_PAGE_TABLE_FAIL_FLAG (1UL<<10) 8386 #define RBUF_WEAK_WR_CMDSTAT_CTX_CACHE_FAIL_FLAG (1UL<<11) 8387 #define RBUF_WEAK_WR_CMDSTAT_CS_TMEM_1_FAIL_FLAG (1UL<<12) 8388 #define RBUF_WEAK_WR_CMDSTAT_RLUP_CID_RAM_FAIL_FLAG (1UL<<13) 8389 #define RBUF_WEAK_WR_CMDSTAT_RV2P_PROC2_FAIL_FLAG (1UL<<14) 8390 #define RBUF_WEAK_WR_CMDSTAT_RV2P_PROC1_FAIL_FLAG (1UL<<15) 8391 #define RBUF_WEAK_WR_CMDSTAT_TSCH_CONN_LIST_FAIL_FLAG (1UL<<16) 8392 #define RBUF_WEAK_WR_CMDSTAT_RX_BDCACHE_FAIL_FLAG (1UL<<17) 8393 #define RBUF_WEAK_WR_CMDSTAT_THBUF_DATAMEM_FAIL_FLAG (1UL<<18) 8394 #define RBUF_WEAK_WR_CMDSTAT_CS_TMEM_2_FAIL_FLAG (1UL<<19) 8395 #define RBUF_WEAK_WR_CMDSTAT_MQ_INDEX_STORAGE_FAIL_FLAG (1UL<<20) 8396 #define RBUF_WEAK_WR_CMDSTAT_RXPQ_1_FAIL_FLAG (1UL<<21) 8397 #define RBUF_WEAK_WR_CMDSTAT_RXPQ_2_FAIL_FLAG (1UL<<22) 8398 #define RBUF_WEAK_WR_CMDSTAT_TX_BDCACHE_FAIL_FLAG (1UL<<23) 8399 #define RBUF_WEAK_WR_CMDSTAT_COM_SCPAD_FAIL_FLAG (1UL<<24) 8400 #define RBUF_WEAK_WR_CMDSTAT_CP_SCPAD_FAIL_FLAG (1UL<<25) 8401 #define RBUF_WEAK_WR_CMDSTAT_CTX_CAM_MIRROR_FAIL_FLAG (1UL<<26) 8402 #define RBUF_WEAK_WR_CMDSTAT_TXP_SCPAD_FAIL_FLAG (1UL<<27) 8403 8404 u32_t unused_1[7907]; 8405 u32_t rbuf_pkt_data[2250]; 8406 u32_t unused_2[5942]; 8407 u32_t rbuf_clist_data[512]; 8408 u32_t unused_3[15872]; 8409 u32_t rbuf_buf_data[16384]; 8410 u32_t unused_4[16384]; 8411 } rbuf_reg_t; 8412 8413 typedef rbuf_reg_t rx_mbuf_reg_t; 8414 8415 /* 8416 * idb_state_val definition 8417 * offset: 0000 8418 */ 8419 typedef struct idb_state_val 8420 { 8421 u32_t idb_state_val_val; 8422 #define IDB_STATE_VAL_VAL_STATE (0x7UL<<0) 8423 #define IDB_STATE_VAL_VAL_STATE_IDLE (0UL<<0) 8424 #define IDB_STATE_VAL_VAL_STATE_FILLING (1UL<<0) 8425 #define IDB_STATE_VAL_VAL_STATE_TRIGGERED (2UL<<0) 8426 #define IDB_STATE_VAL_VAL_STATE_FULL (3UL<<0) 8427 #define IDB_STATE_VAL_VAL_STATE_OUTWAIT (4UL<<0) 8428 #define IDB_STATE_VAL_VAL_CID (0x3fffUL<<7) 8429 8430 } idb_state_val_t; 8431 8432 8433 /* 8434 * mq_reg definition 8435 * offset: 0x3c00 8436 */ 8437 typedef struct mq_reg 8438 { 8439 u32_t mq_command; 8440 #define MQ_COMMAND_ENABLED (1UL<<0) 8441 #define MQ_COMMAND_INIT (1UL<<1) 8442 #define MQ_COMMAND_OVERFLOW (1UL<<4) 8443 #define MQ_COMMAND_WR_ERROR (1UL<<5) 8444 #define MQ_COMMAND_RD_ERROR (1UL<<6) 8445 #define MQ_COMMAND_IDB_CFG_ERROR (1UL<<7) 8446 #define MQ_COMMAND_IDB_OVERFLOW (1UL<<10) 8447 #define MQ_COMMAND_NO_BIN_ERROR (1UL<<11) 8448 #define MQ_COMMAND_NO_MAP_ERROR (1UL<<12) 8449 8450 u32_t mq_status; 8451 #define MQ_STATUS_CTX_ACCESS_STAT (1UL<<16) 8452 #define MQ_STATUS_CTX_ACCESS64_STAT (1UL<<17) 8453 #define MQ_STATUS_PCI_STALL_STAT (1UL<<18) 8454 #define MQ_STATUS_IDB_OFLOW_STAT (1UL<<19) 8455 8456 u32_t mq_config; 8457 #define MQ_CONFIG_TX_HIGH_PRI (1UL<<0) 8458 #define MQ_CONFIG_HALT_DIS (1UL<<1) 8459 #define MQ_CONFIG_BIN_MQ_MODE (1UL<<2) 8460 #define MQ_CONFIG_DIS_IDB_DROP (1UL<<3) 8461 #define MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7UL<<4) 8462 #define MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0UL<<4) 8463 #define MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1UL<<4) 8464 #define MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2UL<<4) 8465 #define MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3UL<<4) 8466 #define MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4UL<<4) 8467 #define MQ_CONFIG_MAX_DEPTH (0x7fUL<<8) 8468 #define MQ_CONFIG_CUR_DEPTH (0x7fUL<<20) 8469 8470 u32_t mq_enqueue1; 8471 #define MQ_ENQUEUE1_OFFSET (0x3fUL<<2) 8472 #define MQ_ENQUEUE1_CID (0x3fffUL<<8) 8473 #define MQ_ENQUEUE1_BYTE_MASK (0xfUL<<24) 8474 #define MQ_ENQUEUE1_KNL_MODE (1UL<<28) 8475 8476 u32_t mq_enqueue2; 8477 u32_t mq_bad_wr_addr; 8478 u32_t mq_bad_rd_addr; 8479 u32_t mq_knl_byp_wind_start; 8480 #define MQ_KNL_BYP_WIND_START_VALUE (0xfffffUL<<12) 8481 8482 u32_t mq_knl_wind_end; 8483 #define MQ_KNL_WIND_END_VALUE (0xffffffUL<<8) 8484 8485 u32_t mq_knl_write_mask1; 8486 u32_t mq_knl_tx_mask1; 8487 u32_t mq_knl_cmd_mask1; 8488 u32_t mq_knl_cond_enqueue_mask1; 8489 u32_t mq_knl_rx_v2p_mask1; 8490 u32_t mq_knl_write_mask2; 8491 u32_t mq_knl_tx_mask2; 8492 u32_t mq_knl_cmd_mask2; 8493 u32_t mq_knl_cond_enqueue_mask2; 8494 u32_t mq_knl_rx_v2p_mask2; 8495 u32_t mq_knl_byp_write_mask1; 8496 u32_t mq_knl_byp_tx_mask1; 8497 u32_t mq_knl_byp_cmd_mask1; 8498 u32_t mq_knl_byp_cond_enqueue_mask1; 8499 u32_t mq_knl_byp_rx_v2p_mask1; 8500 u32_t mq_knl_byp_write_mask2; 8501 u32_t mq_knl_byp_tx_mask2; 8502 u32_t mq_knl_byp_cmd_mask2; 8503 u32_t mq_knl_byp_cond_enqueue_mask2; 8504 u32_t mq_knl_byp_rx_v2p_mask2; 8505 u32_t mq_mem_wr_addr; 8506 #define MQ_MEM_WR_ADDR_VALUE (0x3fUL<<0) 8507 8508 u32_t mq_mem_wr_data0; 8509 #define MQ_MEM_WR_DATA0_VALUE (0xffffffffUL<<0) 8510 8511 u32_t mq_mem_wr_data1; 8512 #define MQ_MEM_WR_DATA1_VALUE (0xffffffffUL<<0) 8513 8514 u32_t mq_mem_wr_data2; 8515 #define MQ_MEM_WR_DATA2_VALUE_TE (0x3fffffffUL<<0) 8516 #define MQ_MEM_WR_DATA2_VALUE_XI (0x7fffffffUL<<0) 8517 8518 u32_t mq_mem_rd_addr; 8519 #define MQ_MEM_RD_ADDR_VALUE (0x3fUL<<0) 8520 8521 u32_t mq_mem_rd_data0; 8522 #define MQ_MEM_RD_DATA0_VALUE (0xffffffffUL<<0) 8523 8524 u32_t mq_mem_rd_data1; 8525 #define MQ_MEM_RD_DATA1_VALUE (0xffffffffUL<<0) 8526 8527 u32_t mq_mem_rd_data2; 8528 #define MQ_MEM_RD_DATA2_VALUE_TE (0x3fffffffUL<<0) 8529 #define MQ_MEM_RD_DATA2_VALUE_XI (0x7fffffffUL<<0) 8530 8531 u32_t mq_debug_vect_peek; 8532 #define MQ_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) 8533 #define MQ_DEBUG_VECT_PEEK_1_EN (1UL<<11) 8534 #define MQ_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) 8535 #define MQ_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) 8536 #define MQ_DEBUG_VECT_PEEK_2_EN (1UL<<27) 8537 #define MQ_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) 8538 8539 u32_t unused_0[2]; 8540 u32_t mq_idb_cfg; 8541 #define MQ_IDB_CFG_MB_START (0x3UL<<0) 8542 #define MQ_IDB_CFG_MB_START_256 (0UL<<0) 8543 #define MQ_IDB_CFG_MB_START_512 (1UL<<0) 8544 #define MQ_IDB_CFG_MB_START_1K (2UL<<0) 8545 #define MQ_IDB_CFG_MB_START_2K (3UL<<0) 8546 #define MQ_IDB_CFG_MB_SIZE (0x3UL<<4) 8547 #define MQ_IDB_CFG_MB_SIZE_256 (0UL<<4) 8548 #define MQ_IDB_CFG_MB_SIZE_512 (1UL<<4) 8549 #define MQ_IDB_CFG_MB_SIZE_1K (2UL<<4) 8550 #define MQ_IDB_CFG_MB_SIZE_2K (3UL<<4) 8551 #define MQ_IDB_CFG_ADD_BYTE_SWAP (1UL<<6) 8552 #define MQ_IDB_CFG_ADD_WORD_SWAP (1UL<<7) 8553 #define MQ_IDB_CFG_WQE_SIZE (0x3UL<<8) 8554 #define MQ_IDB_CFG_WQE_SIZE_NONE (0UL<<8) 8555 #define MQ_IDB_CFG_WQE_SIZE_64B (1UL<<8) 8556 #define MQ_IDB_CFG_WQE_SIZE_128B (2UL<<8) 8557 #define MQ_IDB_CFG_CTX_LOC (0x7ffUL<<10) 8558 #define MQ_IDB_CFG_TRIG_LOC (0x3fUL<<24) 8559 #define MQ_IDB_CFG_ENA (1UL<<31) 8560 8561 u32_t mq_idb_free; 8562 #define MQ_IDB_FREE_CID (0x3fffUL<<7) 8563 8564 u32_t unused_1[2]; 8565 u32_t mq_idb_state0_val; 8566 #define MQ_IDB_STATE0_VAL_STATE (0x7UL<<0) 8567 #define MQ_IDB_STATE0_VAL_STATE_IDLE (0UL<<0) 8568 #define MQ_IDB_STATE0_VAL_STATE_FILLING (1UL<<0) 8569 #define MQ_IDB_STATE0_VAL_STATE_TRIGGERED (2UL<<0) 8570 #define MQ_IDB_STATE0_VAL_STATE_FULL (3UL<<0) 8571 #define MQ_IDB_STATE0_VAL_STATE_OUTWAIT (4UL<<0) 8572 #define MQ_IDB_STATE0_VAL_CID (0x3fffUL<<7) 8573 8574 idb_state_val_t mq_idb_state1; 8575 idb_state_val_t mq_idb_state2; 8576 idb_state_val_t mq_idb_state3; 8577 u32_t unused_2[16]; 8578 u32_t mq_config2; 8579 #define MQ_CONFIG2_CONT_SZ (0x7UL<<4) 8580 #define MQ_CONFIG2_CONT_SZ_4PER (2UL<<4) 8581 #define MQ_CONFIG2_CONT_SZ_6PER (3UL<<4) 8582 #define MQ_CONFIG2_CONT_SZ_8PER (4UL<<4) 8583 #define MQ_CONFIG2_CONT_SZ_10PER (5UL<<4) 8584 #define MQ_CONFIG2_CONT_SZ_12PER (6UL<<4) 8585 #define MQ_CONFIG2_CONT_SZ_14PER (7UL<<4) 8586 #define MQ_CONFIG2_FIRST_L4L5 (0x1fUL<<8) 8587 #define MQ_CONFIG2_IDB_DROP_AUTO_RECOV (1UL<<16) 8588 #define MQ_CONFIG2_IDB_AUTO_ON (0x3UL<<17) 8589 #define MQ_CONFIG2_IDB_AUTO_ON_32 (0UL<<17) 8590 #define MQ_CONFIG2_IDB_AUTO_ON_16 (1UL<<17) 8591 #define MQ_CONFIG2_IDB_AUTO_ON_8 (2UL<<17) 8592 #define MQ_CONFIG2_IDB_AUTO_ON_4 (3UL<<17) 8593 #define MQ_CONFIG2_SCNR_CTHRU_DIS (1UL<<20) 8594 8595 u32_t mq_idx_cmd; 8596 #define MQ_IDX_CMD_RD_CMD (1UL<<0) 8597 #define MQ_IDX_CMD_WR_CMD (0x3UL<<1) 8598 #define MQ_IDX_CMD_WR_CMD_NOTHING (0UL<<1) 8599 #define MQ_IDX_CMD_WR_CMD_LOW (1UL<<1) 8600 #define MQ_IDX_CMD_WR_CMD_HIGH (2UL<<1) 8601 #define MQ_IDX_CMD_WR_CMD_BOTH (3UL<<1) 8602 #define MQ_IDX_CMD_SP (0x3UL<<4) 8603 #define MQ_IDX_CMD_BIN_OFFSET (0x3UL<<12) 8604 #define MQ_IDX_CMD_BIN (0xfffUL<<16) 8605 8606 u32_t mq_idx_data; 8607 u32_t mq_scnr_cmd; 8608 #define MQ_SCNR_CMD_RD_CMD (1UL<<0) 8609 #define MQ_SCNR_CMD_WR_CMD (1UL<<1) 8610 #define MQ_SCNR_CMD_BIN (0xfffUL<<16) 8611 8612 u32_t mq_scnr_data; 8613 u32_t unused_3[3]; 8614 u32_t mq_map_l2_0; 8615 #define MQ_MAP_L2_0_MQ_OFFSET (0xffUL<<0) 8616 #define MQ_MAP_L2_0_SZ (0x3UL<<8) 8617 #define MQ_MAP_L2_0_SZ_8B (1UL<<8) 8618 #define MQ_MAP_L2_0_SZ_16B (2UL<<8) 8619 #define MQ_MAP_L2_0_SZ_32B (3UL<<8) 8620 #define MQ_MAP_L2_0_CTX_OFFSET (0x3ffUL<<10) 8621 #define MQ_MAP_L2_0_BIN_OFFSET (0x7UL<<23) 8622 #define MQ_MAP_L2_0_BIN_OFFSET_0 (0UL<<23) 8623 #define MQ_MAP_L2_0_BIN_OFFSET_1 (1UL<<23) 8624 #define MQ_MAP_L2_0_BIN_OFFSET_2 (2UL<<23) 8625 #define MQ_MAP_L2_0_BIN_OFFSET_4 (4UL<<23) 8626 #define MQ_MAP_L2_0_BIN_OFFSET_5 (5UL<<23) 8627 #define MQ_MAP_L2_0_BIN_OFFSET_6 (6UL<<23) 8628 #define MQ_MAP_L2_0_ARM (0x3UL<<26) 8629 #define MQ_MAP_L2_0_ARM_NONE (0UL<<26) 8630 #define MQ_MAP_L2_0_ARM_TSCH (1UL<<26) 8631 #define MQ_MAP_L2_0_ARM_CS (2UL<<26) 8632 #define MQ_MAP_L2_0_ARM_RV2PCS (3UL<<26) 8633 #define MQ_MAP_L2_0_ENA (1UL<<31) 8634 8635 u32_t mq_map_l2_1; 8636 #define MQ_MAP_L2_1_MQ_OFFSET (0xffUL<<0) 8637 #define MQ_MAP_L2_1_SZ (0x3UL<<8) 8638 #define MQ_MAP_L2_1_CTX_OFFSET (0x3ffUL<<10) 8639 #define MQ_MAP_L2_1_BIN_OFFSET (0x7UL<<23) 8640 #define MQ_MAP_L2_1_ARM (0x3UL<<26) 8641 #define MQ_MAP_L2_1_ENA (1UL<<31) 8642 8643 u32_t mq_map_l2_2; 8644 #define MQ_MAP_L2_2_MQ_OFFSET (0xffUL<<0) 8645 #define MQ_MAP_L2_2_SZ (0x3UL<<8) 8646 #define MQ_MAP_L2_2_CTX_OFFSET (0x3ffUL<<10) 8647 #define MQ_MAP_L2_2_BIN_OFFSET (0x7UL<<23) 8648 #define MQ_MAP_L2_2_ARM (0x3UL<<26) 8649 #define MQ_MAP_L2_2_ENA (1UL<<31) 8650 8651 u32_t mq_map_l2_3; 8652 #define MQ_MAP_L2_3_MQ_OFFSET (0xffUL<<0) 8653 #define MQ_MAP_L2_3_SZ (0x3UL<<8) 8654 #define MQ_MAP_L2_3_CTX_OFFSET (0x3ffUL<<10) 8655 #define MQ_MAP_L2_3_BIN_OFFSET (0x7UL<<23) 8656 #define MQ_MAP_L2_3_ARM (0x3UL<<26) 8657 #define MQ_MAP_L2_3_ENA (1UL<<31) 8658 8659 u32_t mq_map_l2_4; 8660 #define MQ_MAP_L2_4_MQ_OFFSET (0xffUL<<0) 8661 #define MQ_MAP_L2_4_SZ (0x3UL<<8) 8662 #define MQ_MAP_L2_4_CTX_OFFSET (0x3ffUL<<10) 8663 #define MQ_MAP_L2_4_BIN_OFFSET (0x7UL<<23) 8664 #define MQ_MAP_L2_4_ARM (0x3UL<<26) 8665 #define MQ_MAP_L2_4_ENA (1UL<<31) 8666 8667 u32_t mq_map_l2_5; 8668 #define MQ_MAP_L2_5_MQ_OFFSET (0xffUL<<0) 8669 #define MQ_MAP_L2_5_SZ (0x3UL<<8) 8670 #define MQ_MAP_L2_5_CTX_OFFSET (0x3ffUL<<10) 8671 #define MQ_MAP_L2_5_BIN_OFFSET (0x7UL<<23) 8672 #define MQ_MAP_L2_5_ARM (0x3UL<<26) 8673 #define MQ_MAP_L2_5_ENA (1UL<<31) 8674 8675 u32_t unused_4[2]; 8676 u32_t mq_map_l4_0; 8677 #define MQ_MAP_L4_0_MQ_OFFSET (0xffUL<<0) 8678 #define MQ_MAP_L4_0_SZ (0x3UL<<8) 8679 #define MQ_MAP_L4_0_CTX_OFFSET (0x3ffUL<<10) 8680 #define MQ_MAP_L4_0_BIN_OFFSET (0x7UL<<23) 8681 #define MQ_MAP_L4_0_ARM (0x3UL<<26) 8682 #define MQ_MAP_L4_0_ENA (1UL<<31) 8683 8684 u32_t mq_map_l4_1; 8685 #define MQ_MAP_L4_1_MQ_OFFSET (0xffUL<<0) 8686 #define MQ_MAP_L4_1_SZ (0x3UL<<8) 8687 #define MQ_MAP_L4_1_CTX_OFFSET (0x3ffUL<<10) 8688 #define MQ_MAP_L4_1_BIN_OFFSET (0x7UL<<23) 8689 #define MQ_MAP_L4_1_ARM (0x3UL<<26) 8690 #define MQ_MAP_L4_1_ENA (1UL<<31) 8691 8692 u32_t mq_map_l4_2; 8693 #define MQ_MAP_L4_2_MQ_OFFSET (0xffUL<<0) 8694 #define MQ_MAP_L4_2_SZ (0x3UL<<8) 8695 #define MQ_MAP_L4_2_CTX_OFFSET (0x3ffUL<<10) 8696 #define MQ_MAP_L4_2_BIN_OFFSET (0x7UL<<23) 8697 #define MQ_MAP_L4_2_ARM (0x3UL<<26) 8698 #define MQ_MAP_L4_2_ENA (1UL<<31) 8699 8700 u32_t mq_map_l4_3; 8701 #define MQ_MAP_L4_3_MQ_OFFSET (0xffUL<<0) 8702 #define MQ_MAP_L4_3_SZ (0x3UL<<8) 8703 #define MQ_MAP_L4_3_CTX_OFFSET (0x3ffUL<<10) 8704 #define MQ_MAP_L4_3_BIN_OFFSET (0x7UL<<23) 8705 #define MQ_MAP_L4_3_ARM (0x3UL<<26) 8706 #define MQ_MAP_L4_3_ENA (1UL<<31) 8707 8708 u32_t mq_map_l4_4; 8709 #define MQ_MAP_L4_4_MQ_OFFSET (0xffUL<<0) 8710 #define MQ_MAP_L4_4_SZ (0x3UL<<8) 8711 #define MQ_MAP_L4_4_CTX_OFFSET (0x3ffUL<<10) 8712 #define MQ_MAP_L4_4_BIN_OFFSET (0x7UL<<23) 8713 #define MQ_MAP_L4_4_ARM (0x3UL<<26) 8714 #define MQ_MAP_L4_4_ENA (1UL<<31) 8715 8716 u32_t mq_map_l4_5; 8717 #define MQ_MAP_L4_5_MQ_OFFSET (0xffUL<<0) 8718 #define MQ_MAP_L4_5_SZ (0x3UL<<8) 8719 #define MQ_MAP_L4_5_CTX_OFFSET (0x3ffUL<<10) 8720 #define MQ_MAP_L4_5_BIN_OFFSET (0x7UL<<23) 8721 #define MQ_MAP_L4_5_ARM (0x3UL<<26) 8722 #define MQ_MAP_L4_5_ENA (1UL<<31) 8723 8724 u32_t unused_5[2]; 8725 u32_t mq_map_l5_0; 8726 #define MQ_MAP_L5_0_MQ_OFFSET (0xffUL<<0) 8727 #define MQ_MAP_L5_0_SZ (0x3UL<<8) 8728 #define MQ_MAP_L5_0_CTX_OFFSET (0x3ffUL<<10) 8729 #define MQ_MAP_L5_0_BIN_OFFSET (0x7UL<<23) 8730 #define MQ_MAP_L5_0_ARM (0x3UL<<26) 8731 #define MQ_MAP_L5_0_ENA (1UL<<31) 8732 8733 u32_t mq_map_l5_1; 8734 #define MQ_MAP_L5_1_MQ_OFFSET (0xffUL<<0) 8735 #define MQ_MAP_L5_1_SZ (0x3UL<<8) 8736 #define MQ_MAP_L5_1_CTX_OFFSET (0x3ffUL<<10) 8737 #define MQ_MAP_L5_1_BIN_OFFSET (0x7UL<<23) 8738 #define MQ_MAP_L5_1_ARM (0x3UL<<26) 8739 #define MQ_MAP_L5_1_ENA (1UL<<31) 8740 8741 u32_t mq_map_l5_2; 8742 #define MQ_MAP_L5_2_MQ_OFFSET (0xffUL<<0) 8743 #define MQ_MAP_L5_2_SZ (0x3UL<<8) 8744 #define MQ_MAP_L5_2_CTX_OFFSET (0x3ffUL<<10) 8745 #define MQ_MAP_L5_2_BIN_OFFSET (0x7UL<<23) 8746 #define MQ_MAP_L5_2_ARM (0x3UL<<26) 8747 #define MQ_MAP_L5_2_ENA (1UL<<31) 8748 8749 u32_t mq_map_l5_3; 8750 #define MQ_MAP_L5_3_MQ_OFFSET (0xffUL<<0) 8751 #define MQ_MAP_L5_3_SZ (0x3UL<<8) 8752 #define MQ_MAP_L5_3_CTX_OFFSET (0x3ffUL<<10) 8753 #define MQ_MAP_L5_3_BIN_OFFSET (0x7UL<<23) 8754 #define MQ_MAP_L5_3_ARM (0x3UL<<26) 8755 #define MQ_MAP_L5_3_ENA (1UL<<31) 8756 8757 u32_t mq_map_l5_4; 8758 #define MQ_MAP_L5_4_MQ_OFFSET (0xffUL<<0) 8759 #define MQ_MAP_L5_4_SZ (0x3UL<<8) 8760 #define MQ_MAP_L5_4_CTX_OFFSET (0x3ffUL<<10) 8761 #define MQ_MAP_L5_4_BIN_OFFSET (0x7UL<<23) 8762 #define MQ_MAP_L5_4_ARM (0x3UL<<26) 8763 #define MQ_MAP_L5_4_ENA (1UL<<31) 8764 8765 u32_t mq_map_l5_5; 8766 #define MQ_MAP_L5_5_MQ_OFFSET (0xffUL<<0) 8767 #define MQ_MAP_L5_5_SZ (0x3UL<<8) 8768 #define MQ_MAP_L5_5_CTX_OFFSET (0x3ffUL<<10) 8769 #define MQ_MAP_L5_5_BIN_OFFSET (0x7UL<<23) 8770 #define MQ_MAP_L5_5_ARM (0x3UL<<26) 8771 #define MQ_MAP_L5_5_ENA (1UL<<31) 8772 8773 u32_t unused_6[162]; 8774 } mq_reg_t; 8775 8776 typedef mq_reg_t mailbox_queue_reg_t; 8777 8778 /* 8779 * cmd_scheduler_enqueue definition 8780 * offset: 0000 8781 */ 8782 typedef struct cmd_scheduler_enqueue 8783 { 8784 u32_t cmd_scheduler_enqueue_cid; 8785 #define CMD_SCHEDULER_ENQUEUE_CID_VALUE (0x3fffUL<<7) 8786 8787 u32_t cmd_scheduler_enqueue_wd1; 8788 #define CMD_SCHEDULER_ENQUEUE_FLAGS_NORMAL (1<<25) 8789 #define CMD_SCHEDULER_ENQUEUE_FLAGS_DELIST (1<<24) 8790 8791 } cmd_scheduler_enqueue_t; 8792 8793 8794 /* 8795 * csch_reg definition 8796 * offset: 0x4000 8797 */ 8798 typedef struct csch_reg 8799 { 8800 u32_t csch_ch_command; 8801 #define CSCH_CH_COMMAND_ENABLE (1UL<<0) 8802 8803 u32_t csch_ch_status; 8804 #define CSCH_CH_STATUS_CMD_CNT_STAT (1UL<<16) 8805 #define CSCH_CH_STATUS_SLOT_CNT_STAT (1UL<<17) 8806 8807 u32_t csch_ch_list_ram_addr; 8808 #define CSCH_CH_LIST_RAM_ADDR_CSCH_LIST_RAM_ADDR_VALUE (0x1ffUL<<4) 8809 8810 u32_t csch_ch_list_ram_data; 8811 u32_t csch_ch_hard_cid; 8812 #define CSCH_CH_HARD_CID_VALUE (0x3fffUL<<7) 8813 8814 u32_t unused_0[7]; 8815 u32_t csch_ch_valid_array0; 8816 u32_t csch_ch_valid_array1; 8817 u32_t csch_ch_valid_array2; 8818 u32_t csch_ch_valid_array3; 8819 u32_t csch_ch_valid_array4; 8820 u32_t csch_ch_valid_array5; 8821 u32_t csch_ch_valid_array6; 8822 u32_t csch_ch_valid_array7; 8823 u32_t csch_ch_valid_array8; 8824 u32_t csch_ch_valid_array9; 8825 u32_t csch_ch_valid_array10; 8826 u32_t csch_ch_valid_array11; 8827 u32_t csch_ch_valid_array12; 8828 u32_t csch_ch_valid_array13; 8829 u32_t csch_ch_valid_array14; 8830 u32_t csch_ch_valid_array15; 8831 u32_t csch_hc_sch_stat; 8832 #define CSCH_HC_SCH_STAT_PS_CSARB (0xfUL<<0) 8833 #define CSCH_HC_SCH_STAT_PS_CPQIF (1UL<<8) 8834 #define CSCH_HC_SCH_STAT_CUR_ACT_CID (0x3fffUL<<16) 8835 8836 u32_t csch_ch_csqif_stat; 8837 #define CSCH_CH_CSQIF_STAT_CSQIF_STAT_PS_CSQSM (0x3UL<<0) 8838 8839 u32_t csch_ch_tmem_fsm; 8840 #define CSCH_CH_TMEM_FSM_MEMARB (0x3UL<<0) 8841 #define CSCH_CH_TMEM_FSM_TMEMCLR (0x3UL<<8) 8842 #define CSCH_CH_TMEM_FSM_ARBLK_1 (1UL<<16) 8843 #define CSCH_CH_TMEM_FSM_ARBLK_0 (1UL<<17) 8844 #define CSCH_CH_TMEM_FSM_CSQLK (1UL<<18) 8845 8846 u32_t csch_ch_tmem_stat; 8847 #define CSCH_CH_TMEM_STAT_ARB_1 (0x3ffUL<<0) 8848 #define CSCH_CH_TMEM_STAT_ARB_0 (0x3ffUL<<10) 8849 #define CSCH_CH_TMEM_STAT_CSQ (0x3ffUL<<20) 8850 8851 u32_t unused_1[208]; 8852 cmd_scheduler_enqueue_t csch_csq; 8853 u32_t unused_2[12]; 8854 u32_t csch_ch_ftq_cmd; 8855 #define CSCH_CH_FTQ_CMD_OFFSET (0x3ffUL<<0) 8856 #define CSCH_CH_FTQ_CMD_WR_TOP (1UL<<10) 8857 #define CSCH_CH_FTQ_CMD_WR_TOP_0 (0UL<<10) 8858 #define CSCH_CH_FTQ_CMD_WR_TOP_1 (1UL<<10) 8859 #define CSCH_CH_FTQ_CMD_SFT_RESET (1UL<<25) 8860 #define CSCH_CH_FTQ_CMD_RD_DATA (1UL<<26) 8861 #define CSCH_CH_FTQ_CMD_ADD_INTERVEN (1UL<<27) 8862 #define CSCH_CH_FTQ_CMD_ADD_DATA (1UL<<28) 8863 #define CSCH_CH_FTQ_CMD_INTERVENE_CLR (1UL<<29) 8864 #define CSCH_CH_FTQ_CMD_POP (1UL<<30) 8865 #define CSCH_CH_FTQ_CMD_BUSY (1UL<<31) 8866 8867 u32_t csch_ch_ftq_ctl; 8868 #define CSCH_CH_FTQ_CTL_INTERVENE (1UL<<0) 8869 #define CSCH_CH_FTQ_CTL_OVERFLOW (1UL<<1) 8870 #define CSCH_CH_FTQ_CTL_FORCE_INTERVENE (1UL<<2) 8871 #define CSCH_CH_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) 8872 #define CSCH_CH_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) 8873 8874 } csch_reg_t; 8875 8876 typedef csch_reg_t cmd_scheduler_reg_t; 8877 8878 8879 /* 8880 * timer_reg definition 8881 * offset: 0x4400 8882 */ 8883 typedef struct timer_reg 8884 { 8885 u32_t timer_command; 8886 #define TIMER_COMMAND_ENABLED (1UL<<0) 8887 8888 u32_t timer_status; 8889 #define TIMER_STATUS_CMP_FTQ_WAIT (1UL<<0) 8890 #define TIMER_STATUS_POLL_PASS_CNT (1UL<<8) 8891 #define TIMER_STATUS_TMR1_CNT (1UL<<9) 8892 #define TIMER_STATUS_TMR2_CNT (1UL<<10) 8893 #define TIMER_STATUS_TMR3_CNT (1UL<<11) 8894 #define TIMER_STATUS_TMR4_CNT (1UL<<12) 8895 #define TIMER_STATUS_TMR5_CNT (1UL<<13) 8896 8897 u32_t timer_config; 8898 #define TIMER_CONFIG_SCAN_WD_CNT_TE (0xffUL<<0) 8899 #define TIMER_CONFIG_SCAN_WD_CNT_XI (0x7ffUL<<0) 8900 #define TIMER_CONFIG_TMR1_BASE (0x7UL<<16) 8901 #define TIMER_CONFIG_TMR1_BASE_CORE (0UL<<16) 8902 #define TIMER_CONFIG_TMR1_BASE_1US (1UL<<16) 8903 #define TIMER_CONFIG_TMR1_BASE_10US (2UL<<16) 8904 #define TIMER_CONFIG_TMR1_BASE_100US (3UL<<16) 8905 #define TIMER_CONFIG_TMR1_BASE_1MS (4UL<<16) 8906 #define TIMER_CONFIG_TMR1_BASE_10MS (5UL<<16) 8907 #define TIMER_CONFIG_TMR1_BASE_100MS (6UL<<16) 8908 #define TIMER_CONFIG_TMR1_BASE_1S (7UL<<16) 8909 #define TIMER_CONFIG_TMR2_BASE (0x7UL<<19) 8910 #define TIMER_CONFIG_TMR2_BASE_CORE (0UL<<19) 8911 #define TIMER_CONFIG_TMR2_BASE_1US (1UL<<19) 8912 #define TIMER_CONFIG_TMR2_BASE_10US (2UL<<19) 8913 #define TIMER_CONFIG_TMR2_BASE_100US (3UL<<19) 8914 #define TIMER_CONFIG_TMR2_BASE_1MS (4UL<<19) 8915 #define TIMER_CONFIG_TMR2_BASE_10MS (5UL<<19) 8916 #define TIMER_CONFIG_TMR2_BASE_100MS (6UL<<19) 8917 #define TIMER_CONFIG_TMR2_BASE_1S (7UL<<19) 8918 #define TIMER_CONFIG_TMR3_BASE (0x7UL<<22) 8919 #define TIMER_CONFIG_TMR3_BASE_CORE (0UL<<22) 8920 #define TIMER_CONFIG_TMR3_BASE_1US (1UL<<22) 8921 #define TIMER_CONFIG_TMR3_BASE_10US (2UL<<22) 8922 #define TIMER_CONFIG_TMR3_BASE_100US (3UL<<22) 8923 #define TIMER_CONFIG_TMR3_BASE_1MS (4UL<<22) 8924 #define TIMER_CONFIG_TMR3_BASE_10MS (5UL<<22) 8925 #define TIMER_CONFIG_TMR3_BASE_100MS (6UL<<22) 8926 #define TIMER_CONFIG_TMR3_BASE_1S (7UL<<22) 8927 #define TIMER_CONFIG_TMR4_BASE (0x7UL<<25) 8928 #define TIMER_CONFIG_TMR4_BASE_CORE (0UL<<25) 8929 #define TIMER_CONFIG_TMR4_BASE_1US (1UL<<25) 8930 #define TIMER_CONFIG_TMR4_BASE_10US (2UL<<25) 8931 #define TIMER_CONFIG_TMR4_BASE_100US (3UL<<25) 8932 #define TIMER_CONFIG_TMR4_BASE_1MS (4UL<<25) 8933 #define TIMER_CONFIG_TMR4_BASE_10MS (5UL<<25) 8934 #define TIMER_CONFIG_TMR4_BASE_100MS (6UL<<25) 8935 #define TIMER_CONFIG_TMR4_BASE_1S (7UL<<25) 8936 #define TIMER_CONFIG_TMR5_BASE (0x7UL<<28) 8937 #define TIMER_CONFIG_TMR5_BASE_CORE (0UL<<28) 8938 #define TIMER_CONFIG_TMR5_BASE_1US (1UL<<28) 8939 #define TIMER_CONFIG_TMR5_BASE_10US (2UL<<28) 8940 #define TIMER_CONFIG_TMR5_BASE_100US (3UL<<28) 8941 #define TIMER_CONFIG_TMR5_BASE_1MS (4UL<<28) 8942 #define TIMER_CONFIG_TMR5_BASE_10MS (5UL<<28) 8943 #define TIMER_CONFIG_TMR5_BASE_100MS (6UL<<28) 8944 #define TIMER_CONFIG_TMR5_BASE_1S (7UL<<28) 8945 8946 u32_t timer_value1; 8947 u16_t unused_0; 8948 u16_t timer_value2; 8949 u16_t unused_1; 8950 u16_t timer_value3; 8951 u16_t unused_2; 8952 u16_t timer_value4; 8953 u16_t unused_3; 8954 u16_t timer_value5; 8955 u32_t timer_ctx_scan_start_addr; 8956 #define TIMER_CTX_SCAN_START_ADDR_VALUE (0x3ffffUL<<3) 8957 #define TIMER_CTX_SCAN_START_ADDR_RESTART_BASE (0x7UL<<21) 8958 #define TIMER_CTX_SCAN_START_ADDR_RESTART_BASE_CORE (0UL<<21) 8959 #define TIMER_CTX_SCAN_START_ADDR_RESTART_BASE_1US (1UL<<21) 8960 #define TIMER_CTX_SCAN_START_ADDR_RESTART_BASE_10US (2UL<<21) 8961 #define TIMER_CTX_SCAN_START_ADDR_RESTART_BASE_100US (3UL<<21) 8962 #define TIMER_CTX_SCAN_START_ADDR_RESTART_BASE_1MS (4UL<<21) 8963 #define TIMER_CTX_SCAN_START_ADDR_RESTART_BASE_10MS (5UL<<21) 8964 #define TIMER_CTX_SCAN_START_ADDR_RESTART_BASE_100MS (6UL<<21) 8965 #define TIMER_CTX_SCAN_START_ADDR_RESTART_BASE_1S (7UL<<21) 8966 #define TIMER_CTX_SCAN_START_ADDR_RESTART_RELOAD (0xffUL<<24) 8967 8968 u32_t timer_sw_tmr_cfg1; 8969 #define TIMER_SW_TMR_CFG1_ENA (1UL<<0) 8970 #define TIMER_SW_TMR_CFG1_RELOAD (1UL<<1) 8971 #define TIMER_SW_TMR_CFG1_ATTN (1UL<<2) 8972 #define TIMER_SW_TMR_CFG1_COM (1UL<<3) 8973 #define TIMER_SW_TMR_CFG1_BASE (0x7UL<<4) 8974 #define TIMER_SW_TMR_CFG1_BASE_CORE (0UL<<4) 8975 #define TIMER_SW_TMR_CFG1_BASE_1US (1UL<<4) 8976 #define TIMER_SW_TMR_CFG1_BASE_10US (2UL<<4) 8977 #define TIMER_SW_TMR_CFG1_BASE_100US (3UL<<4) 8978 #define TIMER_SW_TMR_CFG1_BASE_1MS (4UL<<4) 8979 #define TIMER_SW_TMR_CFG1_BASE_10MS (5UL<<4) 8980 #define TIMER_SW_TMR_CFG1_BASE_100MS (6UL<<4) 8981 #define TIMER_SW_TMR_CFG1_BASE_1S (7UL<<4) 8982 8983 u32_t timer_sw_tmr_value1; 8984 u32_t timer_sw_tmr_reload_value1; 8985 u32_t timer_sw_tmr_value2; 8986 u32_t timer_sw_tmr_reload_value2; 8987 u32_t timer_sw_tmr_value3; 8988 u32_t timer_sw_tmr_reload_value3; 8989 u32_t timer_sw_tmr_value4; 8990 u32_t timer_sw_tmr_reload_value4; 8991 u32_t timer_25mhz_free_run; 8992 u32_t timer_sw_tmr_cfg2; 8993 #define TIMER_SW_TMR_CFG2_ENA (1UL<<0) 8994 #define TIMER_SW_TMR_CFG2_RELOAD (1UL<<1) 8995 #define TIMER_SW_TMR_CFG2_ATTN (1UL<<2) 8996 #define TIMER_SW_TMR_CFG2_COM (1UL<<3) 8997 #define TIMER_SW_TMR_CFG2_BASE (0x7UL<<4) 8998 #define TIMER_SW_TMR_CFG2_BASE_CORE (0UL<<4) 8999 #define TIMER_SW_TMR_CFG2_BASE_1US (1UL<<4) 9000 #define TIMER_SW_TMR_CFG2_BASE_10US (2UL<<4) 9001 #define TIMER_SW_TMR_CFG2_BASE_100US (3UL<<4) 9002 #define TIMER_SW_TMR_CFG2_BASE_1MS (4UL<<4) 9003 #define TIMER_SW_TMR_CFG2_BASE_10MS (5UL<<4) 9004 #define TIMER_SW_TMR_CFG2_BASE_100MS (6UL<<4) 9005 #define TIMER_SW_TMR_CFG2_BASE_1S (7UL<<4) 9006 9007 u32_t timer_sw_tmr_cfg3; 9008 #define TIMER_SW_TMR_CFG3_ENA (1UL<<0) 9009 #define TIMER_SW_TMR_CFG3_RELOAD (1UL<<1) 9010 #define TIMER_SW_TMR_CFG3_ATTN (1UL<<2) 9011 #define TIMER_SW_TMR_CFG3_COM (1UL<<3) 9012 #define TIMER_SW_TMR_CFG3_BASE (0x7UL<<4) 9013 #define TIMER_SW_TMR_CFG3_BASE_CORE (0UL<<4) 9014 #define TIMER_SW_TMR_CFG3_BASE_1US (1UL<<4) 9015 #define TIMER_SW_TMR_CFG3_BASE_10US (2UL<<4) 9016 #define TIMER_SW_TMR_CFG3_BASE_100US (3UL<<4) 9017 #define TIMER_SW_TMR_CFG3_BASE_1MS (4UL<<4) 9018 #define TIMER_SW_TMR_CFG3_BASE_10MS (5UL<<4) 9019 #define TIMER_SW_TMR_CFG3_BASE_100MS (6UL<<4) 9020 #define TIMER_SW_TMR_CFG3_BASE_1S (7UL<<4) 9021 9022 u32_t timer_sw_tmr_cfg4; 9023 #define TIMER_SW_TMR_CFG4_ENA (1UL<<0) 9024 #define TIMER_SW_TMR_CFG4_RELOAD (1UL<<1) 9025 #define TIMER_SW_TMR_CFG4_ATTN (1UL<<2) 9026 #define TIMER_SW_TMR_CFG4_COM (1UL<<3) 9027 #define TIMER_SW_TMR_CFG4_BASE (0x7UL<<4) 9028 #define TIMER_SW_TMR_CFG4_BASE_CORE (0UL<<4) 9029 #define TIMER_SW_TMR_CFG4_BASE_1US (1UL<<4) 9030 #define TIMER_SW_TMR_CFG4_BASE_10US (2UL<<4) 9031 #define TIMER_SW_TMR_CFG4_BASE_100US (3UL<<4) 9032 #define TIMER_SW_TMR_CFG4_BASE_1MS (4UL<<4) 9033 #define TIMER_SW_TMR_CFG4_BASE_10MS (5UL<<4) 9034 #define TIMER_SW_TMR_CFG4_BASE_100MS (6UL<<4) 9035 #define TIMER_SW_TMR_CFG4_BASE_1S (7UL<<4) 9036 9037 u32_t timer_sw_tmr_event_clr; 9038 #define TIMER_SW_TMR_EVENT_CLR_TMR1_EVENT_CLR (1UL<<0) 9039 #define TIMER_SW_TMR_EVENT_CLR_TMR2_EVENT_CLR (1UL<<1) 9040 #define TIMER_SW_TMR_EVENT_CLR_TMR3_EVENT_CLR (1UL<<2) 9041 #define TIMER_SW_TMR_EVENT_CLR_TMR4_EVENT_CLR (1UL<<3) 9042 9043 u32_t unused_4[2]; 9044 u32_t timer_fsm_tmr; 9045 #define TIMER_FSM_TMR_TMR_CTX_IF (0x7ffUL<<0) 9046 #define TIMER_FSM_TMR_TMR_CTX_IF_IDLE (0UL<<0) 9047 #define TIMER_FSM_TMR_TMR_CTX_IF_CTX_SCAN_REQ (2UL<<0) 9048 #define TIMER_FSM_TMR_TMR_CTX_IF_CTX_SCAN_ACK (4UL<<0) 9049 #define TIMER_FSM_TMR_TMR_CTX_IF_CTX_SCAN_VLD (8UL<<0) 9050 #define TIMER_FSM_TMR_TMR_CTX_IF_BITFLD_EVAL (16UL<<0) 9051 #define TIMER_FSM_TMR_TMR_CTX_IF_CTX_TM_REQ0 (32UL<<0) 9052 #define TIMER_FSM_TMR_TMR_CTX_IF_CTX_TM_REQ1 (64UL<<0) 9053 #define TIMER_FSM_TMR_TMR_CTX_IF_CTX_TM_VLD (128UL<<0) 9054 #define TIMER_FSM_TMR_TMR_CTX_IF_CTX_TM_EVAL (256UL<<0) 9055 #define TIMER_FSM_TMR_TMR_CTX_IF_CTX_LAST_ACK (512UL<<0) 9056 #define TIMER_FSM_TMR_TMR_CTX_IF_CTX_TM_WAIT (1024UL<<0) 9057 #define TIMER_FSM_TMR_COMTQ_IF (0x3UL<<16) 9058 #define TIMER_FSM_TMR_COMTQ_IF_IDLE (0UL<<16) 9059 #define TIMER_FSM_TMR_COMTQ_IF_LOAD (1UL<<16) 9060 #define TIMER_FSM_TMR_COMTQ_IF_REQ (2UL<<16) 9061 9062 u32_t timer_stat_tmr; 9063 #define TIMER_STAT_TMR_SCAN_WC (0xffffUL<<0) 9064 #define TIMER_STAT_TMR_CTX_OFF (0xffffUL<<16) 9065 9066 u32_t unused_5[229]; 9067 } timer_reg_t; 9068 9069 9070 /* 9071 * tx_scheduler_enqueue definition 9072 * offset: 0000 9073 */ 9074 typedef struct tx_scheduler_enqueue 9075 { 9076 u32_t tx_scheduler_enqueue_cid; 9077 #define TX_SCHEDULER_ENQUEUE_CID_VALUE (0x3fffUL<<7) 9078 9079 u32_t tx_scheduler_enqueue_wd1; 9080 #define TX_SCHEDULER_ENQUEUE_FLAGS_DELIST (1<<24) 9081 #define TX_SCHEDULER_ENQUEUE_FLAGS_NORMAL (1<<25) 9082 #define TX_SCHEDULER_ENQUEUE_FLAGS_HIGH (1<<26) 9083 #define TX_SCHEDULER_ENQUEUE_RSVD_FUTURE_VALUE (0x3<<16) 9084 9085 } tx_scheduler_enqueue_t; 9086 9087 9088 /* 9089 * tsch_reg definition 9090 * offset: 0x4c00 9091 */ 9092 typedef struct tsch_reg 9093 { 9094 u32_t tsch_command; 9095 #define TSCH_COMMAND_ENABLE (1UL<<0) 9096 9097 u32_t tsch_status; 9098 #define TSCH_STATUS_LS_INIT (1UL<<0) 9099 #define TSCH_STATUS_LOCK_WT (1UL<<1) 9100 #define TSCH_STATUS_INT_LOC (1UL<<2) 9101 #define TSCH_STATUS_INTERNAL_TBDR_WT (1UL<<3) 9102 #define TSCH_STATUS_CMD_CNT_STAT (1UL<<4) 9103 #define TSCH_STATUS_SLOT_CNT_STAT (1UL<<5) 9104 9105 u32_t tsch_mix; 9106 #define TSCH_MIX_0 (0x3UL<<0) 9107 #define TSCH_MIX_0_NORMAL (0UL<<0) 9108 #define TSCH_MIX_0_HIGH (1UL<<0) 9109 #define TSCH_MIX_0_QUICK (2UL<<0) 9110 #define TSCH_MIX_0_UNDEF (3UL<<0) 9111 #define TSCH_MIX_1 (0x3UL<<2) 9112 #define TSCH_MIX_2 (0x3UL<<4) 9113 #define TSCH_MIX_3 (0x3UL<<6) 9114 #define TSCH_MIX_4 (0x3UL<<8) 9115 #define TSCH_MIX_5 (0x3UL<<10) 9116 #define TSCH_MIX_6 (0x3UL<<12) 9117 #define TSCH_MIX_7 (0x3UL<<14) 9118 #define TSCH_MIX_8 (0x3UL<<16) 9119 #define TSCH_MIX_9 (0x3UL<<18) 9120 #define TSCH_MIX_10 (0x3UL<<20) 9121 #define TSCH_MIX_11 (0x3UL<<22) 9122 #define TSCH_MIX_12 (0x3UL<<24) 9123 #define TSCH_MIX_13 (0x3UL<<26) 9124 #define TSCH_MIX_14 (0x3UL<<28) 9125 #define TSCH_MIX_15 (0x3UL<<30) 9126 9127 u32_t tsch_quick_slot_size; 9128 #define TSCH_QUICK_SLOT_SIZE_VALUE (0x1ffUL<<10) 9129 #define TSCH_QUICK_SLOT_SIZE_CTX_L2_SLOT_SIZE_EN (1UL<<19) 9130 #define TSCH_QUICK_SLOT_SIZE_PESS_DIV (0xfUL<<24) 9131 9132 u32_t tsch_list_ram_addr; 9133 #define TSCH_LIST_RAM_ADDR_VALUE (0x1ffUL<<5) 9134 #define TSCH_LIST_RAM_ADDR_LIST_WD_SEL (1UL<<31) 9135 9136 u32_t tsch_list_ram_data; 9137 u32_t tsch_ctx_access_cfg; 9138 #define TSCH_CTX_ACCESS_CFG_TCMD_CELL_OFFSET (0x3fUL<<0) 9139 #define TSCH_CTX_ACCESS_CFG_L5_TCMD_PREFETCH_SIZE (0x7UL<<8) 9140 #define TSCH_CTX_ACCESS_CFG_CMN_CELL_OFFSET (0x7UL<<16) 9141 #define TSCH_CTX_ACCESS_CFG_ADD_PREFETCH_SIZE (0x3UL<<24) 9142 #define TSCH_CTX_ACCESS_CFG_ADD_PREFETCH_EN (1UL<<26) 9143 9144 u32_t tsch_tss_cfg; 9145 #define TSCH_TSS_CFG_TSS_START_CID (0x7ffUL<<10) 9146 #define TSCH_TSS_CFG_NUM_OF_TSS_CON (0xfUL<<24) 9147 9148 u32_t unused_0[8]; 9149 u32_t tsch_debug_1; 9150 #define TSCH_DEBUG_1_SLOT_PT (0xfUL<<0) 9151 #define TSCH_DEBUG_1_SERV_PT (0xfUL<<4) 9152 #define TSCH_DEBUG_1_SLOT_SM (0x7UL<<8) 9153 #define TSCH_DEBUG_1_SLOT_SM_IDLE (0UL<<8) 9154 #define TSCH_DEBUG_1_SLOT_SM_TRAV (1UL<<8) 9155 #define TSCH_DEBUG_1_SLOT_SM_ACK (2UL<<8) 9156 #define TSCH_DEBUG_1_SLOT_SM_WAIT (3UL<<8) 9157 #define TSCH_DEBUG_1_SLOT_SM_NOTIFY (4UL<<8) 9158 #define TSCH_DEBUG_1_LP_REQ_SM (0x3UL<<12) 9159 #define TSCH_DEBUG_1_LP_REQ_SM_IDLE (0UL<<12) 9160 #define TSCH_DEBUG_1_LP_REQ_SM_REQ_SEL (1UL<<12) 9161 #define TSCH_DEBUG_1_LP_REQ_SM_REQ_CON (2UL<<12) 9162 #define TSCH_DEBUG_1_HP_REQ_SM (0x3UL<<14) 9163 #define TSCH_DEBUG_1_HP_REQ_SM_IDLE (0UL<<14) 9164 #define TSCH_DEBUG_1_HP_REQ_SM_REQ_SEL (1UL<<14) 9165 #define TSCH_DEBUG_1_HP_REQ_SM_REQ_CON (2UL<<14) 9166 #define TSCH_DEBUG_1_LIST_SM (0x7UL<<16) 9167 #define TSCH_DEBUG_1_LIST_SM_IDLE (0UL<<16) 9168 #define TSCH_DEBUG_1_LIST_SM_READ (1UL<<16) 9169 #define TSCH_DEBUG_1_LIST_SM_STORE (2UL<<16) 9170 #define TSCH_DEBUG_1_LIST_SM_FIND_CON (3UL<<16) 9171 #define TSCH_DEBUG_1_LIST_SM_FIND_WORD (4UL<<16) 9172 #define TSCH_DEBUG_1_LIST_SM_WAIT (5UL<<16) 9173 #define TSCH_DEBUG_1_LIST_SM_SEL (6UL<<16) 9174 #define TSCH_DEBUG_1_DO_HLIST (1UL<<19) 9175 #define TSCH_DEBUG_1_LIST_EMPTY (1UL<<20) 9176 #define TSCH_DEBUG_1_HLIST_EMPTY (1UL<<21) 9177 #define TSCH_DEBUG_1_L2_SM (0x3UL<<22) 9178 #define TSCH_DEBUG_1_L2_SM_IDLE (0UL<<22) 9179 #define TSCH_DEBUG_1_L2_SM_FOUND (1UL<<22) 9180 #define TSCH_DEBUG_1_L2_SM_SEL (2UL<<22) 9181 #define TSCH_DEBUG_1_ACT_L2_LIST (0xfUL<<24) 9182 #define TSCH_DEBUG_1_GENQ_SM (0x7UL<<28) 9183 #define TSCH_DEBUG_1_GENQ_SM_IDLE (0UL<<28) 9184 #define TSCH_DEBUG_1_GENQ_SM_READ_INPUT (1UL<<28) 9185 #define TSCH_DEBUG_1_GENQ_SM_READ_OFFLOAD (2UL<<28) 9186 #define TSCH_DEBUG_1_GENQ_SM_READ_STORE (3UL<<28) 9187 #define TSCH_DEBUG_1_GENQ_SM_READ_UPDATE (4UL<<28) 9188 #define TSCH_DEBUG_1_GENQ_SM_READ_WRITE (5UL<<28) 9189 #define TSCH_DEBUG_1_GENQ_SM_READ_POP (6UL<<28) 9190 9191 u32_t tsch_debug_2; 9192 #define TSCH_DEBUG_2_LO_PRI_CID (0x1fffUL<<0) 9193 #define TSCH_DEBUG_2_LO_PRI_REQ (1UL<<15) 9194 #define TSCH_DEBUG_2_HI_PRI_CID (0x1fffUL<<16) 9195 #define TSCH_DEBUG_2_HI_PRI_REQ (1UL<<31) 9196 9197 u32_t tsch_debug_3; 9198 #define TSCH_DEBUG_3_CNTX_AD (0x1fffUL<<0) 9199 #define TSCH_DEBUG_3_CNTX_GO (1UL<<15) 9200 #define TSCH_DEBUG_3_CON_TYP (0x3UL<<24) 9201 #define TSCH_DEBUG_3_L2_PT (0x3UL<<28) 9202 #define TSCH_DEBUG_3_L2_REQ (1UL<<31) 9203 9204 u32_t tsch_debug_4; 9205 #define TSCH_DEBUG_4_ACK_SM (0x3UL<<4) 9206 #define TSCH_DEBUG_4_ACK_SM_IDLE (0UL<<4) 9207 #define TSCH_DEBUG_4_ACK_SM_READ (1UL<<4) 9208 #define TSCH_DEBUG_4_ACK_SM_WRITE (2UL<<4) 9209 #define TSCH_DEBUG_4_ACK_SM_ACK (3UL<<4) 9210 #define TSCH_DEBUG_4_DO_NXT_L5 (1UL<<8) 9211 #define TSCH_DEBUG_4_CNTX_BUSY (1UL<<9) 9212 #define TSCH_DEBUG_4_TBDR_SM (1UL<<11) 9213 #define TSCH_DEBUG_4_LIST_RM_SM (0x3UL<<12) 9214 #define TSCH_DEBUG_4_LIST_RM_SM_IDLE (0UL<<12) 9215 #define TSCH_DEBUG_4_LIST_RM_SM_REM_L2 (1UL<<12) 9216 #define TSCH_DEBUG_4_LIST_RM_SM_REM_L4 (2UL<<12) 9217 #define TSCH_DEBUG_4_CNTX_WR_SM (0x3UL<<16) 9218 #define TSCH_DEBUG_4_CNTX_WR_SM_IDLE (0UL<<16) 9219 #define TSCH_DEBUG_4_CNTX_WR_SM_CTX_WR (1UL<<16) 9220 #define TSCH_DEBUG_4_CNTX_WR_SM_CTX_WR_DONE (2UL<<16) 9221 #define TSCH_DEBUG_4_PROC_SM (0xfUL<<20) 9222 #define TSCH_DEBUG_4_PROC_SM_IDLE (0UL<<20) 9223 #define TSCH_DEBUG_4_PROC_SM_1ST_STAGE (1UL<<20) 9224 #define TSCH_DEBUG_4_PROC_SM_L2_1ST_STAGE (2UL<<20) 9225 #define TSCH_DEBUG_4_PROC_SM_L2_2ND_STAGE (3UL<<20) 9226 #define TSCH_DEBUG_4_PROC_SM_L4_1ST_STAGE (4UL<<20) 9227 #define TSCH_DEBUG_4_PROC_SM_L4_2ND_STAGE (5UL<<20) 9228 #define TSCH_DEBUG_4_PROC_SM_L5_STAGE (6UL<<20) 9229 #define TSCH_DEBUG_4_PROC_SM_L5_WAIT (7UL<<20) 9230 #define TSCH_DEBUG_4_PROC_SM_L5_HALT (8UL<<20) 9231 #define TSCH_DEBUG_4_CNTX_RD_SM (0x7UL<<24) 9232 #define TSCH_DEBUG_4_CNTX_RD_SM_IDLE (0UL<<24) 9233 #define TSCH_DEBUG_4_CNTX_RD_SM_L2_1ST_READ (1UL<<24) 9234 #define TSCH_DEBUG_4_CNTX_RD_SM_L2_LAST_READ (2UL<<24) 9235 #define TSCH_DEBUG_4_CNTX_RD_SM_L4_1ST_READ (3UL<<24) 9236 #define TSCH_DEBUG_4_CNTX_RD_SM_L4_LAST_READ (4UL<<24) 9237 #define TSCH_DEBUG_4_CNTX_RD_SM_L5_1ST_READ (5UL<<24) 9238 #define TSCH_DEBUG_4_CNTX_RD_SM_L5_LAST_READ (6UL<<24) 9239 #define TSCH_DEBUG_4_LOCK_SM (0x7UL<<28) 9240 #define TSCH_DEBUG_4_LOCK_SM_IDLE (0UL<<28) 9241 #define TSCH_DEBUG_4_LOCK_SM_REQ (1UL<<28) 9242 #define TSCH_DEBUG_4_LOCK_SM_WAIT (2UL<<28) 9243 #define TSCH_DEBUG_4_LOCK_SM_UNLOCK (3UL<<28) 9244 #define TSCH_DEBUG_4_LOCK_SM_TBDR (4UL<<28) 9245 #define TSCH_DEBUG_4_LOCK_SM_UPDATE (5UL<<28) 9246 #define TSCH_DEBUG_4_LOCK_SM_ENABLE (6UL<<28) 9247 9248 u32_t tsch_debug_5; 9249 #define TSCH_DEBUG_5_TSCH_DBG5_NU_SLT_SZ (0xffffffffUL<<0) 9250 9251 u32_t unused_1[11]; 9252 u32_t tsch_debug_vect_peek; 9253 #define TSCH_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) 9254 #define TSCH_DEBUG_VECT_PEEK_1_EN (1UL<<11) 9255 #define TSCH_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) 9256 #define TSCH_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) 9257 #define TSCH_DEBUG_VECT_PEEK_2_EN (1UL<<27) 9258 #define TSCH_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) 9259 9260 u32_t unused_2[207]; 9261 tx_scheduler_enqueue_t tsch_tschq; 9262 u32_t unused_3[12]; 9263 u32_t tsch_ftq_cmd; 9264 #define TSCH_FTQ_CMD_OFFSET (0x3ffUL<<0) 9265 #define TSCH_FTQ_CMD_WR_TOP (1UL<<10) 9266 #define TSCH_FTQ_CMD_WR_TOP_0 (0UL<<10) 9267 #define TSCH_FTQ_CMD_WR_TOP_1 (1UL<<10) 9268 #define TSCH_FTQ_CMD_SFT_RESET (1UL<<25) 9269 #define TSCH_FTQ_CMD_RD_DATA (1UL<<26) 9270 #define TSCH_FTQ_CMD_ADD_INTERVEN (1UL<<27) 9271 #define TSCH_FTQ_CMD_ADD_DATA (1UL<<28) 9272 #define TSCH_FTQ_CMD_INTERVENE_CLR (1UL<<29) 9273 #define TSCH_FTQ_CMD_POP (1UL<<30) 9274 #define TSCH_FTQ_CMD_BUSY (1UL<<31) 9275 9276 u32_t tsch_ftq_ctl; 9277 #define TSCH_FTQ_CTL_INTERVENE (1UL<<0) 9278 #define TSCH_FTQ_CTL_OVERFLOW (1UL<<1) 9279 #define TSCH_FTQ_CTL_FORCE_INTERVENE (1UL<<2) 9280 #define TSCH_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) 9281 #define TSCH_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) 9282 9283 } tsch_reg_t; 9284 9285 typedef tsch_reg_t tx_scheduler_reg_t; 9286 9287 /* 9288 * tx_bd_read_enqueue definition 9289 * offset: 0000 9290 */ 9291 typedef struct tx_bd_read_enqueue 9292 { 9293 u32_t tx_bd_read_enqueue_cid; 9294 #define TX_BD_READ_ENQUEUE_CID_VALUE (0x3fffUL<<7) 9295 9296 u32_t tx_bd_read_enqueue_bseq; 9297 u32_t tx_bd_read_enqueue_wd2; 9298 #define TX_BD_READ_ENQUEUE_FLAGS_FLAGS_QUICK_CID_ENA (1<<24) 9299 #define TX_BD_READ_ENQUEUE_FLAGS_FLAGS_QUICK_CID_TE (0x3<<25) 9300 #define TX_BD_READ_ENQUEUE_FLAGS_FLAGS_QUICK_CATCHUP_TE (1<<27) 9301 #define TX_BD_READ_ENQUEUE_FLAGS_FLAGS_RSVD_XI (1<<25) 9302 #define TX_BD_READ_ENQUEUE_FLAGS_FLAGS_BORROWED_XI (1<<26) 9303 #define TX_BD_READ_ENQUEUE_FLAGS_FLAGS_BSEQ_INVLD_XI (1<<27) 9304 #define TX_BD_READ_ENQUEUE_FLAGS_FLAGS_S_RETRAN (1<<28) 9305 9306 u32_t tx_bd_read_enqueue_tcp_rcv_nxt; 9307 u32_t tx_bd_read_enqueue_wd4; 9308 #define TX_BD_READ_ENQUEUE_TCMD_FNUM_VALUE (0x3f<<24) 9309 9310 } tx_bd_read_enqueue_t; 9311 9312 9313 /* 9314 * tbdr_reg definition 9315 * offset: 0x5000 9316 */ 9317 typedef struct tbdr_reg 9318 { 9319 u32_t tbdr_command; 9320 #define TBDR_COMMAND_ENABLE (1UL<<0) 9321 #define TBDR_COMMAND_SOFT_RST (1UL<<1) 9322 #define TBDR_COMMAND_MSTR_ABORT (1UL<<4) 9323 9324 u32_t tbdr_status; 9325 #define TBDR_STATUS_DMA_WAIT (1UL<<0) 9326 #define TBDR_STATUS_FTQ_WAIT (1UL<<1) 9327 #define TBDR_STATUS_FIFO_OVERFLOW (1UL<<2) 9328 #define TBDR_STATUS_FIFO_UNDERFLOW (1UL<<3) 9329 #define TBDR_STATUS_SEARCHMISS_ERROR (1UL<<4) 9330 #define TBDR_STATUS_FTQ_ENTRY_CNT (1UL<<5) 9331 #define TBDR_STATUS_BURST_CNT (1UL<<6) 9332 9333 u32_t tbdr_config; 9334 #define TBDR_CONFIG_MAX_BDS (0xffUL<<0) 9335 #define TBDR_CONFIG_SWAP_MODE (1UL<<8) 9336 #define TBDR_CONFIG_PRIORITY (1UL<<9) 9337 #define TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1UL<<10) 9338 #define TBDR_CONFIG_PAGE_SIZE (0xfUL<<24) 9339 #define TBDR_CONFIG_PAGE_SIZE_256 (0UL<<24) 9340 #define TBDR_CONFIG_PAGE_SIZE_512 (1UL<<24) 9341 #define TBDR_CONFIG_PAGE_SIZE_1K (2UL<<24) 9342 #define TBDR_CONFIG_PAGE_SIZE_2K (3UL<<24) 9343 #define TBDR_CONFIG_PAGE_SIZE_4K (4UL<<24) 9344 #define TBDR_CONFIG_PAGE_SIZE_8K (5UL<<24) 9345 #define TBDR_CONFIG_PAGE_SIZE_16K (6UL<<24) 9346 #define TBDR_CONFIG_PAGE_SIZE_32K (7UL<<24) 9347 #define TBDR_CONFIG_PAGE_SIZE_64K (8UL<<24) 9348 #define TBDR_CONFIG_PAGE_SIZE_128K (9UL<<24) 9349 #define TBDR_CONFIG_PAGE_SIZE_256K (10UL<<24) 9350 #define TBDR_CONFIG_PAGE_SIZE_512K (11UL<<24) 9351 #define TBDR_CONFIG_PAGE_SIZE_1M (12UL<<24) 9352 9353 u32_t tbdr_debug_vect_peek; 9354 #define TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) 9355 #define TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) 9356 #define TBDR_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) 9357 #define TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) 9358 #define TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) 9359 #define TBDR_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) 9360 9361 u32_t tbdr_cksum_error_status; 9362 #define TBDR_CKSUM_ERROR_STATUS_CALCULATED (0xffffUL<<0) 9363 #define TBDR_CKSUM_ERROR_STATUS_EXPECTED (0xffffUL<<16) 9364 9365 u32_t unused_0[235]; 9366 tx_bd_read_enqueue_t tbdr_tbdrq; 9367 u32_t unused_1[9]; 9368 u32_t tbdr_ftq_cmd; 9369 #define TBDR_FTQ_CMD_OFFSET (0x3ffUL<<0) 9370 #define TBDR_FTQ_CMD_WR_TOP (1UL<<10) 9371 #define TBDR_FTQ_CMD_WR_TOP_0 (0UL<<10) 9372 #define TBDR_FTQ_CMD_WR_TOP_1 (1UL<<10) 9373 #define TBDR_FTQ_CMD_SFT_RESET (1UL<<25) 9374 #define TBDR_FTQ_CMD_RD_DATA (1UL<<26) 9375 #define TBDR_FTQ_CMD_ADD_INTERVEN (1UL<<27) 9376 #define TBDR_FTQ_CMD_ADD_DATA (1UL<<28) 9377 #define TBDR_FTQ_CMD_INTERVENE_CLR (1UL<<29) 9378 #define TBDR_FTQ_CMD_POP (1UL<<30) 9379 #define TBDR_FTQ_CMD_BUSY (1UL<<31) 9380 9381 u32_t tbdr_ftq_ctl; 9382 #define TBDR_FTQ_CTL_INTERVENE (1UL<<0) 9383 #define TBDR_FTQ_CTL_OVERFLOW (1UL<<1) 9384 #define TBDR_FTQ_CTL_FORCE_INTERVENE (1UL<<2) 9385 #define TBDR_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) 9386 #define TBDR_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) 9387 9388 } tbdr_reg_t; 9389 9390 typedef tbdr_reg_t tx_bd_read_reg_t; 9391 9392 /* 9393 * tbdc_reg definition 9394 * offset: 0x5400 9395 */ 9396 typedef struct tbdc_reg 9397 { 9398 u32_t tbdc_command; 9399 #define TBDC_COMMAND_CMD_ENABLED (1UL<<0) 9400 #define TBDC_COMMAND_CMD_FLUSH (1UL<<1) 9401 #define TBDC_COMMAND_CMD_SOFT_RST (1UL<<2) 9402 #define TBDC_COMMAND_CMD_REG_ARB (1UL<<3) 9403 #define TBDC_COMMAND_WRCHK_RANGE_ERROR (1UL<<4) 9404 #define TBDC_COMMAND_WRCHK_ALL_ONES_ERROR (1UL<<5) 9405 #define TBDC_COMMAND_WRCHK_ALL_ZEROS_ERROR (1UL<<6) 9406 #define TBDC_COMMAND_WRCHK_ANY_ONES_ERROR (1UL<<7) 9407 #define TBDC_COMMAND_WRCHK_ANY_ZEROS_ERROR (1UL<<8) 9408 9409 u32_t tbdc_status; 9410 #define TBDC_STATUS_FREE_CNT (0x3fUL<<0) 9411 9412 u32_t tbdc_control; 9413 #define TBDC_CONTROL_RANGE (1UL<<0) 9414 #define TBDC_CONTROL_ALL_ONES (1UL<<1) 9415 #define TBDC_CONTROL_ALL_ZEROS (1UL<<2) 9416 #define TBDC_CONTROL_ANY_ONES (1UL<<3) 9417 #define TBDC_CONTROL_ANY_ZEROS (1UL<<4) 9418 9419 u32_t tbdc_bd_haddr_hi; 9420 u32_t tbdc_bd_haddr_lo; 9421 u32_t tbdc_bd_nbytes; 9422 #define TBDC_BD_NBYTES_NBYTES (0xffffUL<<0) 9423 9424 u32_t tbdc_bd_flags; 9425 #define TBDC_BD_FLAGS_FLAGS (0xffffUL<<0) 9426 9427 u32_t tbdc_bd_reserved; 9428 #define TBDC_BD_RESERVED_VALUE (0xffffUL<<0) 9429 9430 u32_t tbdc_bd_vlan_tag; 9431 #define TBDC_BD_VLAN_TAG_VLAN_TAG (0xffffUL<<0) 9432 9433 u32_t tbdc_bd_addr; 9434 #define TBDC_BD_ADDR_ADDRESS (0xffUL<<0) 9435 #define TBDC_BD_ADDR_HIT (1UL<<8) 9436 9437 u32_t tbdc_bd_hiaddr; 9438 #define TBDC_BD_HIADDR_HIADDR (0xffUL<<0) 9439 9440 u32_t tbdc_bdidx; 9441 #define TBDC_BDIDX_BDIDX (0xffffUL<<0) 9442 #define TBDC_BDIDX_CMD (0xffUL<<24) 9443 9444 u32_t tbdc_cid; 9445 #define TBDC_CID_CID (0x3fffUL<<7) 9446 9447 u32_t tbdc_cam_opcode; 9448 #define TBDC_CAM_OPCODE_OPCODE (0x7UL<<0) 9449 #define TBDC_CAM_OPCODE_OPCODE_SEARCH (0UL<<0) 9450 #define TBDC_CAM_OPCODE_OPCODE_CACHE_WRITE (1UL<<0) 9451 #define TBDC_CAM_OPCODE_OPCODE_INVALIDATE (2UL<<0) 9452 #define TBDC_CAM_OPCODE_OPCODE_CAM_WRITE (4UL<<0) 9453 #define TBDC_CAM_OPCODE_OPCODE_CAM_READ (5UL<<0) 9454 #define TBDC_CAM_OPCODE_OPCODE_RAM_WRITE (6UL<<0) 9455 #define TBDC_CAM_OPCODE_OPCODE_RAM_READ (7UL<<0) 9456 #define TBDC_CAM_OPCODE_SMASK_BDIDX (1UL<<4) 9457 #define TBDC_CAM_OPCODE_SMASK_CID (1UL<<5) 9458 #define TBDC_CAM_OPCODE_SMASK_CMD (1UL<<6) 9459 #define TBDC_CAM_OPCODE_WMT_FAILED (1UL<<7) 9460 #define TBDC_CAM_OPCODE_CAM_VALIDS (0xffUL<<8) 9461 9462 u32_t tbdc_haddr_hi; 9463 u32_t tbdc_haddr_lo; 9464 u32_t tbdc_debug_vect_peek; 9465 #define TBDC_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) 9466 #define TBDC_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) 9467 #define TBDC_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) 9468 #define TBDC_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) 9469 #define TBDC_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) 9470 #define TBDC_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) 9471 9472 u32_t unused_0[239]; 9473 } tbdc_reg_t; 9474 9475 typedef tbdc_reg_t tx_bd_cache_reg_t; 9476 9477 /* 9478 * tx_dma_enqueue definition 9479 * offset: 0000 9480 */ 9481 typedef struct tx_dma_enqueue 9482 { 9483 u32_t tx_dma_enqueue_cid; 9484 #define TX_DMA_ENQUEUE_CID_VALUE (0x3fffUL<<7) 9485 9486 u32_t tx_dma_enqueue_wd1; 9487 #define TX_DMA_ENQUEUE_TDMA_BIDX (0xffff<<16) 9488 #define TX_DMA_ENQUEUE_TDMA_BOFF (0xffff<<0) 9489 9490 u32_t tx_dma_enqueue_tdma_bseq; 9491 u32_t tx_dma_enqueue_tdma_snd_next; 9492 u32_t tx_dma_enqueue_wd4; 9493 #define TX_DMA_ENQUEUE_TDMA_CMD (0xff<<24) 9494 #define TX_DMA_ENQUEUE_XNUM (0xff<<16) 9495 #define TX_DMA_ENQUEUE_KNUM (0xff<<8) 9496 9497 u32_t tx_dma_enqueue_flags_flags; 9498 #define TX_DMA_ENQUEUE_FLAGS_FLAGS_PLUS_TWO (1UL<<0) 9499 #define TX_DMA_ENQUEUE_FLAGS_FLAGS_TCP_UDP_CKSUM (1UL<<1) 9500 #define TX_DMA_ENQUEUE_FLAGS_FLAGS_IP_CKSUM (1UL<<2) 9501 #define TX_DMA_ENQUEUE_FLAGS_FLAGS_INCR_CMD (1UL<<3) 9502 #define TX_DMA_ENQUEUE_FLAGS_FLAGS_COAL_NOW (1UL<<4) 9503 #define TX_DMA_ENQUEUE_FLAGS_FLAGS_DONT_GEN_CRC (1UL<<5) 9504 #define TX_DMA_ENQUEUE_FLAGS_FLAGS_LAST_PKT (1UL<<6) 9505 #define TX_DMA_ENQUEUE_FLAGS_FLAGS_PKT_FRAG (1UL<<7) 9506 #define TX_DMA_ENQUEUE_FLAGS_FLAGS_QUICK_CID_ENA (1UL<<9) 9507 #define TX_DMA_ENQUEUE_FLAGS_FLAGS_QUICK_CID_TE (0x3UL<<10) 9508 #define TX_DMA_ENQUEUE_FLAGS_FLAGS_RSVD_FUTURE_XI (0x3UL<<10) 9509 #define TX_DMA_ENQUEUE_FLAGS_FLAGS_L5_PAGE_MODE (1UL<<12) 9510 #define TX_DMA_ENQUEUE_FLAGS_FLAGS_COMPLETE (1UL<<13) 9511 #define TX_DMA_ENQUEUE_FLAGS_FLAGS_RETRAN (1UL<<14) 9512 #define TX_DMA_ENQUEUE_FLAGS_FLAGS_END_PADDING (0xfUL<<16) 9513 #define TX_DMA_ENQUEUE_FLAGS_FLAGS_USAGE_CNT (1UL<<20) 9514 #define TX_DMA_ENQUEUE_FLAGS_FLAGS_USAGE_CNT_AUTODECREMENT (0UL<<20) 9515 #define TX_DMA_ENQUEUE_FLAGS_FLAGS_USAGE_CNT_DONOTDECREMENT (1UL<<20) 9516 #define TX_DMA_ENQUEUE_FLAGS_FLAGS_BSEQ_INVLD (1UL<<21) 9517 #define TX_DMA_ENQUEUE_FLAGS_FLAGS_WORK_AROUND (0x3UL<<22) 9518 #define TX_DMA_ENQUEUE_FLAGS_FLAGS_HOLE_SZ (0x3UL<<25) 9519 #define TX_DMA_ENQUEUE_FLAGS_FLAGS_HOLE_SZ_4 (0UL<<25) 9520 #define TX_DMA_ENQUEUE_FLAGS_FLAGS_HOLE_SZ_8 (1UL<<25) 9521 #define TX_DMA_ENQUEUE_FLAGS_FLAGS_HOLE_SZ_12 (2UL<<25) 9522 #define TX_DMA_ENQUEUE_FLAGS_FLAGS_HOLE_SZ_16 (3UL<<25) 9523 #define TX_DMA_ENQUEUE_FLAGS_FLAGS_HOLE0 (1UL<<28) 9524 #define TX_DMA_ENQUEUE_FLAGS_FLAGS_HOLE1 (1UL<<29) 9525 #define TX_DMA_ENQUEUE_FLAGS_FLAGS_HOLE2 (1UL<<30) 9526 9527 u32_t tx_dma_enqueue_wd6; 9528 #define TX_DMA_ENQUEUE_NBYTES_VALUE (0x3fff<<16) 9529 #define TX_DMA_ENQUEUE_HOLE0_BOFF_VALUE (0x3fff<<0) 9530 9531 u32_t tx_dma_enqueue_wd7; 9532 #define TX_DMA_ENQUEUE_HOLE1_BOFF_VALUE (0x3fff<<16) 9533 #define TX_DMA_ENQUEUE_HOLE2_BOFF_VALUE (0x3fff<<0) 9534 9535 u32_t tx_dma_enqueue_hole0_fill; 9536 u32_t tx_dma_enqueue_hole1_fill; 9537 u32_t tx_dma_enqueue_hole2_fill; 9538 u32_t tx_dma_enqueue_wd11; 9539 #define TX_DMA_ENQUEUE_TCMD_FNUM_VALUE (0x3f<<24) 9540 #define TX_DMA_ENQUEUE_TXP_ACT_CMD (0xff<<16) 9541 9542 } tx_dma_enqueue_t; 9543 9544 9545 /* 9546 * tdma_reg definition 9547 * offset: 0x5c00 9548 */ 9549 typedef struct tdma_reg 9550 { 9551 u32_t tdma_command; 9552 #define TDMA_COMMAND_ENABLED (1UL<<0) 9553 #define TDMA_COMMAND_MASTER_ABORT (1UL<<4) 9554 #define TDMA_COMMAND_CS16_ERR (1UL<<5) 9555 #define TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1UL<<7) 9556 #define TDMA_COMMAND_MASK_CS1 (1UL<<20) 9557 #define TDMA_COMMAND_MASK_CS2 (1UL<<21) 9558 #define TDMA_COMMAND_MASK_CS3 (1UL<<22) 9559 #define TDMA_COMMAND_MASK_CS4 (1UL<<23) 9560 #define TDMA_COMMAND_FORCE_ILOCK_CKERR (1UL<<24) 9561 #define TDMA_COMMAND_OFIFO_CLR (1UL<<30) 9562 #define TDMA_COMMAND_IFIFO_CLR (1UL<<31) 9563 9564 u32_t tdma_status; 9565 #define TDMA_STATUS_DMA_WAIT (1UL<<0) 9566 #define TDMA_STATUS_PAYLOAD_WAIT (1UL<<1) 9567 #define TDMA_STATUS_PATCH_FTQ_WAIT (1UL<<2) 9568 #define TDMA_STATUS_LOCK_WAIT (1UL<<3) 9569 #define TDMA_STATUS_FTQ_ENTRY_CNT (1UL<<16) 9570 #define TDMA_STATUS_BURST_CNT (1UL<<17) 9571 #define TDMA_STATUS_MAX_IFIFO_DEPTH (0x3fUL<<20) 9572 #define TDMA_STATUS_OFIFO_OVERFLOW (1UL<<30) 9573 #define TDMA_STATUS_IFIFO_OVERFLOW (1UL<<31) 9574 9575 u32_t tdma_config; 9576 #define TDMA_CONFIG_ONE_DMA (1UL<<0) 9577 #define TDMA_CONFIG_ONE_RECORD (1UL<<1) 9578 #define TDMA_CONFIG_NUM_DMA_CHAN (0x3UL<<2) 9579 #define TDMA_CONFIG_NUM_DMA_CHAN_0 (0UL<<2) 9580 #define TDMA_CONFIG_NUM_DMA_CHAN_1 (1UL<<2) 9581 #define TDMA_CONFIG_NUM_DMA_CHAN_2 (2UL<<2) 9582 #define TDMA_CONFIG_NUM_DMA_CHAN_3 (3UL<<2) 9583 #define TDMA_CONFIG_LIMIT_SZ (0xfUL<<4) 9584 #define TDMA_CONFIG_LIMIT_SZ_64 (0UL<<4) 9585 #define TDMA_CONFIG_LIMIT_SZ_128 (4UL<<4) 9586 #define TDMA_CONFIG_LIMIT_SZ_256 (6UL<<4) 9587 #define TDMA_CONFIG_LIMIT_SZ_512 (8UL<<4) 9588 #define TDMA_CONFIG_LINE_SZ (0xfUL<<8) 9589 #define TDMA_CONFIG_LINE_SZ_64 (0UL<<8) 9590 #define TDMA_CONFIG_LINE_SZ_128 (4UL<<8) 9591 #define TDMA_CONFIG_LINE_SZ_256 (6UL<<8) 9592 #define TDMA_CONFIG_LINE_SZ_512 (8UL<<8) 9593 #define TDMA_CONFIG_ALIGN_ENA (1UL<<15) 9594 #define TDMA_CONFIG_CHK_L2_BD (1UL<<16) 9595 #define TDMA_CONFIG_CMPL_ENTRY (1UL<<17) 9596 #define TDMA_CONFIG_OFIFO_CMP (1UL<<19) 9597 #define TDMA_CONFIG_OFIFO_CMP_3 (0UL<<19) 9598 #define TDMA_CONFIG_OFIFO_CMP_2 (1UL<<19) 9599 #define TDMA_CONFIG_FIFO_CMP_TE (0xfUL<<20) 9600 #define TDMA_CONFIG_IFIFO_DEPTH_XI (0x7UL<<20) 9601 #define TDMA_CONFIG_IFIFO_DEPTH_0_XI (0UL<<20) 9602 #define TDMA_CONFIG_IFIFO_DEPTH_4_XI (1UL<<20) 9603 #define TDMA_CONFIG_IFIFO_DEPTH_8_XI (2UL<<20) 9604 #define TDMA_CONFIG_IFIFO_DEPTH_16_XI (3UL<<20) 9605 #define TDMA_CONFIG_IFIFO_DEPTH_32_XI (4UL<<20) 9606 #define TDMA_CONFIG_IFIFO_DEPTH_64_XI (5UL<<20) 9607 #define TDMA_CONFIG_FIFO_CMP_EN_XI (1UL<<23) 9608 #define TDMA_CONFIG_BYTES_OST_XI (0x7UL<<24) 9609 #define TDMA_CONFIG_BYTES_OST_512_XI (0UL<<24) 9610 #define TDMA_CONFIG_BYTES_OST_1024_XI (1UL<<24) 9611 #define TDMA_CONFIG_BYTES_OST_2048_XI (2UL<<24) 9612 #define TDMA_CONFIG_BYTES_OST_4096_XI (3UL<<24) 9613 #define TDMA_CONFIG_BYTES_OST_8192_XI (4UL<<24) 9614 #define TDMA_CONFIG_BYTES_OST_16384_XI (5UL<<24) 9615 #define TDMA_CONFIG_HC_BYPASS_XI (1UL<<27) 9616 #define TDMA_CONFIG_LCL_MRRS_XI (0x7UL<<28) 9617 #define TDMA_CONFIG_LCL_MRRS_128_XI (0UL<<28) 9618 #define TDMA_CONFIG_LCL_MRRS_256_XI (1UL<<28) 9619 #define TDMA_CONFIG_LCL_MRRS_512_XI (2UL<<28) 9620 #define TDMA_CONFIG_LCL_MRRS_1024_XI (3UL<<28) 9621 #define TDMA_CONFIG_LCL_MRRS_2048_XI (4UL<<28) 9622 #define TDMA_CONFIG_LCL_MRRS_4096_XI (5UL<<28) 9623 #define TDMA_CONFIG_LCL_MRRS_EN_XI (1UL<<31) 9624 9625 u32_t tdma_payload_prod; 9626 #define TDMA_PAYLOAD_PROD_VALUE (0x1fffUL<<3) 9627 9628 u32_t tdma_dbg_watchdog; 9629 u32_t tdma_dbg_trigger; 9630 u32_t unused_0[26]; 9631 u32_t tdma_dmad_fsm; 9632 #define TDMA_DMAD_FSM_BD_INVLD (1UL<<0) 9633 #define TDMA_DMAD_FSM_PUSH (0xfUL<<4) 9634 #define TDMA_DMAD_FSM_ARB_TBDC (0x3UL<<8) 9635 #define TDMA_DMAD_FSM_ARB_CTX (1UL<<12) 9636 #define TDMA_DMAD_FSM_DR_INTF (1UL<<16) 9637 #define TDMA_DMAD_FSM_DMAD (0x7UL<<20) 9638 #define TDMA_DMAD_FSM_BD (0xfUL<<24) 9639 9640 u32_t tdma_dmad_status; 9641 #define TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY (0x3UL<<0) 9642 #define TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY (0x3UL<<4) 9643 #define TDMA_DMAD_STATUS_RHOLD_BD_ENTRY (0x3UL<<8) 9644 #define TDMA_DMAD_STATUS_IFTQ_ENUM (0xfUL<<12) 9645 9646 u32_t tdma_dr_intf_fsm; 9647 #define TDMA_DR_INTF_FSM_L2_COMP (0x3UL<<0) 9648 #define TDMA_DR_INTF_FSM_TPATQ (0x7UL<<4) 9649 #define TDMA_DR_INTF_FSM_TPBUF (0x3UL<<8) 9650 #define TDMA_DR_INTF_FSM_DR_BUF (0x7UL<<12) 9651 #define TDMA_DR_INTF_FSM_DMAD (0x7UL<<16) 9652 9653 u32_t tdma_dr_intf_status; 9654 #define TDMA_DR_INTF_STATUS_HOLE_PHASE (0x7UL<<0) 9655 #define TDMA_DR_INTF_STATUS_DATA_AVAIL (0x3UL<<4) 9656 #define TDMA_DR_INTF_STATUS_SHIFT_ADDR (0x7UL<<8) 9657 #define TDMA_DR_INTF_STATUS_NXT_PNTR (0xfUL<<12) 9658 #define TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7UL<<16) 9659 9660 u32_t tdma_push_fsm; 9661 u32_t tdma_bd_if_debug; 9662 u32_t tdma_dmad_if_debug; 9663 u32_t tdma_ctx_if_debug; 9664 u32_t tdma_tpbuf_if_debug; 9665 u32_t tdma_dr_if_debug; 9666 u32_t tdma_tpatq_if_debug; 9667 u32_t tdma_tdma_ilock_cksum; 9668 #define TDMA_TDMA_ILOCK_CKSUM_CALCULATED (0xffffUL<<0) 9669 #define TDMA_TDMA_ILOCK_CKSUM_EXPECTED (0xffffUL<<16) 9670 9671 u32_t tdma_tdma_pcie_cksum; 9672 #define TDMA_TDMA_PCIE_CKSUM_CALCULATED (0xffffUL<<0) 9673 #define TDMA_TDMA_PCIE_CKSUM_EXPECTED (0xffffUL<<16) 9674 9675 u32_t unused_1[195]; 9676 tx_dma_enqueue_t tdma_tdmaq; 9677 u32_t unused_2[2]; 9678 u32_t tdma_ftq_cmd; 9679 #define TDMA_FTQ_CMD_OFFSET (0x3ffUL<<0) 9680 #define TDMA_FTQ_CMD_WR_TOP (1UL<<10) 9681 #define TDMA_FTQ_CMD_WR_TOP_0 (0UL<<10) 9682 #define TDMA_FTQ_CMD_WR_TOP_1 (1UL<<10) 9683 #define TDMA_FTQ_CMD_SFT_RESET (1UL<<25) 9684 #define TDMA_FTQ_CMD_RD_DATA (1UL<<26) 9685 #define TDMA_FTQ_CMD_ADD_INTERVEN (1UL<<27) 9686 #define TDMA_FTQ_CMD_ADD_DATA (1UL<<28) 9687 #define TDMA_FTQ_CMD_INTERVENE_CLR (1UL<<29) 9688 #define TDMA_FTQ_CMD_POP (1UL<<30) 9689 #define TDMA_FTQ_CMD_BUSY (1UL<<31) 9690 9691 u32_t tdma_ftq_ctl; 9692 #define TDMA_FTQ_CTL_INTERVENE (1UL<<0) 9693 #define TDMA_FTQ_CTL_OVERFLOW (1UL<<1) 9694 #define TDMA_FTQ_CTL_FORCE_INTERVENE (1UL<<2) 9695 #define TDMA_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) 9696 #define TDMA_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) 9697 9698 } tdma_reg_t; 9699 9700 typedef tdma_reg_t tx_dma_reg_t; 9701 9702 /* 9703 * dbu_reg definition 9704 * offset: 0x6000 9705 */ 9706 typedef struct dbu_reg 9707 { 9708 u32_t dbu_cmd; 9709 #define DBU_CMD_ENABLE (1UL<<0) 9710 #define DBU_CMD_RX_ERROR (1UL<<1) 9711 #define DBU_CMD_RX_OVERFLOW (1UL<<2) 9712 9713 u32_t dbu_status; 9714 #define DBU_STATUS_RXDATA_VALID (1UL<<0) 9715 #define DBU_STATUS_TXDATA_OCCUPIED (1UL<<1) 9716 9717 u32_t dbu_config; 9718 #define DBU_CONFIG_TIMING_OVERRIDE (1UL<<0) 9719 #define DBU_CONFIG_DEBUGSM_ENABLE (1UL<<1) 9720 #define DBU_CONFIG_CRLF_ENABLE (1UL<<2) 9721 9722 u32_t dbu_timing; 9723 #define DBU_TIMING_FB_SMPL_OFFSET (0xffffUL<<0) 9724 #define DBU_TIMING_BIT_INTERVAL (0xffffUL<<16) 9725 9726 u32_t dbu_rxdata; 9727 #define DBU_RXDATA_VALUE (0xffUL<<0) 9728 #define DBU_RXDATA_ERROR (1UL<<8) 9729 9730 u32_t dbu_txdata; 9731 #define DBU_TXDATA_VALUE (0xffUL<<0) 9732 9733 u32_t unused_0[250]; 9734 } dbu_reg_t; 9735 9736 9737 /* 9738 * debug_reg definition 9739 * offset: 0x7000 9740 */ 9741 typedef struct debug_reg 9742 { 9743 u32_t debug_command; 9744 u32_t unused_0[511]; 9745 } debug_reg_t; 9746 9747 9748 /* 9749 * tx_assembler_enqueue definition 9750 * offset: 0000 9751 */ 9752 typedef struct tx_assembler_enqueue 9753 { 9754 u32_t tx_assembler_enqueue_wd0; 9755 #define TX_ASSEMBLER_ENQUEUE_HDR_SKIP_VALUE (0xff<<16) 9756 #define TX_ASSEMBLER_ENQUEUE_HDR_POST_SKIP_VALUE (0xff<<0) 9757 9758 u32_t tx_assembler_enqueue_wd1; 9759 #define TX_ASSEMBLER_ENQUEUE_HDR_SIZE_VALUE_TE (0xff<<16) 9760 #define TX_ASSEMBLER_ENQUEUE_HDR_SIZE_VALUE_XI (0x1fff<<16) 9761 #define TX_ASSEMBLER_ENQUEUE_PAYLOAD_SKIP_VALUE (0x3fff<<0) 9762 9763 u32_t tx_assembler_enqueue_wd2; 9764 #define TX_ASSEMBLER_ENQUEUE_PAYLOAD_SIZE_VALUE (0x3fff<<16) 9765 #define TX_ASSEMBLER_ENQUEUE_FLAGS_PKT_END (1<<0) 9766 #define TX_ASSEMBLER_ENQUEUE_FLAGS_MGMT_PACKET (1<<1) 9767 #define TX_ASSEMBLER_ENQUEUE_FLAGS_CATCHUP_PACKET (1<<2) 9768 #define TX_ASSEMBLER_ENQUEUE_FLAGS_DONT_GEN_CRC (1<<3) 9769 #define TX_ASSEMBLER_ENQUEUE_FLAGS_DROP (1<<4) 9770 #define TX_ASSEMBLER_ENQUEUE_FLAGS_RESERVED (0x3<<5) 9771 #define TX_ASSEMBLER_ENQUEUE_FLAGS_MGMT_PKT_TAG_TE (0xf<<8) 9772 #define TX_ASSEMBLER_ENQUEUE_FLAGS_MGMT_PKT_TAG_XI (0x1f<<8) 9773 #define TX_ASSEMBLER_ENQUEUE_FLAGS_CS16_VLD_XI (1<<15) 9774 9775 u32_t tx_assembler_enqueue_wd3; 9776 #define TX_ASSEMBLER_ENQUEUE_CS16_VALUE (0xffff<<16) 9777 9778 } tx_assembler_enqueue_t; 9779 9780 9781 /* 9782 * tas_reg definition 9783 * offset: 0x1c0000 9784 */ 9785 typedef struct tas_reg 9786 { 9787 u32_t tas_command; 9788 #define TAS_COMMAND_TAS_ENABLE (1UL<<0) 9789 #define TAS_COMMAND_TPBUF_ENABLE (1UL<<1) 9790 #define TAS_COMMAND_THBUF_ENABLE (1UL<<2) 9791 #define TAS_COMMAND_PKT_END_TOSHORT_ABORT (1UL<<5) 9792 #define TAS_COMMAND_THBUF_INIT (1UL<<6) 9793 #define TAS_COMMAND_TPBUF_INIT (1UL<<7) 9794 #define TAS_COMMAND_RESET_STATE (1UL<<31) 9795 9796 u32_t tas_status; 9797 #define TAS_STATUS_ACPI_MODE (1UL<<0) 9798 #define TAS_STATUS_KNUM_TAG (0xfUL<<4) 9799 #define TAS_STATUS_MGMT_TAG_TE (0xfUL<<8) 9800 #define TAS_STATUS_MGMT_TAG_XI (0x1fUL<<8) 9801 #define TAS_STATUS_MAC_PKTS_STAT (1UL<<16) 9802 #define TAS_STATUS_CU_PKTS_STAT (1UL<<17) 9803 9804 u32_t tas_config; 9805 #define TAS_CONFIG_PAYLOAD_MAX_LOW (0x3ffUL<<0) 9806 #define TAS_CONFIG_PAYLOAD_MAX (0x1fUL<<10) 9807 9808 u32_t tas_payload_cons; 9809 #define TAS_PAYLOAD_CONS_VALUE (0x1fffUL<<3) 9810 9811 u32_t tas_header_cons; 9812 #define TAS_HEADER_CONS_VALUE (0x7ffUL<<3) 9813 9814 u32_t tas_debug_vect_peek; 9815 u32_t unused_0[234]; 9816 tx_assembler_enqueue_t tas_tasq; 9817 u32_t unused_1[10]; 9818 u32_t tas_ftq_cmd; 9819 #define TAS_FTQ_CMD_OFFSET (0x3ffUL<<0) 9820 #define TAS_FTQ_CMD_WR_TOP (1UL<<10) 9821 #define TAS_FTQ_CMD_WR_TOP_0 (0UL<<10) 9822 #define TAS_FTQ_CMD_WR_TOP_1 (1UL<<10) 9823 #define TAS_FTQ_CMD_SFT_RESET (1UL<<25) 9824 #define TAS_FTQ_CMD_RD_DATA (1UL<<26) 9825 #define TAS_FTQ_CMD_ADD_INTERVEN (1UL<<27) 9826 #define TAS_FTQ_CMD_ADD_DATA (1UL<<28) 9827 #define TAS_FTQ_CMD_INTERVENE_CLR (1UL<<29) 9828 #define TAS_FTQ_CMD_POP (1UL<<30) 9829 #define TAS_FTQ_CMD_BUSY (1UL<<31) 9830 9831 u32_t tas_ftq_ctl; 9832 #define TAS_FTQ_CTL_INTERVENE (1UL<<0) 9833 #define TAS_FTQ_CTL_OVERFLOW (1UL<<1) 9834 #define TAS_FTQ_CTL_FORCE_INTERVENE (1UL<<2) 9835 #define TAS_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) 9836 #define TAS_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) 9837 9838 u32_t unused_2[32512]; 9839 u32_t tas_thbuf[2048]; 9840 u32_t unused_3[14336]; 9841 u32_t tas_tpbuf[6144]; 9842 u32_t unused_4[10240]; 9843 } tas_reg_t; 9844 9845 typedef tas_reg_t tx_assembler_reg_t; 9846 9847 /* 9848 * hc_reg definition 9849 * offset: 0x6800 9850 */ 9851 typedef struct hc_reg 9852 { 9853 u32_t hc_command; 9854 #define HC_COMMAND_ENABLE (1UL<<0) 9855 #define HC_COMMAND_SKIP_ABORT (1UL<<4) 9856 #define HC_COMMAND_COAL_NOW (1UL<<16) 9857 #define HC_COMMAND_COAL_NOW_WO_INT (1UL<<17) 9858 #define HC_COMMAND_STATS_NOW (1UL<<18) 9859 #define HC_COMMAND_FORCE_INT (0x3UL<<19) 9860 #define HC_COMMAND_FORCE_INT_NULL (0UL<<19) 9861 #define HC_COMMAND_FORCE_INT_HIGH (1UL<<19) 9862 #define HC_COMMAND_FORCE_INT_LOW (2UL<<19) 9863 #define HC_COMMAND_FORCE_INT_FREE (3UL<<19) 9864 #define HC_COMMAND_CLR_STAT_NOW (1UL<<21) 9865 #define HC_COMMAND_MAIN_PWR_INT (1UL<<22) 9866 #define HC_COMMAND_COAL_ON_NEXT_EVENT (1UL<<27) 9867 9868 u32_t hc_status; 9869 #define HC_STATUS_MASTER_ABORT (1UL<<0) 9870 #define HC_STATUS_PARITY_ERROR_STATE (1UL<<1) 9871 #define HC_STATUS_PCI_CLK_CNT_STAT (1UL<<16) 9872 #define HC_STATUS_CORE_CLK_CNT_STAT (1UL<<17) 9873 #define HC_STATUS_NUM_STATUS_BLOCKS_STAT (1UL<<18) 9874 #define HC_STATUS_NUM_INT_GEN_STAT (1UL<<19) 9875 #define HC_STATUS_NUM_INT_MBOX_WR_STAT (1UL<<20) 9876 #define HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1UL<<23) 9877 #define HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1UL<<24) 9878 #define HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1UL<<25) 9879 9880 u32_t hc_config; 9881 #define HC_CONFIG_COLLECT_STATS (1UL<<0) 9882 #define HC_CONFIG_RX_TMR_MODE (1UL<<1) 9883 #define HC_CONFIG_TX_TMR_MODE (1UL<<2) 9884 #define HC_CONFIG_COM_TMR_MODE (1UL<<3) 9885 #define HC_CONFIG_CMD_TMR_MODE (1UL<<4) 9886 #define HC_CONFIG_STATISTIC_PRIORITY (1UL<<5) 9887 #define HC_CONFIG_STATUS_PRIORITY (1UL<<6) 9888 #define HC_CONFIG_STAT_MEM_ADDR (0xffUL<<8) 9889 #define HC_CONFIG_PER_MODE (1UL<<16) 9890 #define HC_CONFIG_ONE_SHOT (1UL<<17) 9891 #define HC_CONFIG_USE_INT_PARAM (1UL<<18) 9892 #define HC_CONFIG_SET_MASK_AT_RD (1UL<<19) 9893 #define HC_CONFIG_PER_COLLECT_LIMIT (0xfUL<<20) 9894 #define HC_CONFIG_SB_ADDR_INC (0x7UL<<24) 9895 #define HC_CONFIG_SB_ADDR_INC_64B (0UL<<24) 9896 #define HC_CONFIG_SB_ADDR_INC_128B (1UL<<24) 9897 #define HC_CONFIG_SB_ADDR_INC_256B (2UL<<24) 9898 #define HC_CONFIG_SB_ADDR_INC_512B (3UL<<24) 9899 #define HC_CONFIG_SB_ADDR_INC_1024B (4UL<<24) 9900 #define HC_CONFIG_SB_ADDR_INC_2048B (5UL<<24) 9901 #define HC_CONFIG_SB_ADDR_INC_4096B (6UL<<24) 9902 #define HC_CONFIG_SB_ADDR_INC_8192B (7UL<<24) 9903 #define HC_CONFIG_GEN_STAT_AVG_INTR (1UL<<29) 9904 #define HC_CONFIG_UNMASK_ALL (1UL<<30) 9905 #define HC_CONFIG_TX_SEL (1UL<<31) 9906 9907 u32_t hc_attn_bits_enable; 9908 u32_t hc_status_addr_l; 9909 u32_t hc_status_addr_h; 9910 u32_t hc_statistics_addr_l; 9911 u32_t hc_statistics_addr_h; 9912 u32_t hc_tx_quick_cons_trip; 9913 #define HC_TX_QUICK_CONS_TRIP_VALUE (0xffUL<<0) 9914 #define HC_TX_QUICK_CONS_TRIP_INT (0xffUL<<16) 9915 9916 u32_t hc_comp_prod_trip; 9917 #define HC_COMP_PROD_TRIP_VALUE (0xffUL<<0) 9918 #define HC_COMP_PROD_TRIP_INT (0xffUL<<16) 9919 9920 u32_t hc_rx_quick_cons_trip; 9921 #define HC_RX_QUICK_CONS_TRIP_VALUE (0xffUL<<0) 9922 #define HC_RX_QUICK_CONS_TRIP_INT (0xffUL<<16) 9923 9924 u32_t hc_rx_ticks; 9925 #define HC_RX_TICKS_VALUE (0x3ffUL<<0) 9926 #define HC_RX_TICKS_INT (0x3ffUL<<16) 9927 9928 u32_t hc_tx_ticks; 9929 #define HC_TX_TICKS_VALUE (0x3ffUL<<0) 9930 #define HC_TX_TICKS_INT (0x3ffUL<<16) 9931 9932 u32_t hc_com_ticks; 9933 #define HC_COM_TICKS_VALUE (0x3ffUL<<0) 9934 #define HC_COM_TICKS_INT (0x3ffUL<<16) 9935 9936 u32_t hc_cmd_ticks; 9937 #define HC_CMD_TICKS_VALUE (0x3ffUL<<0) 9938 #define HC_CMD_TICKS_INT (0x3ffUL<<16) 9939 9940 u32_t hc_periodic_ticks; 9941 #define HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffUL<<0) 9942 #define HC_PERIODIC_TICKS_HC_INT_PERIODIC_TICKS (0xffffUL<<16) 9943 9944 u32_t hc_stat_collect_ticks; 9945 #define HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffUL<<4) 9946 9947 u32_t hc_stats_ticks; 9948 #define HC_STATS_TICKS_HC_STAT_TICKS (0xffffUL<<8) 9949 9950 u32_t hc_stats_interrupt_status; 9951 #define HC_STATS_INTERRUPT_STATUS_SB_STATUS (0x1ffUL<<0) 9952 #define HC_STATS_INTERRUPT_STATUS_INT_STATUS (0x1ffUL<<16) 9953 9954 u32_t hc_stat_mem_data; 9955 u32_t hc_stat_gen_sel_0; 9956 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TE (0x7fUL<<0) 9957 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0_TE (0UL<<0) 9958 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1_TE (1UL<<0) 9959 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2_TE (2UL<<0) 9960 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3_TE (3UL<<0) 9961 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4_TE (4UL<<0) 9962 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5_TE (5UL<<0) 9963 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6_TE (6UL<<0) 9964 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7_TE (7UL<<0) 9965 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8_TE (8UL<<0) 9966 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9_TE (9UL<<0) 9967 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10_TE (10UL<<0) 9968 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11_TE (11UL<<0) 9969 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0_TE (12UL<<0) 9970 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1_TE (13UL<<0) 9971 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2_TE (14UL<<0) 9972 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3_TE (15UL<<0) 9973 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4_TE (16UL<<0) 9974 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5_TE (17UL<<0) 9975 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6_TE (18UL<<0) 9976 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7_TE (19UL<<0) 9977 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0_TE (20UL<<0) 9978 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1_TE (21UL<<0) 9979 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2_TE (22UL<<0) 9980 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3_TE (23UL<<0) 9981 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4_TE (24UL<<0) 9982 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5_TE (25UL<<0) 9983 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6_TE (26UL<<0) 9984 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7_TE (27UL<<0) 9985 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8_TE (28UL<<0) 9986 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9_TE (29UL<<0) 9987 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10_TE (30UL<<0) 9988 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11_TE (31UL<<0) 9989 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0_TE (32UL<<0) 9990 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1_TE (33UL<<0) 9991 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2_TE (34UL<<0) 9992 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3_TE (35UL<<0) 9993 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0_TE (36UL<<0) 9994 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1_TE (37UL<<0) 9995 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2_TE (38UL<<0) 9996 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3_TE (39UL<<0) 9997 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4_TE (40UL<<0) 9998 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5_TE (41UL<<0) 9999 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6_TE (42UL<<0) 10000 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7_TE (43UL<<0) 10001 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0_TE (44UL<<0) 10002 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1_TE (45UL<<0) 10003 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2_TE (46UL<<0) 10004 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3_TE (47UL<<0) 10005 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4_TE (48UL<<0) 10006 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5_TE (49UL<<0) 10007 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6_TE (50UL<<0) 10008 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7_TE (51UL<<0) 10009 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT_TE (52UL<<0) 10010 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT_TE (53UL<<0) 10011 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_TE (54UL<<0) 10012 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_TE (55UL<<0) 10013 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_TE (56UL<<0) 10014 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_TE (59UL<<0) 10015 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_TE (60UL<<0) 10016 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_TE (61UL<<0) 10017 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT_TE (62UL<<0) 10018 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT_TE (63UL<<0) 10019 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT_TE (64UL<<0) 10020 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT_TE (65UL<<0) 10021 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT_TE (66UL<<0) 10022 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT_TE (67UL<<0) 10023 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT_TE (68UL<<0) 10024 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT_TE (69UL<<0) 10025 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT_TE (70UL<<0) 10026 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT_TE (71UL<<0) 10027 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT_TE (72UL<<0) 10028 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT_TE (73UL<<0) 10029 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT_TE (74UL<<0) 10030 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT_TE (75UL<<0) 10031 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT_TE (76UL<<0) 10032 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT_TE (77UL<<0) 10033 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT_TE (78UL<<0) 10034 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT_TE (79UL<<0) 10035 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT_TE (80UL<<0) 10036 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT_TE (81UL<<0) 10037 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT_TE (82UL<<0) 10038 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT_TE (83UL<<0) 10039 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT_TE (84UL<<0) 10040 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT_TE (85UL<<0) 10041 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT_TE (86UL<<0) 10042 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT_TE (87UL<<0) 10043 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT_TE (88UL<<0) 10044 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT_TE (89UL<<0) 10045 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT_TE (90UL<<0) 10046 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT_TE (91UL<<0) 10047 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT_TE (92UL<<0) 10048 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT_TE (93UL<<0) 10049 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT_TE (94UL<<0) 10050 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64_TE (95UL<<0) 10051 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64_TE (96UL<<0) 10052 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS_TE (97UL<<0) 10053 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS_TE (98UL<<0) 10054 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT_TE (99UL<<0) 10055 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT_TE (100UL<<0) 10056 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT_TE (101UL<<0) 10057 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT_TE (102UL<<0) 10058 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT_TE (103UL<<0) 10059 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT_TE (104UL<<0) 10060 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT_TE (105UL<<0) 10061 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT_TE (106UL<<0) 10062 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT_TE (107UL<<0) 10063 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT_TE (108UL<<0) 10064 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT_TE (109UL<<0) 10065 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT_TE (110UL<<0) 10066 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT_TE (111UL<<0) 10067 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT_TE (112UL<<0) 10068 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT_TE (113UL<<0) 10069 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT_TE (114UL<<0) 10070 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0_TE (115UL<<0) 10071 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1_TE (116UL<<0) 10072 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2_TE (117UL<<0) 10073 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3_TE (118UL<<0) 10074 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4_TE (119UL<<0) 10075 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5_TE (120UL<<0) 10076 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS_TE (121UL<<0) 10077 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS_TE (122UL<<0) 10078 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT_TE (127UL<<0) 10079 #define HC_STAT_GEN_SEL_0_GEN_SEL_1_TE (0x7fUL<<8) 10080 #define HC_STAT_GEN_SEL_0_GEN_SEL_2_TE (0x7fUL<<16) 10081 #define HC_STAT_GEN_SEL_0_GEN_SEL_3_TE (0x7fUL<<24) 10082 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_XI (0xffUL<<0) 10083 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0_XI (0UL<<0) 10084 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1_XI (1UL<<0) 10085 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2_XI (2UL<<0) 10086 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3_XI (3UL<<0) 10087 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4_XI (4UL<<0) 10088 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5_XI (5UL<<0) 10089 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6_XI (6UL<<0) 10090 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7_XI (7UL<<0) 10091 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8_XI (8UL<<0) 10092 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9_XI (9UL<<0) 10093 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10_XI (10UL<<0) 10094 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11_XI (11UL<<0) 10095 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0_XI (12UL<<0) 10096 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1_XI (13UL<<0) 10097 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2_XI (14UL<<0) 10098 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3_XI (15UL<<0) 10099 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4_XI (16UL<<0) 10100 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5_XI (17UL<<0) 10101 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6_XI (18UL<<0) 10102 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7_XI (19UL<<0) 10103 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0_XI (20UL<<0) 10104 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1_XI (21UL<<0) 10105 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2_XI (22UL<<0) 10106 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3_XI (23UL<<0) 10107 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4_XI (24UL<<0) 10108 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5_XI (25UL<<0) 10109 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6_XI (26UL<<0) 10110 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7_XI (27UL<<0) 10111 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8_XI (28UL<<0) 10112 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9_XI (29UL<<0) 10113 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10_XI (30UL<<0) 10114 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11_XI (31UL<<0) 10115 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0_XI (32UL<<0) 10116 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1_XI (33UL<<0) 10117 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2_XI (34UL<<0) 10118 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3_XI (35UL<<0) 10119 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0_XI (36UL<<0) 10120 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1_XI (37UL<<0) 10121 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2_XI (38UL<<0) 10122 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3_XI (39UL<<0) 10123 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4_XI (40UL<<0) 10124 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5_XI (41UL<<0) 10125 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6_XI (42UL<<0) 10126 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7_XI (43UL<<0) 10127 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0_XI (44UL<<0) 10128 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1_XI (45UL<<0) 10129 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2_XI (46UL<<0) 10130 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3_XI (47UL<<0) 10131 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4_XI (48UL<<0) 10132 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5_XI (49UL<<0) 10133 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6_XI (50UL<<0) 10134 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7_XI (51UL<<0) 10135 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UMP_RX_FRAME_DROP_XI (52UL<<0) 10136 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT_XI (53UL<<0) 10137 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_XI (54UL<<0) 10138 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_XI (55UL<<0) 10139 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_XI (56UL<<0) 10140 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S0_XI (57UL<<0) 10141 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S1_XI (58UL<<0) 10142 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_XI (59UL<<0) 10143 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_XI (60UL<<0) 10144 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_XI (61UL<<0) 10145 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT_XI (62UL<<0) 10146 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT_XI (63UL<<0) 10147 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT_XI (64UL<<0) 10148 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT_XI (65UL<<0) 10149 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT_XI (66UL<<0) 10150 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT_XI (67UL<<0) 10151 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT_XI (68UL<<0) 10152 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT_XI (69UL<<0) 10153 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT_XI (70UL<<0) 10154 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT_XI (71UL<<0) 10155 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT_XI (72UL<<0) 10156 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT_XI (73UL<<0) 10157 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT_XI (74UL<<0) 10158 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT_XI (75UL<<0) 10159 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT_XI (76UL<<0) 10160 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT_XI (77UL<<0) 10161 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT_XI (78UL<<0) 10162 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT_XI (79UL<<0) 10163 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT_XI (80UL<<0) 10164 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT_XI (81UL<<0) 10165 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT_XI (82UL<<0) 10166 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT_XI (83UL<<0) 10167 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT_XI (84UL<<0) 10168 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S2_XI (85UL<<0) 10169 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S3_XI (86UL<<0) 10170 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S4_XI (87UL<<0) 10171 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S5_XI (88UL<<0) 10172 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S6_XI (89UL<<0) 10173 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S7_XI (90UL<<0) 10174 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S8_XI (91UL<<0) 10175 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S9_XI (92UL<<0) 10176 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S10_XI (93UL<<0) 10177 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MQ_IDB_OFLOW_XI (94UL<<0) 10178 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64_XI (95UL<<0) 10179 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64_XI (96UL<<0) 10180 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS_XI (97UL<<0) 10181 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS_XI (98UL<<0) 10182 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT_XI (99UL<<0) 10183 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT_XI (100UL<<0) 10184 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT_XI (101UL<<0) 10185 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT_XI (102UL<<0) 10186 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT_XI (103UL<<0) 10187 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT_XI (104UL<<0) 10188 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT_XI (105UL<<0) 10189 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT_XI (106UL<<0) 10190 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT_XI (107UL<<0) 10191 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT_XI (108UL<<0) 10192 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT_XI (109UL<<0) 10193 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT_XI (110UL<<0) 10194 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT_XI (111UL<<0) 10195 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT_XI (112UL<<0) 10196 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT_XI (113UL<<0) 10197 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT_XI (114UL<<0) 10198 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0_XI (115UL<<0) 10199 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1_XI (116UL<<0) 10200 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2_XI (117UL<<0) 10201 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3_XI (118UL<<0) 10202 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4_XI (119UL<<0) 10203 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5_XI (120UL<<0) 10204 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS_XI (121UL<<0) 10205 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS_XI (122UL<<0) 10206 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_RD_CNT_XI (123UL<<0) 10207 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_WR_CNT_XI (124UL<<0) 10208 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_HITS_XI (125UL<<0) 10209 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_MISSES_XI (126UL<<0) 10210 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT_XI (127UL<<0) 10211 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC1_XI (128UL<<0) 10212 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC1_XI (129UL<<0) 10213 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC1_XI (130UL<<0) 10214 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC1_XI (131UL<<0) 10215 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC1_XI (132UL<<0) 10216 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC1_XI (133UL<<0) 10217 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC2_XI (134UL<<0) 10218 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC2_XI (135UL<<0) 10219 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC2_XI (136UL<<0) 10220 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC2_XI (137UL<<0) 10221 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC2_XI (138UL<<0) 10222 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC2_XI (139UL<<0) 10223 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC3_XI (140UL<<0) 10224 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC3_XI (141UL<<0) 10225 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC3_XI (142UL<<0) 10226 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC3_XI (143UL<<0) 10227 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC3_XI (144UL<<0) 10228 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC3_XI (145UL<<0) 10229 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC4_XI (146UL<<0) 10230 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC4_XI (147UL<<0) 10231 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC4_XI (148UL<<0) 10232 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC4_XI (149UL<<0) 10233 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC4_XI (150UL<<0) 10234 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC4_XI (151UL<<0) 10235 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC5_XI (152UL<<0) 10236 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC5_XI (153UL<<0) 10237 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC5_XI (154UL<<0) 10238 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC5_XI (155UL<<0) 10239 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC5_XI (156UL<<0) 10240 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC5_XI (157UL<<0) 10241 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC6_XI (158UL<<0) 10242 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC6_XI (159UL<<0) 10243 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC6_XI (160UL<<0) 10244 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC6_XI (161UL<<0) 10245 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC6_XI (162UL<<0) 10246 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC6_XI (163UL<<0) 10247 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC7_XI (164UL<<0) 10248 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC7_XI (165UL<<0) 10249 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC7_XI (166UL<<0) 10250 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC7_XI (167UL<<0) 10251 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC7_XI (168UL<<0) 10252 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC7_XI (169UL<<0) 10253 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC8_XI (170UL<<0) 10254 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC8_XI (171UL<<0) 10255 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC8_XI (172UL<<0) 10256 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC8_XI (173UL<<0) 10257 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC8_XI (174UL<<0) 10258 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC8_XI (175UL<<0) 10259 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_CMD_CNT_XI (176UL<<0) 10260 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_SLOT_CNT_XI (177UL<<0) 10261 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI (178UL<<0) 10262 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S15_XI (179UL<<0) 10263 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S16_XI (180UL<<0) 10264 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S17_XI (181UL<<0) 10265 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S18_XI (182UL<<0) 10266 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S19_XI (183UL<<0) 10267 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S20_XI (184UL<<0) 10268 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S21_XI (185UL<<0) 10269 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S22_XI (186UL<<0) 10270 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S23_XI (187UL<<0) 10271 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S24_XI (188UL<<0) 10272 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S25_XI (189UL<<0) 10273 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S26_XI (190UL<<0) 10274 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S27_XI (191UL<<0) 10275 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S28_XI (192UL<<0) 10276 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S29_XI (193UL<<0) 10277 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S30_XI (194UL<<0) 10278 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S31_XI (195UL<<0) 10279 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S32_XI (196UL<<0) 10280 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S33_XI (197UL<<0) 10281 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S34_XI (198UL<<0) 10282 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S35_XI (199UL<<0) 10283 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S36_XI (200UL<<0) 10284 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S37_XI (201UL<<0) 10285 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S38_XI (202UL<<0) 10286 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S39_XI (203UL<<0) 10287 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S40_XI (204UL<<0) 10288 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S41_XI (205UL<<0) 10289 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S42_XI (206UL<<0) 10290 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S43_XI (207UL<<0) 10291 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S44_XI (208UL<<0) 10292 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S45_XI (209UL<<0) 10293 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S46_XI (210UL<<0) 10294 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S47_XI (211UL<<0) 10295 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S48_XI (212UL<<0) 10296 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S49_XI (213UL<<0) 10297 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S50_XI (214UL<<0) 10298 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S51_XI (215UL<<0) 10299 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S52_XI (216UL<<0) 10300 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S53_XI (217UL<<0) 10301 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S54_XI (218UL<<0) 10302 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S55_XI (219UL<<0) 10303 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S56_XI (220UL<<0) 10304 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S57_XI (221UL<<0) 10305 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S58_XI (222UL<<0) 10306 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S59_XI (223UL<<0) 10307 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S60_XI (224UL<<0) 10308 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S61_XI (225UL<<0) 10309 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S62_XI (226UL<<0) 10310 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S63_XI (227UL<<0) 10311 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S64_XI (228UL<<0) 10312 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S65_XI (229UL<<0) 10313 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S66_XI (230UL<<0) 10314 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S67_XI (231UL<<0) 10315 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S68_XI (232UL<<0) 10316 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S69_XI (233UL<<0) 10317 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S70_XI (234UL<<0) 10318 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S71_XI (235UL<<0) 10319 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S72_XI (236UL<<0) 10320 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S73_XI (237UL<<0) 10321 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S74_XI (238UL<<0) 10322 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S75_XI (239UL<<0) 10323 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S76_XI (240UL<<0) 10324 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S77_XI (241UL<<0) 10325 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S78_XI (242UL<<0) 10326 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S79_XI (243UL<<0) 10327 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S80_XI (244UL<<0) 10328 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S81_XI (245UL<<0) 10329 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S82_XI (246UL<<0) 10330 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S83_XI (247UL<<0) 10331 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S84_XI (248UL<<0) 10332 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S85_XI (249UL<<0) 10333 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S86_XI (250UL<<0) 10334 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S87_XI (251UL<<0) 10335 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S88_XI (252UL<<0) 10336 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S89_XI (253UL<<0) 10337 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S90_XI (254UL<<0) 10338 #define HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S91_XI (255UL<<0) 10339 #define HC_STAT_GEN_SEL_0_GEN_SEL_1_XI (0xffUL<<8) 10340 #define HC_STAT_GEN_SEL_0_GEN_SEL_2_XI (0xffUL<<16) 10341 #define HC_STAT_GEN_SEL_0_GEN_SEL_3_XI (0xffUL<<24) 10342 10343 u32_t hc_stat_gen_sel_1; 10344 #define HC_STAT_GEN_SEL_1_GEN_SEL_4_TE (0x7fUL<<0) 10345 #define HC_STAT_GEN_SEL_1_GEN_SEL_5_TE (0x7fUL<<8) 10346 #define HC_STAT_GEN_SEL_1_GEN_SEL_6_TE (0x7fUL<<16) 10347 #define HC_STAT_GEN_SEL_1_GEN_SEL_7_TE (0x7fUL<<24) 10348 #define HC_STAT_GEN_SEL_1_GEN_SEL_4_XI (0xffUL<<0) 10349 #define HC_STAT_GEN_SEL_1_GEN_SEL_5_XI (0xffUL<<8) 10350 #define HC_STAT_GEN_SEL_1_GEN_SEL_6_XI (0xffUL<<16) 10351 #define HC_STAT_GEN_SEL_1_GEN_SEL_7_XI (0xffUL<<24) 10352 10353 u32_t hc_stat_gen_sel_2; 10354 #define HC_STAT_GEN_SEL_2_GEN_SEL_8_TE (0x7fUL<<0) 10355 #define HC_STAT_GEN_SEL_2_GEN_SEL_9_TE (0x7fUL<<8) 10356 #define HC_STAT_GEN_SEL_2_GEN_SEL_10_TE (0x7fUL<<16) 10357 #define HC_STAT_GEN_SEL_2_GEN_SEL_11_TE (0x7fUL<<24) 10358 #define HC_STAT_GEN_SEL_2_GEN_SEL_8_XI (0xffUL<<0) 10359 #define HC_STAT_GEN_SEL_2_GEN_SEL_9_XI (0xffUL<<8) 10360 #define HC_STAT_GEN_SEL_2_GEN_SEL_10_XI (0xffUL<<16) 10361 #define HC_STAT_GEN_SEL_2_GEN_SEL_11_XI (0xffUL<<24) 10362 10363 u32_t hc_stat_gen_sel_3; 10364 #define HC_STAT_GEN_SEL_3_GEN_SEL_12_TE (0x7fUL<<0) 10365 #define HC_STAT_GEN_SEL_3_GEN_SEL_13_TE (0x7fUL<<8) 10366 #define HC_STAT_GEN_SEL_3_GEN_SEL_14_TE (0x7fUL<<16) 10367 #define HC_STAT_GEN_SEL_3_GEN_SEL_15_TE (0x7fUL<<24) 10368 #define HC_STAT_GEN_SEL_3_GEN_SEL_12_XI (0xffUL<<0) 10369 #define HC_STAT_GEN_SEL_3_GEN_SEL_13_XI (0xffUL<<8) 10370 #define HC_STAT_GEN_SEL_3_GEN_SEL_14_XI (0xffUL<<16) 10371 #define HC_STAT_GEN_SEL_3_GEN_SEL_15_XI (0xffUL<<24) 10372 10373 u32_t unused_0[10]; 10374 u32_t hc_stat_gen_stat[16]; 10375 u32_t hc_stat_gen_stat_ac[16]; 10376 u32_t hc_vis; 10377 #define HC_VIS_STAT_BUILD_STATE (0xfUL<<0) 10378 #define HC_VIS_STAT_BUILD_STATE_IDLE (0UL<<0) 10379 #define HC_VIS_STAT_BUILD_STATE_START (1UL<<0) 10380 #define HC_VIS_STAT_BUILD_STATE_REQUEST (2UL<<0) 10381 #define HC_VIS_STAT_BUILD_STATE_UPDATE64 (3UL<<0) 10382 #define HC_VIS_STAT_BUILD_STATE_UPDATE32 (4UL<<0) 10383 #define HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5UL<<0) 10384 #define HC_VIS_STAT_BUILD_STATE_DMA (6UL<<0) 10385 #define HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7UL<<0) 10386 #define HC_VIS_STAT_BUILD_STATE_MSI_LOW (8UL<<0) 10387 #define HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9UL<<0) 10388 #define HC_VIS_STAT_BUILD_STATE_MSI_DATA (10UL<<0) 10389 #define HC_VIS_DMA_STAT_STATE (0xfUL<<8) 10390 #define HC_VIS_DMA_STAT_STATE_IDLE (0UL<<8) 10391 #define HC_VIS_DMA_STAT_STATE_STATUS_PARAM (1UL<<8) 10392 #define HC_VIS_DMA_STAT_STATE_STATUS_DMA (2UL<<8) 10393 #define HC_VIS_DMA_STAT_STATE_WRITE_COMP (3UL<<8) 10394 #define HC_VIS_DMA_STAT_STATE_COMP (4UL<<8) 10395 #define HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM (5UL<<8) 10396 #define HC_VIS_DMA_STAT_STATE_STATISTIC_DMA (6UL<<8) 10397 #define HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 (7UL<<8) 10398 #define HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 (8UL<<8) 10399 #define HC_VIS_DMA_STAT_STATE_WAIT (9UL<<8) 10400 #define HC_VIS_DMA_STAT_STATE_ABORT (15UL<<8) 10401 #define HC_VIS_DMA_MSI_STATE (0x7UL<<12) 10402 #define HC_VIS_STATISTIC_DMA_EN_STATE (0x3UL<<15) 10403 #define HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0UL<<15) 10404 #define HC_VIS_STATISTIC_DMA_EN_STATE_COUNT (1UL<<15) 10405 #define HC_VIS_STATISTIC_DMA_EN_STATE_START (2UL<<15) 10406 10407 u32_t hc_vis_1; 10408 #define HC_VIS_1_HW_INTACK_STATE (1UL<<4) 10409 #define HC_VIS_1_HW_INTACK_STATE_IDLE (0UL<<4) 10410 #define HC_VIS_1_HW_INTACK_STATE_COUNT (1UL<<4) 10411 #define HC_VIS_1_SW_INTACK_STATE (1UL<<5) 10412 #define HC_VIS_1_SW_INTACK_STATE_IDLE (0UL<<5) 10413 #define HC_VIS_1_SW_INTACK_STATE_COUNT (1UL<<5) 10414 #define HC_VIS_1_DURING_SW_INTACK_STATE (1UL<<6) 10415 #define HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0UL<<6) 10416 #define HC_VIS_1_DURING_SW_INTACK_STATE_COUNT (1UL<<6) 10417 #define HC_VIS_1_MAILBOX_COUNT_STATE (1UL<<7) 10418 #define HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0UL<<7) 10419 #define HC_VIS_1_MAILBOX_COUNT_STATE_COUNT (1UL<<7) 10420 #define HC_VIS_1_RAM_RD_ARB_STATE (0xfUL<<17) 10421 #define HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0UL<<17) 10422 #define HC_VIS_1_RAM_RD_ARB_STATE_DMA (1UL<<17) 10423 #define HC_VIS_1_RAM_RD_ARB_STATE_UPDATE (2UL<<17) 10424 #define HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN (3UL<<17) 10425 #define HC_VIS_1_RAM_RD_ARB_STATE_WAIT (4UL<<17) 10426 #define HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5UL<<17) 10427 #define HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6UL<<17) 10428 #define HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT (7UL<<17) 10429 #define HC_VIS_1_RAM_WR_ARB_STATE (0x3UL<<21) 10430 #define HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0UL<<21) 10431 #define HC_VIS_1_RAM_WR_ARB_STATE_CLEAR (1UL<<21) 10432 #define HC_VIS_1_INT_GEN_STATE (1UL<<23) 10433 #define HC_VIS_1_INT_GEN_STATE_DLE (0UL<<23) 10434 #define HC_VIS_1_INT_GEN_STATE_NTERRUPT (1UL<<23) 10435 #define HC_VIS_1_STAT_CHAN_ID (0x7UL<<24) 10436 #define HC_VIS_1_INT_B (1UL<<27) 10437 10438 u32_t hc_debug_vect_peek; 10439 #define HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) 10440 #define HC_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) 10441 #define HC_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) 10442 #define HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) 10443 #define HC_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) 10444 #define HC_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) 10445 10446 u32_t hc_coalesce_now; 10447 #define HC_COALESCE_NOW_COAL_NOW (0x1ffUL<<1) 10448 #define HC_COALESCE_NOW_COAL_NOW_WO_INT (0x1ffUL<<11) 10449 #define HC_COALESCE_NOW_COAL_ON_NXT_EVENT (0x1ffUL<<21) 10450 10451 u32_t hc_msix_bit_vector; 10452 #define HC_MSIX_BIT_VECTOR_VAL (0x1ffUL<<0) 10453 10454 u32_t unused_1[57]; 10455 u32_t hc_sb_config_1; 10456 #define HC_SB_CONFIG_1_RX_TMR_MODE (1UL<<1) 10457 #define HC_SB_CONFIG_1_TX_TMR_MODE (1UL<<2) 10458 #define HC_SB_CONFIG_1_COM_TMR_MODE (1UL<<3) 10459 #define HC_SB_CONFIG_1_CMD_TMR_MODE (1UL<<4) 10460 #define HC_SB_CONFIG_1_PER_MODE (1UL<<16) 10461 #define HC_SB_CONFIG_1_ONE_SHOT (1UL<<17) 10462 #define HC_SB_CONFIG_1_USE_INT_PARAM (1UL<<18) 10463 #define HC_SB_CONFIG_1_PER_COLLECT_LIMIT (0xfUL<<20) 10464 10465 u32_t hc_tx_quick_cons_trip_1; 10466 #define HC_TX_QUICK_CONS_TRIP_1_VALUE (0xffUL<<0) 10467 #define HC_TX_QUICK_CONS_TRIP_1_INT (0xffUL<<16) 10468 10469 u32_t hc_comp_prod_trip_1; 10470 #define HC_COMP_PROD_TRIP_1_VALUE (0xffUL<<0) 10471 #define HC_COMP_PROD_TRIP_1_INT (0xffUL<<16) 10472 10473 u32_t hc_rx_quick_cons_trip_1; 10474 #define HC_RX_QUICK_CONS_TRIP_1_VALUE (0xffUL<<0) 10475 #define HC_RX_QUICK_CONS_TRIP_1_INT (0xffUL<<16) 10476 10477 u32_t hc_rx_ticks_1; 10478 #define HC_RX_TICKS_1_VALUE (0x3ffUL<<0) 10479 #define HC_RX_TICKS_1_INT (0x3ffUL<<16) 10480 10481 u32_t hc_tx_ticks_1; 10482 #define HC_TX_TICKS_1_VALUE (0x3ffUL<<0) 10483 #define HC_TX_TICKS_1_INT (0x3ffUL<<16) 10484 10485 u32_t hc_com_ticks_1; 10486 #define HC_COM_TICKS_1_VALUE (0x3ffUL<<0) 10487 #define HC_COM_TICKS_1_INT (0x3ffUL<<16) 10488 10489 u32_t hc_cmd_ticks_1; 10490 #define HC_CMD_TICKS_1_VALUE (0x3ffUL<<0) 10491 #define HC_CMD_TICKS_1_INT (0x3ffUL<<16) 10492 10493 u32_t hc_periodic_ticks_1; 10494 #define HC_PERIODIC_TICKS_1_HC_PERIODIC_TICKS (0xffffUL<<0) 10495 #define HC_PERIODIC_TICKS_1_HC_INT_PERIODIC_TICKS (0xffffUL<<16) 10496 10497 u32_t hc_sb_config_2; 10498 #define HC_SB_CONFIG_2_RX_TMR_MODE (1UL<<1) 10499 #define HC_SB_CONFIG_2_TX_TMR_MODE (1UL<<2) 10500 #define HC_SB_CONFIG_2_COM_TMR_MODE (1UL<<3) 10501 #define HC_SB_CONFIG_2_CMD_TMR_MODE (1UL<<4) 10502 #define HC_SB_CONFIG_2_PER_MODE (1UL<<16) 10503 #define HC_SB_CONFIG_2_ONE_SHOT (1UL<<17) 10504 #define HC_SB_CONFIG_2_USE_INT_PARAM (1UL<<18) 10505 #define HC_SB_CONFIG_2_PER_COLLECT_LIMIT (0xfUL<<20) 10506 10507 u32_t hc_tx_quick_cons_trip_2; 10508 #define HC_TX_QUICK_CONS_TRIP_2_VALUE (0xffUL<<0) 10509 #define HC_TX_QUICK_CONS_TRIP_2_INT (0xffUL<<16) 10510 10511 u32_t hc_comp_prod_trip_2; 10512 #define HC_COMP_PROD_TRIP_2_VALUE (0xffUL<<0) 10513 #define HC_COMP_PROD_TRIP_2_INT (0xffUL<<16) 10514 10515 u32_t hc_rx_quick_cons_trip_2; 10516 #define HC_RX_QUICK_CONS_TRIP_2_VALUE (0xffUL<<0) 10517 #define HC_RX_QUICK_CONS_TRIP_2_INT (0xffUL<<16) 10518 10519 u32_t hc_rx_ticks_2; 10520 #define HC_RX_TICKS_2_VALUE (0x3ffUL<<0) 10521 #define HC_RX_TICKS_2_INT (0x3ffUL<<16) 10522 10523 u32_t hc_tx_ticks_2; 10524 #define HC_TX_TICKS_2_VALUE (0x3ffUL<<0) 10525 #define HC_TX_TICKS_2_INT (0x3ffUL<<16) 10526 10527 u32_t hc_com_ticks_2; 10528 #define HC_COM_TICKS_2_VALUE (0x3ffUL<<0) 10529 #define HC_COM_TICKS_2_INT (0x3ffUL<<16) 10530 10531 u32_t hc_cmd_ticks_2; 10532 #define HC_CMD_TICKS_2_VALUE (0x3ffUL<<0) 10533 #define HC_CMD_TICKS_2_INT (0x3ffUL<<16) 10534 10535 u32_t hc_periodic_ticks_2; 10536 #define HC_PERIODIC_TICKS_2_HC_PERIODIC_TICKS (0xffffUL<<0) 10537 #define HC_PERIODIC_TICKS_2_HC_INT_PERIODIC_TICKS (0xffffUL<<16) 10538 10539 u32_t hc_sb_config_3; 10540 #define HC_SB_CONFIG_3_RX_TMR_MODE (1UL<<1) 10541 #define HC_SB_CONFIG_3_TX_TMR_MODE (1UL<<2) 10542 #define HC_SB_CONFIG_3_COM_TMR_MODE (1UL<<3) 10543 #define HC_SB_CONFIG_3_CMD_TMR_MODE (1UL<<4) 10544 #define HC_SB_CONFIG_3_PER_MODE (1UL<<16) 10545 #define HC_SB_CONFIG_3_ONE_SHOT (1UL<<17) 10546 #define HC_SB_CONFIG_3_USE_INT_PARAM (1UL<<18) 10547 #define HC_SB_CONFIG_3_PER_COLLECT_LIMIT (0xfUL<<20) 10548 10549 u32_t hc_tx_quick_cons_trip_3; 10550 #define HC_TX_QUICK_CONS_TRIP_3_VALUE (0xffUL<<0) 10551 #define HC_TX_QUICK_CONS_TRIP_3_INT (0xffUL<<16) 10552 10553 u32_t hc_comp_prod_trip_3; 10554 #define HC_COMP_PROD_TRIP_3_VALUE (0xffUL<<0) 10555 #define HC_COMP_PROD_TRIP_3_INT (0xffUL<<16) 10556 10557 u32_t hc_rx_quick_cons_trip_3; 10558 #define HC_RX_QUICK_CONS_TRIP_3_VALUE (0xffUL<<0) 10559 #define HC_RX_QUICK_CONS_TRIP_3_INT (0xffUL<<16) 10560 10561 u32_t hc_rx_ticks_3; 10562 #define HC_RX_TICKS_3_VALUE (0x3ffUL<<0) 10563 #define HC_RX_TICKS_3_INT (0x3ffUL<<16) 10564 10565 u32_t hc_tx_ticks_3; 10566 #define HC_TX_TICKS_3_VALUE (0x3ffUL<<0) 10567 #define HC_TX_TICKS_3_INT (0x3ffUL<<16) 10568 10569 u32_t hc_com_ticks_3; 10570 #define HC_COM_TICKS_3_VALUE (0x3ffUL<<0) 10571 #define HC_COM_TICKS_3_INT (0x3ffUL<<16) 10572 10573 u32_t hc_cmd_ticks_3; 10574 #define HC_CMD_TICKS_3_VALUE (0x3ffUL<<0) 10575 #define HC_CMD_TICKS_3_INT (0x3ffUL<<16) 10576 10577 u32_t hc_periodic_ticks_3; 10578 #define HC_PERIODIC_TICKS_3_HC_PERIODIC_TICKS (0xffffUL<<0) 10579 #define HC_PERIODIC_TICKS_3_HC_INT_PERIODIC_TICKS (0xffffUL<<16) 10580 10581 u32_t hc_sb_config_4; 10582 #define HC_SB_CONFIG_4_RX_TMR_MODE (1UL<<1) 10583 #define HC_SB_CONFIG_4_TX_TMR_MODE (1UL<<2) 10584 #define HC_SB_CONFIG_4_COM_TMR_MODE (1UL<<3) 10585 #define HC_SB_CONFIG_4_CMD_TMR_MODE (1UL<<4) 10586 #define HC_SB_CONFIG_4_PER_MODE (1UL<<16) 10587 #define HC_SB_CONFIG_4_ONE_SHOT (1UL<<17) 10588 #define HC_SB_CONFIG_4_USE_INT_PARAM (1UL<<18) 10589 #define HC_SB_CONFIG_4_PER_COLLECT_LIMIT (0xfUL<<20) 10590 10591 u32_t hc_tx_quick_cons_trip_4; 10592 #define HC_TX_QUICK_CONS_TRIP_4_VALUE (0xffUL<<0) 10593 #define HC_TX_QUICK_CONS_TRIP_4_INT (0xffUL<<16) 10594 10595 u32_t hc_comp_prod_trip_4; 10596 #define HC_COMP_PROD_TRIP_4_VALUE (0xffUL<<0) 10597 #define HC_COMP_PROD_TRIP_4_INT (0xffUL<<16) 10598 10599 u32_t hc_rx_quick_cons_trip_4; 10600 #define HC_RX_QUICK_CONS_TRIP_4_VALUE (0xffUL<<0) 10601 #define HC_RX_QUICK_CONS_TRIP_4_INT (0xffUL<<16) 10602 10603 u32_t hc_rx_ticks_4; 10604 #define HC_RX_TICKS_4_VALUE (0x3ffUL<<0) 10605 #define HC_RX_TICKS_4_INT (0x3ffUL<<16) 10606 10607 u32_t hc_tx_ticks_4; 10608 #define HC_TX_TICKS_4_VALUE (0x3ffUL<<0) 10609 #define HC_TX_TICKS_4_INT (0x3ffUL<<16) 10610 10611 u32_t hc_com_ticks_4; 10612 #define HC_COM_TICKS_4_VALUE (0x3ffUL<<0) 10613 #define HC_COM_TICKS_4_INT (0x3ffUL<<16) 10614 10615 u32_t hc_cmd_ticks_4; 10616 #define HC_CMD_TICKS_4_VALUE (0x3ffUL<<0) 10617 #define HC_CMD_TICKS_4_INT (0x3ffUL<<16) 10618 10619 u32_t hc_periodic_ticks_4; 10620 #define HC_PERIODIC_TICKS_4_HC_PERIODIC_TICKS (0xffffUL<<0) 10621 #define HC_PERIODIC_TICKS_4_HC_INT_PERIODIC_TICKS (0xffffUL<<16) 10622 10623 u32_t hc_sb_config_5; 10624 #define HC_SB_CONFIG_5_RX_TMR_MODE (1UL<<1) 10625 #define HC_SB_CONFIG_5_TX_TMR_MODE (1UL<<2) 10626 #define HC_SB_CONFIG_5_COM_TMR_MODE (1UL<<3) 10627 #define HC_SB_CONFIG_5_CMD_TMR_MODE (1UL<<4) 10628 #define HC_SB_CONFIG_5_PER_MODE (1UL<<16) 10629 #define HC_SB_CONFIG_5_ONE_SHOT (1UL<<17) 10630 #define HC_SB_CONFIG_5_USE_INT_PARAM (1UL<<18) 10631 #define HC_SB_CONFIG_5_PER_COLLECT_LIMIT (0xfUL<<20) 10632 10633 u32_t hc_tx_quick_cons_trip_5; 10634 #define HC_TX_QUICK_CONS_TRIP_5_VALUE (0xffUL<<0) 10635 #define HC_TX_QUICK_CONS_TRIP_5_INT (0xffUL<<16) 10636 10637 u32_t hc_comp_prod_trip_5; 10638 #define HC_COMP_PROD_TRIP_5_VALUE (0xffUL<<0) 10639 #define HC_COMP_PROD_TRIP_5_INT (0xffUL<<16) 10640 10641 u32_t hc_rx_quick_cons_trip_5; 10642 #define HC_RX_QUICK_CONS_TRIP_5_VALUE (0xffUL<<0) 10643 #define HC_RX_QUICK_CONS_TRIP_5_INT (0xffUL<<16) 10644 10645 u32_t hc_rx_ticks_5; 10646 #define HC_RX_TICKS_5_VALUE (0x3ffUL<<0) 10647 #define HC_RX_TICKS_5_INT (0x3ffUL<<16) 10648 10649 u32_t hc_tx_ticks_5; 10650 #define HC_TX_TICKS_5_VALUE (0x3ffUL<<0) 10651 #define HC_TX_TICKS_5_INT (0x3ffUL<<16) 10652 10653 u32_t hc_com_ticks_5; 10654 #define HC_COM_TICKS_5_VALUE (0x3ffUL<<0) 10655 #define HC_COM_TICKS_5_INT (0x3ffUL<<16) 10656 10657 u32_t hc_cmd_ticks_5; 10658 #define HC_CMD_TICKS_5_VALUE (0x3ffUL<<0) 10659 #define HC_CMD_TICKS_5_INT (0x3ffUL<<16) 10660 10661 u32_t hc_periodic_ticks_5; 10662 #define HC_PERIODIC_TICKS_5_HC_PERIODIC_TICKS (0xffffUL<<0) 10663 #define HC_PERIODIC_TICKS_5_HC_INT_PERIODIC_TICKS (0xffffUL<<16) 10664 10665 u32_t hc_sb_config_6; 10666 #define HC_SB_CONFIG_6_RX_TMR_MODE (1UL<<1) 10667 #define HC_SB_CONFIG_6_TX_TMR_MODE (1UL<<2) 10668 #define HC_SB_CONFIG_6_COM_TMR_MODE (1UL<<3) 10669 #define HC_SB_CONFIG_6_CMD_TMR_MODE (1UL<<4) 10670 #define HC_SB_CONFIG_6_PER_MODE (1UL<<16) 10671 #define HC_SB_CONFIG_6_ONE_SHOT (1UL<<17) 10672 #define HC_SB_CONFIG_6_USE_INT_PARAM (1UL<<18) 10673 #define HC_SB_CONFIG_6_PER_COLLECT_LIMIT (0xfUL<<20) 10674 10675 u32_t hc_tx_quick_cons_trip_6; 10676 #define HC_TX_QUICK_CONS_TRIP_6_VALUE (0xffUL<<0) 10677 #define HC_TX_QUICK_CONS_TRIP_6_INT (0xffUL<<16) 10678 10679 u32_t hc_comp_prod_trip_6; 10680 #define HC_COMP_PROD_TRIP_6_VALUE (0xffUL<<0) 10681 #define HC_COMP_PROD_TRIP_6_INT (0xffUL<<16) 10682 10683 u32_t hc_rx_quick_cons_trip_6; 10684 #define HC_RX_QUICK_CONS_TRIP_6_VALUE (0xffUL<<0) 10685 #define HC_RX_QUICK_CONS_TRIP_6_INT (0xffUL<<16) 10686 10687 u32_t hc_rx_ticks_6; 10688 #define HC_RX_TICKS_6_VALUE (0x3ffUL<<0) 10689 #define HC_RX_TICKS_6_INT (0x3ffUL<<16) 10690 10691 u32_t hc_tx_ticks_6; 10692 #define HC_TX_TICKS_6_VALUE (0x3ffUL<<0) 10693 #define HC_TX_TICKS_6_INT (0x3ffUL<<16) 10694 10695 u32_t hc_com_ticks_6; 10696 #define HC_COM_TICKS_6_VALUE (0x3ffUL<<0) 10697 #define HC_COM_TICKS_6_INT (0x3ffUL<<16) 10698 10699 u32_t hc_cmd_ticks_6; 10700 #define HC_CMD_TICKS_6_VALUE (0x3ffUL<<0) 10701 #define HC_CMD_TICKS_6_INT (0x3ffUL<<16) 10702 10703 u32_t hc_periodic_ticks_6; 10704 #define HC_PERIODIC_TICKS_6_HC_PERIODIC_TICKS (0xffffUL<<0) 10705 #define HC_PERIODIC_TICKS_6_HC_INT_PERIODIC_TICKS (0xffffUL<<16) 10706 10707 u32_t hc_sb_config_7; 10708 #define HC_SB_CONFIG_7_RX_TMR_MODE (1UL<<1) 10709 #define HC_SB_CONFIG_7_TX_TMR_MODE (1UL<<2) 10710 #define HC_SB_CONFIG_7_COM_TMR_MODE (1UL<<3) 10711 #define HC_SB_CONFIG_7_CMD_TMR_MODE (1UL<<4) 10712 #define HC_SB_CONFIG_7_PER_MODE (1UL<<16) 10713 #define HC_SB_CONFIG_7_ONE_SHOT (1UL<<17) 10714 #define HC_SB_CONFIG_7_USE_INT_PARAM (1UL<<18) 10715 #define HC_SB_CONFIG_7_PER_COLLECT_LIMIT (0xfUL<<20) 10716 10717 u32_t hc_tx_quick_cons_trip_7; 10718 #define HC_TX_QUICK_CONS_TRIP_7_VALUE (0xffUL<<0) 10719 #define HC_TX_QUICK_CONS_TRIP_7_INT (0xffUL<<16) 10720 10721 u32_t hc_comp_prod_trip_7; 10722 #define HC_COMP_PROD_TRIP_7_VALUE (0xffUL<<0) 10723 #define HC_COMP_PROD_TRIP_7_INT (0xffUL<<16) 10724 10725 u32_t hc_rx_quick_cons_trip_7; 10726 #define HC_RX_QUICK_CONS_TRIP_7_VALUE (0xffUL<<0) 10727 #define HC_RX_QUICK_CONS_TRIP_7_INT (0xffUL<<16) 10728 10729 u32_t hc_rx_ticks_7; 10730 #define HC_RX_TICKS_7_VALUE (0x3ffUL<<0) 10731 #define HC_RX_TICKS_7_INT (0x3ffUL<<16) 10732 10733 u32_t hc_tx_ticks_7; 10734 #define HC_TX_TICKS_7_VALUE (0x3ffUL<<0) 10735 #define HC_TX_TICKS_7_INT (0x3ffUL<<16) 10736 10737 u32_t hc_com_ticks_7; 10738 #define HC_COM_TICKS_7_VALUE (0x3ffUL<<0) 10739 #define HC_COM_TICKS_7_INT (0x3ffUL<<16) 10740 10741 u32_t hc_cmd_ticks_7; 10742 #define HC_CMD_TICKS_7_VALUE (0x3ffUL<<0) 10743 #define HC_CMD_TICKS_7_INT (0x3ffUL<<16) 10744 10745 u32_t hc_periodic_ticks_7; 10746 #define HC_PERIODIC_TICKS_7_HC_PERIODIC_TICKS (0xffffUL<<0) 10747 #define HC_PERIODIC_TICKS_7_HC_INT_PERIODIC_TICKS (0xffffUL<<16) 10748 10749 u32_t hc_sb_config_8; 10750 #define HC_SB_CONFIG_8_RX_TMR_MODE (1UL<<1) 10751 #define HC_SB_CONFIG_8_TX_TMR_MODE (1UL<<2) 10752 #define HC_SB_CONFIG_8_COM_TMR_MODE (1UL<<3) 10753 #define HC_SB_CONFIG_8_CMD_TMR_MODE (1UL<<4) 10754 #define HC_SB_CONFIG_8_PER_MODE (1UL<<16) 10755 #define HC_SB_CONFIG_8_ONE_SHOT (1UL<<17) 10756 #define HC_SB_CONFIG_8_USE_INT_PARAM (1UL<<18) 10757 #define HC_SB_CONFIG_8_PER_COLLECT_LIMIT (0xfUL<<20) 10758 10759 u32_t hc_tx_quick_cons_trip_8; 10760 #define HC_TX_QUICK_CONS_TRIP_8_VALUE (0xffUL<<0) 10761 #define HC_TX_QUICK_CONS_TRIP_8_INT (0xffUL<<16) 10762 10763 u32_t hc_comp_prod_trip_8; 10764 #define HC_COMP_PROD_TRIP_8_VALUE (0xffUL<<0) 10765 #define HC_COMP_PROD_TRIP_8_INT (0xffUL<<16) 10766 10767 u32_t hc_rx_quick_cons_trip_8; 10768 #define HC_RX_QUICK_CONS_TRIP_8_VALUE (0xffUL<<0) 10769 #define HC_RX_QUICK_CONS_TRIP_8_INT (0xffUL<<16) 10770 10771 u32_t hc_rx_ticks_8; 10772 #define HC_RX_TICKS_8_VALUE (0x3ffUL<<0) 10773 #define HC_RX_TICKS_8_INT (0x3ffUL<<16) 10774 10775 u32_t hc_tx_ticks_8; 10776 #define HC_TX_TICKS_8_VALUE (0x3ffUL<<0) 10777 #define HC_TX_TICKS_8_INT (0x3ffUL<<16) 10778 10779 u32_t hc_com_ticks_8; 10780 #define HC_COM_TICKS_8_VALUE (0x3ffUL<<0) 10781 #define HC_COM_TICKS_8_INT (0x3ffUL<<16) 10782 10783 u32_t hc_cmd_ticks_8; 10784 #define HC_CMD_TICKS_8_VALUE (0x3ffUL<<0) 10785 #define HC_CMD_TICKS_8_INT (0x3ffUL<<16) 10786 10787 u32_t hc_periodic_ticks_8; 10788 #define HC_PERIODIC_TICKS_8_HC_PERIODIC_TICKS (0xffffUL<<0) 10789 #define HC_PERIODIC_TICKS_8_HC_INT_PERIODIC_TICKS (0xffffUL<<16) 10790 10791 u32_t unused_2[56]; 10792 } hc_reg_t; 10793 10794 typedef hc_reg_t host_coalesce_reg_t; 10795 10796 /* 10797 * hc1_reg definition 10798 * offset: 0x310000 10799 */ 10800 typedef struct hc1_reg 10801 { 10802 u32_t hc1_command; 10803 #define HC1_COMMAND_ENABLE (1UL<<0) 10804 #define HC1_COMMAND_COAL_NOW (1UL<<16) 10805 #define HC1_COMMAND_COAL_NOW_WO_INT (1UL<<17) 10806 #define HC1_COMMAND_STATS_NOW (1UL<<18) 10807 #define HC1_COMMAND_FORCE_INT (0x3UL<<19) 10808 #define HC1_COMMAND_FORCE_INT_NULL (0UL<<19) 10809 #define HC1_COMMAND_FORCE_INT_HIGH (1UL<<19) 10810 #define HC1_COMMAND_FORCE_INT_LOW (2UL<<19) 10811 #define HC1_COMMAND_FORCE_INT_FREE (3UL<<19) 10812 #define HC1_COMMAND_CLR_STAT_NOW (1UL<<21) 10813 #define HC1_COMMAND_MAIN_PWR_INT (1UL<<22) 10814 #define HC1_COMMAND_COAL_ON_NEXT_EVENT (1UL<<27) 10815 10816 u32_t hc1_status; 10817 #define HC1_STATUS_PARITY_ERROR_STATE (1UL<<1) 10818 #define HC1_STATUS_CORE_CLK_CNT_STAT (1UL<<17) 10819 #define HC1_STATUS_NUM_STATUS_BLOCKS_STAT (1UL<<18) 10820 #define HC1_STATUS_NUM_INT_GEN_STAT (1UL<<19) 10821 #define HC1_STATUS_NUM_INT_MBOX_WR_STAT (1UL<<20) 10822 #define HC1_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1UL<<23) 10823 #define HC1_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1UL<<24) 10824 #define HC1_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1UL<<25) 10825 10826 u32_t hc1_config; 10827 #define HC1_CONFIG_COLLECT_STATS (1UL<<0) 10828 #define HC1_CONFIG_RX_TMR_MODE (1UL<<1) 10829 #define HC1_CONFIG_TX_TMR_MODE (1UL<<2) 10830 #define HC1_CONFIG_COM_TMR_MODE (1UL<<3) 10831 #define HC1_CONFIG_CMD_TMR_MODE (1UL<<4) 10832 #define HC1_CONFIG_STATISTIC_PRIORITY (1UL<<5) 10833 #define HC1_CONFIG_STATUS_PRIORITY (1UL<<6) 10834 #define HC1_CONFIG_STAT_MEM_ADDR (0xffUL<<8) 10835 #define HC1_CONFIG_PER_MODE (1UL<<16) 10836 #define HC1_CONFIG_ONE_SHOT (1UL<<17) 10837 #define HC1_CONFIG_USE_INT_PARAM (1UL<<18) 10838 #define HC1_CONFIG_SET_MASK_AT_RD (1UL<<19) 10839 #define HC1_CONFIG_PER_COLLECT_LIMIT (0xfUL<<20) 10840 #define HC1_CONFIG_SB_ADDR_INC (0x7UL<<24) 10841 #define HC1_CONFIG_SB_ADDR_INC_64B (0UL<<24) 10842 #define HC1_CONFIG_SB_ADDR_INC_128B (1UL<<24) 10843 #define HC1_CONFIG_SB_ADDR_INC_256B (2UL<<24) 10844 #define HC1_CONFIG_SB_ADDR_INC_512B (3UL<<24) 10845 #define HC1_CONFIG_SB_ADDR_INC_1024B (4UL<<24) 10846 #define HC1_CONFIG_SB_ADDR_INC_2048B (5UL<<24) 10847 #define HC1_CONFIG_SB_ADDR_INC_4096B (6UL<<24) 10848 #define HC1_CONFIG_SB_ADDR_INC_8192B (7UL<<24) 10849 #define HC1_CONFIG_GEN_STAT_AVG_INTR (1UL<<29) 10850 #define HC1_CONFIG_UNMASK_ALL (1UL<<30) 10851 #define HC1_CONFIG_TX_SEL (1UL<<31) 10852 10853 u32_t hc1_attn_bits_enable; 10854 u32_t hc1_status_addr_l; 10855 u32_t hc1_status_addr_h; 10856 u32_t hc1_statistics_addr_l; 10857 u32_t hc1_statistics_addr_h; 10858 u32_t hc1_tx_quick_cons_trip; 10859 #define HC1_TX_QUICK_CONS_TRIP_VALUE (0xffUL<<0) 10860 #define HC1_TX_QUICK_CONS_TRIP_INT (0xffUL<<16) 10861 10862 u32_t hc1_comp_prod_trip; 10863 #define HC1_COMP_PROD_TRIP_VALUE (0xffUL<<0) 10864 #define HC1_COMP_PROD_TRIP_INT (0xffUL<<16) 10865 10866 u32_t hc1_rx_quick_cons_trip; 10867 #define HC1_RX_QUICK_CONS_TRIP_VALUE (0xffUL<<0) 10868 #define HC1_RX_QUICK_CONS_TRIP_INT (0xffUL<<16) 10869 10870 u32_t hc1_rx_ticks; 10871 #define HC1_RX_TICKS_VALUE (0x3ffUL<<0) 10872 #define HC1_RX_TICKS_INT (0x3ffUL<<16) 10873 10874 u32_t hc1_tx_ticks; 10875 #define HC1_TX_TICKS_VALUE (0x3ffUL<<0) 10876 #define HC1_TX_TICKS_INT (0x3ffUL<<16) 10877 10878 u32_t hc1_com_ticks; 10879 #define HC1_COM_TICKS_VALUE (0x3ffUL<<0) 10880 #define HC1_COM_TICKS_INT (0x3ffUL<<16) 10881 10882 u32_t hc1_cmd_ticks; 10883 #define HC1_CMD_TICKS_VALUE (0x3ffUL<<0) 10884 #define HC1_CMD_TICKS_INT (0x3ffUL<<16) 10885 10886 u32_t hc1_periodic_ticks; 10887 #define HC1_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffUL<<0) 10888 #define HC1_PERIODIC_TICKS_HC_INT_PERIODIC_TICKS (0xffffUL<<16) 10889 10890 u32_t hc1_stat_collect_ticks; 10891 #define HC1_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffUL<<4) 10892 10893 u32_t hc1_stats_ticks; 10894 #define HC1_STATS_TICKS_HC_STAT_TICKS (0xffffUL<<8) 10895 10896 u32_t hc1_stats_interrupt_status; 10897 #define HC1_STATS_INTERRUPT_STATUS_SB_STATUS (0x1ffUL<<0) 10898 #define HC1_STATS_INTERRUPT_STATUS_INT_STATUS (0x1ffUL<<16) 10899 10900 u32_t hc1_stat_mem_data; 10901 u32_t hc1_stat_gen_sel_0; 10902 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0 (0xffUL<<0) 10903 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0UL<<0) 10904 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1UL<<0) 10905 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2UL<<0) 10906 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3UL<<0) 10907 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4UL<<0) 10908 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5UL<<0) 10909 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6UL<<0) 10910 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7UL<<0) 10911 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8UL<<0) 10912 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9UL<<0) 10913 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10UL<<0) 10914 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11UL<<0) 10915 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12UL<<0) 10916 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13UL<<0) 10917 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14UL<<0) 10918 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15UL<<0) 10919 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16UL<<0) 10920 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17UL<<0) 10921 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18UL<<0) 10922 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19UL<<0) 10923 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20UL<<0) 10924 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21UL<<0) 10925 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22UL<<0) 10926 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23UL<<0) 10927 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24UL<<0) 10928 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25UL<<0) 10929 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26UL<<0) 10930 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27UL<<0) 10931 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28UL<<0) 10932 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29UL<<0) 10933 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30UL<<0) 10934 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31UL<<0) 10935 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32UL<<0) 10936 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33UL<<0) 10937 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34UL<<0) 10938 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35UL<<0) 10939 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36UL<<0) 10940 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37UL<<0) 10941 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38UL<<0) 10942 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39UL<<0) 10943 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40UL<<0) 10944 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41UL<<0) 10945 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42UL<<0) 10946 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43UL<<0) 10947 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44UL<<0) 10948 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45UL<<0) 10949 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46UL<<0) 10950 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47UL<<0) 10951 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48UL<<0) 10952 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49UL<<0) 10953 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50UL<<0) 10954 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51UL<<0) 10955 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UMP_RX_FRAME_DROP (52UL<<0) 10956 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53UL<<0) 10957 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54UL<<0) 10958 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55UL<<0) 10959 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56UL<<0) 10960 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S0 (57UL<<0) 10961 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S1 (58UL<<0) 10962 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59UL<<0) 10963 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60UL<<0) 10964 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61UL<<0) 10965 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62UL<<0) 10966 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63UL<<0) 10967 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64UL<<0) 10968 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65UL<<0) 10969 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66UL<<0) 10970 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67UL<<0) 10971 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68UL<<0) 10972 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69UL<<0) 10973 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70UL<<0) 10974 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71UL<<0) 10975 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72UL<<0) 10976 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73UL<<0) 10977 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74UL<<0) 10978 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75UL<<0) 10979 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76UL<<0) 10980 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77UL<<0) 10981 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78UL<<0) 10982 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79UL<<0) 10983 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80UL<<0) 10984 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81UL<<0) 10985 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82UL<<0) 10986 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83UL<<0) 10987 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84UL<<0) 10988 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S2 (85UL<<0) 10989 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S3 (86UL<<0) 10990 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S4 (87UL<<0) 10991 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S5 (88UL<<0) 10992 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S6 (89UL<<0) 10993 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S7 (90UL<<0) 10994 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S8 (91UL<<0) 10995 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S9 (92UL<<0) 10996 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S10 (93UL<<0) 10997 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_MQ_IDB_OFLOW (94UL<<0) 10998 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95UL<<0) 10999 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96UL<<0) 11000 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97UL<<0) 11001 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98UL<<0) 11002 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99UL<<0) 11003 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100UL<<0) 11004 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101UL<<0) 11005 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102UL<<0) 11006 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103UL<<0) 11007 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104UL<<0) 11008 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105UL<<0) 11009 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106UL<<0) 11010 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107UL<<0) 11011 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108UL<<0) 11012 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109UL<<0) 11013 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110UL<<0) 11014 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111UL<<0) 11015 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112UL<<0) 11016 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113UL<<0) 11017 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114UL<<0) 11018 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115UL<<0) 11019 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116UL<<0) 11020 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117UL<<0) 11021 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118UL<<0) 11022 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119UL<<0) 11023 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120UL<<0) 11024 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121UL<<0) 11025 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122UL<<0) 11026 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_RD_CNT (123UL<<0) 11027 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_WR_CNT (124UL<<0) 11028 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CTX_HITS (125UL<<0) 11029 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_CTX_MISSES (126UL<<0) 11030 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127UL<<0) 11031 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC1 (128UL<<0) 11032 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC1 (129UL<<0) 11033 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC1 (130UL<<0) 11034 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC1 (131UL<<0) 11035 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC1 (132UL<<0) 11036 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC1 (133UL<<0) 11037 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC2 (134UL<<0) 11038 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC2 (135UL<<0) 11039 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC2 (136UL<<0) 11040 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC2 (137UL<<0) 11041 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC2 (138UL<<0) 11042 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC2 (139UL<<0) 11043 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC3 (140UL<<0) 11044 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC3 (141UL<<0) 11045 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC3 (142UL<<0) 11046 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC3 (143UL<<0) 11047 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC3 (144UL<<0) 11048 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC3 (145UL<<0) 11049 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC4 (146UL<<0) 11050 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC4 (147UL<<0) 11051 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC4 (148UL<<0) 11052 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC4 (149UL<<0) 11053 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC4 (150UL<<0) 11054 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC4 (151UL<<0) 11055 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC5 (152UL<<0) 11056 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC5 (153UL<<0) 11057 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC5 (154UL<<0) 11058 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC5 (155UL<<0) 11059 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC5 (156UL<<0) 11060 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC5 (157UL<<0) 11061 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC6 (158UL<<0) 11062 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC6 (159UL<<0) 11063 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC6 (160UL<<0) 11064 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC6 (161UL<<0) 11065 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC6 (162UL<<0) 11066 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC6 (163UL<<0) 11067 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC7 (164UL<<0) 11068 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC7 (165UL<<0) 11069 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC7 (166UL<<0) 11070 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC7 (167UL<<0) 11071 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC7 (168UL<<0) 11072 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC7 (169UL<<0) 11073 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC8 (170UL<<0) 11074 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC8 (171UL<<0) 11075 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC8 (172UL<<0) 11076 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC8 (173UL<<0) 11077 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC8 (174UL<<0) 11078 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC8 (175UL<<0) 11079 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_CMD_CNT (176UL<<0) 11080 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_SLOT_CNT (177UL<<0) 11081 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT (178UL<<0) 11082 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S15 (179UL<<0) 11083 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S16 (180UL<<0) 11084 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S17 (181UL<<0) 11085 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S18 (182UL<<0) 11086 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S19 (183UL<<0) 11087 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S20 (184UL<<0) 11088 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S21 (185UL<<0) 11089 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S22 (186UL<<0) 11090 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S23 (187UL<<0) 11091 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S24 (188UL<<0) 11092 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S25 (189UL<<0) 11093 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S26 (190UL<<0) 11094 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S27 (191UL<<0) 11095 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S28 (192UL<<0) 11096 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S29 (193UL<<0) 11097 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S30 (194UL<<0) 11098 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S31 (195UL<<0) 11099 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S32 (196UL<<0) 11100 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S33 (197UL<<0) 11101 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S34 (198UL<<0) 11102 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S35 (199UL<<0) 11103 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S36 (200UL<<0) 11104 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S37 (201UL<<0) 11105 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S38 (202UL<<0) 11106 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S39 (203UL<<0) 11107 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S40 (204UL<<0) 11108 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S41 (205UL<<0) 11109 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S42 (206UL<<0) 11110 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S43 (207UL<<0) 11111 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S44 (208UL<<0) 11112 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S45 (209UL<<0) 11113 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S46 (210UL<<0) 11114 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S47 (211UL<<0) 11115 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S48 (212UL<<0) 11116 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S49 (213UL<<0) 11117 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S50 (214UL<<0) 11118 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S51 (215UL<<0) 11119 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S52 (216UL<<0) 11120 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S53 (217UL<<0) 11121 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S54 (218UL<<0) 11122 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S55 (219UL<<0) 11123 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S56 (220UL<<0) 11124 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S57 (221UL<<0) 11125 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S58 (222UL<<0) 11126 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S59 (223UL<<0) 11127 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S60 (224UL<<0) 11128 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S61 (225UL<<0) 11129 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S62 (226UL<<0) 11130 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S63 (227UL<<0) 11131 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S64 (228UL<<0) 11132 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S65 (229UL<<0) 11133 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S66 (230UL<<0) 11134 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S67 (231UL<<0) 11135 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S68 (232UL<<0) 11136 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S69 (233UL<<0) 11137 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S70 (234UL<<0) 11138 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S71 (235UL<<0) 11139 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S72 (236UL<<0) 11140 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S73 (237UL<<0) 11141 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S74 (238UL<<0) 11142 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S75 (239UL<<0) 11143 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S76 (240UL<<0) 11144 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S77 (241UL<<0) 11145 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S78 (242UL<<0) 11146 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S79 (243UL<<0) 11147 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S80 (244UL<<0) 11148 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S81 (245UL<<0) 11149 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S82 (246UL<<0) 11150 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S83 (247UL<<0) 11151 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S84 (248UL<<0) 11152 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S85 (249UL<<0) 11153 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S86 (250UL<<0) 11154 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S87 (251UL<<0) 11155 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S88 (252UL<<0) 11156 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S89 (253UL<<0) 11157 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S90 (254UL<<0) 11158 #define HC1_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S91 (255UL<<0) 11159 #define HC1_STAT_GEN_SEL_0_GEN_SEL_1 (0xffUL<<8) 11160 #define HC1_STAT_GEN_SEL_0_GEN_SEL_2 (0xffUL<<16) 11161 #define HC1_STAT_GEN_SEL_0_GEN_SEL_3 (0xffUL<<24) 11162 11163 u32_t hc1_stat_gen_sel_1; 11164 #define HC1_STAT_GEN_SEL_1_GEN_SEL_4 (0xffUL<<0) 11165 #define HC1_STAT_GEN_SEL_1_GEN_SEL_5 (0xffUL<<8) 11166 #define HC1_STAT_GEN_SEL_1_GEN_SEL_6 (0xffUL<<16) 11167 #define HC1_STAT_GEN_SEL_1_GEN_SEL_7 (0xffUL<<24) 11168 11169 u32_t hc1_stat_gen_sel_2; 11170 #define HC1_STAT_GEN_SEL_2_GEN_SEL_8 (0xffUL<<0) 11171 #define HC1_STAT_GEN_SEL_2_GEN_SEL_9 (0xffUL<<8) 11172 #define HC1_STAT_GEN_SEL_2_GEN_SEL_10 (0xffUL<<16) 11173 #define HC1_STAT_GEN_SEL_2_GEN_SEL_11 (0xffUL<<24) 11174 11175 u32_t hc1_stat_gen_sel_3; 11176 #define HC1_STAT_GEN_SEL_3_GEN_SEL_12 (0xffUL<<0) 11177 #define HC1_STAT_GEN_SEL_3_GEN_SEL_13 (0xffUL<<8) 11178 #define HC1_STAT_GEN_SEL_3_GEN_SEL_14 (0xffUL<<16) 11179 #define HC1_STAT_GEN_SEL_3_GEN_SEL_15 (0xffUL<<24) 11180 11181 u32_t unused_0[10]; 11182 u32_t hc1_stat_gen_stat[16]; 11183 u32_t hc1_stat_gen_stat_ac[16]; 11184 u32_t hc1_vis; 11185 u32_t hc1_vis_1; 11186 u32_t hc1_debug_vect_peek; 11187 #define HC1_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) 11188 #define HC1_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) 11189 #define HC1_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) 11190 #define HC1_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) 11191 #define HC1_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) 11192 #define HC1_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) 11193 11194 u32_t hc1_coalesce_now; 11195 #define HC1_COALESCE_NOW_COAL_NOW (0x1ffUL<<1) 11196 #define HC1_COALESCE_NOW_COAL_NOW_WO_INT (0x1ffUL<<11) 11197 #define HC1_COALESCE_NOW_COAL_ON_NXT_EVENT (0x1ffUL<<21) 11198 11199 u32_t hc1_msix_bit_vector; 11200 #define HC1_MSIX_BIT_VECTOR_VAL (0x1ffUL<<0) 11201 11202 u32_t unused_1[57]; 11203 u32_t hc1_sb_config_1; 11204 #define HC1_SB_CONFIG_1_RX_TMR_MODE (1UL<<1) 11205 #define HC1_SB_CONFIG_1_TX_TMR_MODE (1UL<<2) 11206 #define HC1_SB_CONFIG_1_COM_TMR_MODE (1UL<<3) 11207 #define HC1_SB_CONFIG_1_CMD_TMR_MODE (1UL<<4) 11208 #define HC1_SB_CONFIG_1_PER_MODE (1UL<<16) 11209 #define HC1_SB_CONFIG_1_ONE_SHOT (1UL<<17) 11210 #define HC1_SB_CONFIG_1_USE_INT_PARAM (1UL<<18) 11211 #define HC1_SB_CONFIG_1_PER_COLLECT_LIMIT (0xfUL<<20) 11212 11213 u32_t hc1_tx_quick_cons_trip_1; 11214 #define HC1_TX_QUICK_CONS_TRIP_1_VALUE (0xffUL<<0) 11215 #define HC1_TX_QUICK_CONS_TRIP_1_INT (0xffUL<<16) 11216 11217 u32_t hc1_comp_prod_trip_1; 11218 #define HC1_COMP_PROD_TRIP_1_VALUE (0xffUL<<0) 11219 #define HC1_COMP_PROD_TRIP_1_INT (0xffUL<<16) 11220 11221 u32_t hc1_rx_quick_cons_trip_1; 11222 #define HC1_RX_QUICK_CONS_TRIP_1_VALUE (0xffUL<<0) 11223 #define HC1_RX_QUICK_CONS_TRIP_1_INT (0xffUL<<16) 11224 11225 u32_t hc1_rx_ticks_1; 11226 #define HC1_RX_TICKS_1_VALUE (0x3ffUL<<0) 11227 #define HC1_RX_TICKS_1_INT (0x3ffUL<<16) 11228 11229 u32_t hc1_tx_ticks_1; 11230 #define HC1_TX_TICKS_1_VALUE (0x3ffUL<<0) 11231 #define HC1_TX_TICKS_1_INT (0x3ffUL<<16) 11232 11233 u32_t hc1_com_ticks_1; 11234 #define HC1_COM_TICKS_1_VALUE (0x3ffUL<<0) 11235 #define HC1_COM_TICKS_1_INT (0x3ffUL<<16) 11236 11237 u32_t hc1_cmd_ticks_1; 11238 #define HC1_CMD_TICKS_1_VALUE (0x3ffUL<<0) 11239 #define HC1_CMD_TICKS_1_INT (0x3ffUL<<16) 11240 11241 u32_t hc1_periodic_ticks_1; 11242 #define HC1_PERIODIC_TICKS_1_HC_PERIODIC_TICKS (0xffffUL<<0) 11243 #define HC1_PERIODIC_TICKS_1_HC_INT_PERIODIC_TICKS (0xffffUL<<16) 11244 11245 u32_t hc1_sb_config_2; 11246 #define HC1_SB_CONFIG_2_RX_TMR_MODE (1UL<<1) 11247 #define HC1_SB_CONFIG_2_TX_TMR_MODE (1UL<<2) 11248 #define HC1_SB_CONFIG_2_COM_TMR_MODE (1UL<<3) 11249 #define HC1_SB_CONFIG_2_CMD_TMR_MODE (1UL<<4) 11250 #define HC1_SB_CONFIG_2_PER_MODE (1UL<<16) 11251 #define HC1_SB_CONFIG_2_ONE_SHOT (1UL<<17) 11252 #define HC1_SB_CONFIG_2_USE_INT_PARAM (1UL<<18) 11253 #define HC1_SB_CONFIG_2_PER_COLLECT_LIMIT (0xfUL<<20) 11254 11255 u32_t hc1_tx_quick_cons_trip_2; 11256 #define HC1_TX_QUICK_CONS_TRIP_2_VALUE (0xffUL<<0) 11257 #define HC1_TX_QUICK_CONS_TRIP_2_INT (0xffUL<<16) 11258 11259 u32_t hc1_comp_prod_trip_2; 11260 #define HC1_COMP_PROD_TRIP_2_VALUE (0xffUL<<0) 11261 #define HC1_COMP_PROD_TRIP_2_INT (0xffUL<<16) 11262 11263 u32_t hc1_rx_quick_cons_trip_2; 11264 #define HC1_RX_QUICK_CONS_TRIP_2_VALUE (0xffUL<<0) 11265 #define HC1_RX_QUICK_CONS_TRIP_2_INT (0xffUL<<16) 11266 11267 u32_t hc1_rx_ticks_2; 11268 #define HC1_RX_TICKS_2_VALUE (0x3ffUL<<0) 11269 #define HC1_RX_TICKS_2_INT (0x3ffUL<<16) 11270 11271 u32_t hc1_tx_ticks_2; 11272 #define HC1_TX_TICKS_2_VALUE (0x3ffUL<<0) 11273 #define HC1_TX_TICKS_2_INT (0x3ffUL<<16) 11274 11275 u32_t hc1_com_ticks_2; 11276 #define HC1_COM_TICKS_2_VALUE (0x3ffUL<<0) 11277 #define HC1_COM_TICKS_2_INT (0x3ffUL<<16) 11278 11279 u32_t hc1_cmd_ticks_2; 11280 #define HC1_CMD_TICKS_2_VALUE (0x3ffUL<<0) 11281 #define HC1_CMD_TICKS_2_INT (0x3ffUL<<16) 11282 11283 u32_t hc1_periodic_ticks_2; 11284 #define HC1_PERIODIC_TICKS_2_HC_PERIODIC_TICKS (0xffffUL<<0) 11285 #define HC1_PERIODIC_TICKS_2_HC_INT_PERIODIC_TICKS (0xffffUL<<16) 11286 11287 u32_t hc1_sb_config_3; 11288 #define HC1_SB_CONFIG_3_RX_TMR_MODE (1UL<<1) 11289 #define HC1_SB_CONFIG_3_TX_TMR_MODE (1UL<<2) 11290 #define HC1_SB_CONFIG_3_COM_TMR_MODE (1UL<<3) 11291 #define HC1_SB_CONFIG_3_CMD_TMR_MODE (1UL<<4) 11292 #define HC1_SB_CONFIG_3_PER_MODE (1UL<<16) 11293 #define HC1_SB_CONFIG_3_ONE_SHOT (1UL<<17) 11294 #define HC1_SB_CONFIG_3_USE_INT_PARAM (1UL<<18) 11295 #define HC1_SB_CONFIG_3_PER_COLLECT_LIMIT (0xfUL<<20) 11296 11297 u32_t hc1_tx_quick_cons_trip_3; 11298 #define HC1_TX_QUICK_CONS_TRIP_3_VALUE (0xffUL<<0) 11299 #define HC1_TX_QUICK_CONS_TRIP_3_INT (0xffUL<<16) 11300 11301 u32_t hc1_comp_prod_trip_3; 11302 #define HC1_COMP_PROD_TRIP_3_VALUE (0xffUL<<0) 11303 #define HC1_COMP_PROD_TRIP_3_INT (0xffUL<<16) 11304 11305 u32_t hc1_rx_quick_cons_trip_3; 11306 #define HC1_RX_QUICK_CONS_TRIP_3_VALUE (0xffUL<<0) 11307 #define HC1_RX_QUICK_CONS_TRIP_3_INT (0xffUL<<16) 11308 11309 u32_t hc1_rx_ticks_3; 11310 #define HC1_RX_TICKS_3_VALUE (0x3ffUL<<0) 11311 #define HC1_RX_TICKS_3_INT (0x3ffUL<<16) 11312 11313 u32_t hc1_tx_ticks_3; 11314 #define HC1_TX_TICKS_3_VALUE (0x3ffUL<<0) 11315 #define HC1_TX_TICKS_3_INT (0x3ffUL<<16) 11316 11317 u32_t hc1_com_ticks_3; 11318 #define HC1_COM_TICKS_3_VALUE (0x3ffUL<<0) 11319 #define HC1_COM_TICKS_3_INT (0x3ffUL<<16) 11320 11321 u32_t hc1_cmd_ticks_3; 11322 #define HC1_CMD_TICKS_3_VALUE (0x3ffUL<<0) 11323 #define HC1_CMD_TICKS_3_INT (0x3ffUL<<16) 11324 11325 u32_t hc1_periodic_ticks_3; 11326 #define HC1_PERIODIC_TICKS_3_HC_PERIODIC_TICKS (0xffffUL<<0) 11327 #define HC1_PERIODIC_TICKS_3_HC_INT_PERIODIC_TICKS (0xffffUL<<16) 11328 11329 u32_t hc1_sb_config_4; 11330 #define HC1_SB_CONFIG_4_RX_TMR_MODE (1UL<<1) 11331 #define HC1_SB_CONFIG_4_TX_TMR_MODE (1UL<<2) 11332 #define HC1_SB_CONFIG_4_COM_TMR_MODE (1UL<<3) 11333 #define HC1_SB_CONFIG_4_CMD_TMR_MODE (1UL<<4) 11334 #define HC1_SB_CONFIG_4_PER_MODE (1UL<<16) 11335 #define HC1_SB_CONFIG_4_ONE_SHOT (1UL<<17) 11336 #define HC1_SB_CONFIG_4_USE_INT_PARAM (1UL<<18) 11337 #define HC1_SB_CONFIG_4_PER_COLLECT_LIMIT (0xfUL<<20) 11338 11339 u32_t hc1_tx_quick_cons_trip_4; 11340 #define HC1_TX_QUICK_CONS_TRIP_4_VALUE (0xffUL<<0) 11341 #define HC1_TX_QUICK_CONS_TRIP_4_INT (0xffUL<<16) 11342 11343 u32_t hc1_comp_prod_trip_4; 11344 #define HC1_COMP_PROD_TRIP_4_VALUE (0xffUL<<0) 11345 #define HC1_COMP_PROD_TRIP_4_INT (0xffUL<<16) 11346 11347 u32_t hc1_rx_quick_cons_trip_4; 11348 #define HC1_RX_QUICK_CONS_TRIP_4_VALUE (0xffUL<<0) 11349 #define HC1_RX_QUICK_CONS_TRIP_4_INT (0xffUL<<16) 11350 11351 u32_t hc1_rx_ticks_4; 11352 #define HC1_RX_TICKS_4_VALUE (0x3ffUL<<0) 11353 #define HC1_RX_TICKS_4_INT (0x3ffUL<<16) 11354 11355 u32_t hc1_tx_ticks_4; 11356 #define HC1_TX_TICKS_4_VALUE (0x3ffUL<<0) 11357 #define HC1_TX_TICKS_4_INT (0x3ffUL<<16) 11358 11359 u32_t hc1_com_ticks_4; 11360 #define HC1_COM_TICKS_4_VALUE (0x3ffUL<<0) 11361 #define HC1_COM_TICKS_4_INT (0x3ffUL<<16) 11362 11363 u32_t hc1_cmd_ticks_4; 11364 #define HC1_CMD_TICKS_4_VALUE (0x3ffUL<<0) 11365 #define HC1_CMD_TICKS_4_INT (0x3ffUL<<16) 11366 11367 u32_t hc1_periodic_ticks_4; 11368 #define HC1_PERIODIC_TICKS_4_HC_PERIODIC_TICKS (0xffffUL<<0) 11369 #define HC1_PERIODIC_TICKS_4_HC_INT_PERIODIC_TICKS (0xffffUL<<16) 11370 11371 u32_t hc1_sb_config_5; 11372 #define HC1_SB_CONFIG_5_RX_TMR_MODE (1UL<<1) 11373 #define HC1_SB_CONFIG_5_TX_TMR_MODE (1UL<<2) 11374 #define HC1_SB_CONFIG_5_COM_TMR_MODE (1UL<<3) 11375 #define HC1_SB_CONFIG_5_CMD_TMR_MODE (1UL<<4) 11376 #define HC1_SB_CONFIG_5_PER_MODE (1UL<<16) 11377 #define HC1_SB_CONFIG_5_ONE_SHOT (1UL<<17) 11378 #define HC1_SB_CONFIG_5_USE_INT_PARAM (1UL<<18) 11379 #define HC1_SB_CONFIG_5_PER_COLLECT_LIMIT (0xfUL<<20) 11380 11381 u32_t hc1_tx_quick_cons_trip_5; 11382 #define HC1_TX_QUICK_CONS_TRIP_5_VALUE (0xffUL<<0) 11383 #define HC1_TX_QUICK_CONS_TRIP_5_INT (0xffUL<<16) 11384 11385 u32_t hc1_comp_prod_trip_5; 11386 #define HC1_COMP_PROD_TRIP_5_VALUE (0xffUL<<0) 11387 #define HC1_COMP_PROD_TRIP_5_INT (0xffUL<<16) 11388 11389 u32_t hc1_rx_quick_cons_trip_5; 11390 #define HC1_RX_QUICK_CONS_TRIP_5_VALUE (0xffUL<<0) 11391 #define HC1_RX_QUICK_CONS_TRIP_5_INT (0xffUL<<16) 11392 11393 u32_t hc1_rx_ticks_5; 11394 #define HC1_RX_TICKS_5_VALUE (0x3ffUL<<0) 11395 #define HC1_RX_TICKS_5_INT (0x3ffUL<<16) 11396 11397 u32_t hc1_tx_ticks_5; 11398 #define HC1_TX_TICKS_5_VALUE (0x3ffUL<<0) 11399 #define HC1_TX_TICKS_5_INT (0x3ffUL<<16) 11400 11401 u32_t hc1_com_ticks_5; 11402 #define HC1_COM_TICKS_5_VALUE (0x3ffUL<<0) 11403 #define HC1_COM_TICKS_5_INT (0x3ffUL<<16) 11404 11405 u32_t hc1_cmd_ticks_5; 11406 #define HC1_CMD_TICKS_5_VALUE (0x3ffUL<<0) 11407 #define HC1_CMD_TICKS_5_INT (0x3ffUL<<16) 11408 11409 u32_t hc1_periodic_ticks_5; 11410 #define HC1_PERIODIC_TICKS_5_HC_PERIODIC_TICKS (0xffffUL<<0) 11411 #define HC1_PERIODIC_TICKS_5_HC_INT_PERIODIC_TICKS (0xffffUL<<16) 11412 11413 u32_t hc1_sb_config_6; 11414 #define HC1_SB_CONFIG_6_RX_TMR_MODE (1UL<<1) 11415 #define HC1_SB_CONFIG_6_TX_TMR_MODE (1UL<<2) 11416 #define HC1_SB_CONFIG_6_COM_TMR_MODE (1UL<<3) 11417 #define HC1_SB_CONFIG_6_CMD_TMR_MODE (1UL<<4) 11418 #define HC1_SB_CONFIG_6_PER_MODE (1UL<<16) 11419 #define HC1_SB_CONFIG_6_ONE_SHOT (1UL<<17) 11420 #define HC1_SB_CONFIG_6_USE_INT_PARAM (1UL<<18) 11421 #define HC1_SB_CONFIG_6_PER_COLLECT_LIMIT (0xfUL<<20) 11422 11423 u32_t hc1_tx_quick_cons_trip_6; 11424 #define HC1_TX_QUICK_CONS_TRIP_6_VALUE (0xffUL<<0) 11425 #define HC1_TX_QUICK_CONS_TRIP_6_INT (0xffUL<<16) 11426 11427 u32_t hc1_comp_prod_trip_6; 11428 #define HC1_COMP_PROD_TRIP_6_VALUE (0xffUL<<0) 11429 #define HC1_COMP_PROD_TRIP_6_INT (0xffUL<<16) 11430 11431 u32_t hc1_rx_quick_cons_trip_6; 11432 #define HC1_RX_QUICK_CONS_TRIP_6_VALUE (0xffUL<<0) 11433 #define HC1_RX_QUICK_CONS_TRIP_6_INT (0xffUL<<16) 11434 11435 u32_t hc1_rx_ticks_6; 11436 #define HC1_RX_TICKS_6_VALUE (0x3ffUL<<0) 11437 #define HC1_RX_TICKS_6_INT (0x3ffUL<<16) 11438 11439 u32_t hc1_tx_ticks_6; 11440 #define HC1_TX_TICKS_6_VALUE (0x3ffUL<<0) 11441 #define HC1_TX_TICKS_6_INT (0x3ffUL<<16) 11442 11443 u32_t hc1_com_ticks_6; 11444 #define HC1_COM_TICKS_6_VALUE (0x3ffUL<<0) 11445 #define HC1_COM_TICKS_6_INT (0x3ffUL<<16) 11446 11447 u32_t hc1_cmd_ticks_6; 11448 #define HC1_CMD_TICKS_6_VALUE (0x3ffUL<<0) 11449 #define HC1_CMD_TICKS_6_INT (0x3ffUL<<16) 11450 11451 u32_t hc1_periodic_ticks_6; 11452 #define HC1_PERIODIC_TICKS_6_HC_PERIODIC_TICKS (0xffffUL<<0) 11453 #define HC1_PERIODIC_TICKS_6_HC_INT_PERIODIC_TICKS (0xffffUL<<16) 11454 11455 u32_t hc1_sb_config_7; 11456 #define HC1_SB_CONFIG_7_RX_TMR_MODE (1UL<<1) 11457 #define HC1_SB_CONFIG_7_TX_TMR_MODE (1UL<<2) 11458 #define HC1_SB_CONFIG_7_COM_TMR_MODE (1UL<<3) 11459 #define HC1_SB_CONFIG_7_CMD_TMR_MODE (1UL<<4) 11460 #define HC1_SB_CONFIG_7_PER_MODE (1UL<<16) 11461 #define HC1_SB_CONFIG_7_ONE_SHOT (1UL<<17) 11462 #define HC1_SB_CONFIG_7_USE_INT_PARAM (1UL<<18) 11463 #define HC1_SB_CONFIG_7_PER_COLLECT_LIMIT (0xfUL<<20) 11464 11465 u32_t hc1_tx_quick_cons_trip_7; 11466 #define HC1_TX_QUICK_CONS_TRIP_7_VALUE (0xffUL<<0) 11467 #define HC1_TX_QUICK_CONS_TRIP_7_INT (0xffUL<<16) 11468 11469 u32_t hc1_comp_prod_trip_7; 11470 #define HC1_COMP_PROD_TRIP_7_VALUE (0xffUL<<0) 11471 #define HC1_COMP_PROD_TRIP_7_INT (0xffUL<<16) 11472 11473 u32_t hc1_rx_quick_cons_trip_7; 11474 #define HC1_RX_QUICK_CONS_TRIP_7_VALUE (0xffUL<<0) 11475 #define HC1_RX_QUICK_CONS_TRIP_7_INT (0xffUL<<16) 11476 11477 u32_t hc1_rx_ticks_7; 11478 #define HC1_RX_TICKS_7_VALUE (0x3ffUL<<0) 11479 #define HC1_RX_TICKS_7_INT (0x3ffUL<<16) 11480 11481 u32_t hc1_tx_ticks_7; 11482 #define HC1_TX_TICKS_7_VALUE (0x3ffUL<<0) 11483 #define HC1_TX_TICKS_7_INT (0x3ffUL<<16) 11484 11485 u32_t hc1_com_ticks_7; 11486 #define HC1_COM_TICKS_7_VALUE (0x3ffUL<<0) 11487 #define HC1_COM_TICKS_7_INT (0x3ffUL<<16) 11488 11489 u32_t hc1_cmd_ticks_7; 11490 #define HC1_CMD_TICKS_7_VALUE (0x3ffUL<<0) 11491 #define HC1_CMD_TICKS_7_INT (0x3ffUL<<16) 11492 11493 u32_t hc1_periodic_ticks_7; 11494 #define HC1_PERIODIC_TICKS_7_HC_PERIODIC_TICKS (0xffffUL<<0) 11495 #define HC1_PERIODIC_TICKS_7_HC_INT_PERIODIC_TICKS (0xffffUL<<16) 11496 11497 u32_t hc1_sb_config_8; 11498 #define HC1_SB_CONFIG_8_RX_TMR_MODE (1UL<<1) 11499 #define HC1_SB_CONFIG_8_TX_TMR_MODE (1UL<<2) 11500 #define HC1_SB_CONFIG_8_COM_TMR_MODE (1UL<<3) 11501 #define HC1_SB_CONFIG_8_CMD_TMR_MODE (1UL<<4) 11502 #define HC1_SB_CONFIG_8_PER_MODE (1UL<<16) 11503 #define HC1_SB_CONFIG_8_ONE_SHOT (1UL<<17) 11504 #define HC1_SB_CONFIG_8_USE_INT_PARAM (1UL<<18) 11505 #define HC1_SB_CONFIG_8_PER_COLLECT_LIMIT (0xfUL<<20) 11506 11507 u32_t hc1_tx_quick_cons_trip_8; 11508 #define HC1_TX_QUICK_CONS_TRIP_8_VALUE (0xffUL<<0) 11509 #define HC1_TX_QUICK_CONS_TRIP_8_INT (0xffUL<<16) 11510 11511 u32_t hc1_comp_prod_trip_8; 11512 #define HC1_COMP_PROD_TRIP_8_VALUE (0xffUL<<0) 11513 #define HC1_COMP_PROD_TRIP_8_INT (0xffUL<<16) 11514 11515 u32_t hc1_rx_quick_cons_trip_8; 11516 #define HC1_RX_QUICK_CONS_TRIP_8_VALUE (0xffUL<<0) 11517 #define HC1_RX_QUICK_CONS_TRIP_8_INT (0xffUL<<16) 11518 11519 u32_t hc1_rx_ticks_8; 11520 #define HC1_RX_TICKS_8_VALUE (0x3ffUL<<0) 11521 #define HC1_RX_TICKS_8_INT (0x3ffUL<<16) 11522 11523 u32_t hc1_tx_ticks_8; 11524 #define HC1_TX_TICKS_8_VALUE (0x3ffUL<<0) 11525 #define HC1_TX_TICKS_8_INT (0x3ffUL<<16) 11526 11527 u32_t hc1_com_ticks_8; 11528 #define HC1_COM_TICKS_8_VALUE (0x3ffUL<<0) 11529 #define HC1_COM_TICKS_8_INT (0x3ffUL<<16) 11530 11531 u32_t hc1_cmd_ticks_8; 11532 #define HC1_CMD_TICKS_8_VALUE (0x3ffUL<<0) 11533 #define HC1_CMD_TICKS_8_INT (0x3ffUL<<16) 11534 11535 u32_t hc1_periodic_ticks_8; 11536 #define HC1_PERIODIC_TICKS_8_HC_PERIODIC_TICKS (0xffffUL<<0) 11537 #define HC1_PERIODIC_TICKS_8_HC_INT_PERIODIC_TICKS (0xffffUL<<16) 11538 11539 u32_t unused_2[7992]; 11540 u32_t hc1_msix_vector0_addr_l; 11541 #define HC1_MSIX_VECTOR0_ADDR_L_MSG_ADDR_LOW (0x3fffffffUL<<2) 11542 11543 u32_t hc1_msix_vector0_addr_h; 11544 #define HC1_MSIX_VECTOR0_ADDR_H_MSG_ADDR_HIGH (0xffffffffUL<<0) 11545 11546 u32_t hc1_msix_vector0_data; 11547 #define HC1_MSIX_VECTOR0_DATA_MSG_DATA (0xffffffffUL<<0) 11548 11549 u32_t hc1_msix_vector0_mask; 11550 #define HC1_MSIX_VECTOR0_MASK_MSG_MASK (1UL<<0) 11551 11552 u32_t hc1_msix_vector1_addr_l; 11553 #define HC1_MSIX_VECTOR1_ADDR_L_MSG_ADDR_LOW (0x3fffffffUL<<2) 11554 11555 u32_t hc1_msix_vector1_addr_h; 11556 #define HC1_MSIX_VECTOR1_ADDR_H_MSG_ADDR_HIGH (0xffffffffUL<<0) 11557 11558 u32_t hc1_msix_vector1_data; 11559 #define HC1_MSIX_VECTOR1_DATA_MSG_DATA (0xffffffffUL<<0) 11560 11561 u32_t hc1_msix_vector1_mask; 11562 #define HC1_MSIX_VECTOR1_MASK_MSG_MASK (1UL<<0) 11563 11564 u32_t hc1_msix_vector2_addr_l; 11565 #define HC1_MSIX_VECTOR2_ADDR_L_MSG_ADDR_LOW (0x3fffffffUL<<2) 11566 11567 u32_t hc1_msix_vector2_addr_h; 11568 #define HC1_MSIX_VECTOR2_ADDR_H_MSG_ADDR_HIGH (0xffffffffUL<<0) 11569 11570 u32_t hc1_msix_vector2_data; 11571 #define HC1_MSIX_VECTOR2_DATA_MSG_DATA (0xffffffffUL<<0) 11572 11573 u32_t hc1_msix_vector2_mask; 11574 #define HC1_MSIX_VECTOR2_MASK_MSG_MASK (1UL<<0) 11575 11576 u32_t hc1_msix_vector3_addr_l; 11577 #define HC1_MSIX_VECTOR3_ADDR_L_MSG_ADDR_LOW (0x3fffffffUL<<2) 11578 11579 u32_t hc1_msix_vector3_addr_h; 11580 #define HC1_MSIX_VECTOR3_ADDR_H_MSG_ADDR_HIGH (0xffffffffUL<<0) 11581 11582 u32_t hc1_msix_vector3_data; 11583 #define HC1_MSIX_VECTOR3_DATA_MSG_DATA (0xffffffffUL<<0) 11584 11585 u32_t hc1_msix_vector3_mask; 11586 #define HC1_MSIX_VECTOR3_MASK_MSG_MASK (1UL<<0) 11587 11588 u32_t hc1_msix_vector4_addr_l; 11589 #define HC1_MSIX_VECTOR4_ADDR_L_MSG_ADDR_LOW (0x3fffffffUL<<2) 11590 11591 u32_t hc1_msix_vector4_addr_h; 11592 #define HC1_MSIX_VECTOR4_ADDR_H_MSG_ADDR_HIGH (0xffffffffUL<<0) 11593 11594 u32_t hc1_msix_vector4_data; 11595 #define HC1_MSIX_VECTOR4_DATA_MSG_DATA (0xffffffffUL<<0) 11596 11597 u32_t hc1_msix_vector4_mask; 11598 #define HC1_MSIX_VECTOR4_MASK_MSG_MASK (1UL<<0) 11599 11600 u32_t hc1_msix_vector5_addr_l; 11601 #define HC1_MSIX_VECTOR5_ADDR_L_MSG_ADDR_LOW (0x3fffffffUL<<2) 11602 11603 u32_t hc1_msix_vector5_addr_h; 11604 #define HC1_MSIX_VECTOR5_ADDR_H_MSG_ADDR_HIGH (0xffffffffUL<<0) 11605 11606 u32_t hc1_msix_vector5_data; 11607 #define HC1_MSIX_VECTOR5_DATA_MSG_DATA (0xffffffffUL<<0) 11608 11609 u32_t hc1_msix_vector5_mask; 11610 #define HC1_MSIX_VECTOR5_MASK_MSG_MASK (1UL<<0) 11611 11612 u32_t hc1_msix_vector6_addr_l; 11613 #define HC1_MSIX_VECTOR6_ADDR_L_MSG_ADDR_LOW (0x3fffffffUL<<2) 11614 11615 u32_t hc1_msix_vector6_addr_h; 11616 #define HC1_MSIX_VECTOR6_ADDR_H_MSG_ADDR_HIGH (0xffffffffUL<<0) 11617 11618 u32_t hc1_msix_vector6_data; 11619 #define HC1_MSIX_VECTOR6_DATA_MSG_DATA (0xffffffffUL<<0) 11620 11621 u32_t hc1_msix_vector6_mask; 11622 #define HC1_MSIX_VECTOR6_MASK_MSG_MASK (1UL<<0) 11623 11624 u32_t hc1_msix_vector7_addr_l; 11625 #define HC1_MSIX_VECTOR7_ADDR_L_MSG_ADDR_LOW (0x3fffffffUL<<2) 11626 11627 u32_t hc1_msix_vector7_addr_h; 11628 #define HC1_MSIX_VECTOR7_ADDR_H_MSG_ADDR_HIGH (0xffffffffUL<<0) 11629 11630 u32_t hc1_msix_vector7_data; 11631 #define HC1_MSIX_VECTOR7_DATA_MSG_DATA (0xffffffffUL<<0) 11632 11633 u32_t hc1_msix_vector7_mask; 11634 #define HC1_MSIX_VECTOR7_MASK_MSG_MASK (1UL<<0) 11635 11636 u32_t hc1_msix_vector8_addr_l; 11637 #define HC1_MSIX_VECTOR8_ADDR_L_MSG_ADDR_LOW (0x3fffffffUL<<2) 11638 11639 u32_t hc1_msix_vector8_addr_h; 11640 #define HC1_MSIX_VECTOR8_ADDR_H_MSG_ADDR_HIGH (0xffffffffUL<<0) 11641 11642 u32_t hc1_msix_vector8_data; 11643 #define HC1_MSIX_VECTOR8_DATA_MSG_DATA (0xffffffffUL<<0) 11644 11645 u32_t hc1_msix_vector8_mask; 11646 #define HC1_MSIX_VECTOR8_MASK_MSG_MASK (1UL<<0) 11647 11648 u32_t unused_3[4060]; 11649 u32_t hc1_msix_pending_bits; 11650 #define HC1_MSIX_PENDING_BITS_PENDING_BITS (0x1ffUL<<0) 11651 11652 u32_t unused_4[4095]; 11653 } hc1_reg_t; 11654 11655 typedef hc1_reg_t host_coalesce_full_reg_t; 11656 11657 /* 11658 * tx_processor_enqueue definition 11659 * offset: 0000 11660 */ 11661 typedef struct tx_processor_enqueue 11662 { 11663 u32_t tx_processor_enqueue_cid; 11664 #define TX_PROCESSOR_ENQUEUE_CID_VALUE (0x3fffUL<<7) 11665 11666 u32_t tx_processor_enqueue_bseq; 11667 u32_t tx_processor_enqueue_wd2; 11668 #define TX_PROCESSOR_ENQUEUE_FLAGS_FLAGS_QUICK_CID_ENA (1<<24) 11669 #define TX_PROCESSOR_ENQUEUE_FLAGS_FLAGS_QUICK_CID_TE (0x3<<25) 11670 #define TX_PROCESSOR_ENQUEUE_FLAGS_FLAGS_QUICK_CATCHUP_TE (1<<27) 11671 #define TX_PROCESSOR_ENQUEUE_FLAGS_FLAGS_RSVD_XI (1<<25) 11672 #define TX_PROCESSOR_ENQUEUE_FLAGS_FLAGS_BORROWED_XI (1<<26) 11673 #define TX_PROCESSOR_ENQUEUE_FLAGS_FLAGS_BSEQ_INVLD_XI (1<<27) 11674 #define TX_PROCESSOR_ENQUEUE_FLAGS_FLAGS_S_RETRAN (1<<28) 11675 11676 u32_t tx_processor_enqueue_tcp_rcv_nxt; 11677 #define TX_PROCESSOR_ENQUEUE_TCP_RCV_NXT_VALUE (0xffffffffUL<<0) 11678 11679 u32_t tx_processor_enqueue_wd4; 11680 #define TX_PROCESSOR_ENQUEUE_TCMD_FNUM_VALUE (0x3f<<24) 11681 11682 } tx_processor_enqueue_t; 11683 11684 11685 /* 11686 * txp_reg definition 11687 * offset: 0x40000 11688 */ 11689 typedef struct txp_reg 11690 { 11691 u32_t unused_0[5120]; 11692 u32_t txp_cpu_mode; 11693 #define TXP_CPU_MODE_LOCAL_RST (1UL<<0) 11694 #define TXP_CPU_MODE_STEP_ENA (1UL<<1) 11695 #define TXP_CPU_MODE_PAGE_0_DATA_ENA (1UL<<2) 11696 #define TXP_CPU_MODE_PAGE_0_INST_ENA (1UL<<3) 11697 #define TXP_CPU_MODE_MSG_BIT1 (1UL<<6) 11698 #define TXP_CPU_MODE_INTERRUPT_ENA (1UL<<7) 11699 #define TXP_CPU_MODE_SOFT_HALT (1UL<<10) 11700 #define TXP_CPU_MODE_BAD_DATA_HALT_ENA (1UL<<11) 11701 #define TXP_CPU_MODE_BAD_INST_HALT_ENA (1UL<<12) 11702 #define TXP_CPU_MODE_FIO_ABORT_HALT_ENA (1UL<<13) 11703 #define TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1UL<<15) 11704 11705 u32_t txp_cpu_state; 11706 #define TXP_CPU_STATE_BREAKPOINT (1UL<<0) 11707 #define TXP_CPU_STATE_BAD_INST_HALTED (1UL<<2) 11708 #define TXP_CPU_STATE_PAGE_0_DATA_HALTED (1UL<<3) 11709 #define TXP_CPU_STATE_PAGE_0_INST_HALTED (1UL<<4) 11710 #define TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1UL<<5) 11711 #define TXP_CPU_STATE_BAD_PC_HALTED (1UL<<6) 11712 #define TXP_CPU_STATE_ALIGN_HALTED (1UL<<7) 11713 #define TXP_CPU_STATE_FIO_ABORT_HALTED (1UL<<8) 11714 #define TXP_CPU_STATE_SOFT_HALTED (1UL<<10) 11715 #define TXP_CPU_STATE_SPAD_UNDERFLOW (1UL<<11) 11716 #define TXP_CPU_STATE_INTERRRUPT (1UL<<12) 11717 #define TXP_CPU_STATE_DATA_ACCESS_STALL (1UL<<14) 11718 #define TXP_CPU_STATE_INST_FETCH_STALL (1UL<<15) 11719 #define TXP_CPU_STATE_BLOCKED_READ (1UL<<31) 11720 11721 u32_t txp_cpu_event_mask; 11722 #define TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1UL<<0) 11723 #define TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1UL<<2) 11724 #define TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1UL<<3) 11725 #define TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1UL<<4) 11726 #define TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1UL<<5) 11727 #define TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1UL<<6) 11728 #define TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1UL<<7) 11729 #define TXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1UL<<8) 11730 #define TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1UL<<10) 11731 #define TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1UL<<11) 11732 #define TXP_CPU_EVENT_MASK_INTERRUPT_MASK (1UL<<12) 11733 11734 u32_t unused_1[4]; 11735 u32_t txp_cpu_program_counter; 11736 u32_t txp_cpu_instruction; 11737 u32_t txp_cpu_data_access; 11738 u32_t txp_cpu_interrupt_enable; 11739 u32_t txp_cpu_interrupt_vector; 11740 u32_t txp_cpu_interrupt_saved_PC; 11741 u32_t txp_cpu_hw_breakpoint; 11742 #define TXP_CPU_HW_BREAKPOINT_DISABLE (1UL<<0) 11743 #define TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffUL<<2) 11744 11745 u32_t txp_cpu_debug_vect_peek; 11746 #define TXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) 11747 #define TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) 11748 #define TXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) 11749 #define TXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) 11750 #define TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) 11751 #define TXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) 11752 11753 u32_t unused_2[3]; 11754 u32_t txp_cpu_last_branch_addr; 11755 #define TXP_CPU_LAST_BRANCH_ADDR_TYPE (1UL<<1) 11756 #define TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0UL<<1) 11757 #define TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1UL<<1) 11758 #define TXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffUL<<2) 11759 11760 u32_t unused_3[109]; 11761 u32_t txp_cpu_reg_file[32]; 11762 u32_t unused_4[80]; 11763 tx_processor_enqueue_t txp_txpq; 11764 u32_t unused_5[9]; 11765 u32_t txp_ftq_cmd; 11766 #define TXP_FTQ_CMD_OFFSET (0x3ffUL<<0) 11767 #define TXP_FTQ_CMD_WR_TOP (1UL<<10) 11768 #define TXP_FTQ_CMD_WR_TOP_0 (0UL<<10) 11769 #define TXP_FTQ_CMD_WR_TOP_1 (1UL<<10) 11770 #define TXP_FTQ_CMD_SFT_RESET (1UL<<25) 11771 #define TXP_FTQ_CMD_RD_DATA (1UL<<26) 11772 #define TXP_FTQ_CMD_ADD_INTERVEN (1UL<<27) 11773 #define TXP_FTQ_CMD_ADD_DATA (1UL<<28) 11774 #define TXP_FTQ_CMD_INTERVENE_CLR (1UL<<29) 11775 #define TXP_FTQ_CMD_POP (1UL<<30) 11776 #define TXP_FTQ_CMD_BUSY (1UL<<31) 11777 11778 u32_t txp_ftq_ctl; 11779 #define TXP_FTQ_CTL_INTERVENE (1UL<<0) 11780 #define TXP_FTQ_CTL_OVERFLOW (1UL<<1) 11781 #define TXP_FTQ_CTL_FORCE_INTERVENE (1UL<<2) 11782 #define TXP_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) 11783 #define TXP_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) 11784 11785 u32_t unused_6[27392]; 11786 u32_t txp_scratch[8192]; 11787 u32_t unused_7[24576]; 11788 } txp_reg_t; 11789 11790 typedef txp_reg_t tx_processor_reg_t; 11791 11792 /* 11793 * tx_patchup_enqueue definition 11794 * offset: 0000 11795 */ 11796 typedef struct tx_patchup_enqueue 11797 { 11798 u32_t tx_patchup_enqueue_cid; 11799 #define TX_PATCHUP_ENQUEUE_CID_VALUE (0x3fffUL<<7) 11800 11801 u32_t tx_patchup_enqueue_wd1; 11802 #define TX_PATCHUP_ENQUEUE_NBYTES_VALUE (0x3fff<<16) 11803 #define TX_PATCHUP_ENQUEUE_XNUM (0xff<<8) 11804 #define TX_PATCHUP_ENQUEUE_KNUM (0xff<<0) 11805 11806 u32_t tx_patchup_enqueue_flags_flags; 11807 #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_PLUS_TWO (1UL<<0) 11808 #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_TCP_UDP_CKSUM (1UL<<1) 11809 #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_IP_CKSUM (1UL<<2) 11810 #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_INCR_CMD (1UL<<3) 11811 #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_COAL_NOW (1UL<<4) 11812 #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_DONT_GEN_CRC (1UL<<5) 11813 #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_LAST_PKT (1UL<<6) 11814 #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_PKT_FRAG (1UL<<7) 11815 #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_QUICK_CID_ENA (1UL<<9) 11816 #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_QUICK_CID_TE (0x3UL<<10) 11817 #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_RSVD_FUTURE_XI (0x3UL<<10) 11818 #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_L5_PAGE_MODE (1UL<<12) 11819 #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_COMPLETE (1UL<<13) 11820 #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_RETRAN (1UL<<14) 11821 #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_END_PADDING (0xfUL<<16) 11822 #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_USAGE_CNT (1UL<<20) 11823 #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_USAGE_CNT_AUTODECREMENT (0UL<<20) 11824 #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_USAGE_CNT_DONOTDECREMENT (1UL<<20) 11825 #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_BSEQ_INVLD (1UL<<21) 11826 #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_WORK_AROUND (0x3UL<<22) 11827 #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_HOLE_SZ (0x3UL<<25) 11828 #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_HOLE_SZ_4 (0UL<<25) 11829 #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_HOLE_SZ_8 (1UL<<25) 11830 #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_HOLE_SZ_12 (2UL<<25) 11831 #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_HOLE_SZ_16 (3UL<<25) 11832 #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_HOLE0 (1UL<<28) 11833 #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_HOLE1 (1UL<<29) 11834 #define TX_PATCHUP_ENQUEUE_FLAGS_FLAGS_HOLE2 (1UL<<30) 11835 11836 u32_t tx_patchup_enqueue_wd3; 11837 #define TX_PATCHUP_ENQUEUE_RAW_CHKSUM (0xffff<<16) 11838 #define TX_PATCHUP_ENQUEUE_TPAT_BIDX (0xffff<<0) 11839 11840 u32_t tx_patchup_enqueue_wd4; 11841 #define TX_PATCHUP_ENQUEUE_STATUS_CS16_ERR (1<<24) 11842 11843 } tx_patchup_enqueue_t; 11844 11845 11846 /* 11847 * tpat_reg definition 11848 * offset: 0x80000 11849 */ 11850 typedef struct tpat_reg 11851 { 11852 u32_t unused_0[5120]; 11853 u32_t tpat_cpu_mode; 11854 #define TPAT_CPU_MODE_LOCAL_RST (1UL<<0) 11855 #define TPAT_CPU_MODE_STEP_ENA (1UL<<1) 11856 #define TPAT_CPU_MODE_PAGE_0_DATA_ENA (1UL<<2) 11857 #define TPAT_CPU_MODE_PAGE_0_INST_ENA (1UL<<3) 11858 #define TPAT_CPU_MODE_MSG_BIT1 (1UL<<6) 11859 #define TPAT_CPU_MODE_INTERRUPT_ENA (1UL<<7) 11860 #define TPAT_CPU_MODE_SOFT_HALT (1UL<<10) 11861 #define TPAT_CPU_MODE_BAD_DATA_HALT_ENA (1UL<<11) 11862 #define TPAT_CPU_MODE_BAD_INST_HALT_ENA (1UL<<12) 11863 #define TPAT_CPU_MODE_FIO_ABORT_HALT_ENA (1UL<<13) 11864 #define TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1UL<<15) 11865 11866 u32_t tpat_cpu_state; 11867 #define TPAT_CPU_STATE_BREAKPOINT (1UL<<0) 11868 #define TPAT_CPU_STATE_BAD_INST_HALTED (1UL<<2) 11869 #define TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1UL<<3) 11870 #define TPAT_CPU_STATE_PAGE_0_INST_HALTED (1UL<<4) 11871 #define TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1UL<<5) 11872 #define TPAT_CPU_STATE_BAD_PC_HALTED (1UL<<6) 11873 #define TPAT_CPU_STATE_ALIGN_HALTED (1UL<<7) 11874 #define TPAT_CPU_STATE_FIO_ABORT_HALTED (1UL<<8) 11875 #define TPAT_CPU_STATE_SOFT_HALTED (1UL<<10) 11876 #define TPAT_CPU_STATE_SPAD_UNDERFLOW (1UL<<11) 11877 #define TPAT_CPU_STATE_INTERRRUPT (1UL<<12) 11878 #define TPAT_CPU_STATE_DATA_ACCESS_STALL (1UL<<14) 11879 #define TPAT_CPU_STATE_INST_FETCH_STALL (1UL<<15) 11880 #define TPAT_CPU_STATE_BLOCKED_READ (1UL<<31) 11881 11882 u32_t tpat_cpu_event_mask; 11883 #define TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1UL<<0) 11884 #define TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1UL<<2) 11885 #define TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1UL<<3) 11886 #define TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1UL<<4) 11887 #define TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1UL<<5) 11888 #define TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1UL<<6) 11889 #define TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1UL<<7) 11890 #define TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK (1UL<<8) 11891 #define TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK (1UL<<10) 11892 #define TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1UL<<11) 11893 #define TPAT_CPU_EVENT_MASK_INTERRUPT_MASK (1UL<<12) 11894 11895 u32_t unused_1[4]; 11896 u32_t tpat_cpu_program_counter; 11897 u32_t tpat_cpu_instruction; 11898 u32_t tpat_cpu_data_access; 11899 u32_t tpat_cpu_interrupt_enable; 11900 u32_t tpat_cpu_interrupt_vector; 11901 u32_t tpat_cpu_interrupt_saved_PC; 11902 u32_t tpat_cpu_hw_breakpoint; 11903 #define TPAT_CPU_HW_BREAKPOINT_DISABLE (1UL<<0) 11904 #define TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffUL<<2) 11905 11906 u32_t tpat_cpu_debug_vect_peek; 11907 #define TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) 11908 #define TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) 11909 #define TPAT_CPU_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) 11910 #define TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) 11911 #define TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) 11912 #define TPAT_CPU_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) 11913 11914 u32_t unused_2[3]; 11915 u32_t tpat_cpu_last_branch_addr; 11916 #define TPAT_CPU_LAST_BRANCH_ADDR_TYPE (1UL<<1) 11917 #define TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0UL<<1) 11918 #define TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1UL<<1) 11919 #define TPAT_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffUL<<2) 11920 11921 u32_t unused_3[109]; 11922 u32_t tpat_cpu_reg_file[32]; 11923 u32_t unused_4[80]; 11924 tx_patchup_enqueue_t tpat_tpatq; 11925 u32_t unused_5[9]; 11926 u32_t tpat_ftq_cmd; 11927 #define TPAT_FTQ_CMD_OFFSET (0x3ffUL<<0) 11928 #define TPAT_FTQ_CMD_WR_TOP (1UL<<10) 11929 #define TPAT_FTQ_CMD_WR_TOP_0 (0UL<<10) 11930 #define TPAT_FTQ_CMD_WR_TOP_1 (1UL<<10) 11931 #define TPAT_FTQ_CMD_SFT_RESET (1UL<<25) 11932 #define TPAT_FTQ_CMD_RD_DATA (1UL<<26) 11933 #define TPAT_FTQ_CMD_ADD_INTERVEN (1UL<<27) 11934 #define TPAT_FTQ_CMD_ADD_DATA (1UL<<28) 11935 #define TPAT_FTQ_CMD_INTERVENE_CLR (1UL<<29) 11936 #define TPAT_FTQ_CMD_POP (1UL<<30) 11937 #define TPAT_FTQ_CMD_BUSY (1UL<<31) 11938 11939 u32_t tpat_ftq_ctl; 11940 #define TPAT_FTQ_CTL_INTERVENE (1UL<<0) 11941 #define TPAT_FTQ_CTL_OVERFLOW (1UL<<1) 11942 #define TPAT_FTQ_CTL_FORCE_INTERVENE (1UL<<2) 11943 #define TPAT_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) 11944 #define TPAT_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) 11945 11946 u32_t unused_6[27392]; 11947 u32_t tpat_scratch[3072]; 11948 u32_t unused_7[29696]; 11949 } tpat_reg_t; 11950 11951 typedef tpat_reg_t tx_patchup_reg_t; 11952 11953 /* 11954 * rx_processor_cmd_enqueue definition 11955 * offset: 0000 11956 */ 11957 typedef struct rx_processor_cmd_enqueue 11958 { 11959 u32_t rx_processor_cmd_enqueue_cid; 11960 #define RX_PROCESSOR_CMD_ENQUEUE_CID_VALUE (0x3fffUL<<7) 11961 11962 u32_t rx_processor_cmd_enqueue_wd1; 11963 #define RX_PROCESSOR_CMD_ENQUEUE_WORK_ID (0xffff<<16) 11964 #define RX_PROCESSOR_CMD_ENQUEUE_CMD_TYPE (0xffff<<0) 11965 11966 u32_t rx_processor_cmd_enqueue_wd2; 11967 #define RX_PROCESSOR_CMD_ENQUEUE_CMD_STATUS_VALUE (0xfff<<16) 11968 #define RX_PROCESSOR_CMD_ENQUEUE_CMD_STATUS_DRIVER_ID (0xf<<28) 11969 #define RX_PROCESSOR_CMD_ENQUEUE_OPAQUE (0xffff<<0) 11970 11971 u32_t rx_processor_cmd_enqueue_wd3; 11972 #define RX_PROCESSOR_CMD_ENQUEUE_RSVD_FUTURE_VALUE (0x3<<24) 11973 11974 } rx_processor_cmd_enqueue_t; 11975 11976 11977 /* 11978 * rx_processor_enqueue definition 11979 * offset: 0000 11980 */ 11981 typedef struct rx_processor_enqueue 11982 { 11983 u32_t rx_processor_enqueue_bits_errors; 11984 #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_L2_BAD_CRC (1UL<<1) 11985 #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_L2_PHY_DECODE (1UL<<2) 11986 #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_L2_ALIGNMENT (1UL<<3) 11987 #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_L2_TOO_SHORT (1UL<<4) 11988 #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_L2_GIANT_FRAME (1UL<<5) 11989 #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_IP_BAD_LEN (1UL<<6) 11990 #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_IP_TOO_SHORT (1UL<<7) 11991 #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_IP_BAD_VERSION (1UL<<8) 11992 #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_IP_BAD_HLEN (1UL<<9) 11993 #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_IP_BAD_XSUM (1UL<<10) 11994 #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_TCP_TOO_SHORT (1UL<<11) 11995 #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_TCP_BAD_XSUM (1UL<<12) 11996 #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_TCP_BAD_OFFSET (1UL<<13) 11997 #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_TCP_SYNC_PRESENT (1UL<<14) 11998 #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_UDP_BAD_XSUM (1UL<<15) 11999 #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_IP_BAD_ORDER (1UL<<16) 12000 #define RX_PROCESSOR_ENQUEUE_BITS_ERRORS_IP_HDR_MISMATCH (1UL<<18) 12001 12002 u32_t rx_processor_enqueue_bits_status; 12003 #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_RULE_CLASS (0x7UL<<0) 12004 #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_RULE_P2 (1UL<<3) 12005 #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_RULE_P3 (1UL<<4) 12006 #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_RULE_P4 (1UL<<5) 12007 #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_L2_VLAN_TAG (1UL<<6) 12008 #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_L2_LLC_SNAP (1UL<<7) 12009 #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_RSS_HASH (1UL<<8) 12010 #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_SORT_VECT (0xfUL<<9) 12011 #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_IP_DATAGRAM (1UL<<13) 12012 #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_TCP_SEGMENT (1UL<<14) 12013 #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_UDP_DATAGRAM (1UL<<15) 12014 #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_CU_FRAME (1UL<<16) 12015 #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_IP_PROG_EXT (1UL<<17) 12016 #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_IP_TYPE (1UL<<18) 12017 #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_RULE_P1 (1UL<<19) 12018 #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_VALID_TE (1UL<<20) 12019 #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_RLUP_HIT4_XI (1UL<<20) 12020 #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_IP_FRAGMENT (1UL<<21) 12021 #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_IP_OPTIONS_PRESENT (1UL<<22) 12022 #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_TCP_OPTIONS_PRESENT (1UL<<23) 12023 #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_L2_PM_IDX (0xfUL<<24) 12024 #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_L2_PM_HIT (1UL<<28) 12025 #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_L2_MC_HASH_HIT (1UL<<29) 12026 #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_RDMAC_CRC_PASS (1UL<<30) 12027 #define RX_PROCESSOR_ENQUEUE_BITS_STATUS_MP_HIT (1UL<<31) 12028 12029 u32_t rx_processor_enqueue_wd2; 12030 #define RX_PROCESSOR_ENQUEUE_BITS_MULTICAST_HASH_IDX (0xff<<24) 12031 #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_TE (0x7<<16) 12032 #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_0_TE (0<<16) 12033 #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_1_TE (1<<16) 12034 #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_2_TE (2<<16) 12035 #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_3_TE (3<<16) 12036 #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_4_TE (4<<16) 12037 #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_5_TE (5<<16) 12038 #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_6_TE (6<<16) 12039 #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_NONE_TE (7<<16) 12040 #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_XI (0xf<<16) 12041 #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_0_XI (0<<16) 12042 #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_1_XI (1<<16) 12043 #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_2_XI (2<<16) 12044 #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_3_XI (3<<16) 12045 #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_4_XI (4<<16) 12046 #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_5_XI (5<<16) 12047 #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_6_XI (6<<16) 12048 #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_NONE_XI (7<<16) 12049 #define RX_PROCESSOR_ENQUEUE_BITS_ACPI_PAT_ACPI_PAT_8_XI (8<<16) 12050 #define RX_PROCESSOR_ENQUEUE_KNUM (0xff<<8) 12051 12052 u32_t rx_processor_enqueue_wd3; 12053 #define RX_PROCESSOR_ENQUEUE_RULE_TAG (0xffff<<16) 12054 #define RX_PROCESSOR_ENQUEUE_PKT_LEN_VALUE (0x3fff<<0) 12055 12056 u32_t rx_processor_enqueue_wd4; 12057 #define RX_PROCESSOR_ENQUEUE_VLAN_TAG (0xffff<<16) 12058 #define RX_PROCESSOR_ENQUEUE_IP_HDR_OFFSET (0xff<<8) 12059 #define RX_PROCESSOR_ENQUEUE_RX_QID_VALUE (0xf<<0) 12060 12061 u32_t rx_processor_enqueue_wd5; 12062 #define RX_PROCESSOR_ENQUEUE_IP_XSUM (0xffff<<16) 12063 #define RX_PROCESSOR_ENQUEUE_TCP_UDP_HDR_OFFSET (0xffff<<0) 12064 12065 u32_t rx_processor_enqueue_wd6; 12066 #define RX_PROCESSOR_ENQUEUE_TCP_UDP_XSUM (0xffff<<16) 12067 #define RX_PROCESSOR_ENQUEUE_TCP_PAYLOAD_LEN (0xffff<<0) 12068 12069 u32_t rx_processor_enqueue_wd7; 12070 #define RX_PROCESSOR_ENQUEUE_PSEUD_XSUM (0xffff<<16) 12071 #define RX_PROCESSOR_ENQUEUE_L2_PAYLOAD_RAW_XSUM (0xffff<<0) 12072 12073 u32_t rx_processor_enqueue_wd8; 12074 #define RX_PROCESSOR_ENQUEUE_DATA_OFFSET (0xffff<<16) 12075 #define RX_PROCESSOR_ENQUEUE_L3_PAYLOAD_RAW_XSUM (0xffff<<0) 12076 12077 u32_t rx_processor_enqueue_mbuf_cluster; 12078 #define RX_PROCESSOR_ENQUEUE_MBUF_CLUSTER_VALUE (0x1ffffffUL<<0) 12079 12080 u32_t rx_processor_enqueue_cid; 12081 #define RX_PROCESSOR_ENQUEUE_CID_VALUE (0x3fffUL<<7) 12082 12083 u32_t rx_processor_enqueue_wd11; 12084 #define RX_PROCESSOR_ENQUEUE_CS16_VALUE (0xffff<<16) 12085 12086 u32_t rx_processor_enqueue_wd12; 12087 #define RX_PROCESSOR_ENQUEUE_EXT_STATUS_TCP_SYNC_PRESENT (1<<16) 12088 #define RX_PROCESSOR_ENQUEUE_EXT_STATUS_RLUP_HIT2 (1<<17) 12089 #define RX_PROCESSOR_ENQUEUE_EXT_STATUS_TCP_UDP_XSUM_IS_0 (1<<18) 12090 #define RX_PROCESSOR_ENQUEUE_EXT_STATUS_IP_ROUTING_HDR_PRESENT (0x3<<19) 12091 #define RX_PROCESSOR_ENQUEUE_EXT_STATUS_IP_ROUTING_HDR_PRESENT_00 (0<<19) 12092 #define RX_PROCESSOR_ENQUEUE_EXT_STATUS_IP_ROUTING_HDR_PRESENT_01 (1<<19) 12093 #define RX_PROCESSOR_ENQUEUE_EXT_STATUS_IP_ROUTING_HDR_PRESENT_10 (2<<19) 12094 #define RX_PROCESSOR_ENQUEUE_EXT_STATUS_IP_ROUTING_HDR_PRESENT_11 (3<<19) 12095 #define RX_PROCESSOR_ENQUEUE_EXT_STATUS_ACPI_MATCH (1<<21) 12096 12097 } rx_processor_enqueue_t; 12098 12099 12100 /* 12101 * rxp_reg definition 12102 * offset: 0xc0000 12103 */ 12104 typedef struct rxp_reg 12105 { 12106 u32_t unused_0[5120]; 12107 u32_t rxp_cpu_mode; 12108 #define RXP_CPU_MODE_LOCAL_RST (1UL<<0) 12109 #define RXP_CPU_MODE_STEP_ENA (1UL<<1) 12110 #define RXP_CPU_MODE_PAGE_0_DATA_ENA (1UL<<2) 12111 #define RXP_CPU_MODE_PAGE_0_INST_ENA (1UL<<3) 12112 #define RXP_CPU_MODE_MSG_BIT1 (1UL<<6) 12113 #define RXP_CPU_MODE_INTERRUPT_ENA (1UL<<7) 12114 #define RXP_CPU_MODE_SOFT_HALT (1UL<<10) 12115 #define RXP_CPU_MODE_BAD_DATA_HALT_ENA (1UL<<11) 12116 #define RXP_CPU_MODE_BAD_INST_HALT_ENA (1UL<<12) 12117 #define RXP_CPU_MODE_FIO_ABORT_HALT_ENA (1UL<<13) 12118 #define RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1UL<<15) 12119 12120 u32_t rxp_cpu_state; 12121 #define RXP_CPU_STATE_BREAKPOINT (1UL<<0) 12122 #define RXP_CPU_STATE_BAD_INST_HALTED (1UL<<2) 12123 #define RXP_CPU_STATE_PAGE_0_DATA_HALTED (1UL<<3) 12124 #define RXP_CPU_STATE_PAGE_0_INST_HALTED (1UL<<4) 12125 #define RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1UL<<5) 12126 #define RXP_CPU_STATE_BAD_PC_HALTED (1UL<<6) 12127 #define RXP_CPU_STATE_ALIGN_HALTED (1UL<<7) 12128 #define RXP_CPU_STATE_FIO_ABORT_HALTED (1UL<<8) 12129 #define RXP_CPU_STATE_SOFT_HALTED (1UL<<10) 12130 #define RXP_CPU_STATE_SPAD_UNDERFLOW (1UL<<11) 12131 #define RXP_CPU_STATE_INTERRRUPT (1UL<<12) 12132 #define RXP_CPU_STATE_DATA_ACCESS_STALL (1UL<<14) 12133 #define RXP_CPU_STATE_INST_FETCH_STALL (1UL<<15) 12134 #define RXP_CPU_STATE_BLOCKED_READ (1UL<<31) 12135 12136 u32_t rxp_cpu_event_mask; 12137 #define RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1UL<<0) 12138 #define RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1UL<<2) 12139 #define RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1UL<<3) 12140 #define RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1UL<<4) 12141 #define RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1UL<<5) 12142 #define RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1UL<<6) 12143 #define RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1UL<<7) 12144 #define RXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1UL<<8) 12145 #define RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1UL<<10) 12146 #define RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1UL<<11) 12147 #define RXP_CPU_EVENT_MASK_INTERRUPT_MASK (1UL<<12) 12148 12149 u32_t unused_1[4]; 12150 u32_t rxp_cpu_program_counter; 12151 u32_t rxp_cpu_instruction; 12152 u32_t rxp_cpu_data_access; 12153 u32_t rxp_cpu_interrupt_enable; 12154 u32_t rxp_cpu_interrupt_vector; 12155 u32_t rxp_cpu_interrupt_saved_PC; 12156 u32_t rxp_cpu_hw_breakpoint; 12157 #define RXP_CPU_HW_BREAKPOINT_DISABLE (1UL<<0) 12158 #define RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffUL<<2) 12159 12160 u32_t rxp_cpu_debug_vect_peek; 12161 #define RXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) 12162 #define RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) 12163 #define RXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) 12164 #define RXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) 12165 #define RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) 12166 #define RXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) 12167 12168 u32_t unused_2[3]; 12169 u32_t rxp_cpu_last_branch_addr; 12170 #define RXP_CPU_LAST_BRANCH_ADDR_TYPE (1UL<<1) 12171 #define RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0UL<<1) 12172 #define RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1UL<<1) 12173 #define RXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffUL<<2) 12174 12175 u32_t unused_3[109]; 12176 u32_t rxp_cpu_reg_file[32]; 12177 u32_t unused_4[63]; 12178 u32_t rxp_pfe_pfe_ctl; 12179 #define RXP_PFE_PFE_CTL_INC_USAGE_CNT (1UL<<0) 12180 #define RXP_PFE_PFE_CTL_PFE_SIZE (0xfUL<<4) 12181 #define RXP_PFE_PFE_CTL_PFE_SIZE_0 (0UL<<4) 12182 #define RXP_PFE_PFE_CTL_PFE_SIZE_1 (1UL<<4) 12183 #define RXP_PFE_PFE_CTL_PFE_SIZE_2 (2UL<<4) 12184 #define RXP_PFE_PFE_CTL_PFE_SIZE_3 (3UL<<4) 12185 #define RXP_PFE_PFE_CTL_PFE_SIZE_4 (4UL<<4) 12186 #define RXP_PFE_PFE_CTL_PFE_SIZE_5 (5UL<<4) 12187 #define RXP_PFE_PFE_CTL_PFE_SIZE_6 (6UL<<4) 12188 #define RXP_PFE_PFE_CTL_PFE_SIZE_7 (7UL<<4) 12189 #define RXP_PFE_PFE_CTL_PFE_SIZE_8 (8UL<<4) 12190 #define RXP_PFE_PFE_CTL_PFE_SIZE_9 (9UL<<4) 12191 #define RXP_PFE_PFE_CTL_PFE_SIZE_10 (10UL<<4) 12192 #define RXP_PFE_PFE_CTL_PFE_SIZE_11 (11UL<<4) 12193 #define RXP_PFE_PFE_CTL_PFE_SIZE_12 (12UL<<4) 12194 #define RXP_PFE_PFE_CTL_PFE_SIZE_13 (13UL<<4) 12195 #define RXP_PFE_PFE_CTL_PFE_SIZE_14 (14UL<<4) 12196 #define RXP_PFE_PFE_CTL_PFE_SIZE_15 (15UL<<4) 12197 #define RXP_PFE_PFE_CTL_PFE_COUNT (0xfUL<<12) 12198 #define RXP_PFE_PFE_CTL_OFFSET (0x1ffUL<<16) 12199 12200 rx_processor_cmd_enqueue_t rxp_rxpcq; 12201 u32_t unused_5[10]; 12202 u32_t rxp_cftq_cmd; 12203 #define RXP_CFTQ_CMD_OFFSET (0x3ffUL<<0) 12204 #define RXP_CFTQ_CMD_WR_TOP (1UL<<10) 12205 #define RXP_CFTQ_CMD_WR_TOP_0 (0UL<<10) 12206 #define RXP_CFTQ_CMD_WR_TOP_1 (1UL<<10) 12207 #define RXP_CFTQ_CMD_SFT_RESET (1UL<<25) 12208 #define RXP_CFTQ_CMD_RD_DATA (1UL<<26) 12209 #define RXP_CFTQ_CMD_ADD_INTERVEN (1UL<<27) 12210 #define RXP_CFTQ_CMD_ADD_DATA (1UL<<28) 12211 #define RXP_CFTQ_CMD_INTERVENE_CLR (1UL<<29) 12212 #define RXP_CFTQ_CMD_POP (1UL<<30) 12213 #define RXP_CFTQ_CMD_BUSY (1UL<<31) 12214 12215 u32_t rxp_cftq_ctl; 12216 #define RXP_CFTQ_CTL_INTERVENE (1UL<<0) 12217 #define RXP_CFTQ_CTL_OVERFLOW (1UL<<1) 12218 #define RXP_CFTQ_CTL_FORCE_INTERVENE (1UL<<2) 12219 #define RXP_CFTQ_CTL_MAX_DEPTH (0x3ffUL<<12) 12220 #define RXP_CFTQ_CTL_CUR_DEPTH (0x3ffUL<<22) 12221 12222 rx_processor_enqueue_t rxp_rxpq; 12223 u32_t unused_6; 12224 u32_t rxp_ftq_cmd; 12225 #define RXP_FTQ_CMD_OFFSET (0x3ffUL<<0) 12226 #define RXP_FTQ_CMD_WR_TOP (1UL<<10) 12227 #define RXP_FTQ_CMD_WR_TOP_0 (0UL<<10) 12228 #define RXP_FTQ_CMD_WR_TOP_1 (1UL<<10) 12229 #define RXP_FTQ_CMD_SFT_RESET (1UL<<25) 12230 #define RXP_FTQ_CMD_RD_DATA (1UL<<26) 12231 #define RXP_FTQ_CMD_ADD_INTERVEN (1UL<<27) 12232 #define RXP_FTQ_CMD_ADD_DATA (1UL<<28) 12233 #define RXP_FTQ_CMD_INTERVENE_CLR (1UL<<29) 12234 #define RXP_FTQ_CMD_POP (1UL<<30) 12235 #define RXP_FTQ_CMD_BUSY (1UL<<31) 12236 12237 u32_t rxp_ftq_ctl; 12238 #define RXP_FTQ_CTL_INTERVENE (1UL<<0) 12239 #define RXP_FTQ_CTL_OVERFLOW (1UL<<1) 12240 #define RXP_FTQ_CTL_FORCE_INTERVENE (1UL<<2) 12241 #define RXP_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) 12242 #define RXP_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) 12243 12244 u32_t unused_7[27392]; 12245 u32_t rxp_scratch[10240]; 12246 u32_t unused_8[22528]; 12247 } rxp_reg_t; 12248 12249 typedef rxp_reg_t rx_processor_reg_t; 12250 12251 /* 12252 * completion_tx_enqueue definition 12253 * offset: 0000 12254 */ 12255 typedef struct completion_tx_enqueue 12256 { 12257 u32_t completion_tx_enqueue_cid; 12258 #define COMPLETION_TX_ENQUEUE_CID_VALUE (0x3fffUL<<7) 12259 12260 u32_t completion_tx_enqueue_wd1; 12261 #define COMPLETION_TX_ENQUEUE_FLAGS_CMD (0xff<<16) 12262 #define COMPLETION_TX_ENQUEUE_FLAGS_COMPLETE (1<<24) 12263 #define COMPLETION_TX_ENQUEUE_FLAGS_RETRAN (1<<25) 12264 12265 u32_t completion_tx_enqueue_snd_next; 12266 u32_t completion_tx_enqueue_wd3; 12267 #define COMPLETION_TX_ENQUEUE_NEW_FLAGS_USAGE_CNT (1<<24) 12268 #define COMPLETION_TX_ENQUEUE_NEW_FLAGS_USAGE_CNT_AUTODECREMENT (0<<24) 12269 #define COMPLETION_TX_ENQUEUE_NEW_FLAGS_USAGE_CNT_DONOTDECREMENT (1<<24) 12270 #define COMPLETION_TX_ENQUEUE_NEW_FLAGS_BSEQ_INVLD (1<<25) 12271 #define COMPLETION_TX_ENQUEUE_NEW_FLAGS_WORK_AROUND (0x3<<26) 12272 12273 } completion_tx_enqueue_t; 12274 12275 12276 /* 12277 * completion_timeout_enqueue definition 12278 * offset: 0000 12279 */ 12280 typedef struct completion_timeout_enqueue 12281 { 12282 u32_t completion_timeout_enqueue_cid; 12283 #define COMPLETION_TIMEOUT_ENQUEUE_CID_VALUE (0x3fffUL<<7) 12284 12285 u32_t completion_timeout_enqueue_tmr_val; 12286 u32_t completion_timeout_enqueue_wd2; 12287 #define COMPLETION_TIMEOUT_ENQUEUE_TMR_TYPE_TYPE (0x7<<24) 12288 #define COMPLETION_TIMEOUT_ENQUEUE_TMR_TYPE_TYPE_SW (0<<24) 12289 #define COMPLETION_TIMEOUT_ENQUEUE_TMR_TYPE_TYPE_RETRAN (1<<24) 12290 #define COMPLETION_TIMEOUT_ENQUEUE_TMR_TYPE_TYPE_PUSH (2<<24) 12291 #define COMPLETION_TIMEOUT_ENQUEUE_TMR_TYPE_TYPE_DELAY_ACK (3<<24) 12292 #define COMPLETION_TIMEOUT_ENQUEUE_TMR_TYPE_TYPE_KEEP_ALIVE (4<<24) 12293 #define COMPLETION_TIMEOUT_ENQUEUE_TMR_TYPE_TYPE_NAGLE (5<<24) 12294 #define COMPLETION_TIMEOUT_ENQUEUE_TMR_TYPE_EVENT_UNUSED (1<<28) 12295 #define COMPLETION_TIMEOUT_ENQUEUE_RSVD_FUTURE_VALUE (0x3<<16) 12296 12297 } completion_timeout_enqueue_t; 12298 12299 12300 /* 12301 * completion_enqueue definition 12302 * offset: 0000 12303 */ 12304 typedef struct completion_enqueue 12305 { 12306 u32_t completion_enqueue_cid; 12307 #define COMPLETION_ENQUEUE_CID_VALUE (0x3fffUL<<7) 12308 12309 u32_t completion_enqueue_mbuf_cluster; 12310 #define COMPLETION_ENQUEUE_MBUF_CLUSTER_VALUE (0x1ffffffUL<<0) 12311 12312 u32_t completion_enqueue_wd2; 12313 #define COMPLETION_ENQUEUE_OPERAND_FLAGS (0xffff<<16) 12314 #define COMPLETION_ENQUEUE_KNUM (0xff<<8) 12315 #define COMPLETION_ENQUEUE_OPCODE (0xff<<0) 12316 12317 u32_t completion_enqueue_wd3; 12318 #define COMPLETION_ENQUEUE_OPERAND16_2 (0xffff<<16) 12319 #define COMPLETION_ENQUEUE_OPERAND16_3 (0xffff<<0) 12320 12321 u32_t completion_enqueue_wd4; 12322 #define COMPLETION_ENQUEUE_OPERAND16_4 (0xffff<<16) 12323 #define COMPLETION_ENQUEUE_OPERAND16_5 (0xffff<<0) 12324 12325 u32_t completion_enqueue_wd5; 12326 #define COMPLETION_ENQUEUE_OPERAND16_6 (0xffff<<16) 12327 #define COMPLETION_ENQUEUE_OPERAND16_7 (0xffff<<0) 12328 12329 u32_t completion_enqueue_operand32_2; 12330 u32_t completion_enqueue_operand32_3; 12331 u32_t completion_enqueue_operand32_4; 12332 u32_t completion_enqueue_wd9; 12333 #define COMPLETION_ENQUEUE_RDMA_ACTION_DO_DMA (1<<24) 12334 #define COMPLETION_ENQUEUE_RDMA_ACTION_PREPEND_L2_FRAME_HDR (1<<25) 12335 #define COMPLETION_ENQUEUE_RDMA_ACTION_CRC_ENABLE (1<<26) 12336 #define COMPLETION_ENQUEUE_RDMA_ACTION_CRC_USE_CTX_SEED (1<<27) 12337 #define COMPLETION_ENQUEUE_RDMA_ACTION_CS16_FIRST (1<<28) 12338 #define COMPLETION_ENQUEUE_RDMA_ACTION_CS16_LAST (1<<29) 12339 #define COMPLETION_ENQUEUE_RDMA_ACTION_CS16_VLD (1<<30) 12340 #define COMPLETION_ENQUEUE_RDMA_ACTION_CS16_ERR (1<<31) 12341 #define COMPLETION_ENQUEUE_CS16_PKT_LEN_VALUE (0x7f<<16) 12342 #define COMPLETION_ENQUEUE_CS16 (0xffff<<0) 12343 12344 } completion_enqueue_t; 12345 12346 12347 /* 12348 * com_reg definition 12349 * offset: 0x100000 12350 */ 12351 typedef struct com_reg 12352 { 12353 u32_t com_cksum_error_status; 12354 #define COM_CKSUM_ERROR_STATUS_CALCULATED (0xffffUL<<0) 12355 #define COM_CKSUM_ERROR_STATUS_EXPECTED (0xffffUL<<16) 12356 12357 u32_t unused_0[5119]; 12358 u32_t com_cpu_mode; 12359 #define COM_CPU_MODE_LOCAL_RST (1UL<<0) 12360 #define COM_CPU_MODE_STEP_ENA (1UL<<1) 12361 #define COM_CPU_MODE_PAGE_0_DATA_ENA (1UL<<2) 12362 #define COM_CPU_MODE_PAGE_0_INST_ENA (1UL<<3) 12363 #define COM_CPU_MODE_MSG_BIT1 (1UL<<6) 12364 #define COM_CPU_MODE_INTERRUPT_ENA (1UL<<7) 12365 #define COM_CPU_MODE_SOFT_HALT (1UL<<10) 12366 #define COM_CPU_MODE_BAD_DATA_HALT_ENA (1UL<<11) 12367 #define COM_CPU_MODE_BAD_INST_HALT_ENA (1UL<<12) 12368 #define COM_CPU_MODE_FIO_ABORT_HALT_ENA (1UL<<13) 12369 #define COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1UL<<15) 12370 12371 u32_t com_cpu_state; 12372 #define COM_CPU_STATE_BREAKPOINT (1UL<<0) 12373 #define COM_CPU_STATE_BAD_INST_HALTED (1UL<<2) 12374 #define COM_CPU_STATE_PAGE_0_DATA_HALTED (1UL<<3) 12375 #define COM_CPU_STATE_PAGE_0_INST_HALTED (1UL<<4) 12376 #define COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1UL<<5) 12377 #define COM_CPU_STATE_BAD_PC_HALTED (1UL<<6) 12378 #define COM_CPU_STATE_ALIGN_HALTED (1UL<<7) 12379 #define COM_CPU_STATE_FIO_ABORT_HALTED (1UL<<8) 12380 #define COM_CPU_STATE_SOFT_HALTED (1UL<<10) 12381 #define COM_CPU_STATE_SPAD_UNDERFLOW (1UL<<11) 12382 #define COM_CPU_STATE_INTERRRUPT (1UL<<12) 12383 #define COM_CPU_STATE_DATA_ACCESS_STALL (1UL<<14) 12384 #define COM_CPU_STATE_INST_FETCH_STALL (1UL<<15) 12385 #define COM_CPU_STATE_BLOCKED_READ (1UL<<31) 12386 12387 u32_t com_cpu_event_mask; 12388 #define COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1UL<<0) 12389 #define COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1UL<<2) 12390 #define COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1UL<<3) 12391 #define COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1UL<<4) 12392 #define COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1UL<<5) 12393 #define COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1UL<<6) 12394 #define COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1UL<<7) 12395 #define COM_CPU_EVENT_MASK_FIO_ABORT_MASK (1UL<<8) 12396 #define COM_CPU_EVENT_MASK_SOFT_HALTED_MASK (1UL<<10) 12397 #define COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1UL<<11) 12398 #define COM_CPU_EVENT_MASK_INTERRUPT_MASK (1UL<<12) 12399 12400 u32_t unused_1[4]; 12401 u32_t com_cpu_program_counter; 12402 u32_t com_cpu_instruction; 12403 u32_t com_cpu_data_access; 12404 u32_t com_cpu_interrupt_enable; 12405 u32_t com_cpu_interrupt_vector; 12406 u32_t com_cpu_interrupt_saved_PC; 12407 u32_t com_cpu_hw_breakpoint; 12408 #define COM_CPU_HW_BREAKPOINT_DISABLE (1UL<<0) 12409 #define COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffUL<<2) 12410 12411 u32_t com_cpu_debug_vect_peek; 12412 #define COM_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) 12413 #define COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) 12414 #define COM_CPU_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) 12415 #define COM_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) 12416 #define COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) 12417 #define COM_CPU_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) 12418 12419 u32_t unused_2[3]; 12420 u32_t com_cpu_last_branch_addr; 12421 #define COM_CPU_LAST_BRANCH_ADDR_TYPE (1UL<<1) 12422 #define COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0UL<<1) 12423 #define COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1UL<<1) 12424 #define COM_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffUL<<2) 12425 12426 u32_t unused_3[109]; 12427 u32_t com_cpu_reg_file[32]; 12428 u32_t unused_4[15]; 12429 u32_t com_comtq_pfe_pfe_ctl; 12430 #define COM_COMTQ_PFE_PFE_CTL_INC_USAGE_CNT (1UL<<0) 12431 #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE (0xfUL<<4) 12432 #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_0 (0UL<<4) 12433 #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_1 (1UL<<4) 12434 #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_2 (2UL<<4) 12435 #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_3 (3UL<<4) 12436 #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_4 (4UL<<4) 12437 #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_5 (5UL<<4) 12438 #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_6 (6UL<<4) 12439 #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_7 (7UL<<4) 12440 #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_8 (8UL<<4) 12441 #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_9 (9UL<<4) 12442 #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_10 (10UL<<4) 12443 #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_11 (11UL<<4) 12444 #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_12 (12UL<<4) 12445 #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_13 (13UL<<4) 12446 #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_14 (14UL<<4) 12447 #define COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_15 (15UL<<4) 12448 #define COM_COMTQ_PFE_PFE_CTL_PFE_COUNT (0xfUL<<12) 12449 #define COM_COMTQ_PFE_PFE_CTL_OFFSET (0x1ffUL<<16) 12450 12451 u32_t unused_5[32]; 12452 completion_tx_enqueue_t com_comxq; 12453 u32_t unused_6[10]; 12454 u32_t com_comxq_ftq_cmd; 12455 #define COM_COMXQ_FTQ_CMD_OFFSET (0x3ffUL<<0) 12456 #define COM_COMXQ_FTQ_CMD_WR_TOP (1UL<<10) 12457 #define COM_COMXQ_FTQ_CMD_WR_TOP_0 (0UL<<10) 12458 #define COM_COMXQ_FTQ_CMD_WR_TOP_1 (1UL<<10) 12459 #define COM_COMXQ_FTQ_CMD_SFT_RESET (1UL<<25) 12460 #define COM_COMXQ_FTQ_CMD_RD_DATA (1UL<<26) 12461 #define COM_COMXQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) 12462 #define COM_COMXQ_FTQ_CMD_ADD_DATA (1UL<<28) 12463 #define COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1UL<<29) 12464 #define COM_COMXQ_FTQ_CMD_POP (1UL<<30) 12465 #define COM_COMXQ_FTQ_CMD_BUSY (1UL<<31) 12466 12467 u32_t com_comxq_ftq_ctl; 12468 #define COM_COMXQ_FTQ_CTL_INTERVENE (1UL<<0) 12469 #define COM_COMXQ_FTQ_CTL_OVERFLOW (1UL<<1) 12470 #define COM_COMXQ_FTQ_CTL_FORCE_INTERVENE (1UL<<2) 12471 #define COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) 12472 #define COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) 12473 12474 completion_timeout_enqueue_t com_comtq; 12475 u32_t unused_7[11]; 12476 u32_t com_comtq_ftq_cmd; 12477 #define COM_COMTQ_FTQ_CMD_OFFSET (0x3ffUL<<0) 12478 #define COM_COMTQ_FTQ_CMD_WR_TOP (1UL<<10) 12479 #define COM_COMTQ_FTQ_CMD_WR_TOP_0 (0UL<<10) 12480 #define COM_COMTQ_FTQ_CMD_WR_TOP_1 (1UL<<10) 12481 #define COM_COMTQ_FTQ_CMD_SFT_RESET (1UL<<25) 12482 #define COM_COMTQ_FTQ_CMD_RD_DATA (1UL<<26) 12483 #define COM_COMTQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) 12484 #define COM_COMTQ_FTQ_CMD_ADD_DATA (1UL<<28) 12485 #define COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1UL<<29) 12486 #define COM_COMTQ_FTQ_CMD_POP (1UL<<30) 12487 #define COM_COMTQ_FTQ_CMD_BUSY (1UL<<31) 12488 12489 u32_t com_comtq_ftq_ctl; 12490 #define COM_COMTQ_FTQ_CTL_INTERVENE (1UL<<0) 12491 #define COM_COMTQ_FTQ_CTL_OVERFLOW (1UL<<1) 12492 #define COM_COMTQ_FTQ_CTL_FORCE_INTERVENE (1UL<<2) 12493 #define COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) 12494 #define COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) 12495 12496 completion_enqueue_t com_comq; 12497 u32_t unused_8[4]; 12498 u32_t com_comq_ftq_cmd; 12499 #define COM_COMQ_FTQ_CMD_OFFSET (0x3ffUL<<0) 12500 #define COM_COMQ_FTQ_CMD_WR_TOP (1UL<<10) 12501 #define COM_COMQ_FTQ_CMD_WR_TOP_0 (0UL<<10) 12502 #define COM_COMQ_FTQ_CMD_WR_TOP_1 (1UL<<10) 12503 #define COM_COMQ_FTQ_CMD_SFT_RESET (1UL<<25) 12504 #define COM_COMQ_FTQ_CMD_RD_DATA (1UL<<26) 12505 #define COM_COMQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) 12506 #define COM_COMQ_FTQ_CMD_ADD_DATA (1UL<<28) 12507 #define COM_COMQ_FTQ_CMD_INTERVENE_CLR (1UL<<29) 12508 #define COM_COMQ_FTQ_CMD_POP (1UL<<30) 12509 #define COM_COMQ_FTQ_CMD_BUSY (1UL<<31) 12510 12511 u32_t com_comq_ftq_ctl; 12512 #define COM_COMQ_FTQ_CTL_INTERVENE (1UL<<0) 12513 #define COM_COMQ_FTQ_CTL_OVERFLOW (1UL<<1) 12514 #define COM_COMQ_FTQ_CTL_FORCE_INTERVENE (1UL<<2) 12515 #define COM_COMQ_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) 12516 #define COM_COMQ_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) 12517 12518 u32_t unused_9[27392]; 12519 u32_t com_scratch[10240]; 12520 u32_t unused_10[22528]; 12521 } com_reg_t; 12522 12523 typedef com_reg_t completion_reg_t; 12524 12525 /* 12526 * cmd_processor_enqueue definition 12527 * offset: 0000 12528 */ 12529 typedef struct cmd_processor_enqueue 12530 { 12531 u32_t cmd_processor_enqueue_cid; 12532 #define CMD_PROCESSOR_ENQUEUE_CID_VALUE (0x3fffUL<<7) 12533 12534 } cmd_processor_enqueue_t; 12535 12536 12537 /* 12538 * cp_reg definition 12539 * offset: 0x180000 12540 */ 12541 typedef struct cp_reg 12542 { 12543 u32_t cp_cksum_error_status; 12544 #define CP_CKSUM_ERROR_STATUS_CALCULATED (0xffffUL<<0) 12545 #define CP_CKSUM_ERROR_STATUS_EXPECTED (0xffffUL<<16) 12546 12547 u32_t unused_0[5119]; 12548 u32_t cp_cpu_mode; 12549 #define CP_CPU_MODE_LOCAL_RST (1UL<<0) 12550 #define CP_CPU_MODE_STEP_ENA (1UL<<1) 12551 #define CP_CPU_MODE_PAGE_0_DATA_ENA (1UL<<2) 12552 #define CP_CPU_MODE_PAGE_0_INST_ENA (1UL<<3) 12553 #define CP_CPU_MODE_MSG_BIT1 (1UL<<6) 12554 #define CP_CPU_MODE_INTERRUPT_ENA (1UL<<7) 12555 #define CP_CPU_MODE_SOFT_HALT (1UL<<10) 12556 #define CP_CPU_MODE_BAD_DATA_HALT_ENA (1UL<<11) 12557 #define CP_CPU_MODE_BAD_INST_HALT_ENA (1UL<<12) 12558 #define CP_CPU_MODE_FIO_ABORT_HALT_ENA (1UL<<13) 12559 #define CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1UL<<15) 12560 12561 u32_t cp_cpu_state; 12562 #define CP_CPU_STATE_BREAKPOINT (1UL<<0) 12563 #define CP_CPU_STATE_BAD_INST_HALTED (1UL<<2) 12564 #define CP_CPU_STATE_PAGE_0_DATA_HALTED (1UL<<3) 12565 #define CP_CPU_STATE_PAGE_0_INST_HALTED (1UL<<4) 12566 #define CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1UL<<5) 12567 #define CP_CPU_STATE_BAD_PC_HALTED (1UL<<6) 12568 #define CP_CPU_STATE_ALIGN_HALTED (1UL<<7) 12569 #define CP_CPU_STATE_FIO_ABORT_HALTED (1UL<<8) 12570 #define CP_CPU_STATE_SOFT_HALTED (1UL<<10) 12571 #define CP_CPU_STATE_SPAD_UNDERFLOW (1UL<<11) 12572 #define CP_CPU_STATE_INTERRRUPT (1UL<<12) 12573 #define CP_CPU_STATE_DATA_ACCESS_STALL (1UL<<14) 12574 #define CP_CPU_STATE_INST_FETCH_STALL (1UL<<15) 12575 #define CP_CPU_STATE_BLOCKED_READ (1UL<<31) 12576 12577 u32_t cp_cpu_event_mask; 12578 #define CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1UL<<0) 12579 #define CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1UL<<2) 12580 #define CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1UL<<3) 12581 #define CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1UL<<4) 12582 #define CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1UL<<5) 12583 #define CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1UL<<6) 12584 #define CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1UL<<7) 12585 #define CP_CPU_EVENT_MASK_FIO_ABORT_MASK (1UL<<8) 12586 #define CP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1UL<<10) 12587 #define CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1UL<<11) 12588 #define CP_CPU_EVENT_MASK_INTERRUPT_MASK (1UL<<12) 12589 12590 u32_t unused_1[4]; 12591 u32_t cp_cpu_program_counter; 12592 u32_t cp_cpu_instruction; 12593 u32_t cp_cpu_data_access; 12594 u32_t cp_cpu_interrupt_enable; 12595 u32_t cp_cpu_interrupt_vector; 12596 u32_t cp_cpu_interrupt_saved_PC; 12597 u32_t cp_cpu_hw_breakpoint; 12598 #define CP_CPU_HW_BREAKPOINT_DISABLE (1UL<<0) 12599 #define CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffUL<<2) 12600 12601 u32_t cp_cpu_debug_vect_peek; 12602 #define CP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) 12603 #define CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) 12604 #define CP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) 12605 #define CP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) 12606 #define CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) 12607 #define CP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) 12608 12609 u32_t unused_2[3]; 12610 u32_t cp_cpu_last_branch_addr; 12611 #define CP_CPU_LAST_BRANCH_ADDR_TYPE (1UL<<1) 12612 #define CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0UL<<1) 12613 #define CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1UL<<1) 12614 #define CP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffUL<<2) 12615 12616 u32_t unused_3[109]; 12617 u32_t cp_cpu_reg_file[32]; 12618 u32_t unused_4[79]; 12619 u32_t cp_cpq_pfe_pfe_ctl; 12620 #define CP_CPQ_PFE_PFE_CTL_INC_USAGE_CNT (1UL<<0) 12621 #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE (0xfUL<<4) 12622 #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_0 (0UL<<4) 12623 #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_1 (1UL<<4) 12624 #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_2 (2UL<<4) 12625 #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_3 (3UL<<4) 12626 #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_4 (4UL<<4) 12627 #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_5 (5UL<<4) 12628 #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_6 (6UL<<4) 12629 #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_7 (7UL<<4) 12630 #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_8 (8UL<<4) 12631 #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_9 (9UL<<4) 12632 #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_10 (10UL<<4) 12633 #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_11 (11UL<<4) 12634 #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_12 (12UL<<4) 12635 #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_13 (13UL<<4) 12636 #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_14 (14UL<<4) 12637 #define CP_CPQ_PFE_PFE_CTL_PFE_SIZE_15 (15UL<<4) 12638 #define CP_CPQ_PFE_PFE_CTL_PFE_COUNT (0xfUL<<12) 12639 #define CP_CPQ_PFE_PFE_CTL_OFFSET (0x1ffUL<<16) 12640 12641 cmd_processor_enqueue_t cp_cpq; 12642 u32_t unused_5[13]; 12643 u32_t cp_cpq_ftq_cmd; 12644 #define CP_CPQ_FTQ_CMD_OFFSET (0x3ffUL<<0) 12645 #define CP_CPQ_FTQ_CMD_WR_TOP (1UL<<10) 12646 #define CP_CPQ_FTQ_CMD_WR_TOP_0 (0UL<<10) 12647 #define CP_CPQ_FTQ_CMD_WR_TOP_1 (1UL<<10) 12648 #define CP_CPQ_FTQ_CMD_SFT_RESET (1UL<<25) 12649 #define CP_CPQ_FTQ_CMD_RD_DATA (1UL<<26) 12650 #define CP_CPQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) 12651 #define CP_CPQ_FTQ_CMD_ADD_DATA (1UL<<28) 12652 #define CP_CPQ_FTQ_CMD_INTERVENE_CLR (1UL<<29) 12653 #define CP_CPQ_FTQ_CMD_POP (1UL<<30) 12654 #define CP_CPQ_FTQ_CMD_BUSY (1UL<<31) 12655 12656 u32_t cp_cpq_ftq_ctl; 12657 #define CP_CPQ_FTQ_CTL_INTERVENE (1UL<<0) 12658 #define CP_CPQ_FTQ_CTL_OVERFLOW (1UL<<1) 12659 #define CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1UL<<2) 12660 #define CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) 12661 #define CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) 12662 12663 u32_t unused_6[27392]; 12664 u32_t cp_scratch[10240]; 12665 u32_t unused_7[22528]; 12666 } cp_reg_t; 12667 12668 typedef cp_reg_t cmd_processor_reg_t; 12669 12670 /* 12671 * management_enqueue definition 12672 * offset: 0000 12673 */ 12674 typedef struct management_enqueue 12675 { 12676 u32_t management_enqueue_bits_status; 12677 #define MANAGEMENT_ENQUEUE_BITS_STATUS_RULE_CLASS (0x7UL<<0) 12678 #define MANAGEMENT_ENQUEUE_BITS_STATUS_RULE_P2 (1UL<<3) 12679 #define MANAGEMENT_ENQUEUE_BITS_STATUS_RULE_P3 (1UL<<4) 12680 #define MANAGEMENT_ENQUEUE_BITS_STATUS_RULE_P4 (1UL<<5) 12681 #define MANAGEMENT_ENQUEUE_BITS_STATUS_L2_VLAN_TAG (1UL<<6) 12682 #define MANAGEMENT_ENQUEUE_BITS_STATUS_L2_LLC_SNAP (1UL<<7) 12683 #define MANAGEMENT_ENQUEUE_BITS_STATUS_RSS_HASH (1UL<<8) 12684 #define MANAGEMENT_ENQUEUE_BITS_STATUS_SORT_VECT (0xfUL<<9) 12685 #define MANAGEMENT_ENQUEUE_BITS_STATUS_IP_DATAGRAM (1UL<<13) 12686 #define MANAGEMENT_ENQUEUE_BITS_STATUS_TCP_SEGMENT (1UL<<14) 12687 #define MANAGEMENT_ENQUEUE_BITS_STATUS_UDP_DATAGRAM (1UL<<15) 12688 #define MANAGEMENT_ENQUEUE_BITS_STATUS_CU_FRAME (1UL<<16) 12689 #define MANAGEMENT_ENQUEUE_BITS_STATUS_IP_PROG_EXT (1UL<<17) 12690 #define MANAGEMENT_ENQUEUE_BITS_STATUS_IP_TYPE (1UL<<18) 12691 #define MANAGEMENT_ENQUEUE_BITS_STATUS_RULE_P1 (1UL<<19) 12692 #define MANAGEMENT_ENQUEUE_BITS_STATUS_RLUP_HIT4 (1UL<<20) 12693 #define MANAGEMENT_ENQUEUE_BITS_STATUS_IP_FRAGMENT (1UL<<21) 12694 #define MANAGEMENT_ENQUEUE_BITS_STATUS_IP_OPTIONS_PRESENT (1UL<<22) 12695 #define MANAGEMENT_ENQUEUE_BITS_STATUS_TCP_OPTIONS_PRESENT (1UL<<23) 12696 #define MANAGEMENT_ENQUEUE_BITS_STATUS_L2_PM_IDX (0xfUL<<24) 12697 #define MANAGEMENT_ENQUEUE_BITS_STATUS_L2_PM_HIT (1UL<<28) 12698 #define MANAGEMENT_ENQUEUE_BITS_STATUS_L2_MC_HASH_HIT (1UL<<29) 12699 #define MANAGEMENT_ENQUEUE_BITS_STATUS_RDMAC_CRC_PASS (1UL<<30) 12700 #define MANAGEMENT_ENQUEUE_BITS_STATUS_MP_HIT (1UL<<31) 12701 12702 u32_t management_enqueue_wd1; 12703 #define MANAGEMENT_ENQUEUE_PKT_LEN_VALUE (0x3fff<<16) 12704 #define MANAGEMENT_ENQUEUE_VLAN_TAG (0xffff<<0) 12705 12706 u32_t management_enqueue_mbuf_cluster; 12707 #define MANAGEMENT_ENQUEUE_MBUF_CLUSTER_VALUE (0x1ffffffUL<<0) 12708 12709 u32_t management_enqueue_frm_errors; 12710 #define MANAGEMENT_ENQUEUE_FRM_ERRORS_L2_BAD_CRC (1UL<<1) 12711 #define MANAGEMENT_ENQUEUE_FRM_ERRORS_L2_PHY_DECODE (1UL<<2) 12712 #define MANAGEMENT_ENQUEUE_FRM_ERRORS_L2_ALIGNMENT (1UL<<3) 12713 #define MANAGEMENT_ENQUEUE_FRM_ERRORS_L2_TOO_SHORT (1UL<<4) 12714 #define MANAGEMENT_ENQUEUE_FRM_ERRORS_L2_GIANT_FRAME (1UL<<5) 12715 #define MANAGEMENT_ENQUEUE_FRM_ERRORS_IP_BAD_LEN (1UL<<6) 12716 #define MANAGEMENT_ENQUEUE_FRM_ERRORS_IP_TOO_SHORT (1UL<<7) 12717 #define MANAGEMENT_ENQUEUE_FRM_ERRORS_IP_BAD_VERSION (1UL<<8) 12718 #define MANAGEMENT_ENQUEUE_FRM_ERRORS_IP_BAD_HLEN (1UL<<9) 12719 #define MANAGEMENT_ENQUEUE_FRM_ERRORS_IP_BAD_XSUM (1UL<<10) 12720 #define MANAGEMENT_ENQUEUE_FRM_ERRORS_TCP_TOO_SHORT (1UL<<11) 12721 #define MANAGEMENT_ENQUEUE_FRM_ERRORS_TCP_BAD_XSUM (1UL<<12) 12722 #define MANAGEMENT_ENQUEUE_FRM_ERRORS_TCP_BAD_OFFSET (1UL<<13) 12723 #define MANAGEMENT_ENQUEUE_FRM_ERRORS_UDP_BAD_XSUM (1UL<<15) 12724 #define MANAGEMENT_ENQUEUE_FRM_ERRORS_IP_BAD_ORDER (1UL<<16) 12725 #define MANAGEMENT_ENQUEUE_FRM_ERRORS_IP_HDR_MISMATCH (1UL<<18) 12726 12727 u32_t management_enqueue_wd4; 12728 #define MANAGEMENT_ENQUEUE_EXT_STATUS_TCP_SYNC_PRESENT (1<<16) 12729 #define MANAGEMENT_ENQUEUE_EXT_STATUS_RLUP_HIT2 (1<<17) 12730 #define MANAGEMENT_ENQUEUE_EXT_STATUS_TCP_UDP_XSUM_IS_0 (1<<18) 12731 #define MANAGEMENT_ENQUEUE_EXT_STATUS_IP_ROUTING_HDR_PRESENT (0x3<<19) 12732 #define MANAGEMENT_ENQUEUE_EXT_STATUS_IP_ROUTING_HDR_PRESENT_00 (0<<19) 12733 #define MANAGEMENT_ENQUEUE_EXT_STATUS_IP_ROUTING_HDR_PRESENT_01 (1<<19) 12734 #define MANAGEMENT_ENQUEUE_EXT_STATUS_IP_ROUTING_HDR_PRESENT_10 (2<<19) 12735 #define MANAGEMENT_ENQUEUE_EXT_STATUS_IP_ROUTING_HDR_PRESENT_11 (3<<19) 12736 #define MANAGEMENT_ENQUEUE_EXT_STATUS_ACPI_MATCH (1<<21) 12737 #define MANAGEMENT_ENQUEUE_RESERVED (0xffff<<0) 12738 12739 } management_enqueue_t; 12740 12741 12742 /* 12743 * mcp_reg definition 12744 * offset: 0x140000 12745 */ 12746 typedef struct mcp_reg 12747 { 12748 u32_t unused_0[32]; 12749 u32_t mcp_mcp_control; 12750 #define MCP_MCP_CONTROL_SMBUS_SEL (1UL<<30) 12751 #define MCP_MCP_CONTROL_MCP_ISOLATE (1UL<<31) 12752 12753 u32_t mcp_mcp_attention_status; 12754 #define MCP_MCP_ATTENTION_STATUS_DRV_DOORBELL (1UL<<29) 12755 #define MCP_MCP_ATTENTION_STATUS_WATCHDOG_TIMEOUT (1UL<<30) 12756 #define MCP_MCP_ATTENTION_STATUS_CPU_EVENT (1UL<<31) 12757 12758 u32_t mcp_mcp_heartbeat_control; 12759 #define MCP_MCP_HEARTBEAT_CONTROL_MCP_HEARTBEAT_ENABLE (1UL<<31) 12760 12761 u32_t mcp_mcp_heartbeat_status; 12762 #define MCP_MCP_HEARTBEAT_STATUS_MCP_HEARTBEAT_PERIOD (0x7ffUL<<0) 12763 #define MCP_MCP_HEARTBEAT_STATUS_VALID (1UL<<31) 12764 12765 u32_t mcp_mcp_heartbeat; 12766 #define MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_COUNT (0x3fffffffUL<<0) 12767 #define MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_INC (1UL<<30) 12768 #define MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_RESET (1UL<<31) 12769 12770 u32_t mcp_watchdog_reset; 12771 #define MCP_WATCHDOG_RESET_WATCHDOG_RESET (1UL<<31) 12772 12773 u32_t mcp_watchdog_control; 12774 #define MCP_WATCHDOG_CONTROL_WATCHDOG_TIMEOUT (0xfffffffUL<<0) 12775 #define MCP_WATCHDOG_CONTROL_WATCHDOG_ATTN (1UL<<29) 12776 #define MCP_WATCHDOG_CONTROL_MCP_RST_ENABLE (1UL<<30) 12777 #define MCP_WATCHDOG_CONTROL_WATCHDOG_ENABLE (1UL<<31) 12778 12779 u32_t mcp_access_lock; 12780 #define MCP_ACCESS_LOCK_LOCK (1UL<<31) 12781 12782 u32_t mcp_toe_id; 12783 #define MCP_TOE_ID_FUNCTION_ID (1UL<<31) 12784 12785 u32_t mcp_mailbox_cfg; 12786 #define MCP_MAILBOX_CFG_MAILBOX_OFFSET (0x3fffUL<<0) 12787 #define MCP_MAILBOX_CFG_MAILBOX_SIZE (0xfffUL<<20) 12788 12789 u32_t mcp_mailbox_cfg_other_func; 12790 #define MCP_MAILBOX_CFG_OTHER_FUNC_MAILBOX_OFFSET (0x3fffUL<<0) 12791 #define MCP_MAILBOX_CFG_OTHER_FUNC_MAILBOX_SIZE (0xfffUL<<20) 12792 12793 u32_t mcp_mcp_doorbell; 12794 #define MCP_MCP_DOORBELL_MCP_DOORBELL (1UL<<31) 12795 12796 u32_t mcp_driver_doorbell; 12797 #define MCP_DRIVER_DOORBELL_DRIVER_DOORBELL (1UL<<31) 12798 12799 u32_t mcp_driver_doorbell_other_func; 12800 #define MCP_DRIVER_DOORBELL_OTHER_FUNC_DRIVER_DOORBELL (1UL<<31) 12801 12802 u32_t unused_1[5074]; 12803 u32_t mcp_cpu_mode; 12804 #define MCP_CPU_MODE_LOCAL_RST (1UL<<0) 12805 #define MCP_CPU_MODE_STEP_ENA (1UL<<1) 12806 #define MCP_CPU_MODE_PAGE_0_DATA_ENA (1UL<<2) 12807 #define MCP_CPU_MODE_PAGE_0_INST_ENA (1UL<<3) 12808 #define MCP_CPU_MODE_MSG_BIT1 (1UL<<6) 12809 #define MCP_CPU_MODE_INTERRUPT_ENA (1UL<<7) 12810 #define MCP_CPU_MODE_SOFT_HALT (1UL<<10) 12811 #define MCP_CPU_MODE_BAD_DATA_HALT_ENA (1UL<<11) 12812 #define MCP_CPU_MODE_BAD_INST_HALT_ENA (1UL<<12) 12813 #define MCP_CPU_MODE_FIO_ABORT_HALT_ENA (1UL<<13) 12814 #define MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1UL<<15) 12815 12816 u32_t mcp_cpu_state; 12817 #define MCP_CPU_STATE_BREAKPOINT (1UL<<0) 12818 #define MCP_CPU_STATE_BAD_INST_HALTED (1UL<<2) 12819 #define MCP_CPU_STATE_PAGE_0_DATA_HALTED (1UL<<3) 12820 #define MCP_CPU_STATE_PAGE_0_INST_HALTED (1UL<<4) 12821 #define MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1UL<<5) 12822 #define MCP_CPU_STATE_BAD_PC_HALTED (1UL<<6) 12823 #define MCP_CPU_STATE_ALIGN_HALTED (1UL<<7) 12824 #define MCP_CPU_STATE_FIO_ABORT_HALTED (1UL<<8) 12825 #define MCP_CPU_STATE_SOFT_HALTED (1UL<<10) 12826 #define MCP_CPU_STATE_SPAD_UNDERFLOW (1UL<<11) 12827 #define MCP_CPU_STATE_INTERRRUPT (1UL<<12) 12828 #define MCP_CPU_STATE_DATA_ACCESS_STALL (1UL<<14) 12829 #define MCP_CPU_STATE_INST_FETCH_STALL (1UL<<15) 12830 #define MCP_CPU_STATE_BLOCKED_READ (1UL<<31) 12831 12832 u32_t mcp_cpu_event_mask; 12833 #define MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1UL<<0) 12834 #define MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1UL<<2) 12835 #define MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1UL<<3) 12836 #define MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1UL<<4) 12837 #define MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1UL<<5) 12838 #define MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1UL<<6) 12839 #define MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1UL<<7) 12840 #define MCP_CPU_EVENT_MASK_FIO_ABORT_MASK (1UL<<8) 12841 #define MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1UL<<10) 12842 #define MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1UL<<11) 12843 #define MCP_CPU_EVENT_MASK_INTERRUPT_MASK (1UL<<12) 12844 12845 u32_t unused_2[4]; 12846 u32_t mcp_cpu_program_counter; 12847 u32_t mcp_cpu_instruction; 12848 u32_t mcp_cpu_data_access; 12849 u32_t mcp_cpu_interrupt_enable; 12850 u32_t mcp_cpu_interrupt_vector; 12851 u32_t mcp_cpu_interrupt_saved_PC; 12852 u32_t mcp_cpu_hw_breakpoint; 12853 #define MCP_CPU_HW_BREAKPOINT_DISABLE (1UL<<0) 12854 #define MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffUL<<2) 12855 12856 u32_t mcp_cpu_debug_vect_peek; 12857 #define MCP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffUL<<0) 12858 #define MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1UL<<11) 12859 #define MCP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfUL<<12) 12860 #define MCP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffUL<<16) 12861 #define MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1UL<<27) 12862 #define MCP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfUL<<28) 12863 12864 u32_t unused_3[3]; 12865 u32_t mcp_cpu_last_branch_addr; 12866 #define MCP_CPU_LAST_BRANCH_ADDR_TYPE (1UL<<1) 12867 #define MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0UL<<1) 12868 #define MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1UL<<1) 12869 #define MCP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffUL<<2) 12870 12871 u32_t unused_4[109]; 12872 u32_t mcp_cpu_reg_file[32]; 12873 u32_t unused_5[80]; 12874 management_enqueue_t mcp_mcpq; 12875 u32_t unused_6[9]; 12876 u32_t mcp_mcpq_ftq_cmd; 12877 #define MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffUL<<0) 12878 #define MCP_MCPQ_FTQ_CMD_WR_TOP (1UL<<10) 12879 #define MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0UL<<10) 12880 #define MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1UL<<10) 12881 #define MCP_MCPQ_FTQ_CMD_SFT_RESET (1UL<<25) 12882 #define MCP_MCPQ_FTQ_CMD_RD_DATA (1UL<<26) 12883 #define MCP_MCPQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) 12884 #define MCP_MCPQ_FTQ_CMD_ADD_DATA (1UL<<28) 12885 #define MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1UL<<29) 12886 #define MCP_MCPQ_FTQ_CMD_POP (1UL<<30) 12887 #define MCP_MCPQ_FTQ_CMD_BUSY (1UL<<31) 12888 12889 u32_t mcp_mcpq_ftq_ctl; 12890 #define MCP_MCPQ_FTQ_CTL_INTERVENE (1UL<<0) 12891 #define MCP_MCPQ_FTQ_CTL_OVERFLOW (1UL<<1) 12892 #define MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE (1UL<<2) 12893 #define MCP_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffUL<<12) 12894 #define MCP_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffUL<<22) 12895 12896 u32_t unused_7[1024]; 12897 u32_t mcp_nvm_command; 12898 #define MCP_NVM_COMMAND_RST (1UL<<0) 12899 #define MCP_NVM_COMMAND_DONE (1UL<<3) 12900 #define MCP_NVM_COMMAND_DOIT (1UL<<4) 12901 #define MCP_NVM_COMMAND_WR (1UL<<5) 12902 #define MCP_NVM_COMMAND_ERASE (1UL<<6) 12903 #define MCP_NVM_COMMAND_FIRST (1UL<<7) 12904 #define MCP_NVM_COMMAND_LAST (1UL<<8) 12905 #define MCP_NVM_COMMAND_WREN (1UL<<16) 12906 #define MCP_NVM_COMMAND_WRDI (1UL<<17) 12907 #define MCP_NVM_COMMAND_RD_ID (1UL<<20) 12908 #define MCP_NVM_COMMAND_RD_STATUS (1UL<<21) 12909 #define MCP_NVM_COMMAND_MODE_256 (1UL<<22) 12910 12911 u32_t mcp_nvm_status; 12912 #define MCP_NVM_STATUS_SPI_FSM_STATE (0x1fUL<<0) 12913 #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_IDLE (0UL<<0) 12914 #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_CMD0 (1UL<<0) 12915 #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_CMD1 (2UL<<0) 12916 #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH0 (3UL<<0) 12917 #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH1 (4UL<<0) 12918 #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_ADDR0 (5UL<<0) 12919 #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA0 (6UL<<0) 12920 #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA1 (7UL<<0) 12921 #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA2 (8UL<<0) 12922 #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA0 (9UL<<0) 12923 #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA1 (10UL<<0) 12924 #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA2 (11UL<<0) 12925 #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID0 (12UL<<0) 12926 #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID1 (13UL<<0) 12927 #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID2 (14UL<<0) 12928 #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID3 (15UL<<0) 12929 #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID4 (16UL<<0) 12930 #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_CHECK_BUSY0 (17UL<<0) 12931 #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_ST_WREN (18UL<<0) 12932 #define MCP_NVM_STATUS_SPI_FSM_STATE_SPI_WAIT (19UL<<0) 12933 12934 u32_t mcp_nvm_write; 12935 #define MCP_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffUL<<0) 12936 #define MCP_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0UL<<0) 12937 #define MCP_NVM_WRITE_NVM_WRITE_VALUE_SI (1UL<<0) 12938 #define MCP_NVM_WRITE_NVM_WRITE_VALUE_SO (2UL<<0) 12939 #define MCP_NVM_WRITE_NVM_WRITE_VALUE_CS_B (4UL<<0) 12940 #define MCP_NVM_WRITE_NVM_WRITE_VALUE_SCLK (8UL<<0) 12941 12942 u32_t mcp_nvm_addr; 12943 #define MCP_NVM_ADDR_NVM_ADDR_VALUE (0xffffffUL<<0) 12944 #define MCP_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0UL<<0) 12945 #define MCP_NVM_ADDR_NVM_ADDR_VALUE_SI (1UL<<0) 12946 #define MCP_NVM_ADDR_NVM_ADDR_VALUE_SO (2UL<<0) 12947 #define MCP_NVM_ADDR_NVM_ADDR_VALUE_CS_B (4UL<<0) 12948 #define MCP_NVM_ADDR_NVM_ADDR_VALUE_SCLK (8UL<<0) 12949 12950 u32_t mcp_nvm_read; 12951 #define MCP_NVM_READ_NVM_READ_VALUE (0xffffffffUL<<0) 12952 #define MCP_NVM_READ_NVM_READ_VALUE_BIT_BANG (0UL<<0) 12953 #define MCP_NVM_READ_NVM_READ_VALUE_SI (1UL<<0) 12954 #define MCP_NVM_READ_NVM_READ_VALUE_SO (2UL<<0) 12955 #define MCP_NVM_READ_NVM_READ_VALUE_CS_B (4UL<<0) 12956 #define MCP_NVM_READ_NVM_READ_VALUE_SCLK (8UL<<0) 12957 12958 u32_t mcp_nvm_cfg1; 12959 #define MCP_NVM_CFG1_FLASH_MODE (1UL<<0) 12960 #define MCP_NVM_CFG1_BUFFER_MODE (1UL<<1) 12961 #define MCP_NVM_CFG1_PASS_MODE (1UL<<2) 12962 #define MCP_NVM_CFG1_BITBANG_MODE (1UL<<3) 12963 #define MCP_NVM_CFG1_STATUS_BIT (0x7UL<<4) 12964 #define MCP_NVM_CFG1_SPI_CLK_DIV (0xfUL<<7) 12965 #define MCP_NVM_CFG1_SEE_CLK_DIV (0x7ffUL<<11) 12966 #define MCP_NVM_CFG1_STRAP_CONTROL_0 (1UL<<23) 12967 #define MCP_NVM_CFG1_PROTECT_MODE (1UL<<24) 12968 #define MCP_NVM_CFG1_FLASH_SIZE (1UL<<25) 12969 #define MCP_NVM_CFG1_FW_USTRAP_1 (1UL<<26) 12970 #define MCP_NVM_CFG1_FW_USTRAP_0 (1UL<<27) 12971 #define MCP_NVM_CFG1_FW_USTRAP_2 (1UL<<28) 12972 #define MCP_NVM_CFG1_FW_USTRAP_3 (1UL<<29) 12973 #define MCP_NVM_CFG1_FW_FLASH_TYPE_EN (1UL<<30) 12974 #define MCP_NVM_CFG1_COMPAT_BYPASSS (1UL<<31) 12975 12976 u32_t mcp_nvm_cfg2; 12977 #define MCP_NVM_CFG2_ERASE_CMD (0xffUL<<0) 12978 #define MCP_NVM_CFG2_STATUS_CMD (0xffUL<<16) 12979 #define MCP_NVM_CFG2_READ_ID (0xffUL<<24) 12980 12981 u32_t mcp_nvm_cfg3; 12982 #define MCP_NVM_CFG3_BUFFER_RD_CMD (0xffUL<<0) 12983 #define MCP_NVM_CFG3_WRITE_CMD (0xffUL<<8) 12984 #define MCP_NVM_CFG3_READ_CMD (0xffUL<<24) 12985 12986 u32_t mcp_nvm_sw_arb; 12987 #define MCP_NVM_SW_ARB_ARB_REQ_SET0 (1UL<<0) 12988 #define MCP_NVM_SW_ARB_ARB_REQ_SET1 (1UL<<1) 12989 #define MCP_NVM_SW_ARB_ARB_REQ_SET2 (1UL<<2) 12990 #define MCP_NVM_SW_ARB_ARB_REQ_SET3 (1UL<<3) 12991 #define MCP_NVM_SW_ARB_ARB_REQ_CLR0 (1UL<<4) 12992 #define MCP_NVM_SW_ARB_ARB_REQ_CLR1 (1UL<<5) 12993 #define MCP_NVM_SW_ARB_ARB_REQ_CLR2 (1UL<<6) 12994 #define MCP_NVM_SW_ARB_ARB_REQ_CLR3 (1UL<<7) 12995 #define MCP_NVM_SW_ARB_ARB_ARB0 (1UL<<8) 12996 #define MCP_NVM_SW_ARB_ARB_ARB1 (1UL<<9) 12997 #define MCP_NVM_SW_ARB_ARB_ARB2 (1UL<<10) 12998 #define MCP_NVM_SW_ARB_ARB_ARB3 (1UL<<11) 12999 #define MCP_NVM_SW_ARB_REQ0 (1UL<<12) 13000 #define MCP_NVM_SW_ARB_REQ1 (1UL<<13) 13001 #define MCP_NVM_SW_ARB_REQ2 (1UL<<14) 13002 #define MCP_NVM_SW_ARB_REQ3 (1UL<<15) 13003 13004 u32_t mcp_nvm_access_enable; 13005 #define MCP_NVM_ACCESS_ENABLE_EN (1UL<<0) 13006 #define MCP_NVM_ACCESS_ENABLE_WR_EN (1UL<<1) 13007 13008 u32_t mcp_nvm_write1; 13009 #define MCP_NVM_WRITE1_WREN_CMD (0xffUL<<0) 13010 #define MCP_NVM_WRITE1_WRDI_CMD (0xffUL<<8) 13011 13012 u32_t mcp_nvm_cfg4; 13013 #define MCP_NVM_CFG4_FLASH_SIZE (0x7UL<<0) 13014 #define MCP_NVM_CFG4_FLASH_SIZE_1MBIT (0UL<<0) 13015 #define MCP_NVM_CFG4_FLASH_SIZE_2MBIT (1UL<<0) 13016 #define MCP_NVM_CFG4_FLASH_SIZE_4MBIT (2UL<<0) 13017 #define MCP_NVM_CFG4_FLASH_SIZE_8MBIT (3UL<<0) 13018 #define MCP_NVM_CFG4_FLASH_SIZE_16MBIT (4UL<<0) 13019 #define MCP_NVM_CFG4_FLASH_SIZE_32MBIT (5UL<<0) 13020 #define MCP_NVM_CFG4_FLASH_SIZE_64MBIT (6UL<<0) 13021 #define MCP_NVM_CFG4_FLASH_SIZE_128MBIT (7UL<<0) 13022 #define MCP_NVM_CFG4_FLASH_VENDOR (1UL<<3) 13023 #define MCP_NVM_CFG4_FLASH_VENDOR_ST (0UL<<3) 13024 #define MCP_NVM_CFG4_FLASH_VENDOR_ATMEL (1UL<<3) 13025 #define MCP_NVM_CFG4_MODE_256_EMPTY_BIT_LOC (0x3UL<<4) 13026 #define MCP_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT8 (0UL<<4) 13027 #define MCP_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT9 (1UL<<4) 13028 #define MCP_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT10 (2UL<<4) 13029 #define MCP_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT11 (3UL<<4) 13030 #define MCP_NVM_CFG4_STATUS_BIT_POLARITY (1UL<<6) 13031 #define MCP_NVM_CFG4_RESERVED (0x1ffffffUL<<7) 13032 13033 u32_t mcp_nvm_reconfig; 13034 #define MCP_NVM_RECONFIG_ORIG_STRAP_VALUE (0xfUL<<0) 13035 #define MCP_NVM_RECONFIG_ORIG_STRAP_VALUE_ST (0UL<<0) 13036 #define MCP_NVM_RECONFIG_ORIG_STRAP_VALUE_ATMEL (1UL<<0) 13037 #define MCP_NVM_RECONFIG_RECONFIG_STRAP_VALUE (0xfUL<<4) 13038 #define MCP_NVM_RECONFIG_RESERVED (0x7fffffUL<<8) 13039 #define MCP_NVM_RECONFIG_RECONFIG_DONE (1UL<<31) 13040 13041 u32_t unused_8[1779]; 13042 u32_t mcp_smbus_config; 13043 #define MCP_SMBUS_CONFIG_HW_ARP_ASSIGN_ADDR (1UL<<7) 13044 #define MCP_SMBUS_CONFIG_ARP_EN0 (1UL<<8) 13045 #define MCP_SMBUS_CONFIG_ARP_EN1 (1UL<<9) 13046 #define MCP_SMBUS_CONFIG_MASTER_RTRY_CNT (0xfUL<<16) 13047 #define MCP_SMBUS_CONFIG_TIMESTAMP_CNT_EN (1UL<<26) 13048 #define MCP_SMBUS_CONFIG_PROMISCOUS_MODE (1UL<<27) 13049 #define MCP_SMBUS_CONFIG_EN_NIC_SMB_ADDR_0 (1UL<<28) 13050 #define MCP_SMBUS_CONFIG_BIT_BANG_EN (1UL<<29) 13051 #define MCP_SMBUS_CONFIG_SMB_EN (1UL<<30) 13052 #define MCP_SMBUS_CONFIG_RESET (1UL<<31) 13053 13054 u32_t mcp_smbus_timing_config; 13055 #define MCP_SMBUS_TIMING_CONFIG_SMBUS_IDLE_TIME (0xffUL<<8) 13056 #define MCP_SMBUS_TIMING_CONFIG_PERIODIC_SLAVE_STRETCH (0xffUL<<16) 13057 #define MCP_SMBUS_TIMING_CONFIG_RANDOM_SLAVE_STRETCH (0x7fUL<<24) 13058 #define MCP_SMBUS_TIMING_CONFIG_MODE_400 (1UL<<31) 13059 13060 u32_t mcp_smbus_address; 13061 #define MCP_SMBUS_ADDRESS_NIC_SMB_ADDR0 (0x7fUL<<0) 13062 #define MCP_SMBUS_ADDRESS_EN_NIC_SMB_ADDR0 (1UL<<7) 13063 #define MCP_SMBUS_ADDRESS_NIC_SMB_ADDR1 (0x7fUL<<8) 13064 #define MCP_SMBUS_ADDRESS_EN_NIC_SMB_ADDR1 (1UL<<15) 13065 #define MCP_SMBUS_ADDRESS_NIC_SMB_ADDR2 (0x7fUL<<16) 13066 #define MCP_SMBUS_ADDRESS_EN_NIC_SMB_ADDR2 (1UL<<23) 13067 #define MCP_SMBUS_ADDRESS_NIC_SMB_ADDR3 (0x7fUL<<24) 13068 #define MCP_SMBUS_ADDRESS_EN_NIC_SMB_ADDR3 (1UL<<31) 13069 13070 u32_t mcp_smbus_master_fifo_control; 13071 #define MCP_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_FIFO_THRESHOLD (0x7fUL<<8) 13072 #define MCP_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_PKT_COUNT (0x7fUL<<16) 13073 #define MCP_SMBUS_MASTER_FIFO_CONTROL_MASTER_TX_FIFO_FLUSH (1UL<<30) 13074 #define MCP_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_FIFO_FLUSH (1UL<<31) 13075 13076 u32_t mcp_smbus_slave_fifo_control; 13077 #define MCP_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_FIFO_THRESHOLD (0x7fUL<<8) 13078 #define MCP_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_PKT_COUNT (0x7fUL<<16) 13079 #define MCP_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_TX_FIFO_FLUSH (1UL<<30) 13080 #define MCP_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_FIFO_FLUSH (1UL<<31) 13081 13082 u32_t mcp_smbus_bit_bang_control; 13083 #define MCP_SMBUS_BIT_BANG_CONTROL_SMBDAT_OUT_EN (1UL<<28) 13084 #define MCP_SMBUS_BIT_BANG_CONTROL_SMBDAT_IN (1UL<<29) 13085 #define MCP_SMBUS_BIT_BANG_CONTROL_SMBCLK_OUT_EN (1UL<<30) 13086 #define MCP_SMBUS_BIT_BANG_CONTROL_SMBCLK_IN (1UL<<31) 13087 13088 u32_t mcp_smbus_watchdog; 13089 #define MCP_SMBUS_WATCHDOG_WATCHDOG (0xffffUL<<0) 13090 13091 u32_t mcp_smbus_heartbeat; 13092 #define MCP_SMBUS_HEARTBEAT_HEARTBEAT (0xffffUL<<0) 13093 13094 u32_t mcp_smbus_poll_asf; 13095 #define MCP_SMBUS_POLL_ASF_POLL_ASF (0xffffUL<<0) 13096 13097 u32_t mcp_smbus_poll_legacy; 13098 #define MCP_SMBUS_POLL_LEGACY_POLL_LEGACY (0xffffUL<<0) 13099 13100 u32_t mcp_smbus_retran; 13101 #define MCP_SMBUS_RETRAN_RETRAN (0xffUL<<0) 13102 13103 u32_t mcp_smbus_timestamp; 13104 #define MCP_SMBUS_TIMESTAMP_TIMESTAMP (0xffffffffUL<<0) 13105 13106 u32_t mcp_smbus_master_command; 13107 #define MCP_SMBUS_MASTER_COMMAND_RD_BYTE_COUNT (0xffUL<<0) 13108 #define MCP_SMBUS_MASTER_COMMAND_PEC (1UL<<8) 13109 #define MCP_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL (0xfUL<<9) 13110 #define MCP_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0000 (0UL<<9) 13111 #define MCP_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0001 (1UL<<9) 13112 #define MCP_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0010 (2UL<<9) 13113 #define MCP_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0011 (3UL<<9) 13114 #define MCP_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0100 (4UL<<9) 13115 #define MCP_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0101 (5UL<<9) 13116 #define MCP_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0110 (6UL<<9) 13117 #define MCP_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0111 (7UL<<9) 13118 #define MCP_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_1000 (8UL<<9) 13119 #define MCP_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_1001 (9UL<<9) 13120 #define MCP_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_1010 (10UL<<9) 13121 #define MCP_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_1011 (11UL<<9) 13122 #define MCP_SMBUS_MASTER_COMMAND_STATUS (0x7UL<<25) 13123 #define MCP_SMBUS_MASTER_COMMAND_STATUS_000 (0UL<<25) 13124 #define MCP_SMBUS_MASTER_COMMAND_STATUS_001 (1UL<<25) 13125 #define MCP_SMBUS_MASTER_COMMAND_STATUS_010 (2UL<<25) 13126 #define MCP_SMBUS_MASTER_COMMAND_STATUS_011 (3UL<<25) 13127 #define MCP_SMBUS_MASTER_COMMAND_STATUS_100 (4UL<<25) 13128 #define MCP_SMBUS_MASTER_COMMAND_STATUS_101 (5UL<<25) 13129 #define MCP_SMBUS_MASTER_COMMAND_STATUS_110 (6UL<<25) 13130 #define MCP_SMBUS_MASTER_COMMAND_STATUS_111 (7UL<<25) 13131 #define MCP_SMBUS_MASTER_COMMAND_ABORT (1UL<<30) 13132 #define MCP_SMBUS_MASTER_COMMAND_START_BUSY (1UL<<31) 13133 13134 u32_t mcp_smbus_slave_command; 13135 #define MCP_SMBUS_SLAVE_COMMAND_PEC (1UL<<8) 13136 #define MCP_SMBUS_SLAVE_COMMAND_STATUS (0x7UL<<23) 13137 #define MCP_SMBUS_SLAVE_COMMAND_STATUS_000 (0UL<<23) 13138 #define MCP_SMBUS_SLAVE_COMMAND_STATUS_101 (5UL<<23) 13139 #define MCP_SMBUS_SLAVE_COMMAND_STATUS_111 (7UL<<23) 13140 #define MCP_SMBUS_SLAVE_COMMAND_ABORT (1UL<<30) 13141 #define MCP_SMBUS_SLAVE_COMMAND_START (1UL<<31) 13142 13143 u32_t mcp_smbus_event_enable; 13144 #define MCP_SMBUS_EVENT_ENABLE_WATCHDOG_TO_EN (1UL<<0) 13145 #define MCP_SMBUS_EVENT_ENABLE_HEARTBEAT_TO_EN (1UL<<1) 13146 #define MCP_SMBUS_EVENT_ENABLE_POLL_ASF_TO_EN (1UL<<2) 13147 #define MCP_SMBUS_EVENT_ENABLE_POLL_LEGACY_TO_EN (1UL<<3) 13148 #define MCP_SMBUS_EVENT_ENABLE_RETRANSMIT_TO_EN (1UL<<4) 13149 #define MCP_SMBUS_EVENT_ENABLE_SLAVE_ARP_EVENT_EN (1UL<<20) 13150 #define MCP_SMBUS_EVENT_ENABLE_SLAVE_RD_EVENT_EN (1UL<<21) 13151 #define MCP_SMBUS_EVENT_ENABLE_SLAVE_TX_UNDERRUN_EN (1UL<<22) 13152 #define MCP_SMBUS_EVENT_ENABLE_SLAVE_START_BUSY_EN (1UL<<23) 13153 #define MCP_SMBUS_EVENT_ENABLE_SLAVE_RX_EVENT_EN (1UL<<24) 13154 #define MCP_SMBUS_EVENT_ENABLE_SLAVE_RX_THRESHOLD_HIT_EN (1UL<<25) 13155 #define MCP_SMBUS_EVENT_ENABLE_SLAVE_RX_FIFO_FULL_EN (1UL<<26) 13156 #define MCP_SMBUS_EVENT_ENABLE_MASTER_TX_UNDERRUN_EN (1UL<<27) 13157 #define MCP_SMBUS_EVENT_ENABLE_MASTER_START_BUSY_EN (1UL<<28) 13158 #define MCP_SMBUS_EVENT_ENABLE_MASTER_RX_EVENT_EN (1UL<<29) 13159 #define MCP_SMBUS_EVENT_ENABLE_MASTER_RX_THRESHOLD_HIT_EN (1UL<<30) 13160 #define MCP_SMBUS_EVENT_ENABLE_MASTER_RX_FIFO_FULL_EN (1UL<<31) 13161 13162 u32_t mcp_smbus_event_status; 13163 #define MCP_SMBUS_EVENT_STATUS_WATCHDOG_TO (1UL<<0) 13164 #define MCP_SMBUS_EVENT_STATUS_HEARTBEAT_TO (1UL<<1) 13165 #define MCP_SMBUS_EVENT_STATUS_POLL_ASF_TO (1UL<<2) 13166 #define MCP_SMBUS_EVENT_STATUS_POLL_LEGACY_TO (1UL<<3) 13167 #define MCP_SMBUS_EVENT_STATUS_RETRANSMIT_TO (1UL<<4) 13168 #define MCP_SMBUS_EVENT_STATUS_SLAVE_ARP_EVENT (1UL<<20) 13169 #define MCP_SMBUS_EVENT_STATUS_SLAVE_RD_EVENT (1UL<<21) 13170 #define MCP_SMBUS_EVENT_STATUS_SLAVE_TX_UNDERRUN (1UL<<22) 13171 #define MCP_SMBUS_EVENT_STATUS_SLAVE_START_BUSY (1UL<<23) 13172 #define MCP_SMBUS_EVENT_STATUS_SLAVE_RX_EVENT (1UL<<24) 13173 #define MCP_SMBUS_EVENT_STATUS_SLAVE_RX_THRESHOLD_HIT (1UL<<25) 13174 #define MCP_SMBUS_EVENT_STATUS_SLAVE_RX_FIFO_FULL (1UL<<26) 13175 #define MCP_SMBUS_EVENT_STATUS_MASTER_TX_UNDERRUN (1UL<<27) 13176 #define MCP_SMBUS_EVENT_STATUS_MASTER_START_BUSY (1UL<<28) 13177 #define MCP_SMBUS_EVENT_STATUS_MASTER_RX_EVENT (1UL<<29) 13178 #define MCP_SMBUS_EVENT_STATUS_MASTER_RX_THRESHOLD_HIT (1UL<<30) 13179 #define MCP_SMBUS_EVENT_STATUS_MASTER_RX_FIFO_FULL (1UL<<31) 13180 13181 u32_t mcp_smbus_master_data_write; 13182 #define MCP_SMBUS_MASTER_DATA_WRITE_MASTER_SMBUS_WR_DATA (0xffUL<<0) 13183 #define MCP_SMBUS_MASTER_DATA_WRITE_WR_STATUS (1UL<<31) 13184 13185 u32_t mcp_smbus_master_data_read; 13186 #define MCP_SMBUS_MASTER_DATA_READ_MASTER_SMBUS_RD_DATA (0xffUL<<0) 13187 #define MCP_SMBUS_MASTER_DATA_READ_PEC_ERR (1UL<<29) 13188 #define MCP_SMBUS_MASTER_DATA_READ_RD_STATUS (0x3UL<<30) 13189 #define MCP_SMBUS_MASTER_DATA_READ_RD_STATUS_00 (0UL<<30) 13190 #define MCP_SMBUS_MASTER_DATA_READ_RD_STATUS_01 (1UL<<30) 13191 #define MCP_SMBUS_MASTER_DATA_READ_RD_STATUS_10 (2UL<<30) 13192 #define MCP_SMBUS_MASTER_DATA_READ_RD_STATUS_11 (3UL<<30) 13193 13194 u32_t mcp_smbus_slave_data_write; 13195 #define MCP_SMBUS_SLAVE_DATA_WRITE_SLAVE_SMBUS_WR_DATA (0xffUL<<0) 13196 #define MCP_SMBUS_SLAVE_DATA_WRITE_WR_STATUS (1UL<<31) 13197 #define MCP_SMBUS_SLAVE_DATA_WRITE_WR_STATUS_0 (0UL<<31) 13198 #define MCP_SMBUS_SLAVE_DATA_WRITE_WR_STATUS_1 (1UL<<31) 13199 13200 u32_t mcp_smbus_slave_data_read; 13201 #define MCP_SMBUS_SLAVE_DATA_READ_SLAVE_SMBUS_RD_DATA (0xffUL<<0) 13202 #define MCP_SMBUS_SLAVE_DATA_READ_ERR_STATUS (0x3UL<<28) 13203 #define MCP_SMBUS_SLAVE_DATA_READ_ERR_STATUS_00 (0UL<<28) 13204 #define MCP_SMBUS_SLAVE_DATA_READ_ERR_STATUS_01 (1UL<<28) 13205 #define MCP_SMBUS_SLAVE_DATA_READ_ERR_STATUS_10 (2UL<<28) 13206 #define MCP_SMBUS_SLAVE_DATA_READ_ERR_STATUS_11 (3UL<<28) 13207 #define MCP_SMBUS_SLAVE_DATA_READ_RD_STATUS (0x3UL<<30) 13208 #define MCP_SMBUS_SLAVE_DATA_READ_RD_STATUS_00 (0UL<<30) 13209 #define MCP_SMBUS_SLAVE_DATA_READ_RD_STATUS_01 (1UL<<30) 13210 #define MCP_SMBUS_SLAVE_DATA_READ_RD_STATUS_10 (2UL<<30) 13211 #define MCP_SMBUS_SLAVE_DATA_READ_RD_STATUS_11 (3UL<<30) 13212 13213 u32_t unused_9[12]; 13214 u32_t mcp_smbus_arp_state; 13215 #define MCP_SMBUS_ARP_STATE_AV_FLAG0 (1UL<<0) 13216 #define MCP_SMBUS_ARP_STATE_AR_FLAG0 (1UL<<1) 13217 #define MCP_SMBUS_ARP_STATE_AV_FLAG1 (1UL<<4) 13218 #define MCP_SMBUS_ARP_STATE_AR_FLAG1 (1UL<<5) 13219 13220 u32_t unused_10[3]; 13221 u32_t mcp_smbus_udid0_3; 13222 #define MCP_SMBUS_UDID0_3_BYTE_12 (0xffUL<<0) 13223 #define MCP_SMBUS_UDID0_3_BYTE_13 (0xffUL<<8) 13224 #define MCP_SMBUS_UDID0_3_BYTE_14 (0xffUL<<16) 13225 #define MCP_SMBUS_UDID0_3_BYTE_15 (0xffUL<<24) 13226 13227 u32_t mcp_smbus_udid0_2; 13228 #define MCP_SMBUS_UDID0_2_BYTE_8 (0xffUL<<0) 13229 #define MCP_SMBUS_UDID0_2_BYTE_9 (0xffUL<<8) 13230 #define MCP_SMBUS_UDID0_2_BYTE_10 (0xffUL<<16) 13231 #define MCP_SMBUS_UDID0_2_BYTE_11 (0xffUL<<24) 13232 13233 u32_t mcp_smbus_udid0_1; 13234 #define MCP_SMBUS_UDID0_1_BYTE_4 (0xffUL<<0) 13235 #define MCP_SMBUS_UDID0_1_BYTE_5 (0xffUL<<8) 13236 #define MCP_SMBUS_UDID0_1_BYTE_6 (0xffUL<<16) 13237 #define MCP_SMBUS_UDID0_1_BYTE_7 (0xffUL<<24) 13238 13239 u32_t mcp_smbus_udid0_0; 13240 #define MCP_SMBUS_UDID0_0_BYTE_0 (0xffUL<<0) 13241 #define MCP_SMBUS_UDID0_0_BYTE_1 (0xffUL<<8) 13242 #define MCP_SMBUS_UDID0_0_BYTE_2 (0xffUL<<16) 13243 #define MCP_SMBUS_UDID0_0_BYTE_3 (0xffUL<<24) 13244 13245 u32_t mcp_smbus_udid1_3; 13246 #define MCP_SMBUS_UDID1_3_BYTE_12 (0xffUL<<0) 13247 #define MCP_SMBUS_UDID1_3_BYTE_13 (0xffUL<<8) 13248 #define MCP_SMBUS_UDID1_3_BYTE_14 (0xffUL<<16) 13249 #define MCP_SMBUS_UDID1_3_BYTE_15 (0xffUL<<24) 13250 13251 u32_t mcp_smbus_udid1_2; 13252 #define MCP_SMBUS_UDID1_2_BYTE_8 (0xffUL<<0) 13253 #define MCP_SMBUS_UDID1_2_BYTE_9 (0xffUL<<8) 13254 #define MCP_SMBUS_UDID1_2_BYTE_10 (0xffUL<<16) 13255 #define MCP_SMBUS_UDID1_2_BYTE_11 (0xffUL<<24) 13256 13257 u32_t mcp_smbus_udid1_1; 13258 #define MCP_SMBUS_UDID1_1_BYTE_4 (0xffUL<<0) 13259 #define MCP_SMBUS_UDID1_1_BYTE_5 (0xffUL<<8) 13260 #define MCP_SMBUS_UDID1_1_BYTE_6 (0xffUL<<16) 13261 #define MCP_SMBUS_UDID1_1_BYTE_7 (0xffUL<<24) 13262 13263 u32_t mcp_smbus_udid1_0; 13264 #define MCP_SMBUS_UDID1_0_BYTE_0 (0xffUL<<0) 13265 #define MCP_SMBUS_UDID1_0_BYTE_1 (0xffUL<<8) 13266 #define MCP_SMBUS_UDID1_0_BYTE_2 (0xffUL<<16) 13267 #define MCP_SMBUS_UDID1_0_BYTE_3 (0xffUL<<24) 13268 13269 u32_t unused_11[468]; 13270 u32_t mcp_legacy_smb_asf_control; 13271 #define MCP_LEGACY_SMB_ASF_CONTROL_ASF_RST (1UL<<0) 13272 #define MCP_LEGACY_SMB_ASF_CONTROL_TSC_EN (1UL<<1) 13273 #define MCP_LEGACY_SMB_ASF_CONTROL_WG_TO (1UL<<2) 13274 #define MCP_LEGACY_SMB_ASF_CONTROL_HB_TO (1UL<<3) 13275 #define MCP_LEGACY_SMB_ASF_CONTROL_PA_TO (1UL<<4) 13276 #define MCP_LEGACY_SMB_ASF_CONTROL_PL_TO (1UL<<5) 13277 #define MCP_LEGACY_SMB_ASF_CONTROL_RT_TO (1UL<<6) 13278 #define MCP_LEGACY_SMB_ASF_CONTROL_SMB_EVENT (1UL<<7) 13279 #define MCP_LEGACY_SMB_ASF_CONTROL_STRETCH_EN (1UL<<8) 13280 #define MCP_LEGACY_SMB_ASF_CONTROL_STRETCH_PULSE (1UL<<9) 13281 #define MCP_LEGACY_SMB_ASF_CONTROL_RES (0x3UL<<10) 13282 #define MCP_LEGACY_SMB_ASF_CONTROL_SMB_EN (1UL<<12) 13283 #define MCP_LEGACY_SMB_ASF_CONTROL_SMB_BB_EN (1UL<<13) 13284 #define MCP_LEGACY_SMB_ASF_CONTROL_SMB_NO_ADDR_FILT (1UL<<14) 13285 #define MCP_LEGACY_SMB_ASF_CONTROL_SMB_AUTOREAD (1UL<<15) 13286 #define MCP_LEGACY_SMB_ASF_CONTROL_NIC_SMB_ADDR1 (0x7fUL<<16) 13287 #define MCP_LEGACY_SMB_ASF_CONTROL_NIC_SMB_ADDR2 (0x7fUL<<23) 13288 #define MCP_LEGACY_SMB_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1UL<<30) 13289 #define MCP_LEGACY_SMB_ASF_CONTROL_SMB_EARLY_ATTN (1UL<<31) 13290 13291 u32_t mcp_legacy_smb_in; 13292 #define MCP_LEGACY_SMB_IN_DAT_IN (0xffUL<<0) 13293 #define MCP_LEGACY_SMB_IN_RDY (1UL<<8) 13294 #define MCP_LEGACY_SMB_IN_DONE (1UL<<9) 13295 #define MCP_LEGACY_SMB_IN_FIRSTBYTE (1UL<<10) 13296 #define MCP_LEGACY_SMB_IN_STATUS (0x7UL<<11) 13297 #define MCP_LEGACY_SMB_IN_STATUS_OK (0UL<<11) 13298 #define MCP_LEGACY_SMB_IN_STATUS_PEC (1UL<<11) 13299 #define MCP_LEGACY_SMB_IN_STATUS_OFLOW (2UL<<11) 13300 #define MCP_LEGACY_SMB_IN_STATUS_STOP (3UL<<11) 13301 #define MCP_LEGACY_SMB_IN_STATUS_TIMEOUT (4UL<<11) 13302 13303 u32_t mcp_legacy_smb_out; 13304 #define MCP_LEGACY_SMB_OUT_DAT_OUT (0xffUL<<0) 13305 #define MCP_LEGACY_SMB_OUT_RDY (1UL<<8) 13306 #define MCP_LEGACY_SMB_OUT_START (1UL<<9) 13307 #define MCP_LEGACY_SMB_OUT_LAST (1UL<<10) 13308 #define MCP_LEGACY_SMB_OUT_ACC_TYPE (1UL<<11) 13309 #define MCP_LEGACY_SMB_OUT_ENB_PEC (1UL<<12) 13310 #define MCP_LEGACY_SMB_OUT_GET_RX_LEN (1UL<<13) 13311 #define MCP_LEGACY_SMB_OUT_SMB_READ_LEN (0x3fUL<<14) 13312 #define MCP_LEGACY_SMB_OUT_SMB_OUT_STATUS (0xfUL<<20) 13313 #define MCP_LEGACY_SMB_OUT_SMB_OUT_STATUS_OK (0UL<<20) 13314 #define MCP_LEGACY_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1UL<<20) 13315 #define MCP_LEGACY_SMB_OUT_SMB_OUT_STATUS_UFLOW (2UL<<20) 13316 #define MCP_LEGACY_SMB_OUT_SMB_OUT_STATUS_STOP (3UL<<20) 13317 #define MCP_LEGACY_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4UL<<20) 13318 #define MCP_LEGACY_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5UL<<20) 13319 #define MCP_LEGACY_SMB_OUT_SMB_OUT_STATUS_BADACK (6UL<<20) 13320 #define MCP_LEGACY_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9UL<<20) 13321 #define MCP_LEGACY_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (13UL<<20) 13322 #define MCP_LEGACY_SMB_OUT_SMB_OUT_SLAVEMODE (1UL<<24) 13323 #define MCP_LEGACY_SMB_OUT_SMB_OUT_DAT_EN (1UL<<25) 13324 #define MCP_LEGACY_SMB_OUT_SMB_OUT_DAT_IN (1UL<<26) 13325 #define MCP_LEGACY_SMB_OUT_SMB_OUT_CLK_EN (1UL<<27) 13326 #define MCP_LEGACY_SMB_OUT_SMB_OUT_CLK_IN (1UL<<28) 13327 13328 u32_t mcp_legacy_smb_watchdog; 13329 #define MCP_LEGACY_SMB_WATCHDOG_WATCHDOG (0xffffUL<<0) 13330 13331 u32_t mcp_legacy_smb_heartbeat; 13332 #define MCP_LEGACY_SMB_HEARTBEAT_HEARTBEAT (0xffffUL<<0) 13333 13334 u32_t mcp_legacy_smb_poll_asf; 13335 #define MCP_LEGACY_SMB_POLL_ASF_POLL_ASF (0xffffUL<<0) 13336 13337 u32_t mcp_legacy_smb_poll_legacy; 13338 #define MCP_LEGACY_SMB_POLL_LEGACY_POLL_LEGACY (0xffffUL<<0) 13339 13340 u32_t mcp_legacy_smb_retran; 13341 #define MCP_LEGACY_SMB_RETRAN_RETRAN (0xffUL<<0) 13342 13343 u32_t mcp_legacy_smb_timestamp; 13344 #define MCP_LEGACY_SMB_TIMESTAMP_TIMESTAMP (0xffffffffUL<<0) 13345 13346 u32_t unused_12[7671]; 13347 u32_t mcp_rom[320]; 13348 u32_t unused_13[7872]; 13349 u32_t mcp_ump_ump_cmd; 13350 #define MCP_UMP_UMP_CMD_EGRESS_FIFO_ENABLED (1UL<<0) 13351 #define MCP_UMP_UMP_CMD_INGRESS_FIFO_ENABLED (1UL<<1) 13352 #define MCP_UMP_UMP_CMD_FC_EN (1UL<<2) 13353 #define MCP_UMP_UMP_CMD_MAC_LOOPBACK (1UL<<3) 13354 #define MCP_UMP_UMP_CMD_EGRESS_MAC_DISABLE (1UL<<5) 13355 #define MCP_UMP_UMP_CMD_INGRESS_MAC_DISABLE (1UL<<6) 13356 #define MCP_UMP_UMP_CMD_INGRESS_DRIVE (1UL<<8) 13357 #define MCP_UMP_UMP_CMD_SW_PAUSE (1UL<<9) 13358 #define MCP_UMP_UMP_CMD_AUTO_DRIVE (1UL<<13) 13359 #define MCP_UMP_UMP_CMD_INGRESS_RESET (1UL<<14) 13360 #define MCP_UMP_UMP_CMD_NO_PLUS_TWO (1UL<<15) 13361 #define MCP_UMP_UMP_CMD_EGRESS_PKT_FLUSH (1UL<<16) 13362 #define MCP_UMP_UMP_CMD_CMD_IPG (0x1fUL<<17) 13363 #define MCP_UMP_UMP_CMD_EGRESS_FIO_RESET (1UL<<28) 13364 #define MCP_UMP_UMP_CMD_INGRESS_FIO_RESET (1UL<<29) 13365 #define MCP_UMP_UMP_CMD_EGRESS_MAC_RESET (1UL<<30) 13366 #define MCP_UMP_UMP_CMD_INGRESS_MAC_RESET (1UL<<31) 13367 13368 u32_t mcp_ump_ump_config; 13369 #define MCP_UMP_UMP_CONFIG_RMII_MODE (1UL<<4) 13370 #define MCP_UMP_UMP_CONFIG_RVMII_MODE (1UL<<6) 13371 #define MCP_UMP_UMP_CONFIG_INGRESS_MODE (1UL<<7) 13372 #define MCP_UMP_UMP_CONFIG_INGRESS_WORD_ACCM (0xffUL<<8) 13373 13374 u32_t mcp_ump_ump_fc_trip; 13375 #define MCP_UMP_UMP_FC_TRIP_XON_TRIP (0x1ffUL<<0) 13376 #define MCP_UMP_UMP_FC_TRIP_XOFF_TRIP (0x1ffUL<<16) 13377 13378 u32_t unused_14[33]; 13379 u32_t mcp_ump_ump_egress_frm_rd_status; 13380 #define MCP_UMP_UMP_EGRESS_FRM_RD_STATUS_NEW_FRM (1UL<<0) 13381 #define MCP_UMP_UMP_EGRESS_FRM_RD_STATUS_FRM_IN_PRO (1UL<<1) 13382 #define MCP_UMP_UMP_EGRESS_FRM_RD_STATUS_FIFO_EMPTY (1UL<<2) 13383 #define MCP_UMP_UMP_EGRESS_FRM_RD_STATUS_BCNT (0x7ffUL<<3) 13384 #define MCP_UMP_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE (0x1fUL<<27) 13385 #define MCP_UMP_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_IDLE (0UL<<27) 13386 #define MCP_UMP_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_READY (1UL<<27) 13387 #define MCP_UMP_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_BUSY (2UL<<27) 13388 #define MCP_UMP_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_EXTRA_RD (3UL<<27) 13389 #define MCP_UMP_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_LATCH_IP_HDR (4UL<<27) 13390 13391 u32_t mcp_ump_ump_egress_frm_rd_data; 13392 u32_t mcp_ump_ump_ingress_frm_wr_ctl; 13393 #define MCP_UMP_UMP_INGRESS_FRM_WR_CTL_NEW_FRM (1UL<<0) 13394 #define MCP_UMP_UMP_INGRESS_FRM_WR_CTL_FIFO_RDY (1UL<<1) 13395 #define MCP_UMP_UMP_INGRESS_FRM_WR_CTL_BCNT_RDY (1UL<<2) 13396 #define MCP_UMP_UMP_INGRESS_FRM_WR_CTL_BCNT (0x7ffUL<<3) 13397 #define MCP_UMP_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE (0x3UL<<30) 13398 #define MCP_UMP_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE_IDLE (0UL<<30) 13399 #define MCP_UMP_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE_WAIT (1UL<<30) 13400 #define MCP_UMP_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE_BUSY (2UL<<30) 13401 #define MCP_UMP_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE_EXTRA_WR (3UL<<30) 13402 13403 u32_t mcp_ump_ump_ingress_frm_wr_data; 13404 u32_t mcp_ump_ump_egress_frame_type; 13405 u32_t mcp_ump_ump_fifo_remaining_words; 13406 #define MCP_UMP_UMP_FIFO_REMAINING_WORDS_EGRESS_FIFO_DEPTH (0x7ffUL<<0) 13407 #define MCP_UMP_UMP_FIFO_REMAINING_WORDS_INGRESS_FIFO_DEPTH (0x3ffUL<<16) 13408 13409 u32_t mcp_ump_ump_egress_fifo_ptrs; 13410 #define MCP_UMP_UMP_EGRESS_FIFO_PTRS_EGRESS_FIFO_RD_PTR (0xfffUL<<0) 13411 #define MCP_UMP_UMP_EGRESS_FIFO_PTRS_UPDATE_RDPTR (1UL<<15) 13412 #define MCP_UMP_UMP_EGRESS_FIFO_PTRS_EGRESS_FIFO_WR_PTR (0xfffUL<<16) 13413 #define MCP_UMP_UMP_EGRESS_FIFO_PTRS_UPDATE_WRPTR (1UL<<31) 13414 13415 u32_t mcp_ump_ump_ingress_fifo_ptrs; 13416 #define MCP_UMP_UMP_INGRESS_FIFO_PTRS_INGRESS_FIFO_RD_PTR (0x7ffUL<<0) 13417 #define MCP_UMP_UMP_INGRESS_FIFO_PTRS_UPDATE_RDPTR (1UL<<15) 13418 #define MCP_UMP_UMP_INGRESS_FIFO_PTRS_INGRESS_FIFO_WR_PTR (0x7ffUL<<16) 13419 #define MCP_UMP_UMP_INGRESS_FIFO_PTRS_UPDATE_WRPTR (1UL<<31) 13420 13421 u32_t unused_15; 13422 u32_t mcp_ump_ump_egress_packet_sa_0; 13423 #define MCP_UMP_UMP_EGRESS_PACKET_SA_0_EGRESS_SA (0xffffUL<<0) 13424 13425 u32_t mcp_ump_ump_egress_packet_sa_1; 13426 #define MCP_UMP_UMP_EGRESS_PACKET_SA_1_EGRESS_SA (0xffffffffUL<<0) 13427 13428 u32_t mcp_ump_ump_ingress_burst_command; 13429 #define MCP_UMP_UMP_INGRESS_BURST_COMMAND_INGRESS_DMA_START (1UL<<0) 13430 #define MCP_UMP_UMP_INGRESS_BURST_COMMAND_INGRESS_PORT (1UL<<1) 13431 #define MCP_UMP_UMP_INGRESS_BURST_COMMAND_DMA_LENGTH (0x7ffUL<<2) 13432 #define MCP_UMP_UMP_INGRESS_BURST_COMMAND_RBUF_OFFSET (0x3fffUL<<16) 13433 13434 u32_t mcp_ump_ump_ingress_rbuf_cluster; 13435 #define MCP_UMP_UMP_INGRESS_RBUF_CLUSTER_RBUF_CLUSTER (0x1ffffffUL<<0) 13436 13437 u32_t mcp_ump_ump_ingress_vlan; 13438 #define MCP_UMP_UMP_INGRESS_VLAN_INGRESS_VLAN_TAG (0xffffUL<<0) 13439 #define MCP_UMP_UMP_INGRESS_VLAN_VLAN_INS (1UL<<16) 13440 #define MCP_UMP_UMP_INGRESS_VLAN_VLAN_DEL (1UL<<17) 13441 13442 u32_t mcp_ump_ump_ingress_burst_status; 13443 #define MCP_UMP_UMP_INGRESS_BURST_STATUS_RESULT (0x3UL<<0) 13444 #define MCP_UMP_UMP_INGRESS_BURST_STATUS_RESULT_BUSY (0UL<<0) 13445 #define MCP_UMP_UMP_INGRESS_BURST_STATUS_RESULT_DONE (1UL<<0) 13446 #define MCP_UMP_UMP_INGRESS_BURST_STATUS_RESULT_ERR (2UL<<0) 13447 #define MCP_UMP_UMP_INGRESS_BURST_STATUS_RESULT_ERR1 (3UL<<0) 13448 13449 u32_t mcp_ump_ump_egress_burst_command; 13450 #define MCP_UMP_UMP_EGRESS_BURST_COMMAND_EGRESS_DMA_START (1UL<<0) 13451 #define MCP_UMP_UMP_EGRESS_BURST_COMMAND_EGRESS_PORT (1UL<<1) 13452 #define MCP_UMP_UMP_EGRESS_BURST_COMMAND_DMA_LENGTH (0x7ffUL<<2) 13453 #define MCP_UMP_UMP_EGRESS_BURST_COMMAND_TPBUF_OFFSET (0x1fffUL<<16) 13454 13455 u32_t mcp_ump_ump_egress_vlan; 13456 #define MCP_UMP_UMP_EGRESS_VLAN_EGRESS_VLAN_TAG (0xffffUL<<0) 13457 #define MCP_UMP_UMP_EGRESS_VLAN_VLAN_INS (1UL<<16) 13458 #define MCP_UMP_UMP_EGRESS_VLAN_VLAN_DEL (1UL<<17) 13459 13460 u32_t mcp_ump_ump_egress_burst_status; 13461 #define MCP_UMP_UMP_EGRESS_BURST_STATUS_RESULT (0x3UL<<0) 13462 #define MCP_UMP_UMP_EGRESS_BURST_STATUS_RESULT_BUSY (0UL<<0) 13463 #define MCP_UMP_UMP_EGRESS_BURST_STATUS_RESULT_DONE (1UL<<0) 13464 #define MCP_UMP_UMP_EGRESS_BURST_STATUS_RESULT_ERR0 (2UL<<0) 13465 #define MCP_UMP_UMP_EGRESS_BURST_STATUS_RESULT_RSVD (3UL<<0) 13466 13467 u32_t mcp_ump_ump_egress_statistic; 13468 #define MCP_UMP_UMP_EGRESS_STATISTIC_EGRESS_GOOD_CNT (0xffffUL<<0) 13469 #define MCP_UMP_UMP_EGRESS_STATISTIC_EGRESS_ERROR_CNT (0xffUL<<16) 13470 #define MCP_UMP_UMP_EGRESS_STATISTIC_EGRESS_DROP_CNT (0xffUL<<24) 13471 13472 u32_t mcp_ump_ump_ingress_statistic; 13473 #define MCP_UMP_UMP_INGRESS_STATISTIC_INGRESS_PKT_CNT (0xffffUL<<0) 13474 13475 u32_t mcp_ump_ump_arb_cmd; 13476 #define MCP_UMP_UMP_ARB_CMD_UMP_ID (0x7UL<<0) 13477 #define MCP_UMP_UMP_ARB_CMD_UMP_ARB_DISABLE (1UL<<4) 13478 #define MCP_UMP_UMP_ARB_CMD_UMP_ARB_START (1UL<<5) 13479 #define MCP_UMP_UMP_ARB_CMD_UMP_ARB_BYPASS (1UL<<6) 13480 #define MCP_UMP_UMP_ARB_CMD_UMP_ARB_AUTOBYPASS (1UL<<7) 13481 #define MCP_UMP_UMP_ARB_CMD_UMP_ARB_TOKEN_IPG (0x1fUL<<8) 13482 #define MCP_UMP_UMP_ARB_CMD_UMP_ARB_TOKEN_VALID (1UL<<13) 13483 #define MCP_UMP_UMP_ARB_CMD_UMP_ARB_FC_DISABLE (1UL<<15) 13484 #define MCP_UMP_UMP_ARB_CMD_UMP_ARB_TIMEOUT (0xffffUL<<16) 13485 13486 u32_t unused_16[3]; 13487 u32_t mcp_ump_ump_egress_statistic_ac; 13488 #define MCP_UMP_UMP_EGRESS_STATISTIC_AC_EGRESS_GOOD_CNT (0xffffUL<<0) 13489 #define MCP_UMP_UMP_EGRESS_STATISTIC_AC_EGRESS_ERROR_CNT (0xffUL<<16) 13490 #define MCP_UMP_UMP_EGRESS_STATISTIC_AC_EGRESS_DROP_CNT (0xffUL<<24) 13491 13492 u32_t mcp_ump_ump_ingress_statistic_ac; 13493 #define MCP_UMP_UMP_INGRESS_STATISTIC_AC_INGRESS_PKT_CNT (0xffffUL<<0) 13494 13495 u32_t mcp_ump_ump_event; 13496 #define MCP_UMP_UMP_EVENT_INGRESS_RDY_EVENT (1UL<<0) 13497 #define MCP_UMP_UMP_EVENT_EGRESS_RDY_EVENT (1UL<<1) 13498 #define MCP_UMP_UMP_EVENT_INGRESSBURST_DONE_EVENT (1UL<<2) 13499 #define MCP_UMP_UMP_EVENT_EGRESSBURST_DONE_EVENT (1UL<<3) 13500 #define MCP_UMP_UMP_EVENT_EGRESS_FRAME_DROP_EVENT (1UL<<4) 13501 #define MCP_UMP_UMP_EVENT_INGRESS_RDY_EVENT_EN (1UL<<16) 13502 #define MCP_UMP_UMP_EVENT_EGRESS_RDY_EVENT_EN (1UL<<17) 13503 #define MCP_UMP_UMP_EVENT_INGRESSBURST_DONE_EVENT_EN (1UL<<18) 13504 #define MCP_UMP_UMP_EVENT_EGRESSBURST_DONE_EVENT_EN (1UL<<19) 13505 #define MCP_UMP_UMP_EVENT_EGRESS_FRAME_DROP_EVENT_EN (1UL<<20) 13506 13507 u32_t unused_17[4033]; 13508 u32_t mcp_ump_ump_egress_fifo_flat_space[1920]; 13509 u32_t unused_18[128]; 13510 u32_t mcp_ump_ump_ingress_fifo_flat_space[768]; 13511 u32_t unused_19[1280]; 13512 u32_t mcp_scratch[16384]; 13513 u32_t unused_20[16384]; 13514 } mcp_reg_t; 13515 13516 typedef mcp_reg_t management_reg_t; 13517 13518 /* 13519 * hb_reg definition 13520 * offset: 0x240000 13521 */ 13522 typedef struct hb_reg 13523 { 13524 u32_t hb_command; 13525 #define HB_COMMAND_ARM (1UL<<0) 13526 #define HB_COMMAND_TRIG_NOW (1UL<<1) 13527 #define HB_COMMAND_TRIG_MATCH (1UL<<2) 13528 #define HB_COMMAND_TRIG_POS (0x7UL<<5) 13529 #define HB_COMMAND_TRIG_POS_START (0UL<<5) 13530 #define HB_COMMAND_TRIG_POS_25P (1UL<<5) 13531 #define HB_COMMAND_TRIG_POS_50P (2UL<<5) 13532 #define HB_COMMAND_TRIG_POS_75P (3UL<<5) 13533 #define HB_COMMAND_TRIG_POS_END (4UL<<5) 13534 #define HB_COMMAND_PC_MATCH (0x1ffffUL<<12) 13535 13536 u32_t hb_status; 13537 #define HB_STATUS_ARMED (1UL<<0) 13538 #define HB_STATUS_TRIGGERED (1UL<<1) 13539 #define HB_STATUS_ARM_CNT (0x3ffUL<<8) 13540 #define HB_STATUS_CAP_ADDR (0x1ffUL<<20) 13541 13542 u32_t hb_config; 13543 #define HB_CONFIG_PROC_SEL (0xfUL<<0) 13544 #define HB_CONFIG_PROC_SEL_TXP0 (0UL<<0) 13545 #define HB_CONFIG_PROC_SEL_TXP1 (1UL<<0) 13546 #define HB_CONFIG_PROC_SEL_TPAT0 (2UL<<0) 13547 #define HB_CONFIG_PROC_SEL_TPAT1 (3UL<<0) 13548 #define HB_CONFIG_PROC_SEL_RXP0 (4UL<<0) 13549 #define HB_CONFIG_PROC_SEL_RXP1 (5UL<<0) 13550 #define HB_CONFIG_PROC_SEL_COM0 (6UL<<0) 13551 #define HB_CONFIG_PROC_SEL_COM1 (7UL<<0) 13552 #define HB_CONFIG_PROC_SEL_CP0 (8UL<<0) 13553 #define HB_CONFIG_PROC_SEL_CP1 (9UL<<0) 13554 #define HB_CONFIG_PROC_SEL_MCP (10UL<<0) 13555 13556 u32_t unused_0[1021]; 13557 u32_t hb_hb_buf_data[1024]; 13558 } hb_reg_t; 13559 13560 13561 /* 13562 * reg_space definition 13563 */ 13564 typedef struct reg_space 13565 { 13566 pci_config_t pci_config; 13567 pci_reg_t pci; 13568 misc_reg_t misc; 13569 dma_reg_t dma; 13570 context_reg_t context; 13571 emac_reg_t emac; 13572 rx_parser_reg_t rpm; 13573 rx_cu_parser_reg_t rpc; 13574 rx_lookup_reg_t rlup; 13575 cmd_scheduler_reg_t rv2pcs; 13576 rx_v2p_reg_t rv2p; 13577 rx_dma_reg_t rdma; 13578 rx_bd_cache_reg_t rbdc; 13579 u32_t unused_0[512]; 13580 mailbox_queue_reg_t mq; 13581 cmd_scheduler_reg_t csch; 13582 timer_reg_t timer; 13583 u32_t unused_1[256]; 13584 tx_scheduler_reg_t tsch; 13585 tx_bd_read_reg_t tbdr; 13586 tx_bd_cache_reg_t tbdc; 13587 u32_t unused_2[256]; 13588 tx_dma_reg_t tdma; 13589 dbu_reg_t dbu; 13590 nvm_reg_t nvm; 13591 host_coalesce_reg_t hc; 13592 u32_t unused_3[256]; 13593 debug_reg_t debug; 13594 u32_t unused_4[57856]; 13595 tx_processor_reg_t txp; 13596 tx_patchup_reg_t tpat; 13597 rx_processor_reg_t rxp; 13598 completion_reg_t com; 13599 management_reg_t mcp; 13600 cmd_processor_reg_t cp; 13601 tx_assembler_reg_t tas; 13602 rx_mbuf_reg_t rbuf; 13603 u32_t unused_5[196608]; 13604 pcie_reg_t pci1; 13605 host_coalesce_full_reg_t hc1; 13606 hb_reg_t hb; 13607 } reg_space_t; 13608 13609 13610 /* 13611 * txp_fio definition 13612 * offset: 0x80000000 13613 */ 13614 typedef struct txp_fio 13615 { 13616 u32_t txpf_events_bits; 13617 #define TXPF_EVENTS_BITS_GPIO0 (1UL<<15) 13618 #define TXPF_EVENTS_BITS_GPIO1 (1UL<<16) 13619 #define TXPF_EVENTS_BITS_GPIO2 (1UL<<17) 13620 #define TXPF_EVENTS_BITS_GPIO3 (1UL<<18) 13621 13622 u32_t txpf_attentions_bits; 13623 #define TXPF_ATTENTIONS_BITS_EPB_ERROR (1UL<<30) 13624 13625 u32_t txpf_event_enable; 13626 u32_t txpf_attention_enable; 13627 u32_t txpf_fio_status; 13628 u32_t unused_0[3]; 13629 13630 u32_t txpf_ctx_window_cid1; 13631 13632 u32_t txpf_ctx_window_cid2; 13633 13634 u32_t txpf_ctx_window_cid3; 13635 #define TXPF_CTX_WINDOW_CID3_CTX_WINDOW_CID3_VALUE (0x3fffUL<<7) 13636 13637 u32_t txpf_ctx_window_cid4; 13638 #define TXPF_CTX_WINDOW_CID4_CTX_WINDOW_CID4_VALUE (0x3fffUL<<7) 13639 u32_t unused_1[4]; 13640 13641 u32_t txpf_txp_hc_inc_stat[8]; 13642 u32_t unused_2[4]; 13643 u32_t txpf_free_counter_value; 13644 u32_t txpf_timer_retran_value; 13645 u16_t txpf_timer_rxpush_value; 13646 u16_t txpf_timer_delayack_value; 13647 u16_t txpf_timer_keepalive_value; 13648 u16_t txpf_timer_nagle_value; 13649 u32_t txpf_bdcache_window_cid; 13650 13651 u32_t txpf_bdcache_window_idx; 13652 u16_t unused_3; 13653 13654 u16_t txpf_tas_txp_thbuf_cons; 13655 u32_t unused_4[29]; 13656 13657 u32_t txpf_txpq_cid; 13658 u32_t txpf_txpq_bseq; 13659 u8_t txpf_txpq_flags_flags; 13660 #define TXPF_TXPQ_FLAGS_FLAGS_QUICK_CID (0x3<<1) 13661 #define TXPF_TXPQ_FLAGS_FLAGS_QUICK_CATCHUP (1<<3) 13662 13663 u8_t txpf_txpq_cmd; 13664 u8_t txpf_txpq_xnum; 13665 u8_t txpf_txpq_protocol_flags; 13666 u32_t unused_5[11]; 13667 u32_t txpf_txpq_ftq_cmd; 13668 u32_t unused_6; 13669 13670 u32_t txpf_tdmaq_cid; 13671 u16_t txpf_tdmaq_bidx; 13672 u16_t txpf_tdmaq_boff; 13673 u32_t txpf_tdmaq_bseq; 13674 u32_t txpf_tdmaq_snd_next; 13675 u8_t txpf_tdmaq_cmd; 13676 u8_t txpf_tdmaq_xnum; 13677 u8_t txpf_tdmaq_knum; 13678 u8_t unused_7; 13679 u32_t txpf_tdmaq_flags_flags; 13680 #define TXPF_TDMAQ_FLAGS_FLAGS_QUICK_CID (0x3UL<<10) 13681 13682 u16_t txpf_tdmaq_nbytes; 13683 u16_t txpf_tdmaq_hole0_boff; 13684 u16_t txpf_tdmaq_hole1_boff; 13685 u16_t txpf_tdmaq_hole2_boff; 13686 u32_t txpf_tdmaq_hole0_fill; 13687 u32_t txpf_tdmaq_hole1_fill; 13688 u32_t txpf_tdmaq_hole2_fill; 13689 u32_t unused_8[3]; 13690 u32_t txpf_tdmaq_ftq_cmd; 13691 u32_t unused_9[417]; 13692 13693 u32_t txpf_burst_base0; 13694 13695 u32_t txpf_burst_base1; 13696 13697 u32_t txpf_burst_base2; 13698 13699 u32_t txpf_burst_base3; 13700 13701 u32_t txpf_burst_cmd0; 13702 13703 u32_t txpf_burst_cmd1; 13704 13705 u32_t txpf_burst_cmd2; 13706 13707 u32_t txpf_burst_cmd3; 13708 u32_t unused_10[56]; 13709 13710 u32_t txpf_burst_data0[16]; 13711 u32_t txpf_burst_data1[16]; 13712 u32_t txpf_burst_data2[16]; 13713 u32_t txpf_burst_data3[16]; 13714 u32_t unused_11[128]; 13715 u32_t txpf_bd_cache_window[6]; 13716 u32_t unused_12[122]; 13717 u32_t txpf_bd_scan_cmd; 13718 13719 u32_t txpf_bd_scan_len; 13720 13721 u16_t txpf_bd_scan_flags; 13722 u16_t txpf_bd_scan_vlan_tag; 13723 u16_t txpf_bd_scan_reserved; 13724 u16_t unused_13; 13725 u16_t txpf_bd_scan_bidx_current; 13726 u16_t txpf_bd_scan_boff_current; 13727 u16_t txpf_bd_scan_bidx_prev; 13728 u16_t txpf_bd_scan_boff_prev; 13729 u32_t txpf_bd_scan_bseq_current; 13730 u32_t txpf_bd_scan_bseq_prev; 13731 u32_t unused_14[3192]; 13732 u32_t txpf_thbuf[4096]; 13733 u32_t unused_15[122880]; 13734 u32_t txpf_ctx_window1[32768]; 13735 u32_t txpf_ctx_window2[32768]; 13736 u32_t txpf_ctx_window3[32768]; 13737 u32_t txpf_ctx_window4[32768]; 13738 } txp_fio_t; 13739 13740 13741 /* 13742 * txp_fio definition 13743 * offset: 0x80000000 13744 */ 13745 typedef struct txp_fio_xi 13746 { 13747 u32_t txpf_events_bits; 13748 #define TXPF_EVENTS_BITS_FTQ0_VALID (1UL<<0) 13749 #define TXPF_EVENTS_BITS_FTQ1_VALID (1UL<<1) 13750 #define TXPF_EVENTS_BITS_FTQ2_VALID (1UL<<2) 13751 #define TXPF_EVENTS_BITS_SCANNER_DONE (1UL<<3) 13752 #define TXPF_EVENTS_BITS_DMA_WR_DONE (1UL<<4) 13753 #define TXPF_EVENTS_BITS_DMA_RD_DONE (1UL<<5) 13754 #define TXPF_EVENTS_BITS_CRACKER_DONE (1UL<<6) 13755 #define TXPF_EVENTS_BITS_MULTIPLY_DONE (1UL<<7) 13756 #define TXPF_EVENTS_BITS_EXP_ROM (1UL<<8) 13757 #define TXPF_EVENTS_BITS_VPD (1UL<<9) 13758 #define TXPF_EVENTS_BITS_FLASH (1UL<<10) 13759 #define TXPF_EVENTS_BITS_SMB0 (1UL<<11) 13760 #define TXPF_EVENTS_BITS_RESERVED0 (1UL<<12) 13761 #define TXPF_EVENTS_BITS_RESERVED1 (1UL<<13) 13762 #define TXPF_EVENTS_BITS_RESERVED2 (1UL<<14) 13763 #define TXPF_EVENTS_BITS_GPIO (1UL<<15) 13764 #define TXPF_EVENTS_BITS_SW_TMR_1 (1UL<<19) 13765 #define TXPF_EVENTS_BITS_SW_TMR_2 (1UL<<20) 13766 #define TXPF_EVENTS_BITS_SW_TMR_3 (1UL<<21) 13767 #define TXPF_EVENTS_BITS_SW_TMR_4 (1UL<<22) 13768 #define TXPF_EVENTS_BITS_LINK_CHANGED (1UL<<23) 13769 #define TXPF_EVENTS_BITS_MI_INT (1UL<<25) 13770 #define TXPF_EVENTS_BITS_MI_COMPLETE (1UL<<26) 13771 #define TXPF_EVENTS_BITS_MAIN_PWR_INT (1UL<<27) 13772 #define TXPF_EVENTS_BITS_NOT_ENABLED (1UL<<30) 13773 #define TXPF_EVENTS_BITS_ATTENTIONS_VALID (1UL<<31) 13774 13775 u32_t txpf_attentions_bits; 13776 #define TXPF_ATTENTIONS_BITS_LINK_STATE (1UL<<0) 13777 #define TXPF_ATTENTIONS_BITS_TX_SCHEDULER_ABORT (1UL<<1) 13778 #define TXPF_ATTENTIONS_BITS_TX_BD_READ_ABORT (1UL<<2) 13779 #define TXPF_ATTENTIONS_BITS_TX_BD_CACHE_ABORT (1UL<<3) 13780 #define TXPF_ATTENTIONS_BITS_TX_PROCESSOR_ABORT (1UL<<4) 13781 #define TXPF_ATTENTIONS_BITS_TX_DMA_ABORT (1UL<<5) 13782 #define TXPF_ATTENTIONS_BITS_TX_PATCHUP_ABORT (1UL<<6) 13783 #define TXPF_ATTENTIONS_BITS_TX_ASSEMBLER_ABORT (1UL<<7) 13784 #define TXPF_ATTENTIONS_BITS_RX_PARSER_MAC_ABORT (1UL<<8) 13785 #define TXPF_ATTENTIONS_BITS_RX_PARSER_CATCHUP_ABORT (1UL<<9) 13786 #define TXPF_ATTENTIONS_BITS_RX_MBUF_ABORT (1UL<<10) 13787 #define TXPF_ATTENTIONS_BITS_RX_LOOKUP_ABORT (1UL<<11) 13788 #define TXPF_ATTENTIONS_BITS_RX_PROCESSOR_ABORT (1UL<<12) 13789 #define TXPF_ATTENTIONS_BITS_RX_V2P_ABORT (1UL<<13) 13790 #define TXPF_ATTENTIONS_BITS_RX_BD_CACHE_ABORT (1UL<<14) 13791 #define TXPF_ATTENTIONS_BITS_RX_DMA_ABORT (1UL<<15) 13792 #define TXPF_ATTENTIONS_BITS_COMPLETION_ABORT (1UL<<16) 13793 #define TXPF_ATTENTIONS_BITS_HOST_COALESCE_ABORT (1UL<<17) 13794 #define TXPF_ATTENTIONS_BITS_MAILBOX_QUEUE_ABORT (1UL<<18) 13795 #define TXPF_ATTENTIONS_BITS_CONTEXT_ABORT (1UL<<19) 13796 #define TXPF_ATTENTIONS_BITS_CMD_SCHEDULER_ABORT (1UL<<20) 13797 #define TXPF_ATTENTIONS_BITS_CMD_PROCESSOR_ABORT (1UL<<21) 13798 #define TXPF_ATTENTIONS_BITS_MGMT_PROCESSOR_ABORT (1UL<<22) 13799 #define TXPF_ATTENTIONS_BITS_MAC_ABORT (1UL<<23) 13800 #define TXPF_ATTENTIONS_BITS_TIMER_ABORT (1UL<<24) 13801 #define TXPF_ATTENTIONS_BITS_DMAE_ABORT (1UL<<25) 13802 #define TXPF_ATTENTIONS_BITS_FLSH_ABORT (1UL<<26) 13803 #define TXPF_ATTENTIONS_BITS_GRC_ABORT (1UL<<27) 13804 #define TXPF_ATTENTIONS_BITS_PARITY_ERROR (1UL<<31) 13805 13806 u32_t txpf_event_enable; 13807 u32_t txpf_attention_enable; 13808 u32_t txpf_fio_status; 13809 #define TXPF_FIO_STATUS_ENABLED (1UL<<0) 13810 #define TXPF_FIO_STATUS_FORCE_ENA (1UL<<1) 13811 13812 u32_t txpf_l2_compatibility; 13813 #define TXPF_L2_COMPATIBILITY_CTX_OFFSET (0x1ffUL<<3) 13814 #define TXPF_L2_COMPATIBILITY_COMP_ENABLE (1UL<<31) 13815 u32_t unused_0[2]; 13816 13817 u32_t txpf_ctx_window_cid1; 13818 #define TXPF_CTX_WINDOW_CID1_LOCK_TYPE (0x7UL<<0) 13819 #define TXPF_CTX_WINDOW_CID1_LOCK_TYPE_VOID (0UL<<0) 13820 #define TXPF_CTX_WINDOW_CID1_LOCK_TYPE_PROTOCOL (1UL<<0) 13821 #define TXPF_CTX_WINDOW_CID1_LOCK_TYPE_TX (2UL<<0) 13822 #define TXPF_CTX_WINDOW_CID1_LOCK_TYPE_TIMER (4UL<<0) 13823 #define TXPF_CTX_WINDOW_CID1_LOCK_TYPE_COMPLETE (7UL<<0) 13824 #define TXPF_CTX_WINDOW_CID1_VALUE (0x3fffUL<<7) 13825 #define TXPF_CTX_WINDOW_CID1_MOD_USAGE_CNT (0x3UL<<24) 13826 #define TXPF_CTX_WINDOW_CID1_MOD_USAGE_CNT_00 (0UL<<24) 13827 #define TXPF_CTX_WINDOW_CID1_MOD_USAGE_CNT_01 (1UL<<24) 13828 #define TXPF_CTX_WINDOW_CID1_MOD_USAGE_CNT_10 (2UL<<24) 13829 #define TXPF_CTX_WINDOW_CID1_MOD_USAGE_CNT_11 (3UL<<24) 13830 #define TXPF_CTX_WINDOW_CID1_LOCK_GRANTED (1UL<<26) 13831 #define TXPF_CTX_WINDOW_CID1_LOCK_MODE (0x3UL<<27) 13832 #define TXPF_CTX_WINDOW_CID1_LOCK_MODE_UNLOCK (0UL<<27) 13833 #define TXPF_CTX_WINDOW_CID1_LOCK_MODE_IMMEDIATE (1UL<<27) 13834 #define TXPF_CTX_WINDOW_CID1_LOCK_MODE_SURE (2UL<<27) 13835 #define TXPF_CTX_WINDOW_CID1_NO_EXT_ACC (1UL<<29) 13836 #define TXPF_CTX_WINDOW_CID1_LOCK_STATUS (1UL<<30) 13837 #define TXPF_CTX_WINDOW_CID1_LOCK_REQ (1UL<<31) 13838 13839 u32_t txpf_ctx_window_cid2; 13840 #define TXPF_CTX_WINDOW_CID2_LOCK_TYPE (0x7UL<<0) 13841 #define TXPF_CTX_WINDOW_CID2_LOCK_TYPE_VOID (0UL<<0) 13842 #define TXPF_CTX_WINDOW_CID2_LOCK_TYPE_PROTOCOL (1UL<<0) 13843 #define TXPF_CTX_WINDOW_CID2_LOCK_TYPE_TX (2UL<<0) 13844 #define TXPF_CTX_WINDOW_CID2_LOCK_TYPE_TIMER (4UL<<0) 13845 #define TXPF_CTX_WINDOW_CID2_LOCK_TYPE_COMPLETE (7UL<<0) 13846 #define TXPF_CTX_WINDOW_CID2_VALUE (0x3fffUL<<7) 13847 #define TXPF_CTX_WINDOW_CID2_MOD_USAGE_CNT (0x3UL<<24) 13848 #define TXPF_CTX_WINDOW_CID2_MOD_USAGE_CNT_00 (0UL<<24) 13849 #define TXPF_CTX_WINDOW_CID2_MOD_USAGE_CNT_01 (1UL<<24) 13850 #define TXPF_CTX_WINDOW_CID2_MOD_USAGE_CNT_10 (2UL<<24) 13851 #define TXPF_CTX_WINDOW_CID2_MOD_USAGE_CNT_11 (3UL<<24) 13852 #define TXPF_CTX_WINDOW_CID2_LOCK_GRANTED (1UL<<26) 13853 #define TXPF_CTX_WINDOW_CID2_LOCK_MODE (0x3UL<<27) 13854 #define TXPF_CTX_WINDOW_CID2_LOCK_MODE_UNLOCK (0UL<<27) 13855 #define TXPF_CTX_WINDOW_CID2_LOCK_MODE_IMMEDIATE (1UL<<27) 13856 #define TXPF_CTX_WINDOW_CID2_LOCK_MODE_SURE (2UL<<27) 13857 #define TXPF_CTX_WINDOW_CID2_NO_EXT_ACC (1UL<<29) 13858 #define TXPF_CTX_WINDOW_CID2_LOCK_STATUS (1UL<<30) 13859 #define TXPF_CTX_WINDOW_CID2_LOCK_REQ (1UL<<31) 13860 13861 u32_t txpf_ctx_window_cid3; 13862 #define TXPF_CTX_WINDOW_CID3_LOCK_TYPE (0x7UL<<0) 13863 #define TXPF_CTX_WINDOW_CID3_LOCK_TYPE_VOID (0UL<<0) 13864 #define TXPF_CTX_WINDOW_CID3_LOCK_TYPE_PROTOCOL (1UL<<0) 13865 #define TXPF_CTX_WINDOW_CID3_LOCK_TYPE_TX (2UL<<0) 13866 #define TXPF_CTX_WINDOW_CID3_LOCK_TYPE_TIMER (4UL<<0) 13867 #define TXPF_CTX_WINDOW_CID3_LOCK_TYPE_COMPLETE (7UL<<0) 13868 #define TXPF_CTX_WINDOW_CID3_VALUE (0x3fffUL<<7) 13869 #define TXPF_CTX_WINDOW_CID3_MOD_USAGE_CNT (0x3UL<<24) 13870 #define TXPF_CTX_WINDOW_CID3_MOD_USAGE_CNT_00 (0UL<<24) 13871 #define TXPF_CTX_WINDOW_CID3_MOD_USAGE_CNT_01 (1UL<<24) 13872 #define TXPF_CTX_WINDOW_CID3_MOD_USAGE_CNT_10 (2UL<<24) 13873 #define TXPF_CTX_WINDOW_CID3_MOD_USAGE_CNT_11 (3UL<<24) 13874 #define TXPF_CTX_WINDOW_CID3_LOCK_GRANTED (1UL<<26) 13875 #define TXPF_CTX_WINDOW_CID3_LOCK_MODE (0x3UL<<27) 13876 #define TXPF_CTX_WINDOW_CID3_LOCK_MODE_UNLOCK (0UL<<27) 13877 #define TXPF_CTX_WINDOW_CID3_LOCK_MODE_IMMEDIATE (1UL<<27) 13878 #define TXPF_CTX_WINDOW_CID3_LOCK_MODE_SURE (2UL<<27) 13879 #define TXPF_CTX_WINDOW_CID3_NO_EXT_ACC (1UL<<29) 13880 #define TXPF_CTX_WINDOW_CID3_LOCK_STATUS (1UL<<30) 13881 #define TXPF_CTX_WINDOW_CID3_LOCK_REQ (1UL<<31) 13882 13883 u32_t txpf_ctx_window_cid4; 13884 #define TXPF_CTX_WINDOW_CID4_LOCK_TYPE (0x7UL<<0) 13885 #define TXPF_CTX_WINDOW_CID4_LOCK_TYPE_VOID (0UL<<0) 13886 #define TXPF_CTX_WINDOW_CID4_LOCK_TYPE_PROTOCOL (1UL<<0) 13887 #define TXPF_CTX_WINDOW_CID4_LOCK_TYPE_TX (2UL<<0) 13888 #define TXPF_CTX_WINDOW_CID4_LOCK_TYPE_TIMER (4UL<<0) 13889 #define TXPF_CTX_WINDOW_CID4_LOCK_TYPE_COMPLETE (7UL<<0) 13890 #define TXPF_CTX_WINDOW_CID4_VALUE (0x3fffUL<<7) 13891 #define TXPF_CTX_WINDOW_CID4_MOD_USAGE_CNT (0x3UL<<24) 13892 #define TXPF_CTX_WINDOW_CID4_MOD_USAGE_CNT_00 (0UL<<24) 13893 #define TXPF_CTX_WINDOW_CID4_MOD_USAGE_CNT_01 (1UL<<24) 13894 #define TXPF_CTX_WINDOW_CID4_MOD_USAGE_CNT_10 (2UL<<24) 13895 #define TXPF_CTX_WINDOW_CID4_MOD_USAGE_CNT_11 (3UL<<24) 13896 #define TXPF_CTX_WINDOW_CID4_LOCK_GRANTED (1UL<<26) 13897 #define TXPF_CTX_WINDOW_CID4_LOCK_MODE (0x3UL<<27) 13898 #define TXPF_CTX_WINDOW_CID4_LOCK_MODE_UNLOCK (0UL<<27) 13899 #define TXPF_CTX_WINDOW_CID4_LOCK_MODE_IMMEDIATE (1UL<<27) 13900 #define TXPF_CTX_WINDOW_CID4_LOCK_MODE_SURE (2UL<<27) 13901 #define TXPF_CTX_WINDOW_CID4_NO_EXT_ACC (1UL<<29) 13902 #define TXPF_CTX_WINDOW_CID4_LOCK_STATUS (1UL<<30) 13903 #define TXPF_CTX_WINDOW_CID4_LOCK_REQ (1UL<<31) 13904 u32_t unused_1[4]; 13905 13906 u32_t txpf_txp_hc_inc_stat[8]; 13907 u32_t unused_2[4]; 13908 u32_t txpf_free_counter_value; 13909 u32_t txpf_timer_retran_value; 13910 u16_t txpf_timer_rxpush_value; 13911 u16_t txpf_timer_delayack_value; 13912 u16_t txpf_timer_keepalive_value; 13913 u16_t txpf_timer_nagle_value; 13914 u32_t txpf_bdcache_window_cid; 13915 #define TXPF_BDCACHE_WINDOW_CID_HIT (1UL<<0) 13916 #define TXPF_BDCACHE_WINDOW_CID_RDY (1UL<<1) 13917 #define TXPF_BDCACHE_WINDOW_CID_CID_VALUE (0x3fffUL<<7) 13918 #define TXPF_BDCACHE_WINDOW_CID_CMD_VALUE (0xffUL<<24) 13919 13920 u32_t txpf_bdcache_window_idx; 13921 #define TXPF_BDCACHE_WINDOW_IDX_BDCACHE_WINDOW_IDX_VALUE (0xffffUL<<0) 13922 u16_t unused_3; 13923 13924 u16_t txpf_tas_txp_thbuf_cons; 13925 #define TXPF_TAS_TXP_THBUF_CONS_VALUE (0xfff<<3) 13926 u32_t unused_4; 13927 13928 u32_t txpf_ctx_window_cid5; 13929 #define TXPF_CTX_WINDOW_CID5_LOCK_TYPE (0x7UL<<0) 13930 #define TXPF_CTX_WINDOW_CID5_LOCK_TYPE_VOID (0UL<<0) 13931 #define TXPF_CTX_WINDOW_CID5_LOCK_TYPE_PROTOCOL (1UL<<0) 13932 #define TXPF_CTX_WINDOW_CID5_LOCK_TYPE_TX (2UL<<0) 13933 #define TXPF_CTX_WINDOW_CID5_LOCK_TYPE_TIMER (4UL<<0) 13934 #define TXPF_CTX_WINDOW_CID5_LOCK_TYPE_COMPLETE (7UL<<0) 13935 #define TXPF_CTX_WINDOW_CID5_VALUE (0x3fffUL<<7) 13936 #define TXPF_CTX_WINDOW_CID5_MOD_USAGE_CNT (0x3UL<<24) 13937 #define TXPF_CTX_WINDOW_CID5_MOD_USAGE_CNT_00 (0UL<<24) 13938 #define TXPF_CTX_WINDOW_CID5_MOD_USAGE_CNT_01 (1UL<<24) 13939 #define TXPF_CTX_WINDOW_CID5_MOD_USAGE_CNT_10 (2UL<<24) 13940 #define TXPF_CTX_WINDOW_CID5_MOD_USAGE_CNT_11 (3UL<<24) 13941 #define TXPF_CTX_WINDOW_CID5_LOCK_GRANTED (1UL<<26) 13942 #define TXPF_CTX_WINDOW_CID5_LOCK_MODE (0x3UL<<27) 13943 #define TXPF_CTX_WINDOW_CID5_LOCK_MODE_UNLOCK (0UL<<27) 13944 #define TXPF_CTX_WINDOW_CID5_LOCK_MODE_IMMEDIATE (1UL<<27) 13945 #define TXPF_CTX_WINDOW_CID5_LOCK_MODE_SURE (2UL<<27) 13946 #define TXPF_CTX_WINDOW_CID5_NO_EXT_ACC (1UL<<29) 13947 #define TXPF_CTX_WINDOW_CID5_LOCK_STATUS (1UL<<30) 13948 #define TXPF_CTX_WINDOW_CID5_LOCK_REQ (1UL<<31) 13949 13950 u32_t txpf_ctx_window_cid6; 13951 #define TXPF_CTX_WINDOW_CID6_LOCK_TYPE (0x7UL<<0) 13952 #define TXPF_CTX_WINDOW_CID6_LOCK_TYPE_VOID (0UL<<0) 13953 #define TXPF_CTX_WINDOW_CID6_LOCK_TYPE_PROTOCOL (1UL<<0) 13954 #define TXPF_CTX_WINDOW_CID6_LOCK_TYPE_TX (2UL<<0) 13955 #define TXPF_CTX_WINDOW_CID6_LOCK_TYPE_TIMER (4UL<<0) 13956 #define TXPF_CTX_WINDOW_CID6_LOCK_TYPE_COMPLETE (7UL<<0) 13957 #define TXPF_CTX_WINDOW_CID6_VALUE (0x3fffUL<<7) 13958 #define TXPF_CTX_WINDOW_CID6_MOD_USAGE_CNT (0x3UL<<24) 13959 #define TXPF_CTX_WINDOW_CID6_MOD_USAGE_CNT_00 (0UL<<24) 13960 #define TXPF_CTX_WINDOW_CID6_MOD_USAGE_CNT_01 (1UL<<24) 13961 #define TXPF_CTX_WINDOW_CID6_MOD_USAGE_CNT_10 (2UL<<24) 13962 #define TXPF_CTX_WINDOW_CID6_MOD_USAGE_CNT_11 (3UL<<24) 13963 #define TXPF_CTX_WINDOW_CID6_LOCK_GRANTED (1UL<<26) 13964 #define TXPF_CTX_WINDOW_CID6_LOCK_MODE (0x3UL<<27) 13965 #define TXPF_CTX_WINDOW_CID6_LOCK_MODE_UNLOCK (0UL<<27) 13966 #define TXPF_CTX_WINDOW_CID6_LOCK_MODE_IMMEDIATE (1UL<<27) 13967 #define TXPF_CTX_WINDOW_CID6_LOCK_MODE_SURE (2UL<<27) 13968 #define TXPF_CTX_WINDOW_CID6_NO_EXT_ACC (1UL<<29) 13969 #define TXPF_CTX_WINDOW_CID6_LOCK_STATUS (1UL<<30) 13970 #define TXPF_CTX_WINDOW_CID6_LOCK_REQ (1UL<<31) 13971 u32_t unused_5[26]; 13972 13973 u32_t txpf_txpq_cid; 13974 u32_t txpf_txpq_bseq; 13975 u8_t txpf_txpq_flags_flags; 13976 #define TXPF_TXPQ_FLAGS_FLAGS_QUICK_CID_ENA (1<<0) 13977 #define TXPF_TXPQ_FLAGS_FLAGS_RSVD (1<<1) 13978 #define TXPF_TXPQ_FLAGS_FLAGS_BORROWED (1<<2) 13979 #define TXPF_TXPQ_FLAGS_FLAGS_BSEQ_INVLD (1<<3) 13980 #define TXPF_TXPQ_FLAGS_FLAGS_S_RETRAN (1<<4) 13981 #define TXPF_TXPQ_FLAGS_FLAGS_WORKAROUND (0x3<<5) 13982 13983 u8_t txpf_txpq_cmd; 13984 u8_t txpf_txpq_xnum; 13985 u8_t txpf_txpq_protocol_flags; 13986 u32_t txpf_txpq_tcp_rcv_nxt; 13987 #define TXPF_TXPQ_TCP_RCV_NXT_VALUE (0xffffffffUL<<0) 13988 13989 u8_t txpf_tcmd_fnum; 13990 #define TXPF_TCMD_FNUM_VALUE (0x3f<<0) 13991 u8_t unused_6; 13992 u16_t unused_7; 13993 u32_t unused_8[9]; 13994 13995 u32_t txpf_txpq_ftq_cmd; 13996 #define TXPF_TXPQ_FTQ_CMD_TXPQ_FTQ_CMD_POP (1UL<<30) 13997 u32_t unused_9; 13998 13999 u32_t txpf_tdmaq_cid; 14000 u16_t txpf_tdmaq_bidx; 14001 u16_t txpf_tdmaq_boff; 14002 u32_t txpf_tdmaq_bseq; 14003 u32_t txpf_tdmaq_snd_next; 14004 u8_t txpf_tdmaq_cmd; 14005 u8_t txpf_tdmaq_xnum; 14006 u8_t txpf_tdmaq_knum; 14007 u8_t unused_10; 14008 u32_t txpf_tdmaq_flags_flags; 14009 #define TXPF_TDMAQ_FLAGS_FLAGS_PLUS_TWO (1UL<<0) 14010 #define TXPF_TDMAQ_FLAGS_FLAGS_TCP_UDP_CKSUM (1UL<<1) 14011 #define TXPF_TDMAQ_FLAGS_FLAGS_IP_CKSUM (1UL<<2) 14012 #define TXPF_TDMAQ_FLAGS_FLAGS_INCR_CMD (1UL<<3) 14013 #define TXPF_TDMAQ_FLAGS_FLAGS_COAL_NOW (1UL<<4) 14014 #define TXPF_TDMAQ_FLAGS_FLAGS_DONT_GEN_CRC (1UL<<5) 14015 #define TXPF_TDMAQ_FLAGS_FLAGS_LAST_PKT (1UL<<6) 14016 #define TXPF_TDMAQ_FLAGS_FLAGS_PKT_FRAG (1UL<<7) 14017 #define TXPF_TDMAQ_FLAGS_FLAGS_QUICK_CID_ENA (1UL<<9) 14018 #define TXPF_TDMAQ_FLAGS_FLAGS_RSVD_FUTURE (0x3UL<<10) 14019 #define TXPF_TDMAQ_FLAGS_FLAGS_L5_PAGE_MODE (1UL<<12) 14020 #define TXPF_TDMAQ_FLAGS_FLAGS_COMPLETE (1UL<<13) 14021 #define TXPF_TDMAQ_FLAGS_FLAGS_RETRAN (1UL<<14) 14022 #define TXPF_TDMAQ_FLAGS_FLAGS_END_PADDING (0xfUL<<16) 14023 #define TXPF_TDMAQ_FLAGS_FLAGS_USAGE_CNT (1UL<<20) 14024 #define TXPF_TDMAQ_FLAGS_FLAGS_USAGE_CNT_AUTODECREMENT (0UL<<20) 14025 #define TXPF_TDMAQ_FLAGS_FLAGS_USAGE_CNT_DONOTDECREMENT (1UL<<20) 14026 #define TXPF_TDMAQ_FLAGS_FLAGS_BSEQ_INVLD (1UL<<21) 14027 #define TXPF_TDMAQ_FLAGS_FLAGS_WORK_AROUND (0x3UL<<22) 14028 #define TXPF_TDMAQ_FLAGS_FLAGS_HOLE_SZ (0x3UL<<25) 14029 #define TXPF_TDMAQ_FLAGS_FLAGS_HOLE_SZ_4 (0UL<<25) 14030 #define TXPF_TDMAQ_FLAGS_FLAGS_HOLE_SZ_8 (1UL<<25) 14031 #define TXPF_TDMAQ_FLAGS_FLAGS_HOLE_SZ_12 (2UL<<25) 14032 #define TXPF_TDMAQ_FLAGS_FLAGS_HOLE_SZ_16 (3UL<<25) 14033 #define TXPF_TDMAQ_FLAGS_FLAGS_HOLE0 (1UL<<28) 14034 #define TXPF_TDMAQ_FLAGS_FLAGS_HOLE1 (1UL<<29) 14035 #define TXPF_TDMAQ_FLAGS_FLAGS_HOLE2 (1UL<<30) 14036 14037 u16_t txpf_tdmaq_nbytes; 14038 u16_t txpf_tdmaq_hole0_boff; 14039 u16_t txpf_tdmaq_hole1_boff; 14040 u16_t txpf_tdmaq_hole2_boff; 14041 u32_t txpf_tdmaq_hole0_fill; 14042 u32_t txpf_tdmaq_hole1_fill; 14043 u32_t txpf_tdmaq_hole2_fill; 14044 u8_t txpf_tdmaq_tcmd_fnum; 14045 #define TXPF_TDMAQ_TCMD_FNUM_VALUE (0x3f<<0) 14046 14047 u8_t txpf_tdmaq_txp_act_cmd; 14048 u16_t unused_11; 14049 u32_t unused_12[2]; 14050 u32_t txpf_tdmaq_ftq_cmd; 14051 #define TXPF_TDMAQ_FTQ_CMD_CPY_DATA (1UL<<11) 14052 #define TXPF_TDMAQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) 14053 #define TXPF_TDMAQ_FTQ_CMD_ADD_DATA (1UL<<28) 14054 #define TXPF_TDMAQ_FTQ_CMD_BUSY (1UL<<31) 14055 u32_t unused_13[417]; 14056 14057 u32_t txpf_burst_base0; 14058 #define TXPF_BURST_BASE0_BASE_VAL0 (0x3fffUL<<7) 14059 14060 u32_t txpf_burst_base1; 14061 #define TXPF_BURST_BASE1_BASE_VAL1 (0x3fffUL<<7) 14062 14063 u32_t txpf_burst_base2; 14064 #define TXPF_BURST_BASE2_BASE_VAL2 (0x3fffUL<<7) 14065 14066 u32_t txpf_burst_base3; 14067 #define TXPF_BURST_BASE3_BASE_VAL3 (0x3fffUL<<7) 14068 14069 u32_t txpf_burst_cmd0; 14070 #define TXPF_BURST_CMD0_FTQ_SEL (0x3UL<<0) 14071 #define TXPF_BURST_CMD0_FTQ_SEL_0 (0UL<<0) 14072 #define TXPF_BURST_CMD0_FTQ_SEL_1 (1UL<<0) 14073 #define TXPF_BURST_CMD0_FTQ_SEL_2 (2UL<<0) 14074 #define TXPF_BURST_CMD0_FTQ_SEL_3 (3UL<<0) 14075 #define TXPF_BURST_CMD0_BUSY (1UL<<2) 14076 #define TXPF_BURST_CMD0_OFFSET (0x1ffUL<<3) 14077 #define TXPF_BURST_CMD0_BASE_REG_SEL (1UL<<23) 14078 #define TXPF_BURST_CMD0_MOD_USAGE_CNT (0x3UL<<24) 14079 #define TXPF_BURST_CMD0_MOD_USAGE_CNT_00 (0UL<<24) 14080 #define TXPF_BURST_CMD0_MOD_USAGE_CNT_01 (1UL<<24) 14081 #define TXPF_BURST_CMD0_MOD_USAGE_CNT_10 (2UL<<24) 14082 #define TXPF_BURST_CMD0_MOD_USAGE_CNT_11 (3UL<<24) 14083 #define TXPF_BURST_CMD0_PREFETCH_SIZE (0x3UL<<26) 14084 #define TXPF_BURST_CMD0_NO_RAM_ACCESS (1UL<<28) 14085 #define TXPF_BURST_CMD0_NO_CACHE (1UL<<29) 14086 #define TXPF_BURST_CMD0_CROSS_BOUNDARY (1UL<<30) 14087 14088 u32_t txpf_burst_cmd1; 14089 #define TXPF_BURST_CMD1_FTQ_SEL (0x3UL<<0) 14090 #define TXPF_BURST_CMD1_FTQ_SEL_0 (0UL<<0) 14091 #define TXPF_BURST_CMD1_FTQ_SEL_1 (1UL<<0) 14092 #define TXPF_BURST_CMD1_FTQ_SEL_2 (2UL<<0) 14093 #define TXPF_BURST_CMD1_FTQ_SEL_3 (3UL<<0) 14094 #define TXPF_BURST_CMD1_BUSY (1UL<<2) 14095 #define TXPF_BURST_CMD1_OFFSET (0x1ffUL<<3) 14096 #define TXPF_BURST_CMD1_BASE_REG_SEL (1UL<<23) 14097 #define TXPF_BURST_CMD1_MOD_USAGE_CNT (0x3UL<<24) 14098 #define TXPF_BURST_CMD1_MOD_USAGE_CNT_00 (0UL<<24) 14099 #define TXPF_BURST_CMD1_MOD_USAGE_CNT_01 (1UL<<24) 14100 #define TXPF_BURST_CMD1_MOD_USAGE_CNT_10 (2UL<<24) 14101 #define TXPF_BURST_CMD1_MOD_USAGE_CNT_11 (3UL<<24) 14102 #define TXPF_BURST_CMD1_PREFETCH_SIZE (0x3UL<<26) 14103 #define TXPF_BURST_CMD1_NO_RAM_ACCESS (1UL<<28) 14104 #define TXPF_BURST_CMD1_NO_CACHE (1UL<<29) 14105 #define TXPF_BURST_CMD1_CROSS_BOUNDARY (1UL<<30) 14106 14107 u32_t txpf_burst_cmd2; 14108 #define TXPF_BURST_CMD2_FTQ_SEL (0x3UL<<0) 14109 #define TXPF_BURST_CMD2_FTQ_SEL_0 (0UL<<0) 14110 #define TXPF_BURST_CMD2_FTQ_SEL_1 (1UL<<0) 14111 #define TXPF_BURST_CMD2_FTQ_SEL_2 (2UL<<0) 14112 #define TXPF_BURST_CMD2_FTQ_SEL_3 (3UL<<0) 14113 #define TXPF_BURST_CMD2_BUSY (1UL<<2) 14114 #define TXPF_BURST_CMD2_OFFSET (0x1ffUL<<3) 14115 #define TXPF_BURST_CMD2_BASE_REG_SEL (1UL<<23) 14116 #define TXPF_BURST_CMD2_MOD_USAGE_CNT (0x3UL<<24) 14117 #define TXPF_BURST_CMD2_MOD_USAGE_CNT_00 (0UL<<24) 14118 #define TXPF_BURST_CMD2_MOD_USAGE_CNT_01 (1UL<<24) 14119 #define TXPF_BURST_CMD2_MOD_USAGE_CNT_10 (2UL<<24) 14120 #define TXPF_BURST_CMD2_MOD_USAGE_CNT_11 (3UL<<24) 14121 #define TXPF_BURST_CMD2_PREFETCH_SIZE (0x3UL<<26) 14122 #define TXPF_BURST_CMD2_NO_RAM_ACCESS (1UL<<28) 14123 #define TXPF_BURST_CMD2_NO_CACHE (1UL<<29) 14124 #define TXPF_BURST_CMD2_CROSS_BOUNDARY (1UL<<30) 14125 14126 u32_t txpf_burst_cmd3; 14127 #define TXPF_BURST_CMD3_FTQ_SEL (0x3UL<<0) 14128 #define TXPF_BURST_CMD3_FTQ_SEL_0 (0UL<<0) 14129 #define TXPF_BURST_CMD3_FTQ_SEL_1 (1UL<<0) 14130 #define TXPF_BURST_CMD3_FTQ_SEL_2 (2UL<<0) 14131 #define TXPF_BURST_CMD3_FTQ_SEL_3 (3UL<<0) 14132 #define TXPF_BURST_CMD3_BUSY (1UL<<2) 14133 #define TXPF_BURST_CMD3_OFFSET (0x1ffUL<<3) 14134 #define TXPF_BURST_CMD3_BASE_REG_SEL (1UL<<23) 14135 #define TXPF_BURST_CMD3_MOD_USAGE_CNT (0x3UL<<24) 14136 #define TXPF_BURST_CMD3_MOD_USAGE_CNT_00 (0UL<<24) 14137 #define TXPF_BURST_CMD3_MOD_USAGE_CNT_01 (1UL<<24) 14138 #define TXPF_BURST_CMD3_MOD_USAGE_CNT_10 (2UL<<24) 14139 #define TXPF_BURST_CMD3_MOD_USAGE_CNT_11 (3UL<<24) 14140 #define TXPF_BURST_CMD3_PREFETCH_SIZE (0x3UL<<26) 14141 #define TXPF_BURST_CMD3_NO_RAM_ACCESS (1UL<<28) 14142 #define TXPF_BURST_CMD3_NO_CACHE (1UL<<29) 14143 #define TXPF_BURST_CMD3_CROSS_BOUNDARY (1UL<<30) 14144 14145 u32_t txpf_burst_cmd4; 14146 #define TXPF_BURST_CMD4_FTQ_SEL (0x3UL<<0) 14147 #define TXPF_BURST_CMD4_FTQ_SEL_0 (0UL<<0) 14148 #define TXPF_BURST_CMD4_FTQ_SEL_1 (1UL<<0) 14149 #define TXPF_BURST_CMD4_FTQ_SEL_2 (2UL<<0) 14150 #define TXPF_BURST_CMD4_FTQ_SEL_3 (3UL<<0) 14151 #define TXPF_BURST_CMD4_BUSY (1UL<<2) 14152 #define TXPF_BURST_CMD4_OFFSET (0x1ffUL<<3) 14153 #define TXPF_BURST_CMD4_BASE_REG_SEL (1UL<<23) 14154 #define TXPF_BURST_CMD4_MOD_USAGE_CNT (0x3UL<<24) 14155 #define TXPF_BURST_CMD4_MOD_USAGE_CNT_00 (0UL<<24) 14156 #define TXPF_BURST_CMD4_MOD_USAGE_CNT_01 (1UL<<24) 14157 #define TXPF_BURST_CMD4_MOD_USAGE_CNT_10 (2UL<<24) 14158 #define TXPF_BURST_CMD4_MOD_USAGE_CNT_11 (3UL<<24) 14159 #define TXPF_BURST_CMD4_PREFETCH_SIZE (0x3UL<<26) 14160 #define TXPF_BURST_CMD4_NO_RAM_ACCESS (1UL<<28) 14161 #define TXPF_BURST_CMD4_NO_CACHE (1UL<<29) 14162 #define TXPF_BURST_CMD4_CROSS_BOUNDARY (1UL<<30) 14163 14164 u32_t txpf_burst_cmd5; 14165 #define TXPF_BURST_CMD5_FTQ_SEL (0x3UL<<0) 14166 #define TXPF_BURST_CMD5_FTQ_SEL_0 (0UL<<0) 14167 #define TXPF_BURST_CMD5_FTQ_SEL_1 (1UL<<0) 14168 #define TXPF_BURST_CMD5_FTQ_SEL_2 (2UL<<0) 14169 #define TXPF_BURST_CMD5_FTQ_SEL_3 (3UL<<0) 14170 #define TXPF_BURST_CMD5_BUSY (1UL<<2) 14171 #define TXPF_BURST_CMD5_OFFSET (0x1ffUL<<3) 14172 #define TXPF_BURST_CMD5_BASE_REG_SEL (1UL<<23) 14173 #define TXPF_BURST_CMD5_MOD_USAGE_CNT (0x3UL<<24) 14174 #define TXPF_BURST_CMD5_MOD_USAGE_CNT_00 (0UL<<24) 14175 #define TXPF_BURST_CMD5_MOD_USAGE_CNT_01 (1UL<<24) 14176 #define TXPF_BURST_CMD5_MOD_USAGE_CNT_10 (2UL<<24) 14177 #define TXPF_BURST_CMD5_MOD_USAGE_CNT_11 (3UL<<24) 14178 #define TXPF_BURST_CMD5_PREFETCH_SIZE (0x3UL<<26) 14179 #define TXPF_BURST_CMD5_NO_RAM_ACCESS (1UL<<28) 14180 #define TXPF_BURST_CMD5_NO_CACHE (1UL<<29) 14181 #define TXPF_BURST_CMD5_CROSS_BOUNDARY (1UL<<30) 14182 14183 u32_t txpf_burst_cmd6; 14184 #define TXPF_BURST_CMD6_FTQ_SEL (0x3UL<<0) 14185 #define TXPF_BURST_CMD6_FTQ_SEL_0 (0UL<<0) 14186 #define TXPF_BURST_CMD6_FTQ_SEL_1 (1UL<<0) 14187 #define TXPF_BURST_CMD6_FTQ_SEL_2 (2UL<<0) 14188 #define TXPF_BURST_CMD6_FTQ_SEL_3 (3UL<<0) 14189 #define TXPF_BURST_CMD6_BUSY (1UL<<2) 14190 #define TXPF_BURST_CMD6_OFFSET (0x1ffUL<<3) 14191 #define TXPF_BURST_CMD6_BASE_REG_SEL (1UL<<23) 14192 #define TXPF_BURST_CMD6_MOD_USAGE_CNT (0x3UL<<24) 14193 #define TXPF_BURST_CMD6_MOD_USAGE_CNT_00 (0UL<<24) 14194 #define TXPF_BURST_CMD6_MOD_USAGE_CNT_01 (1UL<<24) 14195 #define TXPF_BURST_CMD6_MOD_USAGE_CNT_10 (2UL<<24) 14196 #define TXPF_BURST_CMD6_MOD_USAGE_CNT_11 (3UL<<24) 14197 #define TXPF_BURST_CMD6_PREFETCH_SIZE (0x3UL<<26) 14198 #define TXPF_BURST_CMD6_NO_RAM_ACCESS (1UL<<28) 14199 #define TXPF_BURST_CMD6_NO_CACHE (1UL<<29) 14200 #define TXPF_BURST_CMD6_CROSS_BOUNDARY (1UL<<30) 14201 14202 u32_t txpf_burst_cmd7; 14203 #define TXPF_BURST_CMD7_FTQ_SEL (0x3UL<<0) 14204 #define TXPF_BURST_CMD7_FTQ_SEL_0 (0UL<<0) 14205 #define TXPF_BURST_CMD7_FTQ_SEL_1 (1UL<<0) 14206 #define TXPF_BURST_CMD7_FTQ_SEL_2 (2UL<<0) 14207 #define TXPF_BURST_CMD7_FTQ_SEL_3 (3UL<<0) 14208 #define TXPF_BURST_CMD7_BUSY (1UL<<2) 14209 #define TXPF_BURST_CMD7_OFFSET (0x1ffUL<<3) 14210 #define TXPF_BURST_CMD7_BASE_REG_SEL (1UL<<23) 14211 #define TXPF_BURST_CMD7_MOD_USAGE_CNT (0x3UL<<24) 14212 #define TXPF_BURST_CMD7_MOD_USAGE_CNT_00 (0UL<<24) 14213 #define TXPF_BURST_CMD7_MOD_USAGE_CNT_01 (1UL<<24) 14214 #define TXPF_BURST_CMD7_MOD_USAGE_CNT_10 (2UL<<24) 14215 #define TXPF_BURST_CMD7_MOD_USAGE_CNT_11 (3UL<<24) 14216 #define TXPF_BURST_CMD7_PREFETCH_SIZE (0x3UL<<26) 14217 #define TXPF_BURST_CMD7_NO_RAM_ACCESS (1UL<<28) 14218 #define TXPF_BURST_CMD7_NO_CACHE (1UL<<29) 14219 #define TXPF_BURST_CMD7_CROSS_BOUNDARY (1UL<<30) 14220 14221 u32_t txpf_ctx_cmd; 14222 #define TXPF_CTX_CMD_NUM_BLOCKS (0x3UL<<0) 14223 #define TXPF_CTX_CMD_OFFSET (0x1ffUL<<3) 14224 #define TXPF_CTX_CMD_CID_VALUE (0x3fffUL<<12) 14225 #define TXPF_CTX_CMD_PREFETCH_SIZE (0x3UL<<26) 14226 #define TXPF_CTX_CMD_MOD_USAGE_CNT (0x3UL<<28) 14227 #define TXPF_CTX_CMD_MOD_USAGE_CNT_00 (0UL<<28) 14228 #define TXPF_CTX_CMD_MOD_USAGE_CNT_01 (1UL<<28) 14229 #define TXPF_CTX_CMD_MOD_USAGE_CNT_10 (2UL<<28) 14230 #define TXPF_CTX_CMD_MOD_USAGE_CNT_11 (3UL<<28) 14231 u32_t unused_14[51]; 14232 14233 u32_t txpf_burst_data0[16]; 14234 u32_t txpf_burst_data1[16]; 14235 u32_t txpf_burst_data2[16]; 14236 u32_t txpf_burst_data3[16]; 14237 u32_t txpf_burst_data4[16]; 14238 u32_t txpf_burst_data5[16]; 14239 u32_t txpf_burst_data6[16]; 14240 u32_t txpf_burst_data7[16]; 14241 u32_t unused_15[64]; 14242 u32_t txpf_bd_cache_window[6]; 14243 u32_t unused_16[122]; 14244 u32_t txpf_bd_scan_cmd; 14245 #define TXPF_BD_SCAN_CMD_CMD (0xffffffUL<<0) 14246 #define TXPF_BD_SCAN_CMD_CMD_SCAN (0UL<<0) 14247 #define TXPF_BD_SCAN_CMD_CMD_RELOAD (16777213UL<<0) 14248 #define TXPF_BD_SCAN_CMD_PAGE_SIZE (0xfUL<<24) 14249 #define TXPF_BD_SCAN_CMD_CLR_OVERRUN (1UL<<29) 14250 #define TXPF_BD_SCAN_CMD_ACCUM (1UL<<30) 14251 #define TXPF_BD_SCAN_CMD_NO_STOP (1UL<<31) 14252 14253 u32_t txpf_bd_scan_len; 14254 #define TXPF_BD_SCAN_LEN_BD_SCAN_LEN_OVERRUN (1UL<<31) 14255 14256 u16_t txpf_bd_scan_flags; 14257 u16_t txpf_bd_scan_vlan_tag; 14258 u16_t txpf_bd_scan_reserved; 14259 u16_t unused_17; 14260 u16_t txpf_bd_scan_bidx_current; 14261 u16_t txpf_bd_scan_boff_current; 14262 u16_t txpf_bd_scan_bidx_prev; 14263 u16_t txpf_bd_scan_boff_prev; 14264 u32_t txpf_bd_scan_bseq_current; 14265 u32_t txpf_bd_scan_bseq_prev; 14266 u32_t unused_18[3192]; 14267 u32_t txpf_thbuf[4096]; 14268 u32_t unused_19[57344]; 14269 u32_t txpf_ctx_window5[32768]; 14270 u32_t txpf_ctx_window6[32768]; 14271 u32_t txpf_ctx_window1[32768]; 14272 u32_t txpf_ctx_window2[32768]; 14273 u32_t txpf_ctx_window3[32768]; 14274 u32_t txpf_ctx_window4[32768]; 14275 } txp_fio_xi_t; 14276 14277 14278 /* 14279 * tpat_fio definition 14280 * offset: 0x80000000 14281 */ 14282 typedef struct tpat_fio 14283 { 14284 u32_t tpatf_events_bits; 14285 #define TPATF_EVENTS_BITS_GPIO0 (1UL<<15) 14286 #define TPATF_EVENTS_BITS_GPIO1 (1UL<<16) 14287 #define TPATF_EVENTS_BITS_GPIO2 (1UL<<17) 14288 #define TPATF_EVENTS_BITS_GPIO3 (1UL<<18) 14289 14290 u32_t tpatf_attentions_bits; 14291 #define TPATF_ATTENTIONS_BITS_EPB_ERROR (1UL<<30) 14292 14293 u32_t tpatf_event_enable; 14294 u32_t tpatf_attention_enable; 14295 u32_t tpatf_fio_status; 14296 u32_t unused_0[3]; 14297 14298 u32_t tpatf_ctx_window_cid1; 14299 #define TPATF_CTX_WINDOW_CID1_1_LOCK_TYPE (0x7UL<<0) 14300 #define TPATF_CTX_WINDOW_CID1_1_LOCK_TYPE_VOID (0UL<<0) 14301 #define TPATF_CTX_WINDOW_CID1_1_LOCK_TYPE_PROTOCOL (1UL<<0) 14302 #define TPATF_CTX_WINDOW_CID1_1_LOCK_TYPE_TX (2UL<<0) 14303 #define TPATF_CTX_WINDOW_CID1_1_LOCK_TYPE_TIMER (4UL<<0) 14304 #define TPATF_CTX_WINDOW_CID1_1_LOCK_TYPE_COMPLETE (7UL<<0) 14305 #define TPATF_CTX_WINDOW_CID1_1_VALUE (0x3fffUL<<7) 14306 #define TPATF_CTX_WINDOW_CID1_1_LOCK_GRANTED (1UL<<26) 14307 #define TPATF_CTX_WINDOW_CID1_1_LOCK_MODE (0x3UL<<27) 14308 #define TPATF_CTX_WINDOW_CID1_1_LOCK_MODE_UNLOCK (0UL<<27) 14309 #define TPATF_CTX_WINDOW_CID1_1_LOCK_MODE_IMMEDIATE (1UL<<27) 14310 #define TPATF_CTX_WINDOW_CID1_1_LOCK_MODE_SURE (2UL<<27) 14311 #define TPATF_CTX_WINDOW_CID1_1_LOCK_STATUS (1UL<<30) 14312 #define TPATF_CTX_WINDOW_CID1_0_LOCK_REQ (1UL<<31) 14313 14314 u32_t tpatf_ctx_window_cid2; 14315 #define TPATF_CTX_WINDOW_CID2_CTX_WINDOW_CID2_VALUE (0x3fffUL<<7) 14316 14317 u32_t tpatf_ctx_window_cid3; 14318 #define TPATF_CTX_WINDOW_CID3_CTX_WINDOW_CID3_VALUE (0x3fffUL<<7) 14319 14320 u32_t tpatf_ctx_window_cid4; 14321 #define TPATF_CTX_WINDOW_CID4_CTX_WINDOW_CID4_VALUE (0x3fffUL<<7) 14322 u32_t unused_1[4]; 14323 14324 u32_t tpatf_tpat_hc_inc_stat[4]; 14325 u32_t unused_2[8]; 14326 u32_t tpatf_free_counter_value; 14327 u32_t unused_3[3]; 14328 u32_t tpatf_tpat_pq_cons; 14329 14330 u32_t tpatf_tpat_hq_cons; 14331 u32_t unused_4[30]; 14332 14333 u32_t tpatf_tpatq_cid; 14334 u16_t tpatf_tpatq_nbytes; 14335 u8_t tpatf_tpatq_xnum; 14336 u8_t tpatf_tpatq_knum; 14337 u32_t tpatf_tpatq_flags_flags; 14338 #define TPATF_TPATQ_FLAGS_FLAGS_QUICK_CID (0x3UL<<10) 14339 14340 u16_t tpatf_tpatq_raw_chksum; 14341 u16_t unused_5; 14342 u32_t unused_6[10]; 14343 u32_t tpatf_tpatq_ftq_cmd; 14344 u32_t unused_7; 14345 14346 u16_t tpatf_tasq_hdr_skip; 14347 u16_t tpatf_tasq_hdr_post_skip; 14348 u16_t tpatf_tasq_hdr_size; 14349 u16_t tpatf_tasq_payload_skip; 14350 u16_t tpatf_tasq_payload_size; 14351 u16_t tpatf_tasq_flags; 14352 #define TPATF_TASQ_FLAGS_PKT_END (1<<0) 14353 #define TPATF_TASQ_FLAGS_SA_REPLACE (1<<4) 14354 #define TPATF_TASQ_FLAGS_SA_SELECT (0x3<<5) 14355 #define TPATF_TASQ_FLAGS_MGMT_PKT_TAG_TE (0xf<<8) 14356 u32_t unused_8[11]; 14357 14358 u32_t tpatf_tasq_ftq_cmd; 14359 u32_t unused_9[929]; 14360 14361 u32_t tpatf_tpat_crack_cmd; 14362 14363 u16_t tpatf_tpat_crack_ip_offset; 14364 u16_t tpatf_tpat_crack_ip_len; 14365 u16_t tpatf_tpat_crack_tcp_offset; 14366 u16_t tpatf_tpat_crack_tcp_len; 14367 u16_t tpatf_tpat_crack_l5_offset; 14368 u16_t tpatf_tpat_crack_l5_len; 14369 u16_t tpatf_tpat_crack_ip_chksum; 14370 u16_t tpatf_tpat_crack_ip_pseudo_chksum; 14371 u16_t tpatf_tpat_crack_tcp_chksum; 14372 u16_t tpatf_tpat_crack_crc32_1_start; 14373 u32_t tpatf_tpat_crack_crc32_1_seed; 14374 u32_t tpatf_tpat_crack_crc32_1_result; 14375 u32_t tpatf_tpat_crack_crc32_2_result; 14376 u32_t unused_10[3063]; 14377 u32_t tpatf_tx_header_queue[4096]; 14378 u32_t tpatf_tx_payload_queue[16384]; 14379 u32_t unused_11[106496]; 14380 u32_t tpatf_ctx_window1[32768]; 14381 u32_t tpatf_ctx_window2[32768]; 14382 u32_t tpatf_ctx_window3[32768]; 14383 u32_t tpatf_ctx_window4[32768]; 14384 } tpat_fio_t; 14385 14386 14387 /* 14388 * tpat_fio definition 14389 * offset: 0x80000000 14390 */ 14391 typedef struct tpat_fio_xi 14392 { 14393 u32_t tpatf_events_bits; 14394 #define TPATF_EVENTS_BITS_FTQ0_VALID (1UL<<0) 14395 #define TPATF_EVENTS_BITS_FTQ1_VALID (1UL<<1) 14396 #define TPATF_EVENTS_BITS_FTQ2_VALID (1UL<<2) 14397 #define TPATF_EVENTS_BITS_SCANNER_DONE (1UL<<3) 14398 #define TPATF_EVENTS_BITS_DMA_WR_DONE (1UL<<4) 14399 #define TPATF_EVENTS_BITS_DMA_RD_DONE (1UL<<5) 14400 #define TPATF_EVENTS_BITS_CRACKER_DONE (1UL<<6) 14401 #define TPATF_EVENTS_BITS_MULTIPLY_DONE (1UL<<7) 14402 #define TPATF_EVENTS_BITS_EXP_ROM (1UL<<8) 14403 #define TPATF_EVENTS_BITS_VPD (1UL<<9) 14404 #define TPATF_EVENTS_BITS_FLASH (1UL<<10) 14405 #define TPATF_EVENTS_BITS_SMB0 (1UL<<11) 14406 #define TPATF_EVENTS_BITS_RESERVED0 (1UL<<12) 14407 #define TPATF_EVENTS_BITS_RESERVED1 (1UL<<13) 14408 #define TPATF_EVENTS_BITS_RESERVED2 (1UL<<14) 14409 #define TPATF_EVENTS_BITS_GPIO (1UL<<15) 14410 #define TPATF_EVENTS_BITS_SW_TMR_1 (1UL<<19) 14411 #define TPATF_EVENTS_BITS_SW_TMR_2 (1UL<<20) 14412 #define TPATF_EVENTS_BITS_SW_TMR_3 (1UL<<21) 14413 #define TPATF_EVENTS_BITS_SW_TMR_4 (1UL<<22) 14414 #define TPATF_EVENTS_BITS_LINK_CHANGED (1UL<<23) 14415 #define TPATF_EVENTS_BITS_MI_INT (1UL<<25) 14416 #define TPATF_EVENTS_BITS_MI_COMPLETE (1UL<<26) 14417 #define TPATF_EVENTS_BITS_MAIN_PWR_INT (1UL<<27) 14418 #define TPATF_EVENTS_BITS_NOT_ENABLED (1UL<<30) 14419 #define TPATF_EVENTS_BITS_ATTENTIONS_VALID (1UL<<31) 14420 14421 u32_t tpatf_attentions_bits; 14422 #define TPATF_ATTENTIONS_BITS_LINK_STATE (1UL<<0) 14423 #define TPATF_ATTENTIONS_BITS_TX_SCHEDULER_ABORT (1UL<<1) 14424 #define TPATF_ATTENTIONS_BITS_TX_BD_READ_ABORT (1UL<<2) 14425 #define TPATF_ATTENTIONS_BITS_TX_BD_CACHE_ABORT (1UL<<3) 14426 #define TPATF_ATTENTIONS_BITS_TX_PROCESSOR_ABORT (1UL<<4) 14427 #define TPATF_ATTENTIONS_BITS_TX_DMA_ABORT (1UL<<5) 14428 #define TPATF_ATTENTIONS_BITS_TX_PATCHUP_ABORT (1UL<<6) 14429 #define TPATF_ATTENTIONS_BITS_TX_ASSEMBLER_ABORT (1UL<<7) 14430 #define TPATF_ATTENTIONS_BITS_RX_PARSER_MAC_ABORT (1UL<<8) 14431 #define TPATF_ATTENTIONS_BITS_RX_PARSER_CATCHUP_ABORT (1UL<<9) 14432 #define TPATF_ATTENTIONS_BITS_RX_MBUF_ABORT (1UL<<10) 14433 #define TPATF_ATTENTIONS_BITS_RX_LOOKUP_ABORT (1UL<<11) 14434 #define TPATF_ATTENTIONS_BITS_RX_PROCESSOR_ABORT (1UL<<12) 14435 #define TPATF_ATTENTIONS_BITS_RX_V2P_ABORT (1UL<<13) 14436 #define TPATF_ATTENTIONS_BITS_RX_BD_CACHE_ABORT (1UL<<14) 14437 #define TPATF_ATTENTIONS_BITS_RX_DMA_ABORT (1UL<<15) 14438 #define TPATF_ATTENTIONS_BITS_COMPLETION_ABORT (1UL<<16) 14439 #define TPATF_ATTENTIONS_BITS_HOST_COALESCE_ABORT (1UL<<17) 14440 #define TPATF_ATTENTIONS_BITS_MAILBOX_QUEUE_ABORT (1UL<<18) 14441 #define TPATF_ATTENTIONS_BITS_CONTEXT_ABORT (1UL<<19) 14442 #define TPATF_ATTENTIONS_BITS_CMD_SCHEDULER_ABORT (1UL<<20) 14443 #define TPATF_ATTENTIONS_BITS_CMD_PROCESSOR_ABORT (1UL<<21) 14444 #define TPATF_ATTENTIONS_BITS_MGMT_PROCESSOR_ABORT (1UL<<22) 14445 #define TPATF_ATTENTIONS_BITS_MAC_ABORT (1UL<<23) 14446 #define TPATF_ATTENTIONS_BITS_TIMER_ABORT (1UL<<24) 14447 #define TPATF_ATTENTIONS_BITS_DMAE_ABORT (1UL<<25) 14448 #define TPATF_ATTENTIONS_BITS_FLSH_ABORT (1UL<<26) 14449 #define TPATF_ATTENTIONS_BITS_GRC_ABORT (1UL<<27) 14450 #define TPATF_ATTENTIONS_BITS_PARITY_ERROR (1UL<<31) 14451 14452 u32_t tpatf_event_enable; 14453 u32_t tpatf_attention_enable; 14454 u32_t tpatf_fio_status; 14455 #define TPATF_FIO_STATUS_ENABLED (1UL<<0) 14456 #define TPATF_FIO_STATUS_FORCE_ENA (1UL<<1) 14457 u32_t unused_0[3]; 14458 14459 u32_t tpatf_ctx_window_cid1; 14460 #define TPATF_CTX_WINDOW_CID1_LOCK_TYPE (0x7UL<<0) 14461 #define TPATF_CTX_WINDOW_CID1_LOCK_TYPE_VOID (0UL<<0) 14462 #define TPATF_CTX_WINDOW_CID1_LOCK_TYPE_PROTOCOL (1UL<<0) 14463 #define TPATF_CTX_WINDOW_CID1_LOCK_TYPE_TX (2UL<<0) 14464 #define TPATF_CTX_WINDOW_CID1_LOCK_TYPE_TIMER (4UL<<0) 14465 #define TPATF_CTX_WINDOW_CID1_LOCK_TYPE_COMPLETE (7UL<<0) 14466 #define TPATF_CTX_WINDOW_CID1_VALUE (0x3fffUL<<7) 14467 #define TPATF_CTX_WINDOW_CID1_MOD_USAGE_CNT (0x3UL<<24) 14468 #define TPATF_CTX_WINDOW_CID1_MOD_USAGE_CNT_00 (0UL<<24) 14469 #define TPATF_CTX_WINDOW_CID1_MOD_USAGE_CNT_01 (1UL<<24) 14470 #define TPATF_CTX_WINDOW_CID1_MOD_USAGE_CNT_10 (2UL<<24) 14471 #define TPATF_CTX_WINDOW_CID1_MOD_USAGE_CNT_11 (3UL<<24) 14472 #define TPATF_CTX_WINDOW_CID1_LOCK_GRANTED (1UL<<26) 14473 #define TPATF_CTX_WINDOW_CID1_LOCK_MODE (0x3UL<<27) 14474 #define TPATF_CTX_WINDOW_CID1_LOCK_MODE_UNLOCK (0UL<<27) 14475 #define TPATF_CTX_WINDOW_CID1_LOCK_MODE_IMMEDIATE (1UL<<27) 14476 #define TPATF_CTX_WINDOW_CID1_LOCK_MODE_SURE (2UL<<27) 14477 #define TPATF_CTX_WINDOW_CID1_NO_EXT_ACC (1UL<<29) 14478 #define TPATF_CTX_WINDOW_CID1_LOCK_STATUS (1UL<<30) 14479 #define TPATF_CTX_WINDOW_CID1_LOCK_REQ (1UL<<31) 14480 14481 u32_t tpatf_ctx_window_cid2; 14482 #define TPATF_CTX_WINDOW_CID2_LOCK_TYPE (0x7UL<<0) 14483 #define TPATF_CTX_WINDOW_CID2_LOCK_TYPE_VOID (0UL<<0) 14484 #define TPATF_CTX_WINDOW_CID2_LOCK_TYPE_PROTOCOL (1UL<<0) 14485 #define TPATF_CTX_WINDOW_CID2_LOCK_TYPE_TX (2UL<<0) 14486 #define TPATF_CTX_WINDOW_CID2_LOCK_TYPE_TIMER (4UL<<0) 14487 #define TPATF_CTX_WINDOW_CID2_LOCK_TYPE_COMPLETE (7UL<<0) 14488 #define TPATF_CTX_WINDOW_CID2_VALUE (0x3fffUL<<7) 14489 #define TPATF_CTX_WINDOW_CID2_MOD_USAGE_CNT (0x3UL<<24) 14490 #define TPATF_CTX_WINDOW_CID2_MOD_USAGE_CNT_00 (0UL<<24) 14491 #define TPATF_CTX_WINDOW_CID2_MOD_USAGE_CNT_01 (1UL<<24) 14492 #define TPATF_CTX_WINDOW_CID2_MOD_USAGE_CNT_10 (2UL<<24) 14493 #define TPATF_CTX_WINDOW_CID2_MOD_USAGE_CNT_11 (3UL<<24) 14494 #define TPATF_CTX_WINDOW_CID2_LOCK_GRANTED (1UL<<26) 14495 #define TPATF_CTX_WINDOW_CID2_LOCK_MODE (0x3UL<<27) 14496 #define TPATF_CTX_WINDOW_CID2_LOCK_MODE_UNLOCK (0UL<<27) 14497 #define TPATF_CTX_WINDOW_CID2_LOCK_MODE_IMMEDIATE (1UL<<27) 14498 #define TPATF_CTX_WINDOW_CID2_LOCK_MODE_SURE (2UL<<27) 14499 #define TPATF_CTX_WINDOW_CID2_NO_EXT_ACC (1UL<<29) 14500 #define TPATF_CTX_WINDOW_CID2_LOCK_STATUS (1UL<<30) 14501 #define TPATF_CTX_WINDOW_CID2_LOCK_REQ (1UL<<31) 14502 14503 u32_t tpatf_ctx_window_cid3; 14504 #define TPATF_CTX_WINDOW_CID3_LOCK_TYPE (0x7UL<<0) 14505 #define TPATF_CTX_WINDOW_CID3_LOCK_TYPE_VOID (0UL<<0) 14506 #define TPATF_CTX_WINDOW_CID3_LOCK_TYPE_PROTOCOL (1UL<<0) 14507 #define TPATF_CTX_WINDOW_CID3_LOCK_TYPE_TX (2UL<<0) 14508 #define TPATF_CTX_WINDOW_CID3_LOCK_TYPE_TIMER (4UL<<0) 14509 #define TPATF_CTX_WINDOW_CID3_LOCK_TYPE_COMPLETE (7UL<<0) 14510 #define TPATF_CTX_WINDOW_CID3_VALUE (0x3fffUL<<7) 14511 #define TPATF_CTX_WINDOW_CID3_MOD_USAGE_CNT (0x3UL<<24) 14512 #define TPATF_CTX_WINDOW_CID3_MOD_USAGE_CNT_00 (0UL<<24) 14513 #define TPATF_CTX_WINDOW_CID3_MOD_USAGE_CNT_01 (1UL<<24) 14514 #define TPATF_CTX_WINDOW_CID3_MOD_USAGE_CNT_10 (2UL<<24) 14515 #define TPATF_CTX_WINDOW_CID3_MOD_USAGE_CNT_11 (3UL<<24) 14516 #define TPATF_CTX_WINDOW_CID3_LOCK_GRANTED (1UL<<26) 14517 #define TPATF_CTX_WINDOW_CID3_LOCK_MODE (0x3UL<<27) 14518 #define TPATF_CTX_WINDOW_CID3_LOCK_MODE_UNLOCK (0UL<<27) 14519 #define TPATF_CTX_WINDOW_CID3_LOCK_MODE_IMMEDIATE (1UL<<27) 14520 #define TPATF_CTX_WINDOW_CID3_LOCK_MODE_SURE (2UL<<27) 14521 #define TPATF_CTX_WINDOW_CID3_NO_EXT_ACC (1UL<<29) 14522 #define TPATF_CTX_WINDOW_CID3_LOCK_STATUS (1UL<<30) 14523 #define TPATF_CTX_WINDOW_CID3_LOCK_REQ (1UL<<31) 14524 14525 u32_t tpatf_ctx_window_cid4; 14526 #define TPATF_CTX_WINDOW_CID4_LOCK_TYPE (0x7UL<<0) 14527 #define TPATF_CTX_WINDOW_CID4_LOCK_TYPE_VOID (0UL<<0) 14528 #define TPATF_CTX_WINDOW_CID4_LOCK_TYPE_PROTOCOL (1UL<<0) 14529 #define TPATF_CTX_WINDOW_CID4_LOCK_TYPE_TX (2UL<<0) 14530 #define TPATF_CTX_WINDOW_CID4_LOCK_TYPE_TIMER (4UL<<0) 14531 #define TPATF_CTX_WINDOW_CID4_LOCK_TYPE_COMPLETE (7UL<<0) 14532 #define TPATF_CTX_WINDOW_CID4_VALUE (0x3fffUL<<7) 14533 #define TPATF_CTX_WINDOW_CID4_MOD_USAGE_CNT (0x3UL<<24) 14534 #define TPATF_CTX_WINDOW_CID4_MOD_USAGE_CNT_00 (0UL<<24) 14535 #define TPATF_CTX_WINDOW_CID4_MOD_USAGE_CNT_01 (1UL<<24) 14536 #define TPATF_CTX_WINDOW_CID4_MOD_USAGE_CNT_10 (2UL<<24) 14537 #define TPATF_CTX_WINDOW_CID4_MOD_USAGE_CNT_11 (3UL<<24) 14538 #define TPATF_CTX_WINDOW_CID4_LOCK_GRANTED (1UL<<26) 14539 #define TPATF_CTX_WINDOW_CID4_LOCK_MODE (0x3UL<<27) 14540 #define TPATF_CTX_WINDOW_CID4_LOCK_MODE_UNLOCK (0UL<<27) 14541 #define TPATF_CTX_WINDOW_CID4_LOCK_MODE_IMMEDIATE (1UL<<27) 14542 #define TPATF_CTX_WINDOW_CID4_LOCK_MODE_SURE (2UL<<27) 14543 #define TPATF_CTX_WINDOW_CID4_NO_EXT_ACC (1UL<<29) 14544 #define TPATF_CTX_WINDOW_CID4_LOCK_STATUS (1UL<<30) 14545 #define TPATF_CTX_WINDOW_CID4_LOCK_REQ (1UL<<31) 14546 u32_t unused_1[4]; 14547 14548 u32_t tpatf_tpat_hc_inc_stat[4]; 14549 u32_t unused_2[8]; 14550 u32_t tpatf_free_counter_value; 14551 u32_t tpatf_tpat_tx_quick_cons_idx; 14552 #define TPATF_TPAT_TX_QUICK_CONS_IDX_INDEX_VAL (0xffffUL<<0) 14553 #define TPATF_TPAT_TX_QUICK_CONS_IDX_INDEX_NUM (0xfUL<<20) 14554 #define TPATF_TPAT_TX_QUICK_CONS_IDX_COALESCE_NOW (1UL<<30) 14555 #define TPATF_TPAT_TX_QUICK_CONS_IDX_REQ_N (1UL<<31) 14556 u32_t unused_3[2]; 14557 14558 u32_t tpatf_tpat_pq_cons; 14559 #define TPATF_TPAT_PQ_CONS_PQ_CONS_VAL (0x1fffUL<<3) 14560 14561 u32_t tpatf_tpat_hq_cons; 14562 #define TPATF_TPAT_HQ_CONS_HQ_CONS_VAL (0x7ffUL<<3) 14563 u32_t unused_4[2]; 14564 14565 u32_t tpatf_ctx_window_cid5; 14566 #define TPATF_CTX_WINDOW_CID5_LOCK_TYPE (0x7UL<<0) 14567 #define TPATF_CTX_WINDOW_CID5_LOCK_TYPE_VOID (0UL<<0) 14568 #define TPATF_CTX_WINDOW_CID5_LOCK_TYPE_PROTOCOL (1UL<<0) 14569 #define TPATF_CTX_WINDOW_CID5_LOCK_TYPE_TX (2UL<<0) 14570 #define TPATF_CTX_WINDOW_CID5_LOCK_TYPE_TIMER (4UL<<0) 14571 #define TPATF_CTX_WINDOW_CID5_LOCK_TYPE_COMPLETE (7UL<<0) 14572 #define TPATF_CTX_WINDOW_CID5_VALUE (0x3fffUL<<7) 14573 #define TPATF_CTX_WINDOW_CID5_MOD_USAGE_CNT (0x3UL<<24) 14574 #define TPATF_CTX_WINDOW_CID5_MOD_USAGE_CNT_00 (0UL<<24) 14575 #define TPATF_CTX_WINDOW_CID5_MOD_USAGE_CNT_01 (1UL<<24) 14576 #define TPATF_CTX_WINDOW_CID5_MOD_USAGE_CNT_10 (2UL<<24) 14577 #define TPATF_CTX_WINDOW_CID5_MOD_USAGE_CNT_11 (3UL<<24) 14578 #define TPATF_CTX_WINDOW_CID5_LOCK_GRANTED (1UL<<26) 14579 #define TPATF_CTX_WINDOW_CID5_LOCK_MODE (0x3UL<<27) 14580 #define TPATF_CTX_WINDOW_CID5_LOCK_MODE_UNLOCK (0UL<<27) 14581 #define TPATF_CTX_WINDOW_CID5_LOCK_MODE_IMMEDIATE (1UL<<27) 14582 #define TPATF_CTX_WINDOW_CID5_LOCK_MODE_SURE (2UL<<27) 14583 #define TPATF_CTX_WINDOW_CID5_NO_EXT_ACC (1UL<<29) 14584 #define TPATF_CTX_WINDOW_CID5_LOCK_STATUS (1UL<<30) 14585 #define TPATF_CTX_WINDOW_CID5_LOCK_REQ (1UL<<31) 14586 14587 u32_t tpatf_ctx_window_cid6; 14588 #define TPATF_CTX_WINDOW_CID6_LOCK_TYPE (0x7UL<<0) 14589 #define TPATF_CTX_WINDOW_CID6_LOCK_TYPE_VOID (0UL<<0) 14590 #define TPATF_CTX_WINDOW_CID6_LOCK_TYPE_PROTOCOL (1UL<<0) 14591 #define TPATF_CTX_WINDOW_CID6_LOCK_TYPE_TX (2UL<<0) 14592 #define TPATF_CTX_WINDOW_CID6_LOCK_TYPE_TIMER (4UL<<0) 14593 #define TPATF_CTX_WINDOW_CID6_LOCK_TYPE_COMPLETE (7UL<<0) 14594 #define TPATF_CTX_WINDOW_CID6_VALUE (0x3fffUL<<7) 14595 #define TPATF_CTX_WINDOW_CID6_MOD_USAGE_CNT (0x3UL<<24) 14596 #define TPATF_CTX_WINDOW_CID6_MOD_USAGE_CNT_00 (0UL<<24) 14597 #define TPATF_CTX_WINDOW_CID6_MOD_USAGE_CNT_01 (1UL<<24) 14598 #define TPATF_CTX_WINDOW_CID6_MOD_USAGE_CNT_10 (2UL<<24) 14599 #define TPATF_CTX_WINDOW_CID6_MOD_USAGE_CNT_11 (3UL<<24) 14600 #define TPATF_CTX_WINDOW_CID6_LOCK_GRANTED (1UL<<26) 14601 #define TPATF_CTX_WINDOW_CID6_LOCK_MODE (0x3UL<<27) 14602 #define TPATF_CTX_WINDOW_CID6_LOCK_MODE_UNLOCK (0UL<<27) 14603 #define TPATF_CTX_WINDOW_CID6_LOCK_MODE_IMMEDIATE (1UL<<27) 14604 #define TPATF_CTX_WINDOW_CID6_LOCK_MODE_SURE (2UL<<27) 14605 #define TPATF_CTX_WINDOW_CID6_NO_EXT_ACC (1UL<<29) 14606 #define TPATF_CTX_WINDOW_CID6_LOCK_STATUS (1UL<<30) 14607 #define TPATF_CTX_WINDOW_CID6_LOCK_REQ (1UL<<31) 14608 u32_t unused_5[26]; 14609 14610 u32_t tpatf_tpatq_cid; 14611 #define TPATF_TPATQ_CID_VALUE (0x3fffUL<<7) 14612 14613 u16_t tpatf_tpatq_nbytes; 14614 #define TPATF_TPATQ_NBYTES_VALUE (0x3fff<<0) 14615 14616 u8_t tpatf_tpatq_xnum; 14617 u8_t tpatf_tpatq_knum; 14618 u32_t tpatf_tpatq_flags_flags; 14619 #define TPATF_TPATQ_FLAGS_FLAGS_PLUS_TWO (1UL<<0) 14620 #define TPATF_TPATQ_FLAGS_FLAGS_TCP_UDP_CKSUM (1UL<<1) 14621 #define TPATF_TPATQ_FLAGS_FLAGS_IP_CKSUM (1UL<<2) 14622 #define TPATF_TPATQ_FLAGS_FLAGS_INCR_CMD (1UL<<3) 14623 #define TPATF_TPATQ_FLAGS_FLAGS_COAL_NOW (1UL<<4) 14624 #define TPATF_TPATQ_FLAGS_FLAGS_DONT_GEN_CRC (1UL<<5) 14625 #define TPATF_TPATQ_FLAGS_FLAGS_LAST_PKT (1UL<<6) 14626 #define TPATF_TPATQ_FLAGS_FLAGS_PKT_FRAG (1UL<<7) 14627 #define TPATF_TPATQ_FLAGS_FLAGS_QUICK_CID_ENA (1UL<<9) 14628 #define TPATF_TPATQ_FLAGS_FLAGS_RSVD_FUTURE (0x3UL<<10) 14629 #define TPATF_TPATQ_FLAGS_FLAGS_L5_PAGE_MODE (1UL<<12) 14630 #define TPATF_TPATQ_FLAGS_FLAGS_COMPLETE (1UL<<13) 14631 #define TPATF_TPATQ_FLAGS_FLAGS_RETRAN (1UL<<14) 14632 #define TPATF_TPATQ_FLAGS_FLAGS_END_PADDING (0xfUL<<16) 14633 #define TPATF_TPATQ_FLAGS_FLAGS_USAGE_CNT (1UL<<20) 14634 #define TPATF_TPATQ_FLAGS_FLAGS_USAGE_CNT_AUTODECREMENT (0UL<<20) 14635 #define TPATF_TPATQ_FLAGS_FLAGS_USAGE_CNT_DONOTDECREMENT (1UL<<20) 14636 #define TPATF_TPATQ_FLAGS_FLAGS_BSEQ_INVLD (1UL<<21) 14637 #define TPATF_TPATQ_FLAGS_FLAGS_WORK_AROUND (0x3UL<<22) 14638 #define TPATF_TPATQ_FLAGS_FLAGS_HOLE_SZ (0x3UL<<25) 14639 #define TPATF_TPATQ_FLAGS_FLAGS_HOLE_SZ_4 (0UL<<25) 14640 #define TPATF_TPATQ_FLAGS_FLAGS_HOLE_SZ_8 (1UL<<25) 14641 #define TPATF_TPATQ_FLAGS_FLAGS_HOLE_SZ_12 (2UL<<25) 14642 #define TPATF_TPATQ_FLAGS_FLAGS_HOLE_SZ_16 (3UL<<25) 14643 #define TPATF_TPATQ_FLAGS_FLAGS_HOLE0 (1UL<<28) 14644 #define TPATF_TPATQ_FLAGS_FLAGS_HOLE1 (1UL<<29) 14645 #define TPATF_TPATQ_FLAGS_FLAGS_HOLE2 (1UL<<30) 14646 14647 u16_t tpatf_tpatq_raw_chksum; 14648 u16_t tpatf_tpatq_tpat_bidx; 14649 u8_t tpatf_tpatq_status; 14650 #define TPATF_TPATQ_STATUS_CS16_ERR (1<<0) 14651 u8_t unused_6; 14652 u16_t unused_7; 14653 u32_t unused_8[9]; 14654 14655 u32_t tpatf_tpatq_ftq_cmd; 14656 #define TPATF_TPATQ_FTQ_CMD_TPATQ_CMD_POP (1UL<<30) 14657 u32_t unused_9; 14658 14659 u16_t tpatf_tasq_hdr_skip; 14660 u16_t tpatf_tasq_hdr_post_skip; 14661 u16_t tpatf_tasq_hdr_size; 14662 u16_t tpatf_tasq_payload_skip; 14663 u16_t tpatf_tasq_payload_size; 14664 u16_t tpatf_tasq_flags; 14665 #define TPATF_TASQ_FLAGS_PKT_END (1<<0) 14666 #define TPATF_TASQ_FLAGS_MGMT_PACKET (1<<1) 14667 #define TPATF_TASQ_FLAGS_CATCHUP_PACKET (1<<2) 14668 #define TPATF_TASQ_FLAGS_DONT_GEN_CRC (1<<3) 14669 #define TPATF_TASQ_FLAGS_DROP (1<<4) 14670 #define TPATF_TASQ_FLAGS_RESERVED (0x3<<5) 14671 #define TPATF_TASQ_FLAGS_MGMT_PKT_TAG_XI (0x1f<<8) 14672 #define TPATF_TASQ_FLAGS_CS16_VLD (1<<15) 14673 14674 u16_t tpatf_tasq_cs16; 14675 #define TPATF_TASQ_CS16_VALUE (0xffff<<0) 14676 u16_t unused_10; 14677 u32_t unused_11[10]; 14678 14679 u32_t tpatf_tasq_ftq_cmd; 14680 #define TPATF_TASQ_FTQ_CMD_CPY_DATA (1UL<<11) 14681 #define TPATF_TASQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) 14682 #define TPATF_TASQ_FTQ_CMD_ADD_DATA (1UL<<28) 14683 #define TPATF_TASQ_FTQ_CMD_BUSY (1UL<<31) 14684 u32_t unused_12[429]; 14685 14686 u32_t tpatf_ctx_cmd; 14687 #define TPATF_CTX_CMD_NUM_BLOCKS (0x3UL<<0) 14688 #define TPATF_CTX_CMD_OFFSET (0x1ffUL<<3) 14689 #define TPATF_CTX_CMD_CID_VALUE (0x3fffUL<<12) 14690 #define TPATF_CTX_CMD_PREFETCH_SIZE (0x3UL<<26) 14691 #define TPATF_CTX_CMD_MOD_USAGE_CNT (0x3UL<<28) 14692 #define TPATF_CTX_CMD_MOD_USAGE_CNT_00 (0UL<<28) 14693 #define TPATF_CTX_CMD_MOD_USAGE_CNT_01 (1UL<<28) 14694 #define TPATF_CTX_CMD_MOD_USAGE_CNT_10 (2UL<<28) 14695 #define TPATF_CTX_CMD_MOD_USAGE_CNT_11 (3UL<<28) 14696 u32_t unused_13[499]; 14697 14698 u32_t tpatf_tpat_crack_cmd; 14699 #define TPATF_TPAT_CRACK_CMD_CRC32_1_LEN (0xffffUL<<0) 14700 #define TPATF_TPAT_CRACK_CMD_CRACK (1UL<<16) 14701 #define TPATF_TPAT_CRACK_CMD_L2_VLAN (1UL<<17) 14702 #define TPATF_TPAT_CRACK_CMD_L2_LLC (1UL<<18) 14703 #define TPATF_TPAT_CRACK_CMD_PLUS_TWO (1UL<<19) 14704 #define TPATF_TPAT_CRACK_CMD_L3_UPDATE (1UL<<20) 14705 #define TPATF_TPAT_CRACK_CMD_L4_UDP (1UL<<21) 14706 #define TPATF_TPAT_CRACK_CMD_L4_USE_RAW (1UL<<22) 14707 #define TPATF_TPAT_CRACK_CMD_PART_HDR_CS (1UL<<23) 14708 #define TPATF_TPAT_CRACK_CMD_L4_UPDATE (1UL<<24) 14709 #define TPATF_TPAT_CRACK_CMD_CRC32_2_START (1UL<<25) 14710 #define TPATF_TPAT_CRACK_CMD_CRC32_1_INIT (1UL<<26) 14711 #define TPATF_TPAT_CRACK_CMD_IPV6_ADDR (1UL<<27) 14712 #define TPATF_TPAT_CRACK_CMD_RESULT_REG_CLEAR (1UL<<28) 14713 #define TPATF_TPAT_CRACK_CMD_DATA_PATH_CLEAR (1UL<<29) 14714 #define TPATF_TPAT_CRACK_CMD_DONE (1UL<<31) 14715 14716 u16_t tpatf_tpat_crack_ip_offset; 14717 u16_t tpatf_tpat_crack_ip_len; 14718 u16_t tpatf_tpat_crack_tcp_offset; 14719 u16_t tpatf_tpat_crack_tcp_len; 14720 u16_t tpatf_tpat_crack_l5_offset; 14721 u16_t tpatf_tpat_crack_l5_len; 14722 u16_t tpatf_tpat_crack_ip_chksum; 14723 u16_t tpatf_tpat_crack_ip_pseudo_chksum; 14724 u16_t tpatf_tpat_crack_tcp_chksum; 14725 u16_t tpatf_tpat_crack_crc32_1_start; 14726 u32_t tpatf_tpat_crack_crc32_1_seed; 14727 u32_t tpatf_tpat_crack_crc32_1_result; 14728 u32_t tpatf_tpat_crack_crc32_2_result; 14729 u32_t tpatf_ipv6_programmable_extension0; 14730 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN (0xffUL<<0) 14731 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER (0xffUL<<16) 14732 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN_TYPE (1UL<<30) 14733 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_EN (1UL<<31) 14734 14735 u32_t tpatf_ipv6_programmable_extension1; 14736 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN (0xffUL<<0) 14737 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER (0xffUL<<16) 14738 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN_TYPE (1UL<<30) 14739 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_EN (1UL<<31) 14740 14741 u32_t tpatf_ipv6_programmable_extension2; 14742 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN (0xffUL<<0) 14743 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER (0xffUL<<16) 14744 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN_TYPE (1UL<<30) 14745 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_EN (1UL<<31) 14746 14747 u32_t tpatf_ipv6_programmable_extension3; 14748 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN (0xffUL<<0) 14749 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER (0xffUL<<16) 14750 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN_TYPE (1UL<<30) 14751 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_EN (1UL<<31) 14752 14753 u32_t tpatf_ipv6_programmable_extension4; 14754 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN (0xffUL<<0) 14755 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER (0xffUL<<16) 14756 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN_TYPE (1UL<<30) 14757 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_EN (1UL<<31) 14758 14759 u32_t tpatf_ipv6_programmable_extension5; 14760 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN (0xffUL<<0) 14761 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER (0xffUL<<16) 14762 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN_TYPE (1UL<<30) 14763 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_EN (1UL<<31) 14764 14765 u32_t tpatf_ipv6_programmable_extension6; 14766 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN (0xffUL<<0) 14767 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER (0xffUL<<16) 14768 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN_TYPE (1UL<<30) 14769 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_EN (1UL<<31) 14770 14771 u32_t tpatf_ipv6_programmable_extension7; 14772 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN (0xffUL<<0) 14773 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER (0xffUL<<16) 14774 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN_TYPE (1UL<<30) 14775 #define TPATF_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_EN (1UL<<31) 14776 14777 u32_t tpatf_tpatc_debug1; 14778 u32_t tpatf_tpatc_debug2; 14779 u32_t unused_14[3053]; 14780 u32_t tpatf_tx_header_queue[4096]; 14781 u32_t tpatf_tx_payload_queue[16384]; 14782 u32_t unused_15[40960]; 14783 u32_t tpatf_ctx_window5[32768]; 14784 u32_t tpatf_ctx_window6[32768]; 14785 u32_t tpatf_ctx_window1[32768]; 14786 u32_t tpatf_ctx_window2[32768]; 14787 u32_t tpatf_ctx_window3[32768]; 14788 u32_t tpatf_ctx_window4[32768]; 14789 } tpat_fio_xi_t; 14790 14791 14792 /* 14793 * rxp_fio definition 14794 * offset: 0x80000000 14795 */ 14796 typedef struct rxp_fio 14797 { 14798 u32_t rxpf_events_bits; 14799 #define RXPF_EVENTS_BITS_GPIO0 (1UL<<15) 14800 #define RXPF_EVENTS_BITS_GPIO1 (1UL<<16) 14801 #define RXPF_EVENTS_BITS_GPIO2 (1UL<<17) 14802 #define RXPF_EVENTS_BITS_GPIO3 (1UL<<18) 14803 14804 u32_t rxpf_attentions_bits; 14805 #define RXPF_ATTENTIONS_BITS_EPB_ERROR (1UL<<30) 14806 14807 u32_t rxpf_event_enable; 14808 u32_t rxpf_attention_enable; 14809 u32_t rxpf_fio_status; 14810 14811 u32_t rxpf_mult_result; 14812 u32_t rxpf_mult_a; 14813 14814 u32_t rxpf_mult_b; 14815 14816 u32_t rxpf_ctx_window_cid1; 14817 14818 u32_t rxpf_ctx_window_cid2; 14819 #define RXPF_CTX_WINDOW_CID2_CTX_WINDOW_CID2_VALUE (0x3fffUL<<7) 14820 14821 u32_t rxpf_ctx_window_cid3; 14822 #define RXPF_CTX_WINDOW_CID3_CTX_WINDOW_CID3_VALUE (0x3fffUL<<7) 14823 14824 u32_t rxpf_ctx_window_cid4; 14825 #define RXPF_CTX_WINDOW_CID4_CTX_WINDOW_CID4_VALUE (0x3fffUL<<7) 14826 u32_t unused_0[4]; 14827 14828 u32_t rxpf_hc_inc_tcp_insegs; 14829 u32_t rxpf_hc_inc_tcp_inerrs; 14830 u32_t rxpf_hc_inc_ip_inreceives; 14831 u32_t rxpf_hc_inc_ip_inhdrerrors; 14832 u32_t rxpf_hc_inc_ip_indiscards; 14833 u32_t rxpf_hc_inc_ip_indelivers; 14834 u32_t rxpf_hc_inc_ip_reasmreqds; 14835 u32_t rxpf_hc_inc_ip_reasmoks; 14836 u32_t rxpf_hc_inc_ip_reasmfails; 14837 u32_t rxpf_hc_inc_stat[3]; 14838 u32_t rxpf_free_counter_value; 14839 u32_t rxpf_timer_retran_value; 14840 u16_t rxpf_timer_rxpush_value; 14841 u16_t rxpf_timer_delayack_value; 14842 u16_t rxpf_timer_keepalive_value; 14843 u16_t rxpf_timer_nagle_value; 14844 u32_t rxpf_rxp_rbuf_cluster; 14845 14846 u32_t rxpf_rxp_rbuf_burst_offset; 14847 #define RXPF_RXP_RBUF_BURST_OFFSET_OFFSET_TE (0x7ffUL<<3) 14848 u32_t unused_1[30]; 14849 14850 u32_t rxpf_rxpq_bits_errors; 14851 #define RXPF_RXPQ_BITS_ERRORS_TCP_SYNC_PRESENT (1UL<<14) 14852 14853 u32_t rxpf_rxpq_bits_status; 14854 #define RXPF_RXPQ_BITS_STATUS_VALID (1UL<<20) 14855 14856 u8_t rxpf_rxpq_bits_multicast_hash_idx; 14857 u8_t rxpf_rxpq_bits_acpi_pat; 14858 #define RXPF_RXPQ_BITS_ACPI_PAT_ACPI_PAT_TE (0x7<<0) 14859 14860 u8_t rxpf_rxpq_knum; 14861 u8_t unused_2; 14862 u16_t rxpf_rxpq_rule_tag; 14863 u16_t rxpf_rxpq_pkt_len; 14864 u16_t rxpf_rxpq_vlan_tag; 14865 u8_t rxpf_rxpq_ip_hdr_offset; 14866 u8_t unused_3; 14867 u16_t rxpf_rxpq_ip_xsum; 14868 u8_t rxpf_rxpq_tcp_udp_hdr_offset; 14869 u8_t unused_4; 14870 u16_t rxpf_rxpq_tcp_udp_xsum; 14871 u16_t rxpf_rxpq_tcp_payload_len; 14872 u16_t rxpf_rxpq_pseud_xsum; 14873 u16_t rxpf_rxpq_l2_payload_raw_xsum; 14874 u8_t rxpf_rxpq_data_offset; 14875 u8_t unused_5[3]; 14876 u32_t rxpf_rxpq_mbuf_cluster; 14877 u32_t rxpf_rxpq_cid; 14878 u32_t unused_6[3]; 14879 u32_t rxpf_rxpq_ftq_cmd; 14880 14881 u32_t rxpf_rx_proc_ftq_trip; 14882 14883 u32_t rxpf_rxpcq_cid; 14884 u32_t rxpf_rxpcq_generic1; 14885 u32_t rxpf_rxpcq_generic2; 14886 u32_t unused_7[11]; 14887 u32_t rxpf_rxpcq_ftq_cmd; 14888 u32_t unused_8; 14889 14890 u32_t rxpf_rv2ppq_cid; 14891 u32_t rxpf_rv2ppq_mbuf_cluster; 14892 u16_t rxpf_rv2ppq_operand_flags; 14893 u8_t rxpf_rv2ppq_knum; 14894 u8_t rxpf_rv2ppq_opcode; 14895 u16_t rxpf_rv2ppq_operand16_0; // Note that 16_0 and 16_1 will be absorbed 14896 u16_t rxpf_rv2ppq_operand16_1; // by RDMA and won't be passed to COM 14897 u16_t rxpf_rv2ppq_operand16_2; 14898 u16_t rxpf_rv2ppq_operand16_3; 14899 u16_t rxpf_rv2ppq_operand16_4; 14900 u16_t rxpf_rv2ppq_operand16_5; 14901 u16_t rxpf_rv2ppq_operand16_6; 14902 u16_t rxpf_rv2ppq_operand16_7; 14903 u32_t rxpf_rv2ppq_operand32_0; // Note that 32_0 and 32_1 will be absorbed 14904 u32_t rxpf_rv2ppq_operand32_1; // by RDMA and won't be passed to COM 14905 u32_t rxpf_rv2ppq_operand32_2; 14906 u32_t rxpf_rv2ppq_operand32_3; 14907 u32_t rxpf_rv2ppq_operand32_4; 14908 u32_t unused_9[2]; 14909 u32_t rxpf_rv2ppq_ftq_cmd; 14910 u32_t unused_10; 14911 14912 u32_t rxpf_mcpq_bits_status; 14913 u16_t rxpf_mcpq_pkt_len; 14914 u16_t unused_11; 14915 u32_t rxpf_mcpq_mbuf_cluster; 14916 u32_t unused_12[11]; 14917 u32_t rxpf_mcpq_ftq_cmd; 14918 u32_t unused_13; 14919 14920 u32_t rxpf_csq_cid; 14921 u8_t rxpf_csq_flags; 14922 u8_t unused_14; 14923 u16_t unused_15; 14924 u32_t unused_16[12]; 14925 u32_t rxpf_csq_ftq_cmd; 14926 u32_t unused_17[369]; 14927 14928 u32_t rxpf_burst_base0; 14929 14930 u32_t rxpf_burst_base1; 14931 14932 u32_t rxpf_burst_base2; 14933 14934 u32_t rxpf_burst_base3; 14935 14936 u32_t rxpf_burst_cmd0; 14937 14938 u32_t rxpf_burst_cmd1; 14939 u32_t unused_18[58]; 14940 14941 u32_t rxpf_burst_data0[16]; 14942 u32_t rxpf_burst_data1[16]; 14943 u32_t unused_19[32]; 14944 u32_t rxpf_rbuf_burst_data[16]; 14945 u32_t unused_20[3440]; 14946 u32_t rxpf_rx_mbuf[4096]; 14947 u32_t unused_21[122880]; 14948 u32_t rxpf_ctx_window1[32768]; 14949 u32_t rxpf_ctx_window2[32768]; 14950 u32_t rxpf_ctx_window3[32768]; 14951 u32_t rxpf_ctx_window4[32768]; 14952 } rxp_fio_t; 14953 14954 14955 /* 14956 * rxp_fio definition 14957 * offset: 0x80000000 14958 */ 14959 typedef struct rxp_fio_xi 14960 { 14961 u32_t rxpf_events_bits; 14962 #define RXPF_EVENTS_BITS_FTQ0_VALID (1UL<<0) 14963 #define RXPF_EVENTS_BITS_FTQ1_VALID (1UL<<1) 14964 #define RXPF_EVENTS_BITS_FTQ2_VALID (1UL<<2) 14965 #define RXPF_EVENTS_BITS_SCANNER_DONE (1UL<<3) 14966 #define RXPF_EVENTS_BITS_DMA_WR_DONE (1UL<<4) 14967 #define RXPF_EVENTS_BITS_DMA_RD_DONE (1UL<<5) 14968 #define RXPF_EVENTS_BITS_CRACKER_DONE (1UL<<6) 14969 #define RXPF_EVENTS_BITS_MULTIPLY_DONE (1UL<<7) 14970 #define RXPF_EVENTS_BITS_EXP_ROM (1UL<<8) 14971 #define RXPF_EVENTS_BITS_VPD (1UL<<9) 14972 #define RXPF_EVENTS_BITS_FLASH (1UL<<10) 14973 #define RXPF_EVENTS_BITS_SMB0 (1UL<<11) 14974 #define RXPF_EVENTS_BITS_RESERVED0 (1UL<<12) 14975 #define RXPF_EVENTS_BITS_RESERVED1 (1UL<<13) 14976 #define RXPF_EVENTS_BITS_RESERVED2 (1UL<<14) 14977 #define RXPF_EVENTS_BITS_GPIO (1UL<<15) 14978 #define RXPF_EVENTS_BITS_SW_TMR_1 (1UL<<19) 14979 #define RXPF_EVENTS_BITS_SW_TMR_2 (1UL<<20) 14980 #define RXPF_EVENTS_BITS_SW_TMR_3 (1UL<<21) 14981 #define RXPF_EVENTS_BITS_SW_TMR_4 (1UL<<22) 14982 #define RXPF_EVENTS_BITS_LINK_CHANGED (1UL<<23) 14983 #define RXPF_EVENTS_BITS_MI_INT (1UL<<25) 14984 #define RXPF_EVENTS_BITS_MI_COMPLETE (1UL<<26) 14985 #define RXPF_EVENTS_BITS_MAIN_PWR_INT (1UL<<27) 14986 #define RXPF_EVENTS_BITS_NOT_ENABLED (1UL<<30) 14987 #define RXPF_EVENTS_BITS_ATTENTIONS_VALID (1UL<<31) 14988 14989 u32_t rxpf_attentions_bits; 14990 #define RXPF_ATTENTIONS_BITS_LINK_STATE (1UL<<0) 14991 #define RXPF_ATTENTIONS_BITS_TX_SCHEDULER_ABORT (1UL<<1) 14992 #define RXPF_ATTENTIONS_BITS_TX_BD_READ_ABORT (1UL<<2) 14993 #define RXPF_ATTENTIONS_BITS_TX_BD_CACHE_ABORT (1UL<<3) 14994 #define RXPF_ATTENTIONS_BITS_TX_PROCESSOR_ABORT (1UL<<4) 14995 #define RXPF_ATTENTIONS_BITS_TX_DMA_ABORT (1UL<<5) 14996 #define RXPF_ATTENTIONS_BITS_TX_PATCHUP_ABORT (1UL<<6) 14997 #define RXPF_ATTENTIONS_BITS_TX_ASSEMBLER_ABORT (1UL<<7) 14998 #define RXPF_ATTENTIONS_BITS_RX_PARSER_MAC_ABORT (1UL<<8) 14999 #define RXPF_ATTENTIONS_BITS_RX_PARSER_CATCHUP_ABORT (1UL<<9) 15000 #define RXPF_ATTENTIONS_BITS_RX_MBUF_ABORT (1UL<<10) 15001 #define RXPF_ATTENTIONS_BITS_RX_LOOKUP_ABORT (1UL<<11) 15002 #define RXPF_ATTENTIONS_BITS_RX_PROCESSOR_ABORT (1UL<<12) 15003 #define RXPF_ATTENTIONS_BITS_RX_V2P_ABORT (1UL<<13) 15004 #define RXPF_ATTENTIONS_BITS_RX_BD_CACHE_ABORT (1UL<<14) 15005 #define RXPF_ATTENTIONS_BITS_RX_DMA_ABORT (1UL<<15) 15006 #define RXPF_ATTENTIONS_BITS_COMPLETION_ABORT (1UL<<16) 15007 #define RXPF_ATTENTIONS_BITS_HOST_COALESCE_ABORT (1UL<<17) 15008 #define RXPF_ATTENTIONS_BITS_MAILBOX_QUEUE_ABORT (1UL<<18) 15009 #define RXPF_ATTENTIONS_BITS_CONTEXT_ABORT (1UL<<19) 15010 #define RXPF_ATTENTIONS_BITS_CMD_SCHEDULER_ABORT (1UL<<20) 15011 #define RXPF_ATTENTIONS_BITS_CMD_PROCESSOR_ABORT (1UL<<21) 15012 #define RXPF_ATTENTIONS_BITS_MGMT_PROCESSOR_ABORT (1UL<<22) 15013 #define RXPF_ATTENTIONS_BITS_MAC_ABORT (1UL<<23) 15014 #define RXPF_ATTENTIONS_BITS_TIMER_ABORT (1UL<<24) 15015 #define RXPF_ATTENTIONS_BITS_DMAE_ABORT (1UL<<25) 15016 #define RXPF_ATTENTIONS_BITS_FLSH_ABORT (1UL<<26) 15017 #define RXPF_ATTENTIONS_BITS_GRC_ABORT (1UL<<27) 15018 #define RXPF_ATTENTIONS_BITS_PARITY_ERROR (1UL<<31) 15019 15020 u32_t rxpf_event_enable; 15021 u32_t rxpf_attention_enable; 15022 u32_t rxpf_fio_status; 15023 #define RXPF_FIO_STATUS_ENABLED (1UL<<0) 15024 #define RXPF_FIO_STATUS_FORCE_ENA (1UL<<1) 15025 15026 u32_t rxpf_mult_result; 15027 u32_t rxpf_mult_a; 15028 #define RXPF_MULT_A_VALUE (0xffffUL<<0) 15029 15030 u32_t rxpf_mult_b; 15031 #define RXPF_MULT_B_VALUE (0xffffUL<<0) 15032 15033 u32_t rxpf_ctx_window_cid1; 15034 #define RXPF_CTX_WINDOW_CID1_LOCK_TYPE (0x7UL<<0) 15035 #define RXPF_CTX_WINDOW_CID1_LOCK_TYPE_VOID (0UL<<0) 15036 #define RXPF_CTX_WINDOW_CID1_LOCK_TYPE_PROTOCOL (1UL<<0) 15037 #define RXPF_CTX_WINDOW_CID1_LOCK_TYPE_TX (2UL<<0) 15038 #define RXPF_CTX_WINDOW_CID1_LOCK_TYPE_TIMER (4UL<<0) 15039 #define RXPF_CTX_WINDOW_CID1_LOCK_TYPE_COMPLETE (7UL<<0) 15040 #define RXPF_CTX_WINDOW_CID1_VALUE (0x3fffUL<<7) 15041 #define RXPF_CTX_WINDOW_CID1_MOD_USAGE_CNT (0x3UL<<24) 15042 #define RXPF_CTX_WINDOW_CID1_MOD_USAGE_CNT_00 (0UL<<24) 15043 #define RXPF_CTX_WINDOW_CID1_MOD_USAGE_CNT_01 (1UL<<24) 15044 #define RXPF_CTX_WINDOW_CID1_MOD_USAGE_CNT_10 (2UL<<24) 15045 #define RXPF_CTX_WINDOW_CID1_MOD_USAGE_CNT_11 (3UL<<24) 15046 #define RXPF_CTX_WINDOW_CID1_LOCK_GRANTED (1UL<<26) 15047 #define RXPF_CTX_WINDOW_CID1_LOCK_MODE (0x3UL<<27) 15048 #define RXPF_CTX_WINDOW_CID1_LOCK_MODE_UNLOCK (0UL<<27) 15049 #define RXPF_CTX_WINDOW_CID1_LOCK_MODE_IMMEDIATE (1UL<<27) 15050 #define RXPF_CTX_WINDOW_CID1_LOCK_MODE_SURE (2UL<<27) 15051 #define RXPF_CTX_WINDOW_CID1_NO_EXT_ACC (1UL<<29) 15052 #define RXPF_CTX_WINDOW_CID1_LOCK_STATUS (1UL<<30) 15053 #define RXPF_CTX_WINDOW_CID1_LOCK_REQ (1UL<<31) 15054 15055 u32_t rxpf_ctx_window_cid2; 15056 #define RXPF_CTX_WINDOW_CID2_LOCK_TYPE (0x7UL<<0) 15057 #define RXPF_CTX_WINDOW_CID2_LOCK_TYPE_VOID (0UL<<0) 15058 #define RXPF_CTX_WINDOW_CID2_LOCK_TYPE_PROTOCOL (1UL<<0) 15059 #define RXPF_CTX_WINDOW_CID2_LOCK_TYPE_TX (2UL<<0) 15060 #define RXPF_CTX_WINDOW_CID2_LOCK_TYPE_TIMER (4UL<<0) 15061 #define RXPF_CTX_WINDOW_CID2_LOCK_TYPE_COMPLETE (7UL<<0) 15062 #define RXPF_CTX_WINDOW_CID2_VALUE (0x3fffUL<<7) 15063 #define RXPF_CTX_WINDOW_CID2_MOD_USAGE_CNT (0x3UL<<24) 15064 #define RXPF_CTX_WINDOW_CID2_MOD_USAGE_CNT_00 (0UL<<24) 15065 #define RXPF_CTX_WINDOW_CID2_MOD_USAGE_CNT_01 (1UL<<24) 15066 #define RXPF_CTX_WINDOW_CID2_MOD_USAGE_CNT_10 (2UL<<24) 15067 #define RXPF_CTX_WINDOW_CID2_MOD_USAGE_CNT_11 (3UL<<24) 15068 #define RXPF_CTX_WINDOW_CID2_LOCK_GRANTED (1UL<<26) 15069 #define RXPF_CTX_WINDOW_CID2_LOCK_MODE (0x3UL<<27) 15070 #define RXPF_CTX_WINDOW_CID2_LOCK_MODE_UNLOCK (0UL<<27) 15071 #define RXPF_CTX_WINDOW_CID2_LOCK_MODE_IMMEDIATE (1UL<<27) 15072 #define RXPF_CTX_WINDOW_CID2_LOCK_MODE_SURE (2UL<<27) 15073 #define RXPF_CTX_WINDOW_CID2_NO_EXT_ACC (1UL<<29) 15074 #define RXPF_CTX_WINDOW_CID2_LOCK_STATUS (1UL<<30) 15075 #define RXPF_CTX_WINDOW_CID2_LOCK_REQ (1UL<<31) 15076 15077 u32_t rxpf_ctx_window_cid3; 15078 #define RXPF_CTX_WINDOW_CID3_LOCK_TYPE (0x7UL<<0) 15079 #define RXPF_CTX_WINDOW_CID3_LOCK_TYPE_VOID (0UL<<0) 15080 #define RXPF_CTX_WINDOW_CID3_LOCK_TYPE_PROTOCOL (1UL<<0) 15081 #define RXPF_CTX_WINDOW_CID3_LOCK_TYPE_TX (2UL<<0) 15082 #define RXPF_CTX_WINDOW_CID3_LOCK_TYPE_TIMER (4UL<<0) 15083 #define RXPF_CTX_WINDOW_CID3_LOCK_TYPE_COMPLETE (7UL<<0) 15084 #define RXPF_CTX_WINDOW_CID3_VALUE (0x3fffUL<<7) 15085 #define RXPF_CTX_WINDOW_CID3_MOD_USAGE_CNT (0x3UL<<24) 15086 #define RXPF_CTX_WINDOW_CID3_MOD_USAGE_CNT_00 (0UL<<24) 15087 #define RXPF_CTX_WINDOW_CID3_MOD_USAGE_CNT_01 (1UL<<24) 15088 #define RXPF_CTX_WINDOW_CID3_MOD_USAGE_CNT_10 (2UL<<24) 15089 #define RXPF_CTX_WINDOW_CID3_MOD_USAGE_CNT_11 (3UL<<24) 15090 #define RXPF_CTX_WINDOW_CID3_LOCK_GRANTED (1UL<<26) 15091 #define RXPF_CTX_WINDOW_CID3_LOCK_MODE (0x3UL<<27) 15092 #define RXPF_CTX_WINDOW_CID3_LOCK_MODE_UNLOCK (0UL<<27) 15093 #define RXPF_CTX_WINDOW_CID3_LOCK_MODE_IMMEDIATE (1UL<<27) 15094 #define RXPF_CTX_WINDOW_CID3_LOCK_MODE_SURE (2UL<<27) 15095 #define RXPF_CTX_WINDOW_CID3_NO_EXT_ACC (1UL<<29) 15096 #define RXPF_CTX_WINDOW_CID3_LOCK_STATUS (1UL<<30) 15097 #define RXPF_CTX_WINDOW_CID3_LOCK_REQ (1UL<<31) 15098 15099 u32_t rxpf_ctx_window_cid4; 15100 #define RXPF_CTX_WINDOW_CID4_LOCK_TYPE (0x7UL<<0) 15101 #define RXPF_CTX_WINDOW_CID4_LOCK_TYPE_VOID (0UL<<0) 15102 #define RXPF_CTX_WINDOW_CID4_LOCK_TYPE_PROTOCOL (1UL<<0) 15103 #define RXPF_CTX_WINDOW_CID4_LOCK_TYPE_TX (2UL<<0) 15104 #define RXPF_CTX_WINDOW_CID4_LOCK_TYPE_TIMER (4UL<<0) 15105 #define RXPF_CTX_WINDOW_CID4_LOCK_TYPE_COMPLETE (7UL<<0) 15106 #define RXPF_CTX_WINDOW_CID4_VALUE (0x3fffUL<<7) 15107 #define RXPF_CTX_WINDOW_CID4_MOD_USAGE_CNT (0x3UL<<24) 15108 #define RXPF_CTX_WINDOW_CID4_MOD_USAGE_CNT_00 (0UL<<24) 15109 #define RXPF_CTX_WINDOW_CID4_MOD_USAGE_CNT_01 (1UL<<24) 15110 #define RXPF_CTX_WINDOW_CID4_MOD_USAGE_CNT_10 (2UL<<24) 15111 #define RXPF_CTX_WINDOW_CID4_MOD_USAGE_CNT_11 (3UL<<24) 15112 #define RXPF_CTX_WINDOW_CID4_LOCK_GRANTED (1UL<<26) 15113 #define RXPF_CTX_WINDOW_CID4_LOCK_MODE (0x3UL<<27) 15114 #define RXPF_CTX_WINDOW_CID4_LOCK_MODE_UNLOCK (0UL<<27) 15115 #define RXPF_CTX_WINDOW_CID4_LOCK_MODE_IMMEDIATE (1UL<<27) 15116 #define RXPF_CTX_WINDOW_CID4_LOCK_MODE_SURE (2UL<<27) 15117 #define RXPF_CTX_WINDOW_CID4_NO_EXT_ACC (1UL<<29) 15118 #define RXPF_CTX_WINDOW_CID4_LOCK_STATUS (1UL<<30) 15119 #define RXPF_CTX_WINDOW_CID4_LOCK_REQ (1UL<<31) 15120 u32_t unused_0[4]; 15121 15122 u32_t rxpf_hc_inc_tcp_insegs; 15123 u32_t rxpf_hc_inc_tcp_inerrs; 15124 u32_t rxpf_hc_inc_ip_inreceives; 15125 u32_t rxpf_hc_inc_ip_inhdrerrors; 15126 u32_t rxpf_hc_inc_ip_indiscards; 15127 u32_t rxpf_hc_inc_ip_indelivers; 15128 u32_t rxpf_hc_inc_ip_reasmreqds; 15129 u32_t rxpf_hc_inc_ip_reasmoks; 15130 u32_t rxpf_hc_inc_ip_reasmfails; 15131 u32_t rxpf_hc_inc_stat[3]; 15132 u32_t rxpf_free_counter_value; 15133 u32_t rxpf_timer_retran_value; 15134 u16_t rxpf_timer_rxpush_value; 15135 u16_t rxpf_timer_delayack_value; 15136 u16_t rxpf_timer_keepalive_value; 15137 u16_t rxpf_timer_nagle_value; 15138 u32_t rxpf_rxp_rbuf_cluster; 15139 #define RXPF_RXP_RBUF_CLUSTER_COUNT (0x7fUL<<0) 15140 #define RXPF_RXP_RBUF_CLUSTER_TAIL (0x1ffUL<<7) 15141 #define RXPF_RXP_RBUF_CLUSTER_HEAD (0x1ffUL<<16) 15142 15143 u32_t rxpf_rxp_rbuf_burst_offset; 15144 #define RXPF_RXP_RBUF_BURST_OFFSET_OFFSET_XI (0x3ffUL<<4) 15145 #define RXPF_RXP_RBUF_BURST_OFFSET_BUSY (1UL<<31) 15146 u32_t unused_1[2]; 15147 15148 u32_t rxpf_ctx_window_cid5; 15149 #define RXPF_CTX_WINDOW_CID5_LOCK_TYPE (0x7UL<<0) 15150 #define RXPF_CTX_WINDOW_CID5_LOCK_TYPE_VOID (0UL<<0) 15151 #define RXPF_CTX_WINDOW_CID5_LOCK_TYPE_PROTOCOL (1UL<<0) 15152 #define RXPF_CTX_WINDOW_CID5_LOCK_TYPE_TX (2UL<<0) 15153 #define RXPF_CTX_WINDOW_CID5_LOCK_TYPE_TIMER (4UL<<0) 15154 #define RXPF_CTX_WINDOW_CID5_LOCK_TYPE_COMPLETE (7UL<<0) 15155 #define RXPF_CTX_WINDOW_CID5_VALUE (0x3fffUL<<7) 15156 #define RXPF_CTX_WINDOW_CID5_MOD_USAGE_CNT (0x3UL<<24) 15157 #define RXPF_CTX_WINDOW_CID5_MOD_USAGE_CNT_00 (0UL<<24) 15158 #define RXPF_CTX_WINDOW_CID5_MOD_USAGE_CNT_01 (1UL<<24) 15159 #define RXPF_CTX_WINDOW_CID5_MOD_USAGE_CNT_10 (2UL<<24) 15160 #define RXPF_CTX_WINDOW_CID5_MOD_USAGE_CNT_11 (3UL<<24) 15161 #define RXPF_CTX_WINDOW_CID5_LOCK_GRANTED (1UL<<26) 15162 #define RXPF_CTX_WINDOW_CID5_LOCK_MODE (0x3UL<<27) 15163 #define RXPF_CTX_WINDOW_CID5_LOCK_MODE_UNLOCK (0UL<<27) 15164 #define RXPF_CTX_WINDOW_CID5_LOCK_MODE_IMMEDIATE (1UL<<27) 15165 #define RXPF_CTX_WINDOW_CID5_LOCK_MODE_SURE (2UL<<27) 15166 #define RXPF_CTX_WINDOW_CID5_NO_EXT_ACC (1UL<<29) 15167 #define RXPF_CTX_WINDOW_CID5_LOCK_STATUS (1UL<<30) 15168 #define RXPF_CTX_WINDOW_CID5_LOCK_REQ (1UL<<31) 15169 15170 u32_t rxpf_ctx_window_cid6; 15171 #define RXPF_CTX_WINDOW_CID6_LOCK_TYPE (0x7UL<<0) 15172 #define RXPF_CTX_WINDOW_CID6_LOCK_TYPE_VOID (0UL<<0) 15173 #define RXPF_CTX_WINDOW_CID6_LOCK_TYPE_PROTOCOL (1UL<<0) 15174 #define RXPF_CTX_WINDOW_CID6_LOCK_TYPE_TX (2UL<<0) 15175 #define RXPF_CTX_WINDOW_CID6_LOCK_TYPE_TIMER (4UL<<0) 15176 #define RXPF_CTX_WINDOW_CID6_LOCK_TYPE_COMPLETE (7UL<<0) 15177 #define RXPF_CTX_WINDOW_CID6_VALUE (0x3fffUL<<7) 15178 #define RXPF_CTX_WINDOW_CID6_MOD_USAGE_CNT (0x3UL<<24) 15179 #define RXPF_CTX_WINDOW_CID6_MOD_USAGE_CNT_00 (0UL<<24) 15180 #define RXPF_CTX_WINDOW_CID6_MOD_USAGE_CNT_01 (1UL<<24) 15181 #define RXPF_CTX_WINDOW_CID6_MOD_USAGE_CNT_10 (2UL<<24) 15182 #define RXPF_CTX_WINDOW_CID6_MOD_USAGE_CNT_11 (3UL<<24) 15183 #define RXPF_CTX_WINDOW_CID6_LOCK_GRANTED (1UL<<26) 15184 #define RXPF_CTX_WINDOW_CID6_LOCK_MODE (0x3UL<<27) 15185 #define RXPF_CTX_WINDOW_CID6_LOCK_MODE_UNLOCK (0UL<<27) 15186 #define RXPF_CTX_WINDOW_CID6_LOCK_MODE_IMMEDIATE (1UL<<27) 15187 #define RXPF_CTX_WINDOW_CID6_LOCK_MODE_SURE (2UL<<27) 15188 #define RXPF_CTX_WINDOW_CID6_NO_EXT_ACC (1UL<<29) 15189 #define RXPF_CTX_WINDOW_CID6_LOCK_STATUS (1UL<<30) 15190 #define RXPF_CTX_WINDOW_CID6_LOCK_REQ (1UL<<31) 15191 u32_t unused_2[2]; 15192 15193 u32_t rxpf_crc32_command; 15194 #define RXPF_CRC32_COMMAND_OFFSET (0x7fUL<<0) 15195 #define RXPF_CRC32_COMMAND_LENGTH (0x7fUL<<8) 15196 #define RXPF_CRC32_COMMAND_USE_INTM_SEED (1UL<<20) 15197 #define RXPF_CRC32_COMMAND_START (1UL<<31) 15198 15199 u32_t rxpf_crc32_seed; 15200 u32_t rxpf_crc32_result; 15201 u32_t rxpf_crc32_intm_seed; 15202 u32_t unused_3[20]; 15203 u32_t rxpf_rxpq_bits_errors; 15204 #define RXPF_RXPQ_BITS_ERRORS_L2_USE_HEADER_LENGTH (1UL<<0) // For Jumbo Frame support 15205 #define RXPF_RXPQ_BITS_ERRORS_L2_BAD_CRC (1UL<<1) 15206 #define RXPF_RXPQ_BITS_ERRORS_L2_PHY_DECODE (1UL<<2) 15207 #define RXPF_RXPQ_BITS_ERRORS_L2_ALIGNMENT (1UL<<3) 15208 #define RXPF_RXPQ_BITS_ERRORS_L2_TOO_SHORT (1UL<<4) 15209 #define RXPF_RXPQ_BITS_ERRORS_L2_GIANT_FRAME (1UL<<5) 15210 #define RXPF_RXPQ_BITS_ERRORS_IP_BAD_LEN (1UL<<6) 15211 #define RXPF_RXPQ_BITS_ERRORS_IP_TOO_SHORT (1UL<<7) 15212 #define RXPF_RXPQ_BITS_ERRORS_IP_BAD_VERSION (1UL<<8) 15213 #define RXPF_RXPQ_BITS_ERRORS_IP_BAD_HLEN (1UL<<9) 15214 #define RXPF_RXPQ_BITS_ERRORS_IP_BAD_XSUM (1UL<<10) 15215 #define RXPF_RXPQ_BITS_ERRORS_TCP_TOO_SHORT (1UL<<11) 15216 #define RXPF_RXPQ_BITS_ERRORS_TCP_BAD_XSUM (1UL<<12) 15217 #define RXPF_RXPQ_BITS_ERRORS_TCP_BAD_OFFSET (1UL<<13) 15218 #define RXPF_RXPQ_BITS_ERRORS_TCP_SYNC_PRESENT (1UL<<14) 15219 #define RXPF_RXPQ_BITS_ERRORS_UDP_BAD_XSUM (1UL<<15) 15220 #define RXPF_RXPQ_BITS_ERRORS_IP_BAD_ORDER (1UL<<16) 15221 #define RXPF_RXPQ_BITS_ERRORS_IP_HDR_MISMATCH (1UL<<18) 15222 15223 u32_t rxpf_rxpq_bits_status; 15224 #define RXPF_RXPQ_BITS_STATUS_RULE_CLASS (0x7UL<<0) 15225 #define RXPF_RXPQ_BITS_STATUS_RULE_P2 (1UL<<3) 15226 #define RXPF_RXPQ_BITS_STATUS_RULE_P3 (1UL<<4) 15227 #define RXPF_RXPQ_BITS_STATUS_RULE_P4 (1UL<<5) 15228 #define RXPF_RXPQ_BITS_STATUS_L2_VLAN_TAG (1UL<<6) 15229 #define RXPF_RXPQ_BITS_STATUS_L2_LLC_SNAP (1UL<<7) 15230 #define RXPF_RXPQ_BITS_STATUS_RSS_HASH (1UL<<8) 15231 #define RXPF_RXPQ_BITS_STATUS_SORT_VECT (0xfUL<<9) 15232 #define RXPF_RXPQ_BITS_STATUS_IP_DATAGRAM (1UL<<13) 15233 #define RXPF_RXPQ_BITS_STATUS_TCP_SEGMENT (1UL<<14) 15234 #define RXPF_RXPQ_BITS_STATUS_UDP_DATAGRAM (1UL<<15) 15235 #define RXPF_RXPQ_BITS_STATUS_CU_FRAME (1UL<<16) 15236 #define RXPF_RXPQ_BITS_STATUS_IP_PROG_EXT (1UL<<17) 15237 #define RXPF_RXPQ_BITS_STATUS_IP_TYPE (1UL<<18) 15238 #define RXPF_RXPQ_BITS_STATUS_RULE_P1 (1UL<<19) 15239 #define RXPF_RXPQ_BITS_STATUS_RLUP_HIT4 (1UL<<20) 15240 #define RXPF_RXPQ_BITS_STATUS_IP_FRAGMENT (1UL<<21) 15241 #define RXPF_RXPQ_BITS_STATUS_IP_OPTIONS_PRESENT (1UL<<22) 15242 #define RXPF_RXPQ_BITS_STATUS_TCP_OPTIONS_PRESENT (1UL<<23) 15243 #define RXPF_RXPQ_BITS_STATUS_L2_PM_IDX (0xfUL<<24) 15244 #define RXPF_RXPQ_BITS_STATUS_L2_PM_HIT (1UL<<28) 15245 #define RXPF_RXPQ_BITS_STATUS_L2_MC_HASH_HIT (1UL<<29) 15246 #define RXPF_RXPQ_BITS_STATUS_RDMAC_CRC_PASS (1UL<<30) 15247 #define RXPF_RXPQ_BITS_STATUS_MP_HIT (1UL<<31) 15248 15249 u8_t rxpf_rxpq_bits_multicast_hash_idx; 15250 u8_t rxpf_rxpq_bits_acpi_pat; 15251 #define RXPF_RXPQ_BITS_ACPI_PAT_ACPI_PAT_XI (0xf<<0) 15252 #define RXPF_RXPQ_BITS_ACPI_PAT_ACPI_PAT_0 (0<<0) 15253 #define RXPF_RXPQ_BITS_ACPI_PAT_ACPI_PAT_1 (1<<0) 15254 #define RXPF_RXPQ_BITS_ACPI_PAT_ACPI_PAT_2 (2<<0) 15255 #define RXPF_RXPQ_BITS_ACPI_PAT_ACPI_PAT_3 (3<<0) 15256 #define RXPF_RXPQ_BITS_ACPI_PAT_ACPI_PAT_4 (4<<0) 15257 #define RXPF_RXPQ_BITS_ACPI_PAT_ACPI_PAT_5 (5<<0) 15258 #define RXPF_RXPQ_BITS_ACPI_PAT_ACPI_PAT_6 (6<<0) 15259 #define RXPF_RXPQ_BITS_ACPI_PAT_ACPI_PAT_NONE (7<<0) 15260 #define RXPF_RXPQ_BITS_ACPI_PAT_ACPI_PAT_8 (8<<0) 15261 15262 u8_t rxpf_rxpq_knum; 15263 u8_t unused_4; 15264 u16_t rxpf_rxpq_rule_tag; 15265 u16_t rxpf_rxpq_pkt_len; 15266 #define RXPF_RXPQ_PKT_LEN_VALUE (0x3fff<<0) 15267 15268 u16_t rxpf_rxpq_vlan_tag; 15269 u8_t rxpf_rxpq_ip_hdr_offset; 15270 u8_t rxpf_rxpq_rx_qid; 15271 #define RXPF_RXPQ_RX_QID_VALUE (0xf<<0) 15272 15273 u16_t rxpf_rxpq_ip_xsum; 15274 u16_t rxpf_rxpq_tcp_udp_hdr_offset; 15275 u16_t rxpf_rxpq_tcp_udp_xsum; 15276 u16_t rxpf_rxpq_tcp_payload_len; 15277 u16_t rxpf_rxpq_pseud_xsum; 15278 u16_t rxpf_rxpq_l2_payload_raw_xsum; 15279 u16_t rxpf_rxpq_data_offset; 15280 u16_t rxpf_rxpq_l3_payload_raw_xsum; 15281 u32_t rxpf_rxpq_mbuf_cluster; 15282 #define RXPF_RXPQ_MBUF_CLUSTER_VALUE (0x1ffffffUL<<0) 15283 15284 u32_t rxpf_rxpq_cid; 15285 #define RXPF_RXPQ_CID_VALUE (0x3fffUL<<7) 15286 15287 u16_t rxpf_rxpq_cs16; 15288 #define RXPF_RXPQ_CS16_VALUE (0xffff<<0) 15289 u16_t unused_5; 15290 15291 u16_t rxpf_rxpq_ext_status; 15292 #define RXPF_RXPQ_EXT_STATUS_TCP_SYNC_PRESENT (1<<0) 15293 #define RXPF_RXPQ_EXT_STATUS_RLUP_HIT2 (1<<1) 15294 #define RXPF_RXPQ_EXT_STATUS_TCP_UDP_XSUM_IS_0 (1<<2) 15295 #define RXPF_RXPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT (0x3<<3) 15296 #define RXPF_RXPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT_00 (0<<3) 15297 #define RXPF_RXPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT_01 (1<<3) 15298 #define RXPF_RXPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT_10 (2<<3) 15299 #define RXPF_RXPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT_11 (3<<3) 15300 #define RXPF_RXPQ_EXT_STATUS_ACPI_MATCH (1<<5) 15301 u16_t unused_6; 15302 u32_t unused_7; 15303 15304 u32_t rxpf_rxpq_ftq_cmd; 15305 #define RXPF_RXPQ_FTQ_CMD_RXPQ_CMD_POP (1UL<<30) 15306 15307 u32_t rxpf_rx_proc_ftq_trip; 15308 #define RXPF_RX_PROC_FTQ_TRIP_FF (0x1ffUL<<0) 15309 #define RXPF_RX_PROC_FTQ_TRIP_N (0x1ffUL<<16) 15310 15311 u32_t rxpf_rxpcq_cid; 15312 u32_t rxpf_rxpcq_generic1; 15313 u32_t rxpf_rxpcq_generic2; 15314 u32_t unused_8[11]; 15315 u32_t rxpf_rxpcq_ftq_cmd; 15316 #define RXPF_RXPCQ_FTQ_CMD_RXPCQ_CMD_POP (1UL<<30) 15317 u32_t unused_9; 15318 15319 u32_t rxpf_rv2ppq_cid; 15320 u32_t rxpf_rv2ppq_mbuf_cluster; 15321 u16_t rxpf_rv2ppq_operand_flags; 15322 u8_t rxpf_rv2ppq_knum; 15323 u8_t rxpf_rv2ppq_opcode; 15324 u16_t rxpf_rv2ppq_operand16_0; 15325 u16_t rxpf_rv2ppq_operand16_1; 15326 u16_t rxpf_rv2ppq_operand16_2; 15327 u16_t rxpf_rv2ppq_operand16_3; 15328 u16_t rxpf_rv2ppq_operand16_4; 15329 u16_t rxpf_rv2ppq_operand16_5; 15330 u16_t rxpf_rv2ppq_operand16_6; 15331 u16_t rxpf_rv2ppq_operand16_7; 15332 u32_t rxpf_rv2ppq_operand32_0; 15333 u32_t rxpf_rv2ppq_operand32_1; 15334 u32_t rxpf_rv2ppq_operand32_2; 15335 u32_t rxpf_rv2ppq_operand32_3; 15336 u32_t rxpf_rv2ppq_operand32_4; 15337 u8_t rxpf_rv2ppq_rdma_action; 15338 #define RXPF_RV2PPQ_RDMA_ACTION_CS16_VLD (1<<6) 15339 #define RXPF_RV2PPQ_RDMA_ACTION_NO_SNOOP (1<<7) 15340 15341 u8_t rxpf_rv2ppq_cs16_pkt_len; 15342 #define RXPF_RV2PPQ_CS16_PKT_LEN_VALUE (0x7f<<0) 15343 15344 u16_t rxpf_rv2ppq_cs16; 15345 u32_t unused_10; 15346 u32_t rxpf_rv2ppq_ftq_cmd; 15347 #define RXPF_RV2PPQ_FTQ_CMD_CPY_DATA (1UL<<11) 15348 #define RXPF_RV2PPQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) 15349 #define RXPF_RV2PPQ_FTQ_CMD_ADD_DATA (1UL<<28) 15350 #define RXPF_RV2PPQ_FTQ_CMD_BUSY (1UL<<31) 15351 u32_t unused_11; 15352 15353 u32_t rxpf_mcpq_bits_status; 15354 u16_t rxpf_mcpq_pkt_len; 15355 u16_t unused_12; 15356 u32_t rxpf_mcpq_mbuf_cluster; 15357 u32_t rxpf_mcpq_rx_errors; 15358 u16_t rxpf_mcpq_ext_status; 15359 u16_t unused_13; 15360 u32_t unused_14[9]; 15361 u32_t rxpf_mcpq_ftq_cmd; 15362 #define RXPF_MCPQ_FTQ_CMD_CPY_DATA (1UL<<11) 15363 #define RXPF_MCPQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) 15364 #define RXPF_MCPQ_FTQ_CMD_ADD_DATA (1UL<<28) 15365 #define RXPF_MCPQ_FTQ_CMD_BUSY (1UL<<31) 15366 u32_t unused_15; 15367 15368 u32_t rxpf_csq_cid; 15369 u8_t rxpf_csq_flags; 15370 u8_t unused_16; 15371 u16_t unused_17; 15372 u32_t unused_18[12]; 15373 u32_t rxpf_csq_ftq_cmd; 15374 #define RXPF_CSQ_FTQ_CMD_CPY_DATA (1UL<<11) 15375 #define RXPF_CSQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) 15376 #define RXPF_CSQ_FTQ_CMD_ADD_DATA (1UL<<28) 15377 #define RXPF_CSQ_FTQ_CMD_BUSY (1UL<<31) 15378 u32_t unused_19; 15379 15380 u32_t rxpf_tschq_cid; 15381 #define RXPF_TSCHQ_CID_VALUE (0x3fffUL<<7) 15382 15383 u8_t rxpf_tschq_flags; 15384 #define RXPF_TSCHQ_FLAGS_DELIST (1<<0) 15385 #define RXPF_TSCHQ_FLAGS_NORMAL (1<<1) 15386 #define RXPF_TSCHQ_FLAGS_HIGH (1<<2) 15387 15388 u8_t rxpf_tschq_rsvd_future; 15389 #define RXPF_TSCHQ_RSVD_FUTURE_VALUE (0x3<<0) 15390 u16_t unused_20; 15391 u32_t unused_21[12]; 15392 15393 u32_t rxpf_tschq_ftq_cmd; 15394 #define RXPF_TSCHQ_FTQ_CMD_CPY_DATA (1UL<<11) 15395 #define RXPF_TSCHQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) 15396 #define RXPF_TSCHQ_FTQ_CMD_ADD_DATA (1UL<<28) 15397 #define RXPF_TSCHQ_FTQ_CMD_BUSY (1UL<<31) 15398 u32_t unused_22[353]; 15399 15400 u32_t rxpf_burst_base0; 15401 #define RXPF_BURST_BASE0_BASE_VAL0 (0x3fffUL<<7) 15402 15403 u32_t rxpf_burst_base1; 15404 #define RXPF_BURST_BASE1_BASE_VAL1 (0x3fffUL<<7) 15405 15406 u32_t rxpf_burst_base2; 15407 #define RXPF_BURST_BASE2_BASE_VAL2 (0x3fffUL<<7) 15408 15409 u32_t rxpf_burst_base3; 15410 #define RXPF_BURST_BASE3_BASE_VAL3 (0x3fffUL<<7) 15411 15412 u32_t rxpf_burst_cmd0; 15413 #define RXPF_BURST_CMD0_FTQ_SEL (0x3UL<<0) 15414 #define RXPF_BURST_CMD0_FTQ_SEL_0 (0UL<<0) 15415 #define RXPF_BURST_CMD0_FTQ_SEL_1 (1UL<<0) 15416 #define RXPF_BURST_CMD0_FTQ_SEL_2 (2UL<<0) 15417 #define RXPF_BURST_CMD0_FTQ_SEL_3 (3UL<<0) 15418 #define RXPF_BURST_CMD0_BUSY (1UL<<2) 15419 #define RXPF_BURST_CMD0_OFFSET (0x1ffUL<<3) 15420 #define RXPF_BURST_CMD0_BASE_REG_SEL (1UL<<23) 15421 #define RXPF_BURST_CMD0_MOD_USAGE_CNT (0x3UL<<24) 15422 #define RXPF_BURST_CMD0_MOD_USAGE_CNT_00 (0UL<<24) 15423 #define RXPF_BURST_CMD0_MOD_USAGE_CNT_01 (1UL<<24) 15424 #define RXPF_BURST_CMD0_MOD_USAGE_CNT_10 (2UL<<24) 15425 #define RXPF_BURST_CMD0_MOD_USAGE_CNT_11 (3UL<<24) 15426 #define RXPF_BURST_CMD0_PREFETCH_SIZE (0x3UL<<26) 15427 #define RXPF_BURST_CMD0_NO_RAM_ACCESS (1UL<<28) 15428 #define RXPF_BURST_CMD0_NO_CACHE (1UL<<29) 15429 #define RXPF_BURST_CMD0_CROSS_BOUNDARY (1UL<<30) 15430 15431 u32_t rxpf_burst_cmd1; 15432 #define RXPF_BURST_CMD1_FTQ_SEL (0x3UL<<0) 15433 #define RXPF_BURST_CMD1_FTQ_SEL_0 (0UL<<0) 15434 #define RXPF_BURST_CMD1_FTQ_SEL_1 (1UL<<0) 15435 #define RXPF_BURST_CMD1_FTQ_SEL_2 (2UL<<0) 15436 #define RXPF_BURST_CMD1_FTQ_SEL_3 (3UL<<0) 15437 #define RXPF_BURST_CMD1_BUSY (1UL<<2) 15438 #define RXPF_BURST_CMD1_OFFSET (0x1ffUL<<3) 15439 #define RXPF_BURST_CMD1_BASE_REG_SEL (1UL<<23) 15440 #define RXPF_BURST_CMD1_MOD_USAGE_CNT (0x3UL<<24) 15441 #define RXPF_BURST_CMD1_MOD_USAGE_CNT_00 (0UL<<24) 15442 #define RXPF_BURST_CMD1_MOD_USAGE_CNT_01 (1UL<<24) 15443 #define RXPF_BURST_CMD1_MOD_USAGE_CNT_10 (2UL<<24) 15444 #define RXPF_BURST_CMD1_MOD_USAGE_CNT_11 (3UL<<24) 15445 #define RXPF_BURST_CMD1_PREFETCH_SIZE (0x3UL<<26) 15446 #define RXPF_BURST_CMD1_NO_RAM_ACCESS (1UL<<28) 15447 #define RXPF_BURST_CMD1_NO_CACHE (1UL<<29) 15448 #define RXPF_BURST_CMD1_CROSS_BOUNDARY (1UL<<30) 15449 15450 u32_t rxpf_burst_cmd2; 15451 #define RXPF_BURST_CMD2_FTQ_SEL (0x3UL<<0) 15452 #define RXPF_BURST_CMD2_FTQ_SEL_0 (0UL<<0) 15453 #define RXPF_BURST_CMD2_FTQ_SEL_1 (1UL<<0) 15454 #define RXPF_BURST_CMD2_FTQ_SEL_2 (2UL<<0) 15455 #define RXPF_BURST_CMD2_FTQ_SEL_3 (3UL<<0) 15456 #define RXPF_BURST_CMD2_BUSY (1UL<<2) 15457 #define RXPF_BURST_CMD2_OFFSET (0x1ffUL<<3) 15458 #define RXPF_BURST_CMD2_BASE_REG_SEL (1UL<<23) 15459 #define RXPF_BURST_CMD2_MOD_USAGE_CNT (0x3UL<<24) 15460 #define RXPF_BURST_CMD2_MOD_USAGE_CNT_00 (0UL<<24) 15461 #define RXPF_BURST_CMD2_MOD_USAGE_CNT_01 (1UL<<24) 15462 #define RXPF_BURST_CMD2_MOD_USAGE_CNT_10 (2UL<<24) 15463 #define RXPF_BURST_CMD2_MOD_USAGE_CNT_11 (3UL<<24) 15464 #define RXPF_BURST_CMD2_PREFETCH_SIZE (0x3UL<<26) 15465 #define RXPF_BURST_CMD2_NO_RAM_ACCESS (1UL<<28) 15466 #define RXPF_BURST_CMD2_NO_CACHE (1UL<<29) 15467 #define RXPF_BURST_CMD2_CROSS_BOUNDARY (1UL<<30) 15468 15469 u32_t rxpf_burst_cmd3; 15470 #define RXPF_BURST_CMD3_FTQ_SEL (0x3UL<<0) 15471 #define RXPF_BURST_CMD3_FTQ_SEL_0 (0UL<<0) 15472 #define RXPF_BURST_CMD3_FTQ_SEL_1 (1UL<<0) 15473 #define RXPF_BURST_CMD3_FTQ_SEL_2 (2UL<<0) 15474 #define RXPF_BURST_CMD3_FTQ_SEL_3 (3UL<<0) 15475 #define RXPF_BURST_CMD3_BUSY (1UL<<2) 15476 #define RXPF_BURST_CMD3_OFFSET (0x1ffUL<<3) 15477 #define RXPF_BURST_CMD3_BASE_REG_SEL (1UL<<23) 15478 #define RXPF_BURST_CMD3_MOD_USAGE_CNT (0x3UL<<24) 15479 #define RXPF_BURST_CMD3_MOD_USAGE_CNT_00 (0UL<<24) 15480 #define RXPF_BURST_CMD3_MOD_USAGE_CNT_01 (1UL<<24) 15481 #define RXPF_BURST_CMD3_MOD_USAGE_CNT_10 (2UL<<24) 15482 #define RXPF_BURST_CMD3_MOD_USAGE_CNT_11 (3UL<<24) 15483 #define RXPF_BURST_CMD3_PREFETCH_SIZE (0x3UL<<26) 15484 #define RXPF_BURST_CMD3_NO_RAM_ACCESS (1UL<<28) 15485 #define RXPF_BURST_CMD3_NO_CACHE (1UL<<29) 15486 #define RXPF_BURST_CMD3_CROSS_BOUNDARY (1UL<<30) 15487 15488 u32_t rxpf_burst_cmd4; 15489 #define RXPF_BURST_CMD4_FTQ_SEL (0x3UL<<0) 15490 #define RXPF_BURST_CMD4_FTQ_SEL_0 (0UL<<0) 15491 #define RXPF_BURST_CMD4_FTQ_SEL_1 (1UL<<0) 15492 #define RXPF_BURST_CMD4_FTQ_SEL_2 (2UL<<0) 15493 #define RXPF_BURST_CMD4_FTQ_SEL_3 (3UL<<0) 15494 #define RXPF_BURST_CMD4_BUSY (1UL<<2) 15495 #define RXPF_BURST_CMD4_OFFSET (0x1ffUL<<3) 15496 #define RXPF_BURST_CMD4_BASE_REG_SEL (1UL<<23) 15497 #define RXPF_BURST_CMD4_MOD_USAGE_CNT (0x3UL<<24) 15498 #define RXPF_BURST_CMD4_MOD_USAGE_CNT_00 (0UL<<24) 15499 #define RXPF_BURST_CMD4_MOD_USAGE_CNT_01 (1UL<<24) 15500 #define RXPF_BURST_CMD4_MOD_USAGE_CNT_10 (2UL<<24) 15501 #define RXPF_BURST_CMD4_MOD_USAGE_CNT_11 (3UL<<24) 15502 #define RXPF_BURST_CMD4_PREFETCH_SIZE (0x3UL<<26) 15503 #define RXPF_BURST_CMD4_NO_RAM_ACCESS (1UL<<28) 15504 #define RXPF_BURST_CMD4_NO_CACHE (1UL<<29) 15505 #define RXPF_BURST_CMD4_CROSS_BOUNDARY (1UL<<30) 15506 15507 u32_t rxpf_burst_cmd5; 15508 #define RXPF_BURST_CMD5_FTQ_SEL (0x3UL<<0) 15509 #define RXPF_BURST_CMD5_FTQ_SEL_0 (0UL<<0) 15510 #define RXPF_BURST_CMD5_FTQ_SEL_1 (1UL<<0) 15511 #define RXPF_BURST_CMD5_FTQ_SEL_2 (2UL<<0) 15512 #define RXPF_BURST_CMD5_FTQ_SEL_3 (3UL<<0) 15513 #define RXPF_BURST_CMD5_BUSY (1UL<<2) 15514 #define RXPF_BURST_CMD5_OFFSET (0x1ffUL<<3) 15515 #define RXPF_BURST_CMD5_BASE_REG_SEL (1UL<<23) 15516 #define RXPF_BURST_CMD5_MOD_USAGE_CNT (0x3UL<<24) 15517 #define RXPF_BURST_CMD5_MOD_USAGE_CNT_00 (0UL<<24) 15518 #define RXPF_BURST_CMD5_MOD_USAGE_CNT_01 (1UL<<24) 15519 #define RXPF_BURST_CMD5_MOD_USAGE_CNT_10 (2UL<<24) 15520 #define RXPF_BURST_CMD5_MOD_USAGE_CNT_11 (3UL<<24) 15521 #define RXPF_BURST_CMD5_PREFETCH_SIZE (0x3UL<<26) 15522 #define RXPF_BURST_CMD5_NO_RAM_ACCESS (1UL<<28) 15523 #define RXPF_BURST_CMD5_NO_CACHE (1UL<<29) 15524 #define RXPF_BURST_CMD5_CROSS_BOUNDARY (1UL<<30) 15525 15526 u32_t rxpf_burst_cmd6; 15527 #define RXPF_BURST_CMD6_FTQ_SEL (0x3UL<<0) 15528 #define RXPF_BURST_CMD6_FTQ_SEL_0 (0UL<<0) 15529 #define RXPF_BURST_CMD6_FTQ_SEL_1 (1UL<<0) 15530 #define RXPF_BURST_CMD6_FTQ_SEL_2 (2UL<<0) 15531 #define RXPF_BURST_CMD6_FTQ_SEL_3 (3UL<<0) 15532 #define RXPF_BURST_CMD6_BUSY (1UL<<2) 15533 #define RXPF_BURST_CMD6_OFFSET (0x1ffUL<<3) 15534 #define RXPF_BURST_CMD6_BASE_REG_SEL (1UL<<23) 15535 #define RXPF_BURST_CMD6_MOD_USAGE_CNT (0x3UL<<24) 15536 #define RXPF_BURST_CMD6_MOD_USAGE_CNT_00 (0UL<<24) 15537 #define RXPF_BURST_CMD6_MOD_USAGE_CNT_01 (1UL<<24) 15538 #define RXPF_BURST_CMD6_MOD_USAGE_CNT_10 (2UL<<24) 15539 #define RXPF_BURST_CMD6_MOD_USAGE_CNT_11 (3UL<<24) 15540 #define RXPF_BURST_CMD6_PREFETCH_SIZE (0x3UL<<26) 15541 #define RXPF_BURST_CMD6_NO_RAM_ACCESS (1UL<<28) 15542 #define RXPF_BURST_CMD6_NO_CACHE (1UL<<29) 15543 #define RXPF_BURST_CMD6_CROSS_BOUNDARY (1UL<<30) 15544 15545 u32_t rxpf_burst_cmd7; 15546 #define RXPF_BURST_CMD7_FTQ_SEL (0x3UL<<0) 15547 #define RXPF_BURST_CMD7_FTQ_SEL_0 (0UL<<0) 15548 #define RXPF_BURST_CMD7_FTQ_SEL_1 (1UL<<0) 15549 #define RXPF_BURST_CMD7_FTQ_SEL_2 (2UL<<0) 15550 #define RXPF_BURST_CMD7_FTQ_SEL_3 (3UL<<0) 15551 #define RXPF_BURST_CMD7_BUSY (1UL<<2) 15552 #define RXPF_BURST_CMD7_OFFSET (0x1ffUL<<3) 15553 #define RXPF_BURST_CMD7_BASE_REG_SEL (1UL<<23) 15554 #define RXPF_BURST_CMD7_MOD_USAGE_CNT (0x3UL<<24) 15555 #define RXPF_BURST_CMD7_MOD_USAGE_CNT_00 (0UL<<24) 15556 #define RXPF_BURST_CMD7_MOD_USAGE_CNT_01 (1UL<<24) 15557 #define RXPF_BURST_CMD7_MOD_USAGE_CNT_10 (2UL<<24) 15558 #define RXPF_BURST_CMD7_MOD_USAGE_CNT_11 (3UL<<24) 15559 #define RXPF_BURST_CMD7_PREFETCH_SIZE (0x3UL<<26) 15560 #define RXPF_BURST_CMD7_NO_RAM_ACCESS (1UL<<28) 15561 #define RXPF_BURST_CMD7_NO_CACHE (1UL<<29) 15562 #define RXPF_BURST_CMD7_CROSS_BOUNDARY (1UL<<30) 15563 15564 u32_t rxpf_ctx_cmd; 15565 #define RXPF_CTX_CMD_NUM_BLOCKS (0x3UL<<0) 15566 #define RXPF_CTX_CMD_OFFSET (0x1ffUL<<3) 15567 #define RXPF_CTX_CMD_CID_VALUE (0x3fffUL<<12) 15568 #define RXPF_CTX_CMD_PREFETCH_SIZE (0x3UL<<26) 15569 #define RXPF_CTX_CMD_MOD_USAGE_CNT (0x3UL<<28) 15570 #define RXPF_CTX_CMD_MOD_USAGE_CNT_00 (0UL<<28) 15571 #define RXPF_CTX_CMD_MOD_USAGE_CNT_01 (1UL<<28) 15572 #define RXPF_CTX_CMD_MOD_USAGE_CNT_10 (2UL<<28) 15573 #define RXPF_CTX_CMD_MOD_USAGE_CNT_11 (3UL<<28) 15574 u32_t unused_23[51]; 15575 15576 u32_t rxpf_burst_data0[16]; 15577 u32_t rxpf_burst_data1[16]; 15578 u32_t rxpf_burst_data2[16]; 15579 u32_t rxpf_burst_data3[16]; 15580 u32_t rxpf_burst_data4[16]; 15581 u32_t rxpf_burst_data5[16]; 15582 u32_t rxpf_burst_data6[16]; 15583 u32_t rxpf_burst_data7[16]; 15584 u32_t unused_24[64]; 15585 u32_t rxpf_rbuf_burst_data[32]; 15586 u32_t unused_25[3296]; 15587 u32_t rxpf_rx_mbuf[4096]; 15588 u32_t unused_26[57344]; 15589 u32_t rxpf_ctx_window5[32768]; 15590 u32_t rxpf_ctx_window6[32768]; 15591 u32_t rxpf_ctx_window1[32768]; 15592 u32_t rxpf_ctx_window2[32768]; 15593 u32_t rxpf_ctx_window3[32768]; 15594 u32_t rxpf_ctx_window4[32768]; 15595 } rxp_fio_xi_t; 15596 15597 15598 /* 15599 * com_fio definition 15600 * offset: 0x80000000 15601 */ 15602 typedef struct com_fio 15603 { 15604 u32_t comf_events_bits; 15605 #define COMF_EVENTS_BITS_GPIO0 (1UL<<15) 15606 #define COMF_EVENTS_BITS_GPIO1 (1UL<<16) 15607 #define COMF_EVENTS_BITS_GPIO2 (1UL<<17) 15608 #define COMF_EVENTS_BITS_GPIO3 (1UL<<18) 15609 15610 u32_t comf_attentions_bits; 15611 #define COMF_ATTENTIONS_BITS_EPB_ERROR (1UL<<30) 15612 15613 u32_t comf_event_enable; 15614 u32_t comf_attention_enable; 15615 u32_t comf_fio_status; 15616 15617 u32_t comf_mult_result; 15618 u32_t comf_mult_a; 15619 15620 u32_t comf_mult_b; 15621 15622 u32_t comf_ctx_window_cid1; 15623 15624 u32_t comf_ctx_window_cid2; 15625 #define COMF_CTX_WINDOW_CID2_CTX_WINDOW_CID2_VALUE (0x3fffUL<<7) 15626 15627 u32_t comf_ctx_window_cid3; 15628 #define COMF_CTX_WINDOW_CID3_CTX_WINDOW_CID3_VALUE (0x3fffUL<<7) 15629 15630 u32_t comf_ctx_window_cid4; 15631 #define COMF_CTX_WINDOW_CID4_CTX_WINDOW_CID4_VALUE (0x3fffUL<<7) 15632 15633 u32_t comf_dma_len; 15634 #define COMF_DMA_LEN_BYTE_SWAP (1UL<<24) 15635 15636 u32_t comf_dma_status; 15637 #define COMF_DMA_STATUS_WRITE_MASTER_ABORT (1UL<<3) 15638 #define COMF_DMA_STATUS_READ_MASTER_ABORT (1UL<<20) 15639 15640 u32_t comf_dma_addr_h; 15641 u32_t comf_dma_addr_l; 15642 u32_t comf_com_hc_inc_stat[12]; 15643 u32_t comf_free_counter_value; 15644 u32_t comf_timer_retran_value; 15645 u16_t comf_timer_rxpush_value; 15646 u16_t comf_timer_delayack_value; 15647 u16_t comf_timer_keepalive_value; 15648 u16_t comf_timer_nagle_value; 15649 u16_t comf_com_hc_rx_quick_cons_idx[16]; 15650 u16_t comf_com_hc_cmd; 15651 #define COMF_COM_HC_CMD_COALESCE_NOW (1<<0) 15652 15653 u16_t comf_com_hc_prod_idx; 15654 u32_t comf_rbdc_flush; 15655 15656 u32_t comf_com_rbuf_cluster; 15657 u32_t unused_0[17]; 15658 15659 u32_t comf_msi_req_value; 15660 u32_t comf_msi_status; 15661 #define COMF_MSI_STATUS_BUSY (1UL<<31) 15662 15663 u32_t comf_msi_addr_h; 15664 u32_t comf_msi_addr_l; 15665 u32_t comf_comq_cid; 15666 u32_t comf_comq_mbuf_cluster; 15667 u16_t comf_comq_operand_flags; 15668 u8_t comf_comq_knum; 15669 u8_t comf_comq_opcode; 15670 u16_t comf_comq_operand16_2; 15671 u16_t comf_comq_operand16_3; 15672 u16_t comf_comq_operand16_4; 15673 u16_t comf_comq_operand16_5; 15674 u16_t comf_comq_operand16_6; 15675 u16_t comf_comq_operand16_7; 15676 u32_t comf_comq_operand32_2; 15677 u32_t comf_comq_operand32_3; 15678 u32_t comf_comq_operand32_4; 15679 u8_t comf_comq_rdma_action; 15680 u8_t unused_1; 15681 u16_t unused_2; 15682 u32_t unused_3[4]; 15683 u32_t comf_comq_ftq_cmd; 15684 u32_t unused_4; 15685 15686 u32_t comf_comtq_cid; 15687 u32_t comf_comtq_val; 15688 u8_t comf_comtq_type; 15689 u8_t unused_5; 15690 u16_t unused_6; 15691 u32_t unused_7[11]; 15692 u32_t comf_comtq_ftq_cmd; 15693 u32_t unused_8; 15694 15695 u32_t comf_comxq_cid; 15696 u16_t comf_comxq_flags; 15697 u16_t unused_9; 15698 15699 u32_t comf_comxq_snd_next; 15700 u32_t unused_10[11]; 15701 u32_t comf_comxq_ftq_cmd; 15702 u32_t unused_11; 15703 15704 u32_t comf_tschq_cid; 15705 u8_t comf_tschq_flags; 15706 u8_t unused_12; 15707 u16_t unused_13; 15708 u32_t unused_14[12]; 15709 15710 u32_t comf_tschq_ftq_cmd; 15711 u32_t unused_15; 15712 15713 u32_t comf_rv2ptq_cid; 15714 u32_t unused_16[13]; 15715 u32_t comf_rv2ptq_ftq_cmd; 15716 u32_t unused_17; 15717 15718 u32_t comf_csq_cid; 15719 u8_t comf_csq_flags; 15720 u8_t unused_18; 15721 u16_t unused_19; 15722 u32_t unused_20[12]; 15723 15724 u32_t comf_csq_ftq_cmd; 15725 u32_t unused_21; 15726 15727 u32_t comf_mcpq_bits_status; 15728 u16_t comf_mcpq_pkt_len; 15729 u16_t unused_22; 15730 u32_t comf_mcpq_mbuf_cluster; 15731 u32_t unused_23[11]; 15732 u32_t comf_mcpq_ftq_cmd; 15733 u32_t unused_24[81]; 15734 15735 u32_t comf_dma_data[128]; 15736 u32_t unused_25[128]; 15737 u32_t comf_burst_base0; 15738 15739 u32_t comf_burst_base1; 15740 15741 u32_t comf_burst_base2; 15742 15743 u32_t comf_burst_base3; 15744 15745 u32_t comf_burst_cmd0; 15746 15747 u32_t comf_burst_cmd1; 15748 15749 u32_t comf_burst_cmd2; 15750 15751 u32_t comf_burst_cmd3; 15752 u32_t unused_26[56]; 15753 15754 u32_t comf_burst_data0[16]; 15755 u32_t comf_burst_data1[16]; 15756 u32_t comf_burst_data2[16]; 15757 u32_t comf_burst_data3[16]; 15758 u32_t unused_27[3456]; 15759 u32_t comf_com_mbuf[4096]; 15760 u32_t unused_28[122880]; 15761 u32_t comf_ctx_window1[32768]; 15762 u32_t comf_ctx_window2[32768]; 15763 u32_t comf_ctx_window3[32768]; 15764 u32_t comf_ctx_window4[32768]; 15765 } com_fio_t; 15766 15767 15768 /* 15769 * com_fio definition 15770 * offset: 0x80000000 15771 */ 15772 typedef struct com_fio_xi 15773 { 15774 u32_t comf_events_bits; 15775 #define COMF_EVENTS_BITS_FTQ0_VALID (1UL<<0) 15776 #define COMF_EVENTS_BITS_FTQ1_VALID (1UL<<1) 15777 #define COMF_EVENTS_BITS_FTQ2_VALID (1UL<<2) 15778 #define COMF_EVENTS_BITS_SCANNER_DONE (1UL<<3) 15779 #define COMF_EVENTS_BITS_DMA_WR_DONE (1UL<<4) 15780 #define COMF_EVENTS_BITS_DMA_RD_DONE (1UL<<5) 15781 #define COMF_EVENTS_BITS_CRACKER_DONE (1UL<<6) 15782 #define COMF_EVENTS_BITS_MULTIPLY_DONE (1UL<<7) 15783 #define COMF_EVENTS_BITS_EXP_ROM (1UL<<8) 15784 #define COMF_EVENTS_BITS_VPD (1UL<<9) 15785 #define COMF_EVENTS_BITS_FLASH (1UL<<10) 15786 #define COMF_EVENTS_BITS_SMB0 (1UL<<11) 15787 #define COMF_EVENTS_BITS_RESERVED0 (1UL<<12) 15788 #define COMF_EVENTS_BITS_RESERVED1 (1UL<<13) 15789 #define COMF_EVENTS_BITS_RESERVED2 (1UL<<14) 15790 #define COMF_EVENTS_BITS_GPIO (1UL<<15) 15791 #define COMF_EVENTS_BITS_SW_TMR_1 (1UL<<19) 15792 #define COMF_EVENTS_BITS_SW_TMR_2 (1UL<<20) 15793 #define COMF_EVENTS_BITS_SW_TMR_3 (1UL<<21) 15794 #define COMF_EVENTS_BITS_SW_TMR_4 (1UL<<22) 15795 #define COMF_EVENTS_BITS_LINK_CHANGED (1UL<<23) 15796 #define COMF_EVENTS_BITS_MI_INT (1UL<<25) 15797 #define COMF_EVENTS_BITS_MI_COMPLETE (1UL<<26) 15798 #define COMF_EVENTS_BITS_MAIN_PWR_INT (1UL<<27) 15799 #define COMF_EVENTS_BITS_NOT_ENABLED (1UL<<30) 15800 #define COMF_EVENTS_BITS_ATTENTIONS_VALID (1UL<<31) 15801 15802 u32_t comf_attentions_bits; 15803 #define COMF_ATTENTIONS_BITS_LINK_STATE (1UL<<0) 15804 #define COMF_ATTENTIONS_BITS_TX_SCHEDULER_ABORT (1UL<<1) 15805 #define COMF_ATTENTIONS_BITS_TX_BD_READ_ABORT (1UL<<2) 15806 #define COMF_ATTENTIONS_BITS_TX_BD_CACHE_ABORT (1UL<<3) 15807 #define COMF_ATTENTIONS_BITS_TX_PROCESSOR_ABORT (1UL<<4) 15808 #define COMF_ATTENTIONS_BITS_TX_DMA_ABORT (1UL<<5) 15809 #define COMF_ATTENTIONS_BITS_TX_PATCHUP_ABORT (1UL<<6) 15810 #define COMF_ATTENTIONS_BITS_TX_ASSEMBLER_ABORT (1UL<<7) 15811 #define COMF_ATTENTIONS_BITS_RX_PARSER_MAC_ABORT (1UL<<8) 15812 #define COMF_ATTENTIONS_BITS_RX_PARSER_CATCHUP_ABORT (1UL<<9) 15813 #define COMF_ATTENTIONS_BITS_RX_MBUF_ABORT (1UL<<10) 15814 #define COMF_ATTENTIONS_BITS_RX_LOOKUP_ABORT (1UL<<11) 15815 #define COMF_ATTENTIONS_BITS_RX_PROCESSOR_ABORT (1UL<<12) 15816 #define COMF_ATTENTIONS_BITS_RX_V2P_ABORT (1UL<<13) 15817 #define COMF_ATTENTIONS_BITS_RX_BD_CACHE_ABORT (1UL<<14) 15818 #define COMF_ATTENTIONS_BITS_RX_DMA_ABORT (1UL<<15) 15819 #define COMF_ATTENTIONS_BITS_COMPLETION_ABORT (1UL<<16) 15820 #define COMF_ATTENTIONS_BITS_HOST_COALESCE_ABORT (1UL<<17) 15821 #define COMF_ATTENTIONS_BITS_MAILBOX_QUEUE_ABORT (1UL<<18) 15822 #define COMF_ATTENTIONS_BITS_CONTEXT_ABORT (1UL<<19) 15823 #define COMF_ATTENTIONS_BITS_CMD_SCHEDULER_ABORT (1UL<<20) 15824 #define COMF_ATTENTIONS_BITS_CMD_PROCESSOR_ABORT (1UL<<21) 15825 #define COMF_ATTENTIONS_BITS_MGMT_PROCESSOR_ABORT (1UL<<22) 15826 #define COMF_ATTENTIONS_BITS_MAC_ABORT (1UL<<23) 15827 #define COMF_ATTENTIONS_BITS_TIMER_ABORT (1UL<<24) 15828 #define COMF_ATTENTIONS_BITS_DMAE_ABORT (1UL<<25) 15829 #define COMF_ATTENTIONS_BITS_FLSH_ABORT (1UL<<26) 15830 #define COMF_ATTENTIONS_BITS_GRC_ABORT (1UL<<27) 15831 #define COMF_ATTENTIONS_BITS_PARITY_ERROR (1UL<<31) 15832 15833 u32_t comf_event_enable; 15834 u32_t comf_attention_enable; 15835 u32_t comf_fio_status; 15836 #define COMF_FIO_STATUS_ENABLED (1UL<<0) 15837 #define COMF_FIO_STATUS_FORCE_ENA (1UL<<1) 15838 15839 u32_t comf_mult_result; 15840 u32_t comf_mult_a; 15841 #define COMF_MULT_A_VALUE (0xffffUL<<0) 15842 15843 u32_t comf_mult_b; 15844 #define COMF_MULT_B_VALUE (0xffffUL<<0) 15845 15846 u32_t comf_ctx_window_cid1; 15847 #define COMF_CTX_WINDOW_CID1_LOCK_TYPE (0x7UL<<0) 15848 #define COMF_CTX_WINDOW_CID1_LOCK_TYPE_VOID (0UL<<0) 15849 #define COMF_CTX_WINDOW_CID1_LOCK_TYPE_PROTOCOL (1UL<<0) 15850 #define COMF_CTX_WINDOW_CID1_LOCK_TYPE_TX (2UL<<0) 15851 #define COMF_CTX_WINDOW_CID1_LOCK_TYPE_TIMER (4UL<<0) 15852 #define COMF_CTX_WINDOW_CID1_LOCK_TYPE_COMPLETE (7UL<<0) 15853 #define COMF_CTX_WINDOW_CID1_VALUE (0x3fffUL<<7) 15854 #define COMF_CTX_WINDOW_CID1_MOD_USAGE_CNT (0x3UL<<24) 15855 #define COMF_CTX_WINDOW_CID1_MOD_USAGE_CNT_00 (0UL<<24) 15856 #define COMF_CTX_WINDOW_CID1_MOD_USAGE_CNT_01 (1UL<<24) 15857 #define COMF_CTX_WINDOW_CID1_MOD_USAGE_CNT_10 (2UL<<24) 15858 #define COMF_CTX_WINDOW_CID1_MOD_USAGE_CNT_11 (3UL<<24) 15859 #define COMF_CTX_WINDOW_CID1_LOCK_GRANTED (1UL<<26) 15860 #define COMF_CTX_WINDOW_CID1_LOCK_MODE (0x3UL<<27) 15861 #define COMF_CTX_WINDOW_CID1_LOCK_MODE_UNLOCK (0UL<<27) 15862 #define COMF_CTX_WINDOW_CID1_LOCK_MODE_IMMEDIATE (1UL<<27) 15863 #define COMF_CTX_WINDOW_CID1_LOCK_MODE_SURE (2UL<<27) 15864 #define COMF_CTX_WINDOW_CID1_NO_EXT_ACC (1UL<<29) 15865 #define COMF_CTX_WINDOW_CID1_LOCK_STATUS (1UL<<30) 15866 #define COMF_CTX_WINDOW_CID1_LOCK_REQ (1UL<<31) 15867 15868 u32_t comf_ctx_window_cid2; 15869 #define COMF_CTX_WINDOW_CID2_LOCK_TYPE (0x7UL<<0) 15870 #define COMF_CTX_WINDOW_CID2_LOCK_TYPE_VOID (0UL<<0) 15871 #define COMF_CTX_WINDOW_CID2_LOCK_TYPE_PROTOCOL (1UL<<0) 15872 #define COMF_CTX_WINDOW_CID2_LOCK_TYPE_TX (2UL<<0) 15873 #define COMF_CTX_WINDOW_CID2_LOCK_TYPE_TIMER (4UL<<0) 15874 #define COMF_CTX_WINDOW_CID2_LOCK_TYPE_COMPLETE (7UL<<0) 15875 #define COMF_CTX_WINDOW_CID2_VALUE (0x3fffUL<<7) 15876 #define COMF_CTX_WINDOW_CID2_MOD_USAGE_CNT (0x3UL<<24) 15877 #define COMF_CTX_WINDOW_CID2_MOD_USAGE_CNT_00 (0UL<<24) 15878 #define COMF_CTX_WINDOW_CID2_MOD_USAGE_CNT_01 (1UL<<24) 15879 #define COMF_CTX_WINDOW_CID2_MOD_USAGE_CNT_10 (2UL<<24) 15880 #define COMF_CTX_WINDOW_CID2_MOD_USAGE_CNT_11 (3UL<<24) 15881 #define COMF_CTX_WINDOW_CID2_LOCK_GRANTED (1UL<<26) 15882 #define COMF_CTX_WINDOW_CID2_LOCK_MODE (0x3UL<<27) 15883 #define COMF_CTX_WINDOW_CID2_LOCK_MODE_UNLOCK (0UL<<27) 15884 #define COMF_CTX_WINDOW_CID2_LOCK_MODE_IMMEDIATE (1UL<<27) 15885 #define COMF_CTX_WINDOW_CID2_LOCK_MODE_SURE (2UL<<27) 15886 #define COMF_CTX_WINDOW_CID2_NO_EXT_ACC (1UL<<29) 15887 #define COMF_CTX_WINDOW_CID2_LOCK_STATUS (1UL<<30) 15888 #define COMF_CTX_WINDOW_CID2_LOCK_REQ (1UL<<31) 15889 15890 u32_t comf_ctx_window_cid3; 15891 #define COMF_CTX_WINDOW_CID3_LOCK_TYPE (0x7UL<<0) 15892 #define COMF_CTX_WINDOW_CID3_LOCK_TYPE_VOID (0UL<<0) 15893 #define COMF_CTX_WINDOW_CID3_LOCK_TYPE_PROTOCOL (1UL<<0) 15894 #define COMF_CTX_WINDOW_CID3_LOCK_TYPE_TX (2UL<<0) 15895 #define COMF_CTX_WINDOW_CID3_LOCK_TYPE_TIMER (4UL<<0) 15896 #define COMF_CTX_WINDOW_CID3_LOCK_TYPE_COMPLETE (7UL<<0) 15897 #define COMF_CTX_WINDOW_CID3_VALUE (0x3fffUL<<7) 15898 #define COMF_CTX_WINDOW_CID3_MOD_USAGE_CNT (0x3UL<<24) 15899 #define COMF_CTX_WINDOW_CID3_MOD_USAGE_CNT_00 (0UL<<24) 15900 #define COMF_CTX_WINDOW_CID3_MOD_USAGE_CNT_01 (1UL<<24) 15901 #define COMF_CTX_WINDOW_CID3_MOD_USAGE_CNT_10 (2UL<<24) 15902 #define COMF_CTX_WINDOW_CID3_MOD_USAGE_CNT_11 (3UL<<24) 15903 #define COMF_CTX_WINDOW_CID3_LOCK_GRANTED (1UL<<26) 15904 #define COMF_CTX_WINDOW_CID3_LOCK_MODE (0x3UL<<27) 15905 #define COMF_CTX_WINDOW_CID3_LOCK_MODE_UNLOCK (0UL<<27) 15906 #define COMF_CTX_WINDOW_CID3_LOCK_MODE_IMMEDIATE (1UL<<27) 15907 #define COMF_CTX_WINDOW_CID3_LOCK_MODE_SURE (2UL<<27) 15908 #define COMF_CTX_WINDOW_CID3_NO_EXT_ACC (1UL<<29) 15909 #define COMF_CTX_WINDOW_CID3_LOCK_STATUS (1UL<<30) 15910 #define COMF_CTX_WINDOW_CID3_LOCK_REQ (1UL<<31) 15911 15912 u32_t comf_ctx_window_cid4; 15913 #define COMF_CTX_WINDOW_CID4_LOCK_TYPE (0x7UL<<0) 15914 #define COMF_CTX_WINDOW_CID4_LOCK_TYPE_VOID (0UL<<0) 15915 #define COMF_CTX_WINDOW_CID4_LOCK_TYPE_PROTOCOL (1UL<<0) 15916 #define COMF_CTX_WINDOW_CID4_LOCK_TYPE_TX (2UL<<0) 15917 #define COMF_CTX_WINDOW_CID4_LOCK_TYPE_TIMER (4UL<<0) 15918 #define COMF_CTX_WINDOW_CID4_LOCK_TYPE_COMPLETE (7UL<<0) 15919 #define COMF_CTX_WINDOW_CID4_VALUE (0x3fffUL<<7) 15920 #define COMF_CTX_WINDOW_CID4_MOD_USAGE_CNT (0x3UL<<24) 15921 #define COMF_CTX_WINDOW_CID4_MOD_USAGE_CNT_00 (0UL<<24) 15922 #define COMF_CTX_WINDOW_CID4_MOD_USAGE_CNT_01 (1UL<<24) 15923 #define COMF_CTX_WINDOW_CID4_MOD_USAGE_CNT_10 (2UL<<24) 15924 #define COMF_CTX_WINDOW_CID4_MOD_USAGE_CNT_11 (3UL<<24) 15925 #define COMF_CTX_WINDOW_CID4_LOCK_GRANTED (1UL<<26) 15926 #define COMF_CTX_WINDOW_CID4_LOCK_MODE (0x3UL<<27) 15927 #define COMF_CTX_WINDOW_CID4_LOCK_MODE_UNLOCK (0UL<<27) 15928 #define COMF_CTX_WINDOW_CID4_LOCK_MODE_IMMEDIATE (1UL<<27) 15929 #define COMF_CTX_WINDOW_CID4_LOCK_MODE_SURE (2UL<<27) 15930 #define COMF_CTX_WINDOW_CID4_NO_EXT_ACC (1UL<<29) 15931 #define COMF_CTX_WINDOW_CID4_LOCK_STATUS (1UL<<30) 15932 #define COMF_CTX_WINDOW_CID4_LOCK_REQ (1UL<<31) 15933 15934 u32_t comf_dma_len; 15935 #define COMF_DMA_LEN_LEN (0x3ffUL<<0) 15936 #define COMF_DMA_LEN_WRITE_START (1UL<<16) 15937 #define COMF_DMA_LEN_WRITE_STOP (1UL<<17) 15938 #define COMF_DMA_LEN_WRITE_EVENT_CLEAR (1UL<<18) 15939 #define COMF_DMA_LEN_READ_START (1UL<<20) 15940 #define COMF_DMA_LEN_READ_STOP (1UL<<21) 15941 #define COMF_DMA_LEN_READ_EVENT_CLEAR (1UL<<22) 15942 #define COMF_DMA_LEN_TYPE (0x3UL<<23) 15943 #define COMF_DMA_LEN_TYPE_CONFIG (0UL<<23) 15944 #define COMF_DMA_LEN_TYPE_DATA (1UL<<23) 15945 #define COMF_DMA_LEN_TYPE_CONTROL (2UL<<23) 15946 #define COMF_DMA_LEN_NO_SNOOP (1UL<<25) 15947 #define COMF_DMA_LEN_PRIORITY (1UL<<26) 15948 #define COMF_DMA_LEN_RELAXED_ORDERING (1UL<<27) 15949 #define COMF_DMA_LEN_WRITE_RESET (1UL<<30) 15950 #define COMF_DMA_LEN_READ_RESET (1UL<<31) 15951 15952 u32_t comf_dma_status; 15953 #define COMF_DMA_STATUS_WRITE_CHAN_REQ (1UL<<0) 15954 #define COMF_DMA_STATUS_WRITE_ACTIVE (1UL<<1) 15955 #define COMF_DMA_STATUS_WRITE_DONE (1UL<<2) 15956 #define COMF_DMA_STATUS_READ_CHAN_REQ (1UL<<16) 15957 #define COMF_DMA_STATUS_READ_ACTIVE (1UL<<17) 15958 #define COMF_DMA_STATUS_READ_DONE (1UL<<19) 15959 #define COMF_DMA_STATUS_READ_CS16_ERROR (1UL<<20) 15960 15961 u32_t comf_dma_addr_h; 15962 u32_t comf_dma_addr_l; 15963 u32_t comf_com_hc_inc_stat[12]; 15964 u32_t comf_free_counter_value; 15965 u32_t comf_timer_retran_value; 15966 u16_t comf_timer_rxpush_value; 15967 u16_t comf_timer_delayack_value; 15968 u16_t comf_timer_keepalive_value; 15969 u16_t comf_timer_nagle_value; 15970 u32_t comf_com_rx_quick_cons_idx; 15971 #define COMF_COM_RX_QUICK_CONS_IDX_INDEX_VAL (0xffffUL<<0) 15972 #define COMF_COM_RX_QUICK_CONS_IDX_INDEX_NUM (0xfUL<<20) 15973 #define COMF_COM_RX_QUICK_CONS_IDX_COALESCE_NOW (1UL<<30) 15974 #define COMF_COM_RX_QUICK_CONS_IDX_REQ_N (1UL<<31) 15975 u32_t unused_0[3]; 15976 15977 u32_t comf_ctx_window_cid5; 15978 #define COMF_CTX_WINDOW_CID5_LOCK_TYPE (0x7UL<<0) 15979 #define COMF_CTX_WINDOW_CID5_LOCK_TYPE_VOID (0UL<<0) 15980 #define COMF_CTX_WINDOW_CID5_LOCK_TYPE_PROTOCOL (1UL<<0) 15981 #define COMF_CTX_WINDOW_CID5_LOCK_TYPE_TX (2UL<<0) 15982 #define COMF_CTX_WINDOW_CID5_LOCK_TYPE_TIMER (4UL<<0) 15983 #define COMF_CTX_WINDOW_CID5_LOCK_TYPE_COMPLETE (7UL<<0) 15984 #define COMF_CTX_WINDOW_CID5_VALUE (0x3fffUL<<7) 15985 #define COMF_CTX_WINDOW_CID5_MOD_USAGE_CNT (0x3UL<<24) 15986 #define COMF_CTX_WINDOW_CID5_MOD_USAGE_CNT_00 (0UL<<24) 15987 #define COMF_CTX_WINDOW_CID5_MOD_USAGE_CNT_01 (1UL<<24) 15988 #define COMF_CTX_WINDOW_CID5_MOD_USAGE_CNT_10 (2UL<<24) 15989 #define COMF_CTX_WINDOW_CID5_MOD_USAGE_CNT_11 (3UL<<24) 15990 #define COMF_CTX_WINDOW_CID5_LOCK_GRANTED (1UL<<26) 15991 #define COMF_CTX_WINDOW_CID5_LOCK_MODE (0x3UL<<27) 15992 #define COMF_CTX_WINDOW_CID5_LOCK_MODE_UNLOCK (0UL<<27) 15993 #define COMF_CTX_WINDOW_CID5_LOCK_MODE_IMMEDIATE (1UL<<27) 15994 #define COMF_CTX_WINDOW_CID5_LOCK_MODE_SURE (2UL<<27) 15995 #define COMF_CTX_WINDOW_CID5_NO_EXT_ACC (1UL<<29) 15996 #define COMF_CTX_WINDOW_CID5_LOCK_STATUS (1UL<<30) 15997 #define COMF_CTX_WINDOW_CID5_LOCK_REQ (1UL<<31) 15998 15999 u32_t comf_ctx_window_cid6; 16000 #define COMF_CTX_WINDOW_CID6_LOCK_TYPE (0x7UL<<0) 16001 #define COMF_CTX_WINDOW_CID6_LOCK_TYPE_VOID (0UL<<0) 16002 #define COMF_CTX_WINDOW_CID6_LOCK_TYPE_PROTOCOL (1UL<<0) 16003 #define COMF_CTX_WINDOW_CID6_LOCK_TYPE_TX (2UL<<0) 16004 #define COMF_CTX_WINDOW_CID6_LOCK_TYPE_TIMER (4UL<<0) 16005 #define COMF_CTX_WINDOW_CID6_LOCK_TYPE_COMPLETE (7UL<<0) 16006 #define COMF_CTX_WINDOW_CID6_VALUE (0x3fffUL<<7) 16007 #define COMF_CTX_WINDOW_CID6_MOD_USAGE_CNT (0x3UL<<24) 16008 #define COMF_CTX_WINDOW_CID6_MOD_USAGE_CNT_00 (0UL<<24) 16009 #define COMF_CTX_WINDOW_CID6_MOD_USAGE_CNT_01 (1UL<<24) 16010 #define COMF_CTX_WINDOW_CID6_MOD_USAGE_CNT_10 (2UL<<24) 16011 #define COMF_CTX_WINDOW_CID6_MOD_USAGE_CNT_11 (3UL<<24) 16012 #define COMF_CTX_WINDOW_CID6_LOCK_GRANTED (1UL<<26) 16013 #define COMF_CTX_WINDOW_CID6_LOCK_MODE (0x3UL<<27) 16014 #define COMF_CTX_WINDOW_CID6_LOCK_MODE_UNLOCK (0UL<<27) 16015 #define COMF_CTX_WINDOW_CID6_LOCK_MODE_IMMEDIATE (1UL<<27) 16016 #define COMF_CTX_WINDOW_CID6_LOCK_MODE_SURE (2UL<<27) 16017 #define COMF_CTX_WINDOW_CID6_NO_EXT_ACC (1UL<<29) 16018 #define COMF_CTX_WINDOW_CID6_LOCK_STATUS (1UL<<30) 16019 #define COMF_CTX_WINDOW_CID6_LOCK_REQ (1UL<<31) 16020 u32_t unused_1[2]; 16021 16022 u32_t comf_com_comp_prod_idx; 16023 #define COMF_COM_COMP_PROD_IDX_INDEX_VAL (0xffffUL<<0) 16024 #define COMF_COM_COMP_PROD_IDX_INDEX_NUM (0xfUL<<20) 16025 #define COMF_COM_COMP_PROD_IDX_COALESCE_NOW (1UL<<30) 16026 #define COMF_COM_COMP_PROD_IDX_REQ_N (1UL<<31) 16027 16028 u32_t comf_rbdc_flush; 16029 #define COMF_RBDC_FLUSH_TYPE (1UL<<0) 16030 #define COMF_RBDC_FLUSH_CID (0x3fffUL<<7) 16031 16032 u32_t comf_com_rbuf_cluster; 16033 #define COMF_COM_RBUF_CLUSTER_COUNT (0x7fUL<<0) 16034 #define COMF_COM_RBUF_CLUSTER_TAIL (0x1ffUL<<7) 16035 #define COMF_COM_RBUF_CLUSTER_HEAD (0x1ffUL<<16) 16036 #define COMF_COM_RBUF_CLUSTER_TYPE (1UL<<25) 16037 #define COMF_COM_RBUF_CLUSTER_FREE (1UL<<31) 16038 u32_t unused_2[21]; 16039 16040 const u32_t comf_comq_cid; 16041 const u32_t comf_comq_mbuf_cluster; 16042 const u16_t comf_comq_operand_flags; 16043 const u8_t comf_comq_knum; 16044 const u8_t comf_comq_opcode; 16045 const u16_t comf_comq_operand16_2; 16046 const u16_t comf_comq_operand16_3; 16047 const u16_t comf_comq_operand16_4; 16048 const u16_t comf_comq_operand16_5; 16049 const u16_t comf_comq_operand16_6; 16050 const u16_t comf_comq_operand16_7; 16051 const u32_t comf_comq_operand32_2; 16052 const u32_t comf_comq_operand32_3; 16053 const u32_t comf_comq_operand32_4; 16054 const u8_t comf_comq_rdma_action; 16055 const u8_t comf_comq_cs16_pkt_len; 16056 const u16_t comf_comq_cs16; 16057 const u32_t unused_3[4]; 16058 u32_t comf_comq_ftq_cmd; 16059 #define COMF_COMQ_FTQ_CMD_POP (1UL<<30) 16060 const u32_t unused_4; 16061 16062 const u32_t comf_comtq_cid; 16063 const u32_t comf_comtq_val; 16064 const u8_t comf_comtq_type; 16065 const u8_t comf_comtq_rsvd_future; 16066 const u16_t unused_5; 16067 const u32_t unused_6[11]; 16068 u32_t comf_comtq_ftq_cmd; 16069 #define COMF_COMTQ_FTQ_CMD_POP (1UL<<30) 16070 const u32_t unused_7; 16071 const u32_t comf_comxq_cid; 16072 const u16_t comf_comxq_flags; 16073 #define COMF_COMXQ_FLAGS_COMPLETE (1<<8) 16074 #define COMF_COMXQ_FLAGS_RETRAN (1<<9) 16075 const u16_t unused_8; 16076 const u32_t comf_comxq_snd_next; 16077 const u8_t comf_comxq_new_flags; 16078 const u8_t unused_9; 16079 const u16_t unused_10; 16080 const u32_t unused_11[10]; 16081 u32_t comf_comxq_ftq_cmd; 16082 #define COMF_COMXQ_FTQ_CMD_POP (1UL<<30) 16083 u32_t unused_12; 16084 16085 u32_t comf_tschq_cid; 16086 u8_t comf_tschq_flags; 16087 #define COMF_TSCHQ_FLAGS_DELIST (1<<0) 16088 #define COMF_TSCHQ_FLAGS_NORMAL (1<<1) 16089 #define COMF_TSCHQ_FLAGS_HIGH (1<<2) 16090 16091 u8_t comf_tschq_rsvd_future; 16092 u16_t unused_13; 16093 u32_t unused_14[12]; 16094 u32_t comf_tschq_ftq_cmd; 16095 #define COMF_TSCHQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) 16096 #define COMF_TSCHQ_FTQ_CMD_ADD_DATA (1UL<<28) 16097 #define COMF_TSCHQ_FTQ_CMD_BUSY (1UL<<31) 16098 u32_t unused_15; 16099 16100 u32_t comf_rv2ptq_cid; 16101 u32_t unused_16[13]; 16102 u32_t comf_rv2ptq_ftq_cmd; 16103 #define COMF_RV2PTQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) 16104 #define COMF_RV2PTQ_FTQ_CMD_ADD_DATA (1UL<<28) 16105 #define COMF_RV2PTQ_FTQ_CMD_BUSY (1UL<<31) 16106 u32_t unused_17; 16107 16108 u32_t comf_csq_cid; 16109 u8_t comf_csq_flags; 16110 #define COMF_CSQ_FLAGS_DELIST (1<<0) 16111 #define COMF_CSQ_FLAGS_NORMAL (1<<1) 16112 #define COMF_CSQ_FLAGS_HIGH (1<<2) 16113 u8_t unused_18; 16114 u16_t unused_19; 16115 u32_t unused_20[12]; 16116 16117 u32_t comf_csq_ftq_cmd; 16118 #define COMF_CSQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) 16119 #define COMF_CSQ_FTQ_CMD_ADD_DATA (1UL<<28) 16120 #define COMF_CSQ_FTQ_CMD_BUSY (1UL<<31) 16121 u32_t unused_21; 16122 16123 u32_t comf_mcpq_bits_status; 16124 u16_t comf_mcpq_pkt_len; 16125 u16_t comf_mcpq_vlan_tag; 16126 u32_t comf_mcpq_mbuf_cluster; 16127 u32_t comf_mcpq_rx_errors; 16128 u16_t comf_mcpq_ext_status; 16129 u16_t unused_23; 16130 u32_t unused_24[9]; 16131 u32_t comf_mcpq_ftq_cmd; 16132 #define COMF_MCPQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) 16133 #define COMF_MCPQ_FTQ_CMD_ADD_DATA (1UL<<28) 16134 #define COMF_MCPQ_FTQ_CMD_BUSY (1UL<<31) 16135 u32_t unused_25[81]; 16136 16137 u32_t comf_dma_data[128]; 16138 u32_t unused_26[128]; 16139 u32_t comf_burst_base0; 16140 #define COMF_BURST_BASE0_BASE_VAL0 (0x3fffUL<<7) 16141 16142 u32_t comf_burst_base1; 16143 #define COMF_BURST_BASE1_BASE_VAL1 (0x3fffUL<<7) 16144 16145 u32_t comf_burst_base2; 16146 #define COMF_BURST_BASE2_BASE_VAL2 (0x3fffUL<<7) 16147 16148 u32_t comf_burst_base3; 16149 #define COMF_BURST_BASE3_BASE_VAL3 (0x3fffUL<<7) 16150 16151 u32_t comf_burst_cmd0; 16152 #define COMF_BURST_CMD0_FTQ_SEL (0x3UL<<0) 16153 #define COMF_BURST_CMD0_FTQ_SEL_0 (0UL<<0) 16154 #define COMF_BURST_CMD0_FTQ_SEL_1 (1UL<<0) 16155 #define COMF_BURST_CMD0_FTQ_SEL_2 (2UL<<0) 16156 #define COMF_BURST_CMD0_FTQ_SEL_3 (3UL<<0) 16157 #define COMF_BURST_CMD0_BUSY (1UL<<2) 16158 #define COMF_BURST_CMD0_OFFSET (0x1ffUL<<3) 16159 #define COMF_BURST_CMD0_BASE_REG_SEL (1UL<<23) 16160 #define COMF_BURST_CMD0_MOD_USAGE_CNT (0x3UL<<24) 16161 #define COMF_BURST_CMD0_MOD_USAGE_CNT_00 (0UL<<24) 16162 #define COMF_BURST_CMD0_MOD_USAGE_CNT_01 (1UL<<24) 16163 #define COMF_BURST_CMD0_MOD_USAGE_CNT_10 (2UL<<24) 16164 #define COMF_BURST_CMD0_MOD_USAGE_CNT_11 (3UL<<24) 16165 #define COMF_BURST_CMD0_PREFETCH_SIZE (0x3UL<<26) 16166 #define COMF_BURST_CMD0_NO_RAM_ACCESS (1UL<<28) 16167 #define COMF_BURST_CMD0_NO_CACHE (1UL<<29) 16168 #define COMF_BURST_CMD0_CROSS_BOUNDARY (1UL<<30) 16169 16170 u32_t comf_burst_cmd1; 16171 #define COMF_BURST_CMD1_FTQ_SEL (0x3UL<<0) 16172 #define COMF_BURST_CMD1_FTQ_SEL_0 (0UL<<0) 16173 #define COMF_BURST_CMD1_FTQ_SEL_1 (1UL<<0) 16174 #define COMF_BURST_CMD1_FTQ_SEL_2 (2UL<<0) 16175 #define COMF_BURST_CMD1_FTQ_SEL_3 (3UL<<0) 16176 #define COMF_BURST_CMD1_BUSY (1UL<<2) 16177 #define COMF_BURST_CMD1_OFFSET (0x1ffUL<<3) 16178 #define COMF_BURST_CMD1_BASE_REG_SEL (1UL<<23) 16179 #define COMF_BURST_CMD1_MOD_USAGE_CNT (0x3UL<<24) 16180 #define COMF_BURST_CMD1_MOD_USAGE_CNT_00 (0UL<<24) 16181 #define COMF_BURST_CMD1_MOD_USAGE_CNT_01 (1UL<<24) 16182 #define COMF_BURST_CMD1_MOD_USAGE_CNT_10 (2UL<<24) 16183 #define COMF_BURST_CMD1_MOD_USAGE_CNT_11 (3UL<<24) 16184 #define COMF_BURST_CMD1_PREFETCH_SIZE (0x3UL<<26) 16185 #define COMF_BURST_CMD1_NO_RAM_ACCESS (1UL<<28) 16186 #define COMF_BURST_CMD1_NO_CACHE (1UL<<29) 16187 #define COMF_BURST_CMD1_CROSS_BOUNDARY (1UL<<30) 16188 16189 u32_t comf_burst_cmd2; 16190 #define COMF_BURST_CMD2_FTQ_SEL (0x3UL<<0) 16191 #define COMF_BURST_CMD2_FTQ_SEL_0 (0UL<<0) 16192 #define COMF_BURST_CMD2_FTQ_SEL_1 (1UL<<0) 16193 #define COMF_BURST_CMD2_FTQ_SEL_2 (2UL<<0) 16194 #define COMF_BURST_CMD2_FTQ_SEL_3 (3UL<<0) 16195 #define COMF_BURST_CMD2_BUSY (1UL<<2) 16196 #define COMF_BURST_CMD2_OFFSET (0x1ffUL<<3) 16197 #define COMF_BURST_CMD2_BASE_REG_SEL (1UL<<23) 16198 #define COMF_BURST_CMD2_MOD_USAGE_CNT (0x3UL<<24) 16199 #define COMF_BURST_CMD2_MOD_USAGE_CNT_00 (0UL<<24) 16200 #define COMF_BURST_CMD2_MOD_USAGE_CNT_01 (1UL<<24) 16201 #define COMF_BURST_CMD2_MOD_USAGE_CNT_10 (2UL<<24) 16202 #define COMF_BURST_CMD2_MOD_USAGE_CNT_11 (3UL<<24) 16203 #define COMF_BURST_CMD2_PREFETCH_SIZE (0x3UL<<26) 16204 #define COMF_BURST_CMD2_NO_RAM_ACCESS (1UL<<28) 16205 #define COMF_BURST_CMD2_NO_CACHE (1UL<<29) 16206 #define COMF_BURST_CMD2_CROSS_BOUNDARY (1UL<<30) 16207 16208 u32_t comf_burst_cmd3; 16209 #define COMF_BURST_CMD3_FTQ_SEL (0x3UL<<0) 16210 #define COMF_BURST_CMD3_FTQ_SEL_0 (0UL<<0) 16211 #define COMF_BURST_CMD3_FTQ_SEL_1 (1UL<<0) 16212 #define COMF_BURST_CMD3_FTQ_SEL_2 (2UL<<0) 16213 #define COMF_BURST_CMD3_FTQ_SEL_3 (3UL<<0) 16214 #define COMF_BURST_CMD3_BUSY (1UL<<2) 16215 #define COMF_BURST_CMD3_OFFSET (0x1ffUL<<3) 16216 #define COMF_BURST_CMD3_BASE_REG_SEL (1UL<<23) 16217 #define COMF_BURST_CMD3_MOD_USAGE_CNT (0x3UL<<24) 16218 #define COMF_BURST_CMD3_MOD_USAGE_CNT_00 (0UL<<24) 16219 #define COMF_BURST_CMD3_MOD_USAGE_CNT_01 (1UL<<24) 16220 #define COMF_BURST_CMD3_MOD_USAGE_CNT_10 (2UL<<24) 16221 #define COMF_BURST_CMD3_MOD_USAGE_CNT_11 (3UL<<24) 16222 #define COMF_BURST_CMD3_PREFETCH_SIZE (0x3UL<<26) 16223 #define COMF_BURST_CMD3_NO_RAM_ACCESS (1UL<<28) 16224 #define COMF_BURST_CMD3_NO_CACHE (1UL<<29) 16225 #define COMF_BURST_CMD3_CROSS_BOUNDARY (1UL<<30) 16226 u32_t unused_27[4]; 16227 16228 u32_t comf_ctx_cmd; 16229 #define COMF_CTX_CMD_NUM_BLOCKS (0x3UL<<0) 16230 #define COMF_CTX_CMD_OFFSET (0x1ffUL<<3) 16231 #define COMF_CTX_CMD_CID_VALUE (0x3fffUL<<12) 16232 #define COMF_CTX_CMD_PREFETCH_SIZE (0x3UL<<26) 16233 #define COMF_CTX_CMD_MOD_USAGE_CNT (0x3UL<<28) 16234 #define COMF_CTX_CMD_MOD_USAGE_CNT_00 (0UL<<28) 16235 #define COMF_CTX_CMD_MOD_USAGE_CNT_01 (1UL<<28) 16236 #define COMF_CTX_CMD_MOD_USAGE_CNT_10 (2UL<<28) 16237 #define COMF_CTX_CMD_MOD_USAGE_CNT_11 (3UL<<28) 16238 u32_t unused_28[51]; 16239 16240 u32_t comf_burst_data0[16]; 16241 u32_t comf_burst_data1[16]; 16242 u32_t comf_burst_data2[16]; 16243 u32_t comf_burst_data3[16]; 16244 u32_t unused_29[64896]; 16245 u32_t comf_ctx_window5[32768]; 16246 u32_t comf_ctx_window6[32768]; 16247 u32_t comf_ctx_window1[32768]; 16248 u32_t comf_ctx_window2[32768]; 16249 u32_t comf_ctx_window3[32768]; 16250 u32_t comf_ctx_window4[32768]; 16251 } com_fio_xi_t; 16252 16253 16254 /* 16255 * cp_fio definition 16256 * offset: 0x80000000 16257 */ 16258 typedef struct cp_fio 16259 { 16260 u32_t cpf_events_bits; 16261 #define CPF_EVENTS_BITS_GPIO0 (1UL<<15) 16262 #define CPF_EVENTS_BITS_GPIO1 (1UL<<16) 16263 #define CPF_EVENTS_BITS_GPIO2 (1UL<<17) 16264 #define CPF_EVENTS_BITS_GPIO3 (1UL<<18) 16265 16266 u32_t cpf_attentions_bits; 16267 #define CPF_ATTENTIONS_BITS_EPB_ERROR (1UL<<30) 16268 16269 u32_t cpf_event_enable; 16270 u32_t cpf_attention_enable; 16271 u32_t cpf_fio_status; 16272 16273 u32_t cpf_mult_result; 16274 u32_t cpf_mult_a; 16275 16276 u32_t cpf_mult_b; 16277 16278 u32_t cpf_ctx_window_cid1; 16279 16280 u32_t cpf_ctx_window_cid2; 16281 #define CPF_CTX_WINDOW_CID2_CTX_WINDOW_CID2_VALUE (0x3fffUL<<7) 16282 16283 u32_t cpf_ctx_window_cid3; 16284 #define CPF_CTX_WINDOW_CID3_CTX_WINDOW_CID3_VALUE (0x3fffUL<<7) 16285 16286 u32_t cpf_ctx_window_cid4; 16287 #define CPF_CTX_WINDOW_CID4_CTX_WINDOW_CID4_VALUE (0x3fffUL<<7) 16288 16289 u32_t cpf_dma_len; 16290 #define CPF_DMA_LEN_BYTE_SWAP (1UL<<24) 16291 16292 u32_t cpf_dma_status; 16293 #define CPF_DMA_STATUS_WRITE_MASTER_ABORT (1UL<<3) 16294 #define CPF_DMA_STATUS_READ_MASTER_ABORT (1UL<<20) 16295 16296 u32_t cpf_dma_addr_h; 16297 u32_t cpf_dma_addr_l; 16298 u32_t cpf_cp_hc_inc_stat[8]; 16299 u32_t unused_0[4]; 16300 u32_t cpf_free_counter_value; 16301 u32_t cpf_timer_retran_value; 16302 u16_t cpf_timer_rxpush_value; 16303 u16_t cpf_timer_delayack_value; 16304 u16_t cpf_timer_keepalive_value; 16305 u16_t cpf_timer_nagle_value; 16306 u16_t cpf_cp_hc_cons_idx; 16307 u16_t cpf_cp_hc_cmd; 16308 #define CPF_CP_HC_CMD_COALESCE_NOW (1<<0) 16309 u32_t unused_1[31]; 16310 16311 u32_t cpf_cpq_cid; 16312 u32_t cpf_cpq_val; 16313 u8_t cpf_cpq_type; 16314 u8_t unused_2; 16315 u16_t unused_3; 16316 u32_t unused_4[11]; 16317 u32_t cpf_cpq_ftq_cmd; 16318 u32_t unused_5; 16319 16320 u32_t cpf_tschq_cid; 16321 u8_t cpf_tschq_flags; 16322 u8_t unused_6; 16323 u16_t unused_7; 16324 u32_t unused_8[12]; 16325 16326 u32_t cpf_tschq_ftq_cmd; 16327 u32_t unused_9; 16328 16329 u32_t cpf_rxpcq_cid; 16330 u32_t cpf_rxpcq_generic1; 16331 u32_t cpf_rxpcq_generic2; 16332 u32_t unused_10[11]; 16333 u32_t cpf_rxpcq_ftq_cmd; 16334 u32_t unused_11[145]; 16335 16336 u32_t cpf_dma_data[128]; 16337 u32_t unused_12[128]; 16338 u32_t cpf_burst_base0; 16339 16340 u32_t cpf_burst_base1; 16341 16342 u32_t cpf_burst_base2; 16343 16344 u32_t cpf_burst_base3; 16345 16346 u32_t cpf_burst_cmd0; 16347 16348 u32_t cpf_burst_cmd1; 16349 16350 u32_t cpf_burst_cmd2; 16351 16352 u32_t cpf_burst_cmd3; 16353 u32_t unused_13[56]; 16354 16355 u32_t cpf_burst_data0[16]; 16356 u32_t cpf_burst_data1[16]; 16357 u32_t cpf_burst_data2[16]; 16358 u32_t cpf_burst_data3[16]; 16359 u32_t unused_14[130432]; 16360 u32_t cpf_ctx_window1[32768]; 16361 u32_t cpf_ctx_window2[32768]; 16362 u32_t cpf_ctx_window3[32768]; 16363 u32_t cpf_ctx_window4[32768]; 16364 } cp_fio_t; 16365 16366 16367 /* 16368 * cp_fio definition 16369 * offset: 0x80000000 16370 */ 16371 typedef struct cp_fio_xi 16372 { 16373 u32_t cpf_events_bits; 16374 #define CPF_EVENTS_BITS_FTQ0_VALID (1UL<<0) 16375 #define CPF_EVENTS_BITS_FTQ1_VALID (1UL<<1) 16376 #define CPF_EVENTS_BITS_FTQ2_VALID (1UL<<2) 16377 #define CPF_EVENTS_BITS_SCANNER_DONE (1UL<<3) 16378 #define CPF_EVENTS_BITS_DMA_WR_DONE (1UL<<4) 16379 #define CPF_EVENTS_BITS_DMA_RD_DONE (1UL<<5) 16380 #define CPF_EVENTS_BITS_CRACKER_DONE (1UL<<6) 16381 #define CPF_EVENTS_BITS_MULTIPLY_DONE (1UL<<7) 16382 #define CPF_EVENTS_BITS_EXP_ROM (1UL<<8) 16383 #define CPF_EVENTS_BITS_VPD (1UL<<9) 16384 #define CPF_EVENTS_BITS_FLASH (1UL<<10) 16385 #define CPF_EVENTS_BITS_SMB0 (1UL<<11) 16386 #define CPF_EVENTS_BITS_RESERVED0 (1UL<<12) 16387 #define CPF_EVENTS_BITS_RESERVED1 (1UL<<13) 16388 #define CPF_EVENTS_BITS_RESERVED2 (1UL<<14) 16389 #define CPF_EVENTS_BITS_GPIO (1UL<<15) 16390 #define CPF_EVENTS_BITS_SW_TMR_1 (1UL<<19) 16391 #define CPF_EVENTS_BITS_SW_TMR_2 (1UL<<20) 16392 #define CPF_EVENTS_BITS_SW_TMR_3 (1UL<<21) 16393 #define CPF_EVENTS_BITS_SW_TMR_4 (1UL<<22) 16394 #define CPF_EVENTS_BITS_LINK_CHANGED (1UL<<23) 16395 #define CPF_EVENTS_BITS_MI_INT (1UL<<25) 16396 #define CPF_EVENTS_BITS_MI_COMPLETE (1UL<<26) 16397 #define CPF_EVENTS_BITS_MAIN_PWR_INT (1UL<<27) 16398 #define CPF_EVENTS_BITS_NOT_ENABLED (1UL<<30) 16399 #define CPF_EVENTS_BITS_ATTENTIONS_VALID (1UL<<31) 16400 16401 u32_t cpf_attentions_bits; 16402 #define CPF_ATTENTIONS_BITS_LINK_STATE (1UL<<0) 16403 #define CPF_ATTENTIONS_BITS_TX_SCHEDULER_ABORT (1UL<<1) 16404 #define CPF_ATTENTIONS_BITS_TX_BD_READ_ABORT (1UL<<2) 16405 #define CPF_ATTENTIONS_BITS_TX_BD_CACHE_ABORT (1UL<<3) 16406 #define CPF_ATTENTIONS_BITS_TX_PROCESSOR_ABORT (1UL<<4) 16407 #define CPF_ATTENTIONS_BITS_TX_DMA_ABORT (1UL<<5) 16408 #define CPF_ATTENTIONS_BITS_TX_PATCHUP_ABORT (1UL<<6) 16409 #define CPF_ATTENTIONS_BITS_TX_ASSEMBLER_ABORT (1UL<<7) 16410 #define CPF_ATTENTIONS_BITS_RX_PARSER_MAC_ABORT (1UL<<8) 16411 #define CPF_ATTENTIONS_BITS_RX_PARSER_CATCHUP_ABORT (1UL<<9) 16412 #define CPF_ATTENTIONS_BITS_RX_MBUF_ABORT (1UL<<10) 16413 #define CPF_ATTENTIONS_BITS_RX_LOOKUP_ABORT (1UL<<11) 16414 #define CPF_ATTENTIONS_BITS_RX_PROCESSOR_ABORT (1UL<<12) 16415 #define CPF_ATTENTIONS_BITS_RX_V2P_ABORT (1UL<<13) 16416 #define CPF_ATTENTIONS_BITS_RX_BD_CACHE_ABORT (1UL<<14) 16417 #define CPF_ATTENTIONS_BITS_RX_DMA_ABORT (1UL<<15) 16418 #define CPF_ATTENTIONS_BITS_COMPLETION_ABORT (1UL<<16) 16419 #define CPF_ATTENTIONS_BITS_HOST_COALESCE_ABORT (1UL<<17) 16420 #define CPF_ATTENTIONS_BITS_MAILBOX_QUEUE_ABORT (1UL<<18) 16421 #define CPF_ATTENTIONS_BITS_CONTEXT_ABORT (1UL<<19) 16422 #define CPF_ATTENTIONS_BITS_CMD_SCHEDULER_ABORT (1UL<<20) 16423 #define CPF_ATTENTIONS_BITS_CMD_PROCESSOR_ABORT (1UL<<21) 16424 #define CPF_ATTENTIONS_BITS_MGMT_PROCESSOR_ABORT (1UL<<22) 16425 #define CPF_ATTENTIONS_BITS_MAC_ABORT (1UL<<23) 16426 #define CPF_ATTENTIONS_BITS_TIMER_ABORT (1UL<<24) 16427 #define CPF_ATTENTIONS_BITS_DMAE_ABORT (1UL<<25) 16428 #define CPF_ATTENTIONS_BITS_FLSH_ABORT (1UL<<26) 16429 #define CPF_ATTENTIONS_BITS_GRC_ABORT (1UL<<27) 16430 #define CPF_ATTENTIONS_BITS_PARITY_ERROR (1UL<<31) 16431 16432 u32_t cpf_event_enable; 16433 u32_t cpf_attention_enable; 16434 u32_t cpf_fio_status; 16435 #define CPF_FIO_STATUS_ENABLED (1UL<<0) 16436 #define CPF_FIO_STATUS_FORCE_ENA (1UL<<1) 16437 16438 u32_t cpf_mult_result; 16439 u32_t cpf_mult_a; 16440 #define CPF_MULT_A_VALUE (0xffffUL<<0) 16441 16442 u32_t cpf_mult_b; 16443 #define CPF_MULT_B_VALUE (0xffffUL<<0) 16444 16445 u32_t cpf_ctx_window_cid1; 16446 #define CPF_CTX_WINDOW_CID1_LOCK_TYPE (0x7UL<<0) 16447 #define CPF_CTX_WINDOW_CID1_LOCK_TYPE_VOID (0UL<<0) 16448 #define CPF_CTX_WINDOW_CID1_LOCK_TYPE_PROTOCOL (1UL<<0) 16449 #define CPF_CTX_WINDOW_CID1_LOCK_TYPE_TX (2UL<<0) 16450 #define CPF_CTX_WINDOW_CID1_LOCK_TYPE_TIMER (4UL<<0) 16451 #define CPF_CTX_WINDOW_CID1_LOCK_TYPE_COMPLETE (7UL<<0) 16452 #define CPF_CTX_WINDOW_CID1_VALUE (0x3fffUL<<7) 16453 #define CPF_CTX_WINDOW_CID1_MOD_USAGE_CNT (0x3UL<<24) 16454 #define CPF_CTX_WINDOW_CID1_MOD_USAGE_CNT_00 (0UL<<24) 16455 #define CPF_CTX_WINDOW_CID1_MOD_USAGE_CNT_01 (1UL<<24) 16456 #define CPF_CTX_WINDOW_CID1_MOD_USAGE_CNT_10 (2UL<<24) 16457 #define CPF_CTX_WINDOW_CID1_MOD_USAGE_CNT_11 (3UL<<24) 16458 #define CPF_CTX_WINDOW_CID1_LOCK_GRANTED (1UL<<26) 16459 #define CPF_CTX_WINDOW_CID1_LOCK_MODE (0x3UL<<27) 16460 #define CPF_CTX_WINDOW_CID1_LOCK_MODE_UNLOCK (0UL<<27) 16461 #define CPF_CTX_WINDOW_CID1_LOCK_MODE_IMMEDIATE (1UL<<27) 16462 #define CPF_CTX_WINDOW_CID1_LOCK_MODE_SURE (2UL<<27) 16463 #define CPF_CTX_WINDOW_CID1_NO_EXT_ACC (1UL<<29) 16464 #define CPF_CTX_WINDOW_CID1_LOCK_STATUS (1UL<<30) 16465 #define CPF_CTX_WINDOW_CID1_LOCK_REQ (1UL<<31) 16466 16467 u32_t cpf_ctx_window_cid2; 16468 #define CPF_CTX_WINDOW_CID2_LOCK_TYPE (0x7UL<<0) 16469 #define CPF_CTX_WINDOW_CID2_LOCK_TYPE_VOID (0UL<<0) 16470 #define CPF_CTX_WINDOW_CID2_LOCK_TYPE_PROTOCOL (1UL<<0) 16471 #define CPF_CTX_WINDOW_CID2_LOCK_TYPE_TX (2UL<<0) 16472 #define CPF_CTX_WINDOW_CID2_LOCK_TYPE_TIMER (4UL<<0) 16473 #define CPF_CTX_WINDOW_CID2_LOCK_TYPE_COMPLETE (7UL<<0) 16474 #define CPF_CTX_WINDOW_CID2_VALUE (0x3fffUL<<7) 16475 #define CPF_CTX_WINDOW_CID2_MOD_USAGE_CNT (0x3UL<<24) 16476 #define CPF_CTX_WINDOW_CID2_MOD_USAGE_CNT_00 (0UL<<24) 16477 #define CPF_CTX_WINDOW_CID2_MOD_USAGE_CNT_01 (1UL<<24) 16478 #define CPF_CTX_WINDOW_CID2_MOD_USAGE_CNT_10 (2UL<<24) 16479 #define CPF_CTX_WINDOW_CID2_MOD_USAGE_CNT_11 (3UL<<24) 16480 #define CPF_CTX_WINDOW_CID2_LOCK_GRANTED (1UL<<26) 16481 #define CPF_CTX_WINDOW_CID2_LOCK_MODE (0x3UL<<27) 16482 #define CPF_CTX_WINDOW_CID2_LOCK_MODE_UNLOCK (0UL<<27) 16483 #define CPF_CTX_WINDOW_CID2_LOCK_MODE_IMMEDIATE (1UL<<27) 16484 #define CPF_CTX_WINDOW_CID2_LOCK_MODE_SURE (2UL<<27) 16485 #define CPF_CTX_WINDOW_CID2_NO_EXT_ACC (1UL<<29) 16486 #define CPF_CTX_WINDOW_CID2_LOCK_STATUS (1UL<<30) 16487 #define CPF_CTX_WINDOW_CID2_LOCK_REQ (1UL<<31) 16488 16489 u32_t cpf_ctx_window_cid3; 16490 #define CPF_CTX_WINDOW_CID3_LOCK_TYPE (0x7UL<<0) 16491 #define CPF_CTX_WINDOW_CID3_LOCK_TYPE_VOID (0UL<<0) 16492 #define CPF_CTX_WINDOW_CID3_LOCK_TYPE_PROTOCOL (1UL<<0) 16493 #define CPF_CTX_WINDOW_CID3_LOCK_TYPE_TX (2UL<<0) 16494 #define CPF_CTX_WINDOW_CID3_LOCK_TYPE_TIMER (4UL<<0) 16495 #define CPF_CTX_WINDOW_CID3_LOCK_TYPE_COMPLETE (7UL<<0) 16496 #define CPF_CTX_WINDOW_CID3_VALUE (0x3fffUL<<7) 16497 #define CPF_CTX_WINDOW_CID3_MOD_USAGE_CNT (0x3UL<<24) 16498 #define CPF_CTX_WINDOW_CID3_MOD_USAGE_CNT_00 (0UL<<24) 16499 #define CPF_CTX_WINDOW_CID3_MOD_USAGE_CNT_01 (1UL<<24) 16500 #define CPF_CTX_WINDOW_CID3_MOD_USAGE_CNT_10 (2UL<<24) 16501 #define CPF_CTX_WINDOW_CID3_MOD_USAGE_CNT_11 (3UL<<24) 16502 #define CPF_CTX_WINDOW_CID3_LOCK_GRANTED (1UL<<26) 16503 #define CPF_CTX_WINDOW_CID3_LOCK_MODE (0x3UL<<27) 16504 #define CPF_CTX_WINDOW_CID3_LOCK_MODE_UNLOCK (0UL<<27) 16505 #define CPF_CTX_WINDOW_CID3_LOCK_MODE_IMMEDIATE (1UL<<27) 16506 #define CPF_CTX_WINDOW_CID3_LOCK_MODE_SURE (2UL<<27) 16507 #define CPF_CTX_WINDOW_CID3_NO_EXT_ACC (1UL<<29) 16508 #define CPF_CTX_WINDOW_CID3_LOCK_STATUS (1UL<<30) 16509 #define CPF_CTX_WINDOW_CID3_LOCK_REQ (1UL<<31) 16510 16511 u32_t cpf_ctx_window_cid4; 16512 #define CPF_CTX_WINDOW_CID4_LOCK_TYPE (0x7UL<<0) 16513 #define CPF_CTX_WINDOW_CID4_LOCK_TYPE_VOID (0UL<<0) 16514 #define CPF_CTX_WINDOW_CID4_LOCK_TYPE_PROTOCOL (1UL<<0) 16515 #define CPF_CTX_WINDOW_CID4_LOCK_TYPE_TX (2UL<<0) 16516 #define CPF_CTX_WINDOW_CID4_LOCK_TYPE_TIMER (4UL<<0) 16517 #define CPF_CTX_WINDOW_CID4_LOCK_TYPE_COMPLETE (7UL<<0) 16518 #define CPF_CTX_WINDOW_CID4_VALUE (0x3fffUL<<7) 16519 #define CPF_CTX_WINDOW_CID4_MOD_USAGE_CNT (0x3UL<<24) 16520 #define CPF_CTX_WINDOW_CID4_MOD_USAGE_CNT_00 (0UL<<24) 16521 #define CPF_CTX_WINDOW_CID4_MOD_USAGE_CNT_01 (1UL<<24) 16522 #define CPF_CTX_WINDOW_CID4_MOD_USAGE_CNT_10 (2UL<<24) 16523 #define CPF_CTX_WINDOW_CID4_MOD_USAGE_CNT_11 (3UL<<24) 16524 #define CPF_CTX_WINDOW_CID4_LOCK_GRANTED (1UL<<26) 16525 #define CPF_CTX_WINDOW_CID4_LOCK_MODE (0x3UL<<27) 16526 #define CPF_CTX_WINDOW_CID4_LOCK_MODE_UNLOCK (0UL<<27) 16527 #define CPF_CTX_WINDOW_CID4_LOCK_MODE_IMMEDIATE (1UL<<27) 16528 #define CPF_CTX_WINDOW_CID4_LOCK_MODE_SURE (2UL<<27) 16529 #define CPF_CTX_WINDOW_CID4_NO_EXT_ACC (1UL<<29) 16530 #define CPF_CTX_WINDOW_CID4_LOCK_STATUS (1UL<<30) 16531 #define CPF_CTX_WINDOW_CID4_LOCK_REQ (1UL<<31) 16532 16533 u32_t cpf_dma_len; 16534 #define CPF_DMA_LEN_LEN (0x3ffUL<<0) 16535 #define CPF_DMA_LEN_WRITE_START (1UL<<16) 16536 #define CPF_DMA_LEN_WRITE_STOP (1UL<<17) 16537 #define CPF_DMA_LEN_WRITE_EVENT_CLEAR (1UL<<18) 16538 #define CPF_DMA_LEN_READ_START (1UL<<20) 16539 #define CPF_DMA_LEN_READ_STOP (1UL<<21) 16540 #define CPF_DMA_LEN_READ_EVENT_CLEAR (1UL<<22) 16541 #define CPF_DMA_LEN_TYPE (0x3UL<<23) 16542 #define CPF_DMA_LEN_TYPE_CONFIG (0UL<<23) 16543 #define CPF_DMA_LEN_TYPE_DATA (1UL<<23) 16544 #define CPF_DMA_LEN_TYPE_CONTROL (2UL<<23) 16545 #define CPF_DMA_LEN_NO_SNOOP (1UL<<25) 16546 #define CPF_DMA_LEN_PRIORITY (1UL<<26) 16547 #define CPF_DMA_LEN_RELAXED_ORDERING (1UL<<27) 16548 #define CPF_DMA_LEN_WRITE_RESET (1UL<<30) 16549 #define CPF_DMA_LEN_READ_RESET (1UL<<31) 16550 16551 u32_t cpf_dma_status; 16552 #define CPF_DMA_STATUS_WRITE_CHAN_REQ (1UL<<0) 16553 #define CPF_DMA_STATUS_WRITE_ACTIVE (1UL<<1) 16554 #define CPF_DMA_STATUS_WRITE_DONE (1UL<<2) 16555 #define CPF_DMA_STATUS_READ_CHAN_REQ (1UL<<16) 16556 #define CPF_DMA_STATUS_READ_ACTIVE (1UL<<17) 16557 #define CPF_DMA_STATUS_READ_DONE (1UL<<19) 16558 #define CPF_DMA_STATUS_READ_CS16_ERROR (1UL<<20) 16559 16560 u32_t cpf_dma_addr_h; 16561 u32_t cpf_dma_addr_l; 16562 u32_t cpf_cp_hc_inc_stat[8]; 16563 u32_t unused_0[4]; 16564 u32_t cpf_free_counter_value; 16565 u32_t cpf_timer_retran_value; 16566 u16_t cpf_timer_rxpush_value; 16567 u16_t cpf_timer_delayack_value; 16568 u16_t cpf_timer_keepalive_value; 16569 u16_t cpf_timer_nagle_value; 16570 u32_t cpf_cp_cmd_cons_idx; 16571 #define CPF_CP_CMD_CONS_IDX_INDEX_VAL (0xffffUL<<0) 16572 #define CPF_CP_CMD_CONS_IDX_INDEX_NUM (0xfUL<<20) 16573 #define CPF_CP_CMD_CONS_IDX_COALESCE_NOW (1UL<<30) 16574 #define CPF_CP_CMD_CONS_IDX_REQ_N (1UL<<31) 16575 u32_t unused_1[3]; 16576 16577 u32_t cpf_ctx_window_cid5; 16578 #define CPF_CTX_WINDOW_CID5_LOCK_TYPE (0x7UL<<0) 16579 #define CPF_CTX_WINDOW_CID5_LOCK_TYPE_VOID (0UL<<0) 16580 #define CPF_CTX_WINDOW_CID5_LOCK_TYPE_PROTOCOL (1UL<<0) 16581 #define CPF_CTX_WINDOW_CID5_LOCK_TYPE_TX (2UL<<0) 16582 #define CPF_CTX_WINDOW_CID5_LOCK_TYPE_TIMER (4UL<<0) 16583 #define CPF_CTX_WINDOW_CID5_LOCK_TYPE_COMPLETE (7UL<<0) 16584 #define CPF_CTX_WINDOW_CID5_VALUE (0x3fffUL<<7) 16585 #define CPF_CTX_WINDOW_CID5_MOD_USAGE_CNT (0x3UL<<24) 16586 #define CPF_CTX_WINDOW_CID5_MOD_USAGE_CNT_00 (0UL<<24) 16587 #define CPF_CTX_WINDOW_CID5_MOD_USAGE_CNT_01 (1UL<<24) 16588 #define CPF_CTX_WINDOW_CID5_MOD_USAGE_CNT_10 (2UL<<24) 16589 #define CPF_CTX_WINDOW_CID5_MOD_USAGE_CNT_11 (3UL<<24) 16590 #define CPF_CTX_WINDOW_CID5_LOCK_GRANTED (1UL<<26) 16591 #define CPF_CTX_WINDOW_CID5_LOCK_MODE (0x3UL<<27) 16592 #define CPF_CTX_WINDOW_CID5_LOCK_MODE_UNLOCK (0UL<<27) 16593 #define CPF_CTX_WINDOW_CID5_LOCK_MODE_IMMEDIATE (1UL<<27) 16594 #define CPF_CTX_WINDOW_CID5_LOCK_MODE_SURE (2UL<<27) 16595 #define CPF_CTX_WINDOW_CID5_NO_EXT_ACC (1UL<<29) 16596 #define CPF_CTX_WINDOW_CID5_LOCK_STATUS (1UL<<30) 16597 #define CPF_CTX_WINDOW_CID5_LOCK_REQ (1UL<<31) 16598 16599 u32_t cpf_ctx_window_cid6; 16600 #define CPF_CTX_WINDOW_CID6_LOCK_TYPE (0x7UL<<0) 16601 #define CPF_CTX_WINDOW_CID6_LOCK_TYPE_VOID (0UL<<0) 16602 #define CPF_CTX_WINDOW_CID6_LOCK_TYPE_PROTOCOL (1UL<<0) 16603 #define CPF_CTX_WINDOW_CID6_LOCK_TYPE_TX (2UL<<0) 16604 #define CPF_CTX_WINDOW_CID6_LOCK_TYPE_TIMER (4UL<<0) 16605 #define CPF_CTX_WINDOW_CID6_LOCK_TYPE_COMPLETE (7UL<<0) 16606 #define CPF_CTX_WINDOW_CID6_VALUE (0x3fffUL<<7) 16607 #define CPF_CTX_WINDOW_CID6_MOD_USAGE_CNT (0x3UL<<24) 16608 #define CPF_CTX_WINDOW_CID6_MOD_USAGE_CNT_00 (0UL<<24) 16609 #define CPF_CTX_WINDOW_CID6_MOD_USAGE_CNT_01 (1UL<<24) 16610 #define CPF_CTX_WINDOW_CID6_MOD_USAGE_CNT_10 (2UL<<24) 16611 #define CPF_CTX_WINDOW_CID6_MOD_USAGE_CNT_11 (3UL<<24) 16612 #define CPF_CTX_WINDOW_CID6_LOCK_GRANTED (1UL<<26) 16613 #define CPF_CTX_WINDOW_CID6_LOCK_MODE (0x3UL<<27) 16614 #define CPF_CTX_WINDOW_CID6_LOCK_MODE_UNLOCK (0UL<<27) 16615 #define CPF_CTX_WINDOW_CID6_LOCK_MODE_IMMEDIATE (1UL<<27) 16616 #define CPF_CTX_WINDOW_CID6_LOCK_MODE_SURE (2UL<<27) 16617 #define CPF_CTX_WINDOW_CID6_NO_EXT_ACC (1UL<<29) 16618 #define CPF_CTX_WINDOW_CID6_LOCK_STATUS (1UL<<30) 16619 #define CPF_CTX_WINDOW_CID6_LOCK_REQ (1UL<<31) 16620 u32_t unused_2[26]; 16621 16622 u32_t cpf_cpq_cid; 16623 u32_t unused_3[13]; 16624 u32_t cpf_cpq_ftq_cmd; 16625 #define CPF_CPQ_FTQ_CMD_POP (1UL<<30) 16626 u32_t unused_4; 16627 16628 u32_t cpf_tschq_cid; 16629 u8_t cpf_tschq_flags; 16630 #define CPF_TSCHQ_FLAGS_DELIST (1<<0) 16631 #define CPF_TSCHQ_FLAGS_NORMAL (1<<1) 16632 #define CPF_TSCHQ_FLAGS_HIGH (1<<2) 16633 16634 u8_t cpf_tschq_rsvd_future; 16635 u16_t unused_5; 16636 u32_t unused_6[12]; 16637 u32_t cpf_tschq_ftq_cmd; 16638 #define CPF_TSCHQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) 16639 #define CPF_TSCHQ_FTQ_CMD_ADD_DATA (1UL<<28) 16640 #define CPF_TSCHQ_FTQ_CMD_BUSY (1UL<<31) 16641 u32_t unused_7; 16642 16643 u32_t cpf_rxpcq_cid; 16644 u32_t cpf_rxpcq_generic1; 16645 u32_t cpf_rxpcq_generic2; 16646 u32_t unused_8[11]; 16647 u32_t cpf_rxpcq_ftq_cmd; 16648 #define CPF_RXPCQ_FTQ_CMD_ADD_INTERVEN (1UL<<27) 16649 #define CPF_RXPCQ_FTQ_CMD_ADD_DATA (1UL<<28) 16650 #define CPF_RXPCQ_FTQ_CMD_BUSY (1UL<<31) 16651 u32_t unused_9[145]; 16652 16653 u32_t cpf_dma_data[128]; 16654 u32_t unused_10[128]; 16655 u32_t cpf_burst_base0; 16656 #define CPF_BURST_BASE0_BASE_VAL0 (0x3fffUL<<7) 16657 16658 u32_t cpf_burst_base1; 16659 #define CPF_BURST_BASE1_BASE_VAL1 (0x3fffUL<<7) 16660 16661 u32_t cpf_burst_base2; 16662 #define CPF_BURST_BASE2_BASE_VAL2 (0x3fffUL<<7) 16663 16664 u32_t cpf_burst_base3; 16665 #define CPF_BURST_BASE3_BASE_VAL3 (0x3fffUL<<7) 16666 16667 u32_t cpf_burst_cmd0; 16668 #define CPF_BURST_CMD0_FTQ_SEL (0x3UL<<0) 16669 #define CPF_BURST_CMD0_FTQ_SEL_0 (0UL<<0) 16670 #define CPF_BURST_CMD0_FTQ_SEL_1 (1UL<<0) 16671 #define CPF_BURST_CMD0_FTQ_SEL_2 (2UL<<0) 16672 #define CPF_BURST_CMD0_FTQ_SEL_3 (3UL<<0) 16673 #define CPF_BURST_CMD0_BUSY (1UL<<2) 16674 #define CPF_BURST_CMD0_OFFSET (0x1ffUL<<3) 16675 #define CPF_BURST_CMD0_BASE_REG_SEL (1UL<<23) 16676 #define CPF_BURST_CMD0_MOD_USAGE_CNT (0x3UL<<24) 16677 #define CPF_BURST_CMD0_MOD_USAGE_CNT_00 (0UL<<24) 16678 #define CPF_BURST_CMD0_MOD_USAGE_CNT_01 (1UL<<24) 16679 #define CPF_BURST_CMD0_MOD_USAGE_CNT_10 (2UL<<24) 16680 #define CPF_BURST_CMD0_MOD_USAGE_CNT_11 (3UL<<24) 16681 #define CPF_BURST_CMD0_PREFETCH_SIZE (0x3UL<<26) 16682 #define CPF_BURST_CMD0_NO_RAM_ACCESS (1UL<<28) 16683 #define CPF_BURST_CMD0_NO_CACHE (1UL<<29) 16684 #define CPF_BURST_CMD0_CROSS_BOUNDARY (1UL<<30) 16685 16686 u32_t cpf_burst_cmd1; 16687 #define CPF_BURST_CMD1_FTQ_SEL (0x3UL<<0) 16688 #define CPF_BURST_CMD1_FTQ_SEL_0 (0UL<<0) 16689 #define CPF_BURST_CMD1_FTQ_SEL_1 (1UL<<0) 16690 #define CPF_BURST_CMD1_FTQ_SEL_2 (2UL<<0) 16691 #define CPF_BURST_CMD1_FTQ_SEL_3 (3UL<<0) 16692 #define CPF_BURST_CMD1_BUSY (1UL<<2) 16693 #define CPF_BURST_CMD1_OFFSET (0x1ffUL<<3) 16694 #define CPF_BURST_CMD1_BASE_REG_SEL (1UL<<23) 16695 #define CPF_BURST_CMD1_MOD_USAGE_CNT (0x3UL<<24) 16696 #define CPF_BURST_CMD1_MOD_USAGE_CNT_00 (0UL<<24) 16697 #define CPF_BURST_CMD1_MOD_USAGE_CNT_01 (1UL<<24) 16698 #define CPF_BURST_CMD1_MOD_USAGE_CNT_10 (2UL<<24) 16699 #define CPF_BURST_CMD1_MOD_USAGE_CNT_11 (3UL<<24) 16700 #define CPF_BURST_CMD1_PREFETCH_SIZE (0x3UL<<26) 16701 #define CPF_BURST_CMD1_NO_RAM_ACCESS (1UL<<28) 16702 #define CPF_BURST_CMD1_NO_CACHE (1UL<<29) 16703 #define CPF_BURST_CMD1_CROSS_BOUNDARY (1UL<<30) 16704 16705 u32_t cpf_burst_cmd2; 16706 #define CPF_BURST_CMD2_FTQ_SEL (0x3UL<<0) 16707 #define CPF_BURST_CMD2_FTQ_SEL_0 (0UL<<0) 16708 #define CPF_BURST_CMD2_FTQ_SEL_1 (1UL<<0) 16709 #define CPF_BURST_CMD2_FTQ_SEL_2 (2UL<<0) 16710 #define CPF_BURST_CMD2_FTQ_SEL_3 (3UL<<0) 16711 #define CPF_BURST_CMD2_BUSY (1UL<<2) 16712 #define CPF_BURST_CMD2_OFFSET (0x1ffUL<<3) 16713 #define CPF_BURST_CMD2_BASE_REG_SEL (1UL<<23) 16714 #define CPF_BURST_CMD2_MOD_USAGE_CNT (0x3UL<<24) 16715 #define CPF_BURST_CMD2_MOD_USAGE_CNT_00 (0UL<<24) 16716 #define CPF_BURST_CMD2_MOD_USAGE_CNT_01 (1UL<<24) 16717 #define CPF_BURST_CMD2_MOD_USAGE_CNT_10 (2UL<<24) 16718 #define CPF_BURST_CMD2_MOD_USAGE_CNT_11 (3UL<<24) 16719 #define CPF_BURST_CMD2_PREFETCH_SIZE (0x3UL<<26) 16720 #define CPF_BURST_CMD2_NO_RAM_ACCESS (1UL<<28) 16721 #define CPF_BURST_CMD2_NO_CACHE (1UL<<29) 16722 #define CPF_BURST_CMD2_CROSS_BOUNDARY (1UL<<30) 16723 16724 u32_t cpf_burst_cmd3; 16725 #define CPF_BURST_CMD3_FTQ_SEL (0x3UL<<0) 16726 #define CPF_BURST_CMD3_FTQ_SEL_0 (0UL<<0) 16727 #define CPF_BURST_CMD3_FTQ_SEL_1 (1UL<<0) 16728 #define CPF_BURST_CMD3_FTQ_SEL_2 (2UL<<0) 16729 #define CPF_BURST_CMD3_FTQ_SEL_3 (3UL<<0) 16730 #define CPF_BURST_CMD3_BUSY (1UL<<2) 16731 #define CPF_BURST_CMD3_OFFSET (0x1ffUL<<3) 16732 #define CPF_BURST_CMD3_BASE_REG_SEL (1UL<<23) 16733 #define CPF_BURST_CMD3_MOD_USAGE_CNT (0x3UL<<24) 16734 #define CPF_BURST_CMD3_MOD_USAGE_CNT_00 (0UL<<24) 16735 #define CPF_BURST_CMD3_MOD_USAGE_CNT_01 (1UL<<24) 16736 #define CPF_BURST_CMD3_MOD_USAGE_CNT_10 (2UL<<24) 16737 #define CPF_BURST_CMD3_MOD_USAGE_CNT_11 (3UL<<24) 16738 #define CPF_BURST_CMD3_PREFETCH_SIZE (0x3UL<<26) 16739 #define CPF_BURST_CMD3_NO_RAM_ACCESS (1UL<<28) 16740 #define CPF_BURST_CMD3_NO_CACHE (1UL<<29) 16741 #define CPF_BURST_CMD3_CROSS_BOUNDARY (1UL<<30) 16742 16743 u32_t cpf_burst_cmd4; 16744 #define CPF_BURST_CMD4_FTQ_SEL (0x3UL<<0) 16745 #define CPF_BURST_CMD4_FTQ_SEL_0 (0UL<<0) 16746 #define CPF_BURST_CMD4_FTQ_SEL_1 (1UL<<0) 16747 #define CPF_BURST_CMD4_FTQ_SEL_2 (2UL<<0) 16748 #define CPF_BURST_CMD4_FTQ_SEL_3 (3UL<<0) 16749 #define CPF_BURST_CMD4_BUSY (1UL<<2) 16750 #define CPF_BURST_CMD4_OFFSET (0x1ffUL<<3) 16751 #define CPF_BURST_CMD4_BASE_REG_SEL (1UL<<23) 16752 #define CPF_BURST_CMD4_MOD_USAGE_CNT (0x3UL<<24) 16753 #define CPF_BURST_CMD4_MOD_USAGE_CNT_00 (0UL<<24) 16754 #define CPF_BURST_CMD4_MOD_USAGE_CNT_01 (1UL<<24) 16755 #define CPF_BURST_CMD4_MOD_USAGE_CNT_10 (2UL<<24) 16756 #define CPF_BURST_CMD4_MOD_USAGE_CNT_11 (3UL<<24) 16757 #define CPF_BURST_CMD4_PREFETCH_SIZE (0x3UL<<26) 16758 #define CPF_BURST_CMD4_NO_RAM_ACCESS (1UL<<28) 16759 #define CPF_BURST_CMD4_NO_CACHE (1UL<<29) 16760 #define CPF_BURST_CMD4_CROSS_BOUNDARY (1UL<<30) 16761 16762 u32_t cpf_burst_cmd5; 16763 #define CPF_BURST_CMD5_FTQ_SEL (0x3UL<<0) 16764 #define CPF_BURST_CMD5_FTQ_SEL_0 (0UL<<0) 16765 #define CPF_BURST_CMD5_FTQ_SEL_1 (1UL<<0) 16766 #define CPF_BURST_CMD5_FTQ_SEL_2 (2UL<<0) 16767 #define CPF_BURST_CMD5_FTQ_SEL_3 (3UL<<0) 16768 #define CPF_BURST_CMD5_BUSY (1UL<<2) 16769 #define CPF_BURST_CMD5_OFFSET (0x1ffUL<<3) 16770 #define CPF_BURST_CMD5_BASE_REG_SEL (1UL<<23) 16771 #define CPF_BURST_CMD5_MOD_USAGE_CNT (0x3UL<<24) 16772 #define CPF_BURST_CMD5_MOD_USAGE_CNT_00 (0UL<<24) 16773 #define CPF_BURST_CMD5_MOD_USAGE_CNT_01 (1UL<<24) 16774 #define CPF_BURST_CMD5_MOD_USAGE_CNT_10 (2UL<<24) 16775 #define CPF_BURST_CMD5_MOD_USAGE_CNT_11 (3UL<<24) 16776 #define CPF_BURST_CMD5_PREFETCH_SIZE (0x3UL<<26) 16777 #define CPF_BURST_CMD5_NO_RAM_ACCESS (1UL<<28) 16778 #define CPF_BURST_CMD5_NO_CACHE (1UL<<29) 16779 #define CPF_BURST_CMD5_CROSS_BOUNDARY (1UL<<30) 16780 16781 u32_t cpf_burst_cmd6; 16782 #define CPF_BURST_CMD6_FTQ_SEL (0x3UL<<0) 16783 #define CPF_BURST_CMD6_FTQ_SEL_0 (0UL<<0) 16784 #define CPF_BURST_CMD6_FTQ_SEL_1 (1UL<<0) 16785 #define CPF_BURST_CMD6_FTQ_SEL_2 (2UL<<0) 16786 #define CPF_BURST_CMD6_FTQ_SEL_3 (3UL<<0) 16787 #define CPF_BURST_CMD6_BUSY (1UL<<2) 16788 #define CPF_BURST_CMD6_OFFSET (0x1ffUL<<3) 16789 #define CPF_BURST_CMD6_BASE_REG_SEL (1UL<<23) 16790 #define CPF_BURST_CMD6_MOD_USAGE_CNT (0x3UL<<24) 16791 #define CPF_BURST_CMD6_MOD_USAGE_CNT_00 (0UL<<24) 16792 #define CPF_BURST_CMD6_MOD_USAGE_CNT_01 (1UL<<24) 16793 #define CPF_BURST_CMD6_MOD_USAGE_CNT_10 (2UL<<24) 16794 #define CPF_BURST_CMD6_MOD_USAGE_CNT_11 (3UL<<24) 16795 #define CPF_BURST_CMD6_PREFETCH_SIZE (0x3UL<<26) 16796 #define CPF_BURST_CMD6_NO_RAM_ACCESS (1UL<<28) 16797 #define CPF_BURST_CMD6_NO_CACHE (1UL<<29) 16798 #define CPF_BURST_CMD6_CROSS_BOUNDARY (1UL<<30) 16799 16800 u32_t cpf_burst_cmd7; 16801 #define CPF_BURST_CMD7_FTQ_SEL (0x3UL<<0) 16802 #define CPF_BURST_CMD7_FTQ_SEL_0 (0UL<<0) 16803 #define CPF_BURST_CMD7_FTQ_SEL_1 (1UL<<0) 16804 #define CPF_BURST_CMD7_FTQ_SEL_2 (2UL<<0) 16805 #define CPF_BURST_CMD7_FTQ_SEL_3 (3UL<<0) 16806 #define CPF_BURST_CMD7_BUSY (1UL<<2) 16807 #define CPF_BURST_CMD7_OFFSET (0x1ffUL<<3) 16808 #define CPF_BURST_CMD7_BASE_REG_SEL (1UL<<23) 16809 #define CPF_BURST_CMD7_MOD_USAGE_CNT (0x3UL<<24) 16810 #define CPF_BURST_CMD7_MOD_USAGE_CNT_00 (0UL<<24) 16811 #define CPF_BURST_CMD7_MOD_USAGE_CNT_01 (1UL<<24) 16812 #define CPF_BURST_CMD7_MOD_USAGE_CNT_10 (2UL<<24) 16813 #define CPF_BURST_CMD7_MOD_USAGE_CNT_11 (3UL<<24) 16814 #define CPF_BURST_CMD7_PREFETCH_SIZE (0x3UL<<26) 16815 #define CPF_BURST_CMD7_NO_RAM_ACCESS (1UL<<28) 16816 #define CPF_BURST_CMD7_NO_CACHE (1UL<<29) 16817 #define CPF_BURST_CMD7_CROSS_BOUNDARY (1UL<<30) 16818 16819 u32_t cpf_ctx_cmd; 16820 #define CPF_CTX_CMD_NUM_BLOCKS (0x3UL<<0) 16821 #define CPF_CTX_CMD_OFFSET (0x1ffUL<<3) 16822 #define CPF_CTX_CMD_CID_VALUE (0x3fffUL<<12) 16823 #define CPF_CTX_CMD_PREFETCH_SIZE (0x3UL<<26) 16824 #define CPF_CTX_CMD_MOD_USAGE_CNT (0x3UL<<28) 16825 #define CPF_CTX_CMD_MOD_USAGE_CNT_00 (0UL<<28) 16826 #define CPF_CTX_CMD_MOD_USAGE_CNT_01 (1UL<<28) 16827 #define CPF_CTX_CMD_MOD_USAGE_CNT_10 (2UL<<28) 16828 #define CPF_CTX_CMD_MOD_USAGE_CNT_11 (3UL<<28) 16829 u32_t unused_11[51]; 16830 16831 u32_t cpf_burst_data0[16]; 16832 u32_t cpf_burst_data1[16]; 16833 u32_t cpf_burst_data2[16]; 16834 u32_t cpf_burst_data3[16]; 16835 u32_t cpf_burst_data4[16]; 16836 u32_t cpf_burst_data5[16]; 16837 u32_t cpf_burst_data6[16]; 16838 u32_t cpf_burst_data7[16]; 16839 u32_t unused_12[64832]; 16840 u32_t cpf_ctx_window5[32768]; 16841 u32_t cpf_ctx_window6[32768]; 16842 u32_t cpf_ctx_window1[32768]; 16843 u32_t cpf_ctx_window2[32768]; 16844 u32_t cpf_ctx_window3[32768]; 16845 u32_t cpf_ctx_window4[32768]; 16846 } cp_fio_xi_t; 16847 16848 16849 /* 16850 * mcp_fio definition 16851 * offset: 0x80000000 16852 */ 16853 typedef struct mcp_fio 16854 { 16855 u32_t mcpf_events_bits; 16856 #define MCPF_EVENTS_BITS_FTQ2_VALID (1UL<<2) 16857 #define MCPF_EVENTS_BITS_SCANNER_DONE (1UL<<3) 16858 #define MCPF_EVENTS_BITS_DMA_WR_DONE (1UL<<4) 16859 #define MCPF_EVENTS_BITS_DMA_RD_DONE (1UL<<5) 16860 #define MCPF_EVENTS_BITS_CRACKER_DONE (1UL<<6) 16861 #define MCPF_EVENTS_BITS_MULTIPLY_DONE (1UL<<7) 16862 #define MCPF_EVENTS_BITS_GPIO0 (1UL<<15) 16863 #define MCPF_EVENTS_BITS_GPIO1 (1UL<<16) 16864 #define MCPF_EVENTS_BITS_GPIO2 (1UL<<17) 16865 #define MCPF_EVENTS_BITS_GPIO3 (1UL<<18) 16866 16867 u32_t mcpf_attentions_bits; 16868 #define MCPF_ATTENTIONS_BITS_EPB_ERROR (1UL<<30) 16869 16870 u32_t mcpf_event_enable; 16871 u32_t mcpf_attention_enable; 16872 u32_t mcpf_fio_status; 16873 u32_t unused_0[11]; 16874 16875 u32_t mcpf_mcp_hc_inc_stat[8]; 16876 u32_t unused_1[4]; 16877 u32_t mcpf_free_counter_value; 16878 u32_t unused_2[3]; 16879 u32_t mcpf_ump_cmd; 16880 #define MCPF_UMP_CMD_RX_FIFO_ENABLED (1UL<<0) 16881 #define MCPF_UMP_CMD_TX_FIFO_ENABLED (1UL<<1) 16882 #define MCPF_UMP_CMD_FLOWMODE (1UL<<3) 16883 #define MCPF_UMP_CMD_HDFLOWSEL (1UL<<4) 16884 #define MCPF_UMP_CMD_RX_MAC_DISABLE (1UL<<5) 16885 #define MCPF_UMP_CMD_TX_MAC_DISABLE (1UL<<6) 16886 #define MCPF_UMP_CMD_TX_DROP (1UL<<7) 16887 #define MCPF_UMP_CMD_TX_DRIVE (1UL<<8) 16888 #define MCPF_UMP_CMD_TX_RESET (1UL<<14) 16889 16890 u32_t mcpf_ump_status; 16891 #define MCPF_UMP_STATUS_TX_IDLE (1UL<<0) 16892 #define MCPF_UMP_STATUS_FDX (1UL<<1) 16893 #define MCPF_UMP_STATUS_RX_FRM_DROP (1UL<<3) 16894 #define MCPF_UMP_STATUS_SRC_ADDR_CHG (1UL<<5) 16895 #define MCPF_UMP_STATUS_XOFF_TRIP (0xffUL<<16) 16896 #define MCPF_UMP_STATUS_XON_TRIP (0xffUL<<24) 16897 u32_t unused_3[2]; 16898 16899 u32_t mcpf_ump_frm_rd_status; 16900 #define MCPF_UMP_FRM_RD_STATUS_NEW_FRM (1UL<<0) 16901 #define MCPF_UMP_FRM_RD_STATUS_FRM_IN_PRO (1UL<<1) 16902 #define MCPF_UMP_FRM_RD_STATUS_FIFO_EMPTY (1UL<<2) 16903 #define MCPF_UMP_FRM_RD_STATUS_BCNT (0x7ffUL<<3) 16904 #define MCPF_UMP_FRM_RD_STATUS_RX_FIFO_STATE (0x7UL<<29) 16905 #define MCPF_UMP_FRM_RD_STATUS_RX_FIFO_STATE_IDLE (0UL<<29) 16906 #define MCPF_UMP_FRM_RD_STATUS_RX_FIFO_STATE_READY (1UL<<29) 16907 #define MCPF_UMP_FRM_RD_STATUS_RX_FIFO_STATE_BUSY (2UL<<29) 16908 #define MCPF_UMP_FRM_RD_STATUS_RX_FIFO_STATE_EXTRA_RD (3UL<<29) 16909 #define MCPF_UMP_FRM_RD_STATUS_RX_FIFO_STATE_LATCH_IP_HDR (4UL<<29) 16910 16911 u32_t mcpf_ump_frm_rd_data; 16912 u32_t mcpf_ump_frm_wr_ctl; 16913 #define MCPF_UMP_FRM_WR_CTL_NEW_FRM (1UL<<0) 16914 #define MCPF_UMP_FRM_WR_CTL_FIFO_RDY (1UL<<1) 16915 #define MCPF_UMP_FRM_WR_CTL_BCNT_RDY (1UL<<2) 16916 #define MCPF_UMP_FRM_WR_CTL_BCNT (0x7ffUL<<3) 16917 #define MCPF_UMP_FRM_WR_CTL_TX_FIFO_STATE (0x3UL<<30) 16918 #define MCPF_UMP_FRM_WR_CTL_TX_FIFO_STATE_IDLE (0UL<<30) 16919 #define MCPF_UMP_FRM_WR_CTL_TX_FIFO_STATE_WAIT (1UL<<30) 16920 #define MCPF_UMP_FRM_WR_CTL_TX_FIFO_STATE_BUSY (2UL<<30) 16921 #define MCPF_UMP_FRM_WR_CTL_TX_FIFO_STATE_EXTRA_WR (3UL<<30) 16922 16923 u32_t mcpf_ump_frm_wr_data; 16924 u32_t mcpf_ump_frm_pre_fetch; 16925 u32_t mcpf_ump_fifo_remain; 16926 #define MCPF_UMP_FIFO_REMAIN_TX_FIFO_REMAIN (0x1ffUL<<0) 16927 #define MCPF_UMP_FIFO_REMAIN_RX_FIFO_REMAIN (0x1ffUL<<16) 16928 16929 u32_t mcpf_ump_rxfifo_ptrs; 16930 #define MCPF_UMP_RXFIFO_PTRS_WA_CPU (0x1ffUL<<0) 16931 #define MCPF_UMP_RXFIFO_PTRS_WA_TOGGLE_CPU (1UL<<9) 16932 #define MCPF_UMP_RXFIFO_PTRS_RA (0x1ffUL<<16) 16933 #define MCPF_UMP_RXFIFO_PTRS_RA_TOGGLE (1UL<<25) 16934 16935 u32_t mcpf_ump_txfifo_ptrs; 16936 #define MCPF_UMP_TXFIFO_PTRS_WA (0x1ffUL<<0) 16937 #define MCPF_UMP_TXFIFO_PTRS_WA_TOGGLE (1UL<<9) 16938 #define MCPF_UMP_TXFIFO_PTRS_RA_CPU (0x1ffUL<<16) 16939 #define MCPF_UMP_TXFIFO_PTRS_RA_TOGGLE_CPU (1UL<<25) 16940 16941 u32_t mcpf_ump_ump_debug; 16942 #define MCPF_UMP_UMP_DEBUG_RXBUF_ALM_FULL_CORE (1UL<<0) 16943 #define MCPF_UMP_UMP_DEBUG_FIFO_FULL_ERR (1UL<<1) 16944 #define MCPF_UMP_UMP_DEBUG_NEW_PACKET (1UL<<2) 16945 #define MCPF_UMP_UMP_DEBUG_LOCAL_PKT_ABT (1UL<<3) 16946 #define MCPF_UMP_UMP_DEBUG_SETABT (1UL<<4) 16947 u32_t unused_4[19]; 16948 16949 u32_t mcpf_mcpq_bits_status; 16950 u16_t mcpf_mcpq_pkt_len; 16951 u16_t unused_5; 16952 u32_t mcpf_mcpq_mbuf_cluster; 16953 u32_t unused_6[11]; 16954 u32_t mcpf_mcpq_cmd; 16955 u32_t unused_7; 16956 16957 } mcp_fio_t; 16958 16959 16960 /* 16961 * mcp_fio definition 16962 * offset: 0x80000000 16963 */ 16964 typedef struct mcp_fio_xi 16965 { 16966 u32_t mcpf_events_bits; 16967 #define MCPF_EVENTS_BITS_FTQ0_VALID (1UL<<0) 16968 #define MCPF_EVENTS_BITS_FTQ1_VALID (1UL<<1) 16969 #define MCPF_EVENTS_BITS_UMP_EVENT (1UL<<2) 16970 #define MCPF_EVENTS_BITS_SMBUS_EVENT (1UL<<3) 16971 #define MCPF_EVENTS_BITS_FLASH_EVENT (1UL<<4) 16972 #define MCPF_EVENTS_BITS_MCP_DOORBELL (1UL<<5) 16973 #define MCPF_EVENTS_BITS_UNUSED_A (1UL<<6) 16974 #define MCPF_EVENTS_BITS_UNUSED_B (1UL<<7) 16975 #define MCPF_EVENTS_BITS_EXP_ROM (1UL<<8) 16976 #define MCPF_EVENTS_BITS_VPD (1UL<<9) 16977 #define MCPF_EVENTS_BITS_FLASH (1UL<<10) 16978 #define MCPF_EVENTS_BITS_SMB0 (1UL<<11) 16979 #define MCPF_EVENTS_BITS_RESERVED0 (1UL<<12) 16980 #define MCPF_EVENTS_BITS_RESERVED1 (1UL<<13) 16981 #define MCPF_EVENTS_BITS_RESERVED2 (1UL<<14) 16982 #define MCPF_EVENTS_BITS_GPIO (1UL<<15) 16983 #define MCPF_EVENTS_BITS_SW_TMR_1 (1UL<<19) 16984 #define MCPF_EVENTS_BITS_SW_TMR_2 (1UL<<20) 16985 #define MCPF_EVENTS_BITS_SW_TMR_3 (1UL<<21) 16986 #define MCPF_EVENTS_BITS_SW_TMR_4 (1UL<<22) 16987 #define MCPF_EVENTS_BITS_LINK_CHANGED (1UL<<23) 16988 #define MCPF_EVENTS_BITS_MI_INT (1UL<<25) 16989 #define MCPF_EVENTS_BITS_MI_COMPLETE (1UL<<26) 16990 #define MCPF_EVENTS_BITS_MAIN_PWR_INT (1UL<<27) 16991 #define MCPF_EVENTS_BITS_NOT_ENABLED (1UL<<30) 16992 #define MCPF_EVENTS_BITS_ATTENTIONS_VALID (1UL<<31) 16993 16994 u32_t mcpf_attentions_bits; 16995 #define MCPF_ATTENTIONS_BITS_LINK_STATE (1UL<<0) 16996 #define MCPF_ATTENTIONS_BITS_TX_SCHEDULER_ABORT (1UL<<1) 16997 #define MCPF_ATTENTIONS_BITS_TX_BD_READ_ABORT (1UL<<2) 16998 #define MCPF_ATTENTIONS_BITS_TX_BD_CACHE_ABORT (1UL<<3) 16999 #define MCPF_ATTENTIONS_BITS_TX_PROCESSOR_ABORT (1UL<<4) 17000 #define MCPF_ATTENTIONS_BITS_TX_DMA_ABORT (1UL<<5) 17001 #define MCPF_ATTENTIONS_BITS_TX_PATCHUP_ABORT (1UL<<6) 17002 #define MCPF_ATTENTIONS_BITS_TX_ASSEMBLER_ABORT (1UL<<7) 17003 #define MCPF_ATTENTIONS_BITS_RX_PARSER_MAC_ABORT (1UL<<8) 17004 #define MCPF_ATTENTIONS_BITS_RX_PARSER_CATCHUP_ABORT (1UL<<9) 17005 #define MCPF_ATTENTIONS_BITS_RX_MBUF_ABORT (1UL<<10) 17006 #define MCPF_ATTENTIONS_BITS_RX_LOOKUP_ABORT (1UL<<11) 17007 #define MCPF_ATTENTIONS_BITS_RX_PROCESSOR_ABORT (1UL<<12) 17008 #define MCPF_ATTENTIONS_BITS_RX_V2P_ABORT (1UL<<13) 17009 #define MCPF_ATTENTIONS_BITS_RX_BD_CACHE_ABORT (1UL<<14) 17010 #define MCPF_ATTENTIONS_BITS_RX_DMA_ABORT (1UL<<15) 17011 #define MCPF_ATTENTIONS_BITS_COMPLETION_ABORT (1UL<<16) 17012 #define MCPF_ATTENTIONS_BITS_HOST_COALESCE_ABORT (1UL<<17) 17013 #define MCPF_ATTENTIONS_BITS_MAILBOX_QUEUE_ABORT (1UL<<18) 17014 #define MCPF_ATTENTIONS_BITS_CONTEXT_ABORT (1UL<<19) 17015 #define MCPF_ATTENTIONS_BITS_CMD_SCHEDULER_ABORT (1UL<<20) 17016 #define MCPF_ATTENTIONS_BITS_CMD_PROCESSOR_ABORT (1UL<<21) 17017 #define MCPF_ATTENTIONS_BITS_MGMT_PROCESSOR_ABORT (1UL<<22) 17018 #define MCPF_ATTENTIONS_BITS_MAC_ABORT (1UL<<23) 17019 #define MCPF_ATTENTIONS_BITS_TIMER_ABORT (1UL<<24) 17020 #define MCPF_ATTENTIONS_BITS_DMAE_ABORT (1UL<<25) 17021 #define MCPF_ATTENTIONS_BITS_FLSH_ABORT (1UL<<26) 17022 #define MCPF_ATTENTIONS_BITS_GRC_ABORT (1UL<<27) 17023 #define MCPF_ATTENTIONS_BITS_PARITY_ERROR (1UL<<31) 17024 17025 u32_t mcpf_event_enable; 17026 u32_t mcpf_attention_enable; 17027 u32_t mcpf_fio_status; 17028 #define MCPF_FIO_STATUS_ENABLED (1UL<<0) 17029 #define MCPF_FIO_STATUS_FORCE_ENA (1UL<<1) 17030 17031 u32_t mcpf_interrupt_status; 17032 #define MCPF_INTERRUPT_STATUS_EVENT0 (1UL<<0) 17033 #define MCPF_INTERRUPT_STATUS_ATTN0 (1UL<<1) 17034 #define MCPF_INTERRUPT_STATUS_EVENT1 (1UL<<2) 17035 #define MCPF_INTERRUPT_STATUS_ATTN1 (1UL<<3) 17036 u32_t unused_0[10]; 17037 17038 u32_t mcpf_mcp_hc_inc_stat[8]; 17039 u32_t unused_1[4]; 17040 u32_t mcpf_free_counter_value; 17041 u32_t unused_2[35]; 17042 u32_t mcpf_mcpq_bits_status; 17043 #define MCPF_MCPQ_BITS_STATUS_RULE_CLASS (0x7UL<<0) 17044 #define MCPF_MCPQ_BITS_STATUS_RULE_P2 (1UL<<3) 17045 #define MCPF_MCPQ_BITS_STATUS_RULE_P3 (1UL<<4) 17046 #define MCPF_MCPQ_BITS_STATUS_RULE_P4 (1UL<<5) 17047 #define MCPF_MCPQ_BITS_STATUS_L2_VLAN_TAG (1UL<<6) 17048 #define MCPF_MCPQ_BITS_STATUS_L2_LLC_SNAP (1UL<<7) 17049 #define MCPF_MCPQ_BITS_STATUS_RSS_HASH (1UL<<8) 17050 #define MCPF_MCPQ_BITS_STATUS_SORT_VECT (0xfUL<<9) 17051 #define MCPF_MCPQ_BITS_STATUS_IP_DATAGRAM (1UL<<13) 17052 #define MCPF_MCPQ_BITS_STATUS_TCP_SEGMENT (1UL<<14) 17053 #define MCPF_MCPQ_BITS_STATUS_UDP_DATAGRAM (1UL<<15) 17054 #define MCPF_MCPQ_BITS_STATUS_CU_FRAME (1UL<<16) 17055 #define MCPF_MCPQ_BITS_STATUS_IP_PROG_EXT (1UL<<17) 17056 #define MCPF_MCPQ_BITS_STATUS_IP_TYPE (1UL<<18) 17057 #define MCPF_MCPQ_BITS_STATUS_RULE_P1 (1UL<<19) 17058 #define MCPF_MCPQ_BITS_STATUS_RLUP_HIT4 (1UL<<20) 17059 #define MCPF_MCPQ_BITS_STATUS_IP_FRAGMENT (1UL<<21) 17060 #define MCPF_MCPQ_BITS_STATUS_IP_OPTIONS_PRESENT (1UL<<22) 17061 #define MCPF_MCPQ_BITS_STATUS_TCP_OPTIONS_PRESENT (1UL<<23) 17062 #define MCPF_MCPQ_BITS_STATUS_L2_PM_IDX (0xfUL<<24) 17063 #define MCPF_MCPQ_BITS_STATUS_L2_PM_HIT (1UL<<28) 17064 #define MCPF_MCPQ_BITS_STATUS_L2_MC_HASH_HIT (1UL<<29) 17065 #define MCPF_MCPQ_BITS_STATUS_RDMAC_CRC_PASS (1UL<<30) 17066 #define MCPF_MCPQ_BITS_STATUS_MP_HIT (1UL<<31) 17067 17068 u16_t mcpf_mcpq_pkt_len; 17069 #define MCPF_MCPQ_PKT_LEN_VALUE (0x3fff<<0) 17070 17071 u16_t mcpf_mcpq_vlan_tag; 17072 u32_t mcpf_mcpq_mbuf_cluster; 17073 #define MCPF_MCPQ_MBUF_CLUSTER_VALUE (0x1ffffffUL<<0) 17074 17075 u32_t mcpf_mcpq_frm_errors; 17076 #define MCPF_MCPQ_FRM_ERRORS_L2_BAD_CRC (1UL<<1) 17077 #define MCPF_MCPQ_FRM_ERRORS_L2_PHY_DECODE (1UL<<2) 17078 #define MCPF_MCPQ_FRM_ERRORS_L2_ALIGNMENT (1UL<<3) 17079 #define MCPF_MCPQ_FRM_ERRORS_L2_TOO_SHORT (1UL<<4) 17080 #define MCPF_MCPQ_FRM_ERRORS_L2_GIANT_FRAME (1UL<<5) 17081 #define MCPF_MCPQ_FRM_ERRORS_IP_BAD_LEN (1UL<<6) 17082 #define MCPF_MCPQ_FRM_ERRORS_IP_TOO_SHORT (1UL<<7) 17083 #define MCPF_MCPQ_FRM_ERRORS_IP_BAD_VERSION (1UL<<8) 17084 #define MCPF_MCPQ_FRM_ERRORS_IP_BAD_HLEN (1UL<<9) 17085 #define MCPF_MCPQ_FRM_ERRORS_IP_BAD_XSUM (1UL<<10) 17086 #define MCPF_MCPQ_FRM_ERRORS_TCP_TOO_SHORT (1UL<<11) 17087 #define MCPF_MCPQ_FRM_ERRORS_TCP_BAD_XSUM (1UL<<12) 17088 #define MCPF_MCPQ_FRM_ERRORS_TCP_BAD_OFFSET (1UL<<13) 17089 #define MCPF_MCPQ_FRM_ERRORS_UDP_BAD_XSUM (1UL<<15) 17090 #define MCPF_MCPQ_FRM_ERRORS_IP_BAD_ORDER (1UL<<16) 17091 #define MCPF_MCPQ_FRM_ERRORS_IP_HDR_MISMATCH (1UL<<18) 17092 17093 u16_t mcpf_mcpq_ext_status; 17094 #define MCPF_MCPQ_EXT_STATUS_TCP_SYNC_PRESENT (1<<0) 17095 #define MCPF_MCPQ_EXT_STATUS_RLUP_HIT2 (1<<1) 17096 #define MCPF_MCPQ_EXT_STATUS_TCP_UDP_XSUM_IS_0 (1<<2) 17097 #define MCPF_MCPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT (0x3<<3) 17098 #define MCPF_MCPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT_00 (0<<3) 17099 #define MCPF_MCPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT_01 (1<<3) 17100 #define MCPF_MCPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT_10 (2<<3) 17101 #define MCPF_MCPQ_EXT_STATUS_IP_ROUTING_HDR_PRESENT_11 (3<<3) 17102 #define MCPF_MCPQ_EXT_STATUS_ACPI_MATCH (1<<5) 17103 17104 u16_t mcpf_mcpq_reserved; 17105 u32_t unused_3[9]; 17106 u32_t mcpf_mcpq_cmd; 17107 #define MCPF_MCPQ_CMD_MCPQ_CMD_POP (1UL<<30) 17108 u32_t unused_4[39089]; 17109 17110 u32_t mcpf_nvm_command; 17111 #define MCPF_NVM_COMMAND_RST (1UL<<0) 17112 #define MCPF_NVM_COMMAND_DONE (1UL<<3) 17113 #define MCPF_NVM_COMMAND_DOIT (1UL<<4) 17114 #define MCPF_NVM_COMMAND_WR (1UL<<5) 17115 #define MCPF_NVM_COMMAND_ERASE (1UL<<6) 17116 #define MCPF_NVM_COMMAND_FIRST (1UL<<7) 17117 #define MCPF_NVM_COMMAND_LAST (1UL<<8) 17118 #define MCPF_NVM_COMMAND_WREN (1UL<<16) 17119 #define MCPF_NVM_COMMAND_WRDI (1UL<<17) 17120 #define MCPF_NVM_COMMAND_RD_ID (1UL<<20) 17121 #define MCPF_NVM_COMMAND_RD_STATUS (1UL<<21) 17122 #define MCPF_NVM_COMMAND_MODE_256 (1UL<<22) 17123 17124 u32_t mcpf_nvm_status; 17125 #define MCPF_NVM_STATUS_SPI_FSM_STATE (0x1fUL<<0) 17126 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_IDLE (0UL<<0) 17127 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_CMD0 (1UL<<0) 17128 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_CMD1 (2UL<<0) 17129 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH0 (3UL<<0) 17130 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH1 (4UL<<0) 17131 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_ADDR0 (5UL<<0) 17132 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA0 (6UL<<0) 17133 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA1 (7UL<<0) 17134 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA2 (8UL<<0) 17135 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA0 (9UL<<0) 17136 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA1 (10UL<<0) 17137 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA2 (11UL<<0) 17138 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID0 (12UL<<0) 17139 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID1 (13UL<<0) 17140 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID2 (14UL<<0) 17141 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID3 (15UL<<0) 17142 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID4 (16UL<<0) 17143 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_CHECK_BUSY0 (17UL<<0) 17144 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_ST_WREN (18UL<<0) 17145 #define MCPF_NVM_STATUS_SPI_FSM_STATE_SPI_WAIT (19UL<<0) 17146 17147 u32_t mcpf_nvm_write; 17148 #define MCPF_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffUL<<0) 17149 #define MCPF_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0UL<<0) 17150 #define MCPF_NVM_WRITE_NVM_WRITE_VALUE_SI (1UL<<0) 17151 #define MCPF_NVM_WRITE_NVM_WRITE_VALUE_SO (2UL<<0) 17152 #define MCPF_NVM_WRITE_NVM_WRITE_VALUE_CS_B (4UL<<0) 17153 #define MCPF_NVM_WRITE_NVM_WRITE_VALUE_SCLK (8UL<<0) 17154 17155 u32_t mcpf_nvm_addr; 17156 #define MCPF_NVM_ADDR_NVM_ADDR_VALUE (0xffffffUL<<0) 17157 #define MCPF_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0UL<<0) 17158 #define MCPF_NVM_ADDR_NVM_ADDR_VALUE_SI (1UL<<0) 17159 #define MCPF_NVM_ADDR_NVM_ADDR_VALUE_SO (2UL<<0) 17160 #define MCPF_NVM_ADDR_NVM_ADDR_VALUE_CS_B (4UL<<0) 17161 #define MCPF_NVM_ADDR_NVM_ADDR_VALUE_SCLK (8UL<<0) 17162 17163 u32_t mcpf_nvm_read; 17164 #define MCPF_NVM_READ_NVM_READ_VALUE (0xffffffffUL<<0) 17165 #define MCPF_NVM_READ_NVM_READ_VALUE_BIT_BANG (0UL<<0) 17166 #define MCPF_NVM_READ_NVM_READ_VALUE_SI (1UL<<0) 17167 #define MCPF_NVM_READ_NVM_READ_VALUE_SO (2UL<<0) 17168 #define MCPF_NVM_READ_NVM_READ_VALUE_CS_B (4UL<<0) 17169 #define MCPF_NVM_READ_NVM_READ_VALUE_SCLK (8UL<<0) 17170 17171 u32_t mcpf_nvm_cfg1; 17172 #define MCPF_NVM_CFG1_FLASH_MODE (1UL<<0) 17173 #define MCPF_NVM_CFG1_BUFFER_MODE (1UL<<1) 17174 #define MCPF_NVM_CFG1_PASS_MODE (1UL<<2) 17175 #define MCPF_NVM_CFG1_BITBANG_MODE (1UL<<3) 17176 #define MCPF_NVM_CFG1_STATUS_BIT (0x7UL<<4) 17177 #define MCPF_NVM_CFG1_SPI_CLK_DIV (0xfUL<<7) 17178 #define MCPF_NVM_CFG1_SEE_CLK_DIV (0x7ffUL<<11) 17179 #define MCPF_NVM_CFG1_STRAP_CONTROL_0 (1UL<<23) 17180 #define MCPF_NVM_CFG1_PROTECT_MODE (1UL<<24) 17181 #define MCPF_NVM_CFG1_FLASH_SIZE (1UL<<25) 17182 #define MCPF_NVM_CFG1_FW_USTRAP_1 (1UL<<26) 17183 #define MCPF_NVM_CFG1_FW_USTRAP_0 (1UL<<27) 17184 #define MCPF_NVM_CFG1_FW_USTRAP_2 (1UL<<28) 17185 #define MCPF_NVM_CFG1_FW_USTRAP_3 (1UL<<29) 17186 #define MCPF_NVM_CFG1_FW_FLASH_TYPE_EN (1UL<<30) 17187 #define MCPF_NVM_CFG1_COMPAT_BYPASSS (1UL<<31) 17188 17189 u32_t mcpf_nvm_cfg2; 17190 #define MCPF_NVM_CFG2_ERASE_CMD (0xffUL<<0) 17191 #define MCPF_NVM_CFG2_STATUS_CMD (0xffUL<<16) 17192 #define MCPF_NVM_CFG2_READ_ID (0xffUL<<24) 17193 17194 u32_t mcpf_nvm_cfg3; 17195 #define MCPF_NVM_CFG3_BUFFER_RD_CMD (0xffUL<<0) 17196 #define MCPF_NVM_CFG3_WRITE_CMD (0xffUL<<8) 17197 #define MCPF_NVM_CFG3_READ_CMD (0xffUL<<24) 17198 17199 u32_t mcpf_nvm_sw_arb; 17200 #define MCPF_NVM_SW_ARB_ARB_REQ_SET0 (1UL<<0) 17201 #define MCPF_NVM_SW_ARB_ARB_REQ_SET1 (1UL<<1) 17202 #define MCPF_NVM_SW_ARB_ARB_REQ_SET2 (1UL<<2) 17203 #define MCPF_NVM_SW_ARB_ARB_REQ_SET3 (1UL<<3) 17204 #define MCPF_NVM_SW_ARB_ARB_REQ_CLR0 (1UL<<4) 17205 #define MCPF_NVM_SW_ARB_ARB_REQ_CLR1 (1UL<<5) 17206 #define MCPF_NVM_SW_ARB_ARB_REQ_CLR2 (1UL<<6) 17207 #define MCPF_NVM_SW_ARB_ARB_REQ_CLR3 (1UL<<7) 17208 #define MCPF_NVM_SW_ARB_ARB_ARB0 (1UL<<8) 17209 #define MCPF_NVM_SW_ARB_ARB_ARB1 (1UL<<9) 17210 #define MCPF_NVM_SW_ARB_ARB_ARB2 (1UL<<10) 17211 #define MCPF_NVM_SW_ARB_ARB_ARB3 (1UL<<11) 17212 #define MCPF_NVM_SW_ARB_REQ0 (1UL<<12) 17213 #define MCPF_NVM_SW_ARB_REQ1 (1UL<<13) 17214 #define MCPF_NVM_SW_ARB_REQ2 (1UL<<14) 17215 #define MCPF_NVM_SW_ARB_REQ3 (1UL<<15) 17216 17217 u32_t mcpf_nvm_access_enable; 17218 #define MCPF_NVM_ACCESS_ENABLE_EN (1UL<<0) 17219 #define MCPF_NVM_ACCESS_ENABLE_WR_EN (1UL<<1) 17220 17221 u32_t mcpf_nvm_write1; 17222 #define MCPF_NVM_WRITE1_WREN_CMD (0xffUL<<0) 17223 #define MCPF_NVM_WRITE1_WRDI_CMD (0xffUL<<8) 17224 17225 u32_t mcpf_nvm_cfg4; 17226 #define MCPF_NVM_CFG4_FLASH_SIZE (0x7UL<<0) 17227 #define MCPF_NVM_CFG4_FLASH_SIZE_1MBIT (0UL<<0) 17228 #define MCPF_NVM_CFG4_FLASH_SIZE_2MBIT (1UL<<0) 17229 #define MCPF_NVM_CFG4_FLASH_SIZE_4MBIT (2UL<<0) 17230 #define MCPF_NVM_CFG4_FLASH_SIZE_8MBIT (3UL<<0) 17231 #define MCPF_NVM_CFG4_FLASH_SIZE_16MBIT (4UL<<0) 17232 #define MCPF_NVM_CFG4_FLASH_SIZE_32MBIT (5UL<<0) 17233 #define MCPF_NVM_CFG4_FLASH_SIZE_64MBIT (6UL<<0) 17234 #define MCPF_NVM_CFG4_FLASH_SIZE_128MBIT (7UL<<0) 17235 #define MCPF_NVM_CFG4_FLASH_VENDOR (1UL<<3) 17236 #define MCPF_NVM_CFG4_FLASH_VENDOR_ST (0UL<<3) 17237 #define MCPF_NVM_CFG4_FLASH_VENDOR_ATMEL (1UL<<3) 17238 #define MCPF_NVM_CFG4_MODE_256_EMPTY_BIT_LOC (0x3UL<<4) 17239 #define MCPF_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT8 (0UL<<4) 17240 #define MCPF_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT9 (1UL<<4) 17241 #define MCPF_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT10 (2UL<<4) 17242 #define MCPF_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT11 (3UL<<4) 17243 #define MCPF_NVM_CFG4_STATUS_BIT_POLARITY (1UL<<6) 17244 #define MCPF_NVM_CFG4_RESERVED (0x1ffffffUL<<7) 17245 17246 u32_t mcpf_nvm_reconfig; 17247 #define MCPF_NVM_RECONFIG_ORIG_STRAP_VALUE (0xfUL<<0) 17248 #define MCPF_NVM_RECONFIG_ORIG_STRAP_VALUE_ST (0UL<<0) 17249 #define MCPF_NVM_RECONFIG_ORIG_STRAP_VALUE_ATMEL (1UL<<0) 17250 #define MCPF_NVM_RECONFIG_RECONFIG_STRAP_VALUE (0xfUL<<4) 17251 #define MCPF_NVM_RECONFIG_RESERVED (0x7fffffUL<<8) 17252 #define MCPF_NVM_RECONFIG_RECONFIG_DONE (1UL<<31) 17253 u32_t unused_5[1779]; 17254 17255 u32_t mcpf_smbus_config; 17256 #define MCPF_SMBUS_CONFIG_HW_ARP_ASSIGN_ADDR (1UL<<7) 17257 #define MCPF_SMBUS_CONFIG_ARP_EN0 (1UL<<8) 17258 #define MCPF_SMBUS_CONFIG_ARP_EN1 (1UL<<9) 17259 #define MCPF_SMBUS_CONFIG_MASTER_RTRY_CNT (0xfUL<<16) 17260 #define MCPF_SMBUS_CONFIG_TIMESTAMP_CNT_EN (1UL<<26) 17261 #define MCPF_SMBUS_CONFIG_PROMISCOUS_MODE (1UL<<27) 17262 #define MCPF_SMBUS_CONFIG_EN_NIC_SMB_ADDR_0 (1UL<<28) 17263 #define MCPF_SMBUS_CONFIG_BIT_BANG_EN (1UL<<29) 17264 #define MCPF_SMBUS_CONFIG_SMB_EN (1UL<<30) 17265 #define MCPF_SMBUS_CONFIG_RESET (1UL<<31) 17266 17267 u32_t mcpf_smbus_timing_config; 17268 #define MCPF_SMBUS_TIMING_CONFIG_SMBUS_IDLE_TIME (0xffUL<<8) 17269 #define MCPF_SMBUS_TIMING_CONFIG_PERIODIC_SLAVE_STRETCH (0xffUL<<16) 17270 #define MCPF_SMBUS_TIMING_CONFIG_RANDOM_SLAVE_STRETCH (0x7fUL<<24) 17271 #define MCPF_SMBUS_TIMING_CONFIG_MODE_400 (1UL<<31) 17272 17273 u32_t mcpf_smbus_address; 17274 #define MCPF_SMBUS_ADDRESS_NIC_SMB_ADDR0 (0x7fUL<<0) 17275 #define MCPF_SMBUS_ADDRESS_EN_NIC_SMB_ADDR0 (1UL<<7) 17276 #define MCPF_SMBUS_ADDRESS_NIC_SMB_ADDR1 (0x7fUL<<8) 17277 #define MCPF_SMBUS_ADDRESS_EN_NIC_SMB_ADDR1 (1UL<<15) 17278 #define MCPF_SMBUS_ADDRESS_NIC_SMB_ADDR2 (0x7fUL<<16) 17279 #define MCPF_SMBUS_ADDRESS_EN_NIC_SMB_ADDR2 (1UL<<23) 17280 #define MCPF_SMBUS_ADDRESS_NIC_SMB_ADDR3 (0x7fUL<<24) 17281 #define MCPF_SMBUS_ADDRESS_EN_NIC_SMB_ADDR3 (1UL<<31) 17282 17283 u32_t mcpf_smbus_master_fifo_control; 17284 #define MCPF_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_FIFO_THRESHOLD (0x7fUL<<8) 17285 #define MCPF_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_PKT_COUNT (0x7fUL<<16) 17286 #define MCPF_SMBUS_MASTER_FIFO_CONTROL_MASTER_TX_FIFO_FLUSH (1UL<<30) 17287 #define MCPF_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_FIFO_FLUSH (1UL<<31) 17288 17289 u32_t mcpf_smbus_slave_fifo_control; 17290 #define MCPF_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_FIFO_THRESHOLD (0x7fUL<<8) 17291 #define MCPF_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_PKT_COUNT (0x7fUL<<16) 17292 #define MCPF_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_TX_FIFO_FLUSH (1UL<<30) 17293 #define MCPF_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_FIFO_FLUSH (1UL<<31) 17294 17295 u32_t mcpf_smbus_bit_bang_control; 17296 #define MCPF_SMBUS_BIT_BANG_CONTROL_SMBDAT_OUT_EN (1UL<<28) 17297 #define MCPF_SMBUS_BIT_BANG_CONTROL_SMBDAT_IN (1UL<<29) 17298 #define MCPF_SMBUS_BIT_BANG_CONTROL_SMBCLK_OUT_EN (1UL<<30) 17299 #define MCPF_SMBUS_BIT_BANG_CONTROL_SMBCLK_IN (1UL<<31) 17300 17301 u32_t mcpf_smbus_watchdog; 17302 #define MCPF_SMBUS_WATCHDOG_WATCHDOG (0xffffUL<<0) 17303 17304 u32_t mcpf_smbus_heartbeat; 17305 #define MCPF_SMBUS_HEARTBEAT_HEARTBEAT (0xffffUL<<0) 17306 17307 u32_t mcpf_smbus_poll_asf; 17308 #define MCPF_SMBUS_POLL_ASF_POLL_ASF (0xffffUL<<0) 17309 17310 u32_t mcpf_smbus_poll_legacy; 17311 #define MCPF_SMBUS_POLL_LEGACY_POLL_LEGACY (0xffffUL<<0) 17312 17313 u32_t mcpf_smbus_retran; 17314 #define MCPF_SMBUS_RETRAN_RETRAN (0xffUL<<0) 17315 17316 u32_t mcpf_smbus_timestamp; 17317 #define MCPF_SMBUS_TIMESTAMP_TIMESTAMP (0xffffffffUL<<0) 17318 17319 u32_t mcpf_smbus_master_command; 17320 #define MCPF_SMBUS_MASTER_COMMAND_RD_BYTE_COUNT (0xffUL<<0) 17321 #define MCPF_SMBUS_MASTER_COMMAND_PEC (1UL<<8) 17322 #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL (0xfUL<<9) 17323 #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0000 (0UL<<9) 17324 #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0001 (1UL<<9) 17325 #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0010 (2UL<<9) 17326 #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0011 (3UL<<9) 17327 #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0100 (4UL<<9) 17328 #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0101 (5UL<<9) 17329 #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0110 (6UL<<9) 17330 #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_0111 (7UL<<9) 17331 #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_1000 (8UL<<9) 17332 #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_1001 (9UL<<9) 17333 #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_1010 (10UL<<9) 17334 #define MCPF_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_1011 (11UL<<9) 17335 #define MCPF_SMBUS_MASTER_COMMAND_STATUS (0x7UL<<25) 17336 #define MCPF_SMBUS_MASTER_COMMAND_STATUS_000 (0UL<<25) 17337 #define MCPF_SMBUS_MASTER_COMMAND_STATUS_001 (1UL<<25) 17338 #define MCPF_SMBUS_MASTER_COMMAND_STATUS_010 (2UL<<25) 17339 #define MCPF_SMBUS_MASTER_COMMAND_STATUS_011 (3UL<<25) 17340 #define MCPF_SMBUS_MASTER_COMMAND_STATUS_100 (4UL<<25) 17341 #define MCPF_SMBUS_MASTER_COMMAND_STATUS_101 (5UL<<25) 17342 #define MCPF_SMBUS_MASTER_COMMAND_STATUS_110 (6UL<<25) 17343 #define MCPF_SMBUS_MASTER_COMMAND_STATUS_111 (7UL<<25) 17344 #define MCPF_SMBUS_MASTER_COMMAND_ABORT (1UL<<30) 17345 #define MCPF_SMBUS_MASTER_COMMAND_START_BUSY (1UL<<31) 17346 17347 u32_t mcpf_smbus_slave_command; 17348 #define MCPF_SMBUS_SLAVE_COMMAND_PEC (1UL<<8) 17349 #define MCPF_SMBUS_SLAVE_COMMAND_STATUS (0x7UL<<23) 17350 #define MCPF_SMBUS_SLAVE_COMMAND_STATUS_000 (0UL<<23) 17351 #define MCPF_SMBUS_SLAVE_COMMAND_STATUS_101 (5UL<<23) 17352 #define MCPF_SMBUS_SLAVE_COMMAND_STATUS_111 (7UL<<23) 17353 #define MCPF_SMBUS_SLAVE_COMMAND_ABORT (1UL<<30) 17354 #define MCPF_SMBUS_SLAVE_COMMAND_START (1UL<<31) 17355 17356 u32_t mcpf_smbus_event_enable; 17357 #define MCPF_SMBUS_EVENT_ENABLE_WATCHDOG_TO_EN (1UL<<0) 17358 #define MCPF_SMBUS_EVENT_ENABLE_HEARTBEAT_TO_EN (1UL<<1) 17359 #define MCPF_SMBUS_EVENT_ENABLE_POLL_ASF_TO_EN (1UL<<2) 17360 #define MCPF_SMBUS_EVENT_ENABLE_POLL_LEGACY_TO_EN (1UL<<3) 17361 #define MCPF_SMBUS_EVENT_ENABLE_RETRANSMIT_TO_EN (1UL<<4) 17362 #define MCPF_SMBUS_EVENT_ENABLE_SLAVE_ARP_EVENT_EN (1UL<<20) 17363 #define MCPF_SMBUS_EVENT_ENABLE_SLAVE_RD_EVENT_EN (1UL<<21) 17364 #define MCPF_SMBUS_EVENT_ENABLE_SLAVE_TX_UNDERRUN_EN (1UL<<22) 17365 #define MCPF_SMBUS_EVENT_ENABLE_SLAVE_START_BUSY_EN (1UL<<23) 17366 #define MCPF_SMBUS_EVENT_ENABLE_SLAVE_RX_EVENT_EN (1UL<<24) 17367 #define MCPF_SMBUS_EVENT_ENABLE_SLAVE_RX_THRESHOLD_HIT_EN (1UL<<25) 17368 #define MCPF_SMBUS_EVENT_ENABLE_SLAVE_RX_FIFO_FULL_EN (1UL<<26) 17369 #define MCPF_SMBUS_EVENT_ENABLE_MASTER_TX_UNDERRUN_EN (1UL<<27) 17370 #define MCPF_SMBUS_EVENT_ENABLE_MASTER_START_BUSY_EN (1UL<<28) 17371 #define MCPF_SMBUS_EVENT_ENABLE_MASTER_RX_EVENT_EN (1UL<<29) 17372 #define MCPF_SMBUS_EVENT_ENABLE_MASTER_RX_THRESHOLD_HIT_EN (1UL<<30) 17373 #define MCPF_SMBUS_EVENT_ENABLE_MASTER_RX_FIFO_FULL_EN (1UL<<31) 17374 17375 u32_t mcpf_smbus_event_status; 17376 #define MCPF_SMBUS_EVENT_STATUS_WATCHDOG_TO (1UL<<0) 17377 #define MCPF_SMBUS_EVENT_STATUS_HEARTBEAT_TO (1UL<<1) 17378 #define MCPF_SMBUS_EVENT_STATUS_POLL_ASF_TO (1UL<<2) 17379 #define MCPF_SMBUS_EVENT_STATUS_POLL_LEGACY_TO (1UL<<3) 17380 #define MCPF_SMBUS_EVENT_STATUS_RETRANSMIT_TO (1UL<<4) 17381 #define MCPF_SMBUS_EVENT_STATUS_SLAVE_ARP_EVENT (1UL<<20) 17382 #define MCPF_SMBUS_EVENT_STATUS_SLAVE_RD_EVENT (1UL<<21) 17383 #define MCPF_SMBUS_EVENT_STATUS_SLAVE_TX_UNDERRUN (1UL<<22) 17384 #define MCPF_SMBUS_EVENT_STATUS_SLAVE_START_BUSY (1UL<<23) 17385 #define MCPF_SMBUS_EVENT_STATUS_SLAVE_RX_EVENT (1UL<<24) 17386 #define MCPF_SMBUS_EVENT_STATUS_SLAVE_RX_THRESHOLD_HIT (1UL<<25) 17387 #define MCPF_SMBUS_EVENT_STATUS_SLAVE_RX_FIFO_FULL (1UL<<26) 17388 #define MCPF_SMBUS_EVENT_STATUS_MASTER_TX_UNDERRUN (1UL<<27) 17389 #define MCPF_SMBUS_EVENT_STATUS_MASTER_START_BUSY (1UL<<28) 17390 #define MCPF_SMBUS_EVENT_STATUS_MASTER_RX_EVENT (1UL<<29) 17391 #define MCPF_SMBUS_EVENT_STATUS_MASTER_RX_THRESHOLD_HIT (1UL<<30) 17392 #define MCPF_SMBUS_EVENT_STATUS_MASTER_RX_FIFO_FULL (1UL<<31) 17393 17394 u32_t mcpf_smbus_master_data_write; 17395 #define MCPF_SMBUS_MASTER_DATA_WRITE_MASTER_SMBUS_WR_DATA (0xffUL<<0) 17396 #define MCPF_SMBUS_MASTER_DATA_WRITE_WR_STATUS (1UL<<31) 17397 17398 u32_t mcpf_smbus_master_data_read; 17399 #define MCPF_SMBUS_MASTER_DATA_READ_MASTER_SMBUS_RD_DATA (0xffUL<<0) 17400 #define MCPF_SMBUS_MASTER_DATA_READ_PEC_ERR (1UL<<29) 17401 #define MCPF_SMBUS_MASTER_DATA_READ_RD_STATUS (0x3UL<<30) 17402 #define MCPF_SMBUS_MASTER_DATA_READ_RD_STATUS_00 (0UL<<30) 17403 #define MCPF_SMBUS_MASTER_DATA_READ_RD_STATUS_01 (1UL<<30) 17404 #define MCPF_SMBUS_MASTER_DATA_READ_RD_STATUS_10 (2UL<<30) 17405 #define MCPF_SMBUS_MASTER_DATA_READ_RD_STATUS_11 (3UL<<30) 17406 17407 u32_t mcpf_smbus_slave_data_write; 17408 #define MCPF_SMBUS_SLAVE_DATA_WRITE_SLAVE_SMBUS_WR_DATA (0xffUL<<0) 17409 #define MCPF_SMBUS_SLAVE_DATA_WRITE_WR_STATUS (1UL<<31) 17410 #define MCPF_SMBUS_SLAVE_DATA_WRITE_WR_STATUS_0 (0UL<<31) 17411 #define MCPF_SMBUS_SLAVE_DATA_WRITE_WR_STATUS_1 (1UL<<31) 17412 17413 u32_t mcpf_smbus_slave_data_read; 17414 #define MCPF_SMBUS_SLAVE_DATA_READ_SLAVE_SMBUS_RD_DATA (0xffUL<<0) 17415 #define MCPF_SMBUS_SLAVE_DATA_READ_ERR_STATUS (0x3UL<<28) 17416 #define MCPF_SMBUS_SLAVE_DATA_READ_ERR_STATUS_00 (0UL<<28) 17417 #define MCPF_SMBUS_SLAVE_DATA_READ_ERR_STATUS_01 (1UL<<28) 17418 #define MCPF_SMBUS_SLAVE_DATA_READ_ERR_STATUS_10 (2UL<<28) 17419 #define MCPF_SMBUS_SLAVE_DATA_READ_ERR_STATUS_11 (3UL<<28) 17420 #define MCPF_SMBUS_SLAVE_DATA_READ_RD_STATUS (0x3UL<<30) 17421 #define MCPF_SMBUS_SLAVE_DATA_READ_RD_STATUS_00 (0UL<<30) 17422 #define MCPF_SMBUS_SLAVE_DATA_READ_RD_STATUS_01 (1UL<<30) 17423 #define MCPF_SMBUS_SLAVE_DATA_READ_RD_STATUS_10 (2UL<<30) 17424 #define MCPF_SMBUS_SLAVE_DATA_READ_RD_STATUS_11 (3UL<<30) 17425 u32_t unused_6[12]; 17426 17427 u32_t mcpf_smbus_arp_state; 17428 #define MCPF_SMBUS_ARP_STATE_AV_FLAG0 (1UL<<0) 17429 #define MCPF_SMBUS_ARP_STATE_AR_FLAG0 (1UL<<1) 17430 #define MCPF_SMBUS_ARP_STATE_AV_FLAG1 (1UL<<4) 17431 #define MCPF_SMBUS_ARP_STATE_AR_FLAG1 (1UL<<5) 17432 u32_t unused_7[3]; 17433 17434 u32_t mcpf_smbus_udid0_3; 17435 #define MCPF_SMBUS_UDID0_3_BYTE_12 (0xffUL<<0) 17436 #define MCPF_SMBUS_UDID0_3_BYTE_13 (0xffUL<<8) 17437 #define MCPF_SMBUS_UDID0_3_BYTE_14 (0xffUL<<16) 17438 #define MCPF_SMBUS_UDID0_3_BYTE_15 (0xffUL<<24) 17439 17440 u32_t mcpf_smbus_udid0_2; 17441 #define MCPF_SMBUS_UDID0_2_BYTE_8 (0xffUL<<0) 17442 #define MCPF_SMBUS_UDID0_2_BYTE_9 (0xffUL<<8) 17443 #define MCPF_SMBUS_UDID0_2_BYTE_10 (0xffUL<<16) 17444 #define MCPF_SMBUS_UDID0_2_BYTE_11 (0xffUL<<24) 17445 17446 u32_t mcpf_smbus_udid0_1; 17447 #define MCPF_SMBUS_UDID0_1_BYTE_4 (0xffUL<<0) 17448 #define MCPF_SMBUS_UDID0_1_BYTE_5 (0xffUL<<8) 17449 #define MCPF_SMBUS_UDID0_1_BYTE_6 (0xffUL<<16) 17450 #define MCPF_SMBUS_UDID0_1_BYTE_7 (0xffUL<<24) 17451 17452 u32_t mcpf_smbus_udid0_0; 17453 #define MCPF_SMBUS_UDID0_0_BYTE_0 (0xffUL<<0) 17454 #define MCPF_SMBUS_UDID0_0_BYTE_1 (0xffUL<<8) 17455 #define MCPF_SMBUS_UDID0_0_BYTE_2 (0xffUL<<16) 17456 #define MCPF_SMBUS_UDID0_0_BYTE_3 (0xffUL<<24) 17457 17458 u32_t mcpf_smbus_udid1_3; 17459 #define MCPF_SMBUS_UDID1_3_BYTE_12 (0xffUL<<0) 17460 #define MCPF_SMBUS_UDID1_3_BYTE_13 (0xffUL<<8) 17461 #define MCPF_SMBUS_UDID1_3_BYTE_14 (0xffUL<<16) 17462 #define MCPF_SMBUS_UDID1_3_BYTE_15 (0xffUL<<24) 17463 17464 u32_t mcpf_smbus_udid1_2; 17465 #define MCPF_SMBUS_UDID1_2_BYTE_8 (0xffUL<<0) 17466 #define MCPF_SMBUS_UDID1_2_BYTE_9 (0xffUL<<8) 17467 #define MCPF_SMBUS_UDID1_2_BYTE_10 (0xffUL<<16) 17468 #define MCPF_SMBUS_UDID1_2_BYTE_11 (0xffUL<<24) 17469 17470 u32_t mcpf_smbus_udid1_1; 17471 #define MCPF_SMBUS_UDID1_1_BYTE_4 (0xffUL<<0) 17472 #define MCPF_SMBUS_UDID1_1_BYTE_5 (0xffUL<<8) 17473 #define MCPF_SMBUS_UDID1_1_BYTE_6 (0xffUL<<16) 17474 #define MCPF_SMBUS_UDID1_1_BYTE_7 (0xffUL<<24) 17475 17476 u32_t mcpf_smbus_udid1_0; 17477 #define MCPF_SMBUS_UDID1_0_BYTE_0 (0xffUL<<0) 17478 #define MCPF_SMBUS_UDID1_0_BYTE_1 (0xffUL<<8) 17479 #define MCPF_SMBUS_UDID1_0_BYTE_2 (0xffUL<<16) 17480 #define MCPF_SMBUS_UDID1_0_BYTE_3 (0xffUL<<24) 17481 u32_t unused_8[468]; 17482 17483 u32_t mcpf_legacy_smb_asf_control; 17484 #define MCPF_LEGACY_SMB_ASF_CONTROL_ASF_RST (1UL<<0) 17485 #define MCPF_LEGACY_SMB_ASF_CONTROL_TSC_EN (1UL<<1) 17486 #define MCPF_LEGACY_SMB_ASF_CONTROL_WG_TO (1UL<<2) 17487 #define MCPF_LEGACY_SMB_ASF_CONTROL_HB_TO (1UL<<3) 17488 #define MCPF_LEGACY_SMB_ASF_CONTROL_PA_TO (1UL<<4) 17489 #define MCPF_LEGACY_SMB_ASF_CONTROL_PL_TO (1UL<<5) 17490 #define MCPF_LEGACY_SMB_ASF_CONTROL_RT_TO (1UL<<6) 17491 #define MCPF_LEGACY_SMB_ASF_CONTROL_SMB_EVENT (1UL<<7) 17492 #define MCPF_LEGACY_SMB_ASF_CONTROL_STRETCH_EN (1UL<<8) 17493 #define MCPF_LEGACY_SMB_ASF_CONTROL_STRETCH_PULSE (1UL<<9) 17494 #define MCPF_LEGACY_SMB_ASF_CONTROL_RES (0x3UL<<10) 17495 #define MCPF_LEGACY_SMB_ASF_CONTROL_SMB_EN (1UL<<12) 17496 #define MCPF_LEGACY_SMB_ASF_CONTROL_SMB_BB_EN (1UL<<13) 17497 #define MCPF_LEGACY_SMB_ASF_CONTROL_SMB_NO_ADDR_FILT (1UL<<14) 17498 #define MCPF_LEGACY_SMB_ASF_CONTROL_SMB_AUTOREAD (1UL<<15) 17499 #define MCPF_LEGACY_SMB_ASF_CONTROL_NIC_SMB_ADDR1 (0x7fUL<<16) 17500 #define MCPF_LEGACY_SMB_ASF_CONTROL_NIC_SMB_ADDR2 (0x7fUL<<23) 17501 #define MCPF_LEGACY_SMB_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1UL<<30) 17502 #define MCPF_LEGACY_SMB_ASF_CONTROL_SMB_EARLY_ATTN (1UL<<31) 17503 17504 u32_t mcpf_legacy_smb_in; 17505 #define MCPF_LEGACY_SMB_IN_DAT_IN (0xffUL<<0) 17506 #define MCPF_LEGACY_SMB_IN_RDY (1UL<<8) 17507 #define MCPF_LEGACY_SMB_IN_DONE (1UL<<9) 17508 #define MCPF_LEGACY_SMB_IN_FIRSTBYTE (1UL<<10) 17509 #define MCPF_LEGACY_SMB_IN_STATUS (0x7UL<<11) 17510 #define MCPF_LEGACY_SMB_IN_STATUS_OK (0UL<<11) 17511 #define MCPF_LEGACY_SMB_IN_STATUS_PEC (1UL<<11) 17512 #define MCPF_LEGACY_SMB_IN_STATUS_OFLOW (2UL<<11) 17513 #define MCPF_LEGACY_SMB_IN_STATUS_STOP (3UL<<11) 17514 #define MCPF_LEGACY_SMB_IN_STATUS_TIMEOUT (4UL<<11) 17515 17516 u32_t mcpf_legacy_smb_out; 17517 #define MCPF_LEGACY_SMB_OUT_DAT_OUT (0xffUL<<0) 17518 #define MCPF_LEGACY_SMB_OUT_RDY (1UL<<8) 17519 #define MCPF_LEGACY_SMB_OUT_START (1UL<<9) 17520 #define MCPF_LEGACY_SMB_OUT_LAST (1UL<<10) 17521 #define MCPF_LEGACY_SMB_OUT_ACC_TYPE (1UL<<11) 17522 #define MCPF_LEGACY_SMB_OUT_ENB_PEC (1UL<<12) 17523 #define MCPF_LEGACY_SMB_OUT_GET_RX_LEN (1UL<<13) 17524 #define MCPF_LEGACY_SMB_OUT_SMB_READ_LEN (0x3fUL<<14) 17525 #define MCPF_LEGACY_SMB_OUT_SMB_OUT_STATUS (0xfUL<<20) 17526 #define MCPF_LEGACY_SMB_OUT_SMB_OUT_STATUS_OK (0UL<<20) 17527 #define MCPF_LEGACY_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1UL<<20) 17528 #define MCPF_LEGACY_SMB_OUT_SMB_OUT_STATUS_UFLOW (2UL<<20) 17529 #define MCPF_LEGACY_SMB_OUT_SMB_OUT_STATUS_STOP (3UL<<20) 17530 #define MCPF_LEGACY_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4UL<<20) 17531 #define MCPF_LEGACY_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5UL<<20) 17532 #define MCPF_LEGACY_SMB_OUT_SMB_OUT_STATUS_BADACK (6UL<<20) 17533 #define MCPF_LEGACY_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9UL<<20) 17534 #define MCPF_LEGACY_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (13UL<<20) 17535 #define MCPF_LEGACY_SMB_OUT_SMB_OUT_SLAVEMODE (1UL<<24) 17536 #define MCPF_LEGACY_SMB_OUT_SMB_OUT_DAT_EN (1UL<<25) 17537 #define MCPF_LEGACY_SMB_OUT_SMB_OUT_DAT_IN (1UL<<26) 17538 #define MCPF_LEGACY_SMB_OUT_SMB_OUT_CLK_EN (1UL<<27) 17539 #define MCPF_LEGACY_SMB_OUT_SMB_OUT_CLK_IN (1UL<<28) 17540 17541 u32_t mcpf_legacy_smb_watchdog; 17542 #define MCPF_LEGACY_SMB_WATCHDOG_WATCHDOG (0xffffUL<<0) 17543 17544 u32_t mcpf_legacy_smb_heartbeat; 17545 #define MCPF_LEGACY_SMB_HEARTBEAT_HEARTBEAT (0xffffUL<<0) 17546 17547 u32_t mcpf_legacy_smb_poll_asf; 17548 #define MCPF_LEGACY_SMB_POLL_ASF_POLL_ASF (0xffffUL<<0) 17549 17550 u32_t mcpf_legacy_smb_poll_legacy; 17551 #define MCPF_LEGACY_SMB_POLL_LEGACY_POLL_LEGACY (0xffffUL<<0) 17552 17553 u32_t mcpf_legacy_smb_retran; 17554 #define MCPF_LEGACY_SMB_RETRAN_RETRAN (0xffUL<<0) 17555 17556 u32_t mcpf_legacy_smb_timestamp; 17557 #define MCPF_LEGACY_SMB_TIMESTAMP_TIMESTAMP (0xffffffffUL<<0) 17558 u32_t unused_9[15863]; 17559 17560 u32_t mcpf_ump_cmd; 17561 #define MCPF_UMP_CMD_EGRESS_FIFO_ENABLED (1UL<<0) 17562 #define MCPF_UMP_CMD_INGRESS_FIFO_ENABLED (1UL<<1) 17563 #define MCPF_UMP_CMD_FC_EN (1UL<<2) 17564 #define MCPF_UMP_CMD_MAC_LOOPBACK (1UL<<3) 17565 #define MCPF_UMP_CMD_EGRESS_MAC_DISABLE (1UL<<5) 17566 #define MCPF_UMP_CMD_INGRESS_MAC_DISABLE (1UL<<6) 17567 #define MCPF_UMP_CMD_INGRESS_DRIVE (1UL<<8) 17568 #define MCPF_UMP_CMD_SW_PAUSE (1UL<<9) 17569 #define MCPF_UMP_CMD_AUTO_DRIVE (1UL<<13) 17570 #define MCPF_UMP_CMD_INGRESS_RESET (1UL<<14) 17571 #define MCPF_UMP_CMD_NO_PLUS_TWO (1UL<<15) 17572 #define MCPF_UMP_CMD_EGRESS_PKT_FLUSH (1UL<<16) 17573 #define MCPF_UMP_CMD_CMD_IPG (0x1fUL<<17) 17574 #define MCPF_UMP_CMD_EGRESS_FIO_RESET (1UL<<28) 17575 #define MCPF_UMP_CMD_INGRESS_FIO_RESET (1UL<<29) 17576 #define MCPF_UMP_CMD_EGRESS_MAC_RESET (1UL<<30) 17577 #define MCPF_UMP_CMD_INGRESS_MAC_RESET (1UL<<31) 17578 17579 u32_t mcpf_ump_config; 17580 #define MCPF_UMP_CONFIG_RMII_MODE (1UL<<4) 17581 #define MCPF_UMP_CONFIG_RVMII_MODE (1UL<<6) 17582 #define MCPF_UMP_CONFIG_INGRESS_MODE (1UL<<7) 17583 #define MCPF_UMP_CONFIG_INGRESS_WORD_ACCM (0xffUL<<8) 17584 17585 u32_t mcpf_ump_fc_trip; 17586 #define MCPF_UMP_FC_TRIP_XON_TRIP (0x1ffUL<<0) 17587 #define MCPF_UMP_FC_TRIP_XOFF_TRIP (0x1ffUL<<16) 17588 u32_t unused_10[33]; 17589 17590 u32_t mcpf_ump_egress_frm_rd_status; 17591 #define MCPF_UMP_EGRESS_FRM_RD_STATUS_NEW_FRM (1UL<<0) 17592 #define MCPF_UMP_EGRESS_FRM_RD_STATUS_FRM_IN_PRO (1UL<<1) 17593 #define MCPF_UMP_EGRESS_FRM_RD_STATUS_FIFO_EMPTY (1UL<<2) 17594 #define MCPF_UMP_EGRESS_FRM_RD_STATUS_BCNT (0x7ffUL<<3) 17595 #define MCPF_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE (0x1fUL<<27) 17596 #define MCPF_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_IDLE (0UL<<27) 17597 #define MCPF_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_READY (1UL<<27) 17598 #define MCPF_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_BUSY (2UL<<27) 17599 #define MCPF_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_EXTRA_RD (3UL<<27) 17600 #define MCPF_UMP_EGRESS_FRM_RD_STATUS_EGRESS_FIFO_STATE_LATCH_IP_HDR (4UL<<27) 17601 17602 u32_t mcpf_ump_egress_frm_rd_data; 17603 u32_t mcpf_ump_ingress_frm_wr_ctl; 17604 #define MCPF_UMP_INGRESS_FRM_WR_CTL_NEW_FRM (1UL<<0) 17605 #define MCPF_UMP_INGRESS_FRM_WR_CTL_FIFO_RDY (1UL<<1) 17606 #define MCPF_UMP_INGRESS_FRM_WR_CTL_BCNT_RDY (1UL<<2) 17607 #define MCPF_UMP_INGRESS_FRM_WR_CTL_BCNT (0x7ffUL<<3) 17608 #define MCPF_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE (0x3UL<<30) 17609 #define MCPF_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE_IDLE (0UL<<30) 17610 #define MCPF_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE_WAIT (1UL<<30) 17611 #define MCPF_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE_BUSY (2UL<<30) 17612 #define MCPF_UMP_INGRESS_FRM_WR_CTL_INGRESS_FIFO_STATE_EXTRA_WR (3UL<<30) 17613 17614 u32_t mcpf_ump_ingress_frm_wr_data; 17615 u32_t mcpf_ump_egress_frame_type; 17616 u32_t mcpf_ump_fifo_remaining_words; 17617 #define MCPF_UMP_FIFO_REMAINING_WORDS_EGRESS_FIFO_DEPTH (0x7ffUL<<0) 17618 #define MCPF_UMP_FIFO_REMAINING_WORDS_INGRESS_FIFO_DEPTH (0x3ffUL<<16) 17619 17620 u32_t mcpf_ump_egress_fifo_ptrs; 17621 #define MCPF_UMP_EGRESS_FIFO_PTRS_EGRESS_FIFO_RD_PTR (0xfffUL<<0) 17622 #define MCPF_UMP_EGRESS_FIFO_PTRS_UPDATE_RDPTR (1UL<<15) 17623 #define MCPF_UMP_EGRESS_FIFO_PTRS_EGRESS_FIFO_WR_PTR (0xfffUL<<16) 17624 #define MCPF_UMP_EGRESS_FIFO_PTRS_UPDATE_WRPTR (1UL<<31) 17625 17626 u32_t mcpf_ump_ingress_fifo_ptrs; 17627 #define MCPF_UMP_INGRESS_FIFO_PTRS_INGRESS_FIFO_RD_PTR (0x7ffUL<<0) 17628 #define MCPF_UMP_INGRESS_FIFO_PTRS_UPDATE_RDPTR (1UL<<15) 17629 #define MCPF_UMP_INGRESS_FIFO_PTRS_INGRESS_FIFO_WR_PTR (0x7ffUL<<16) 17630 #define MCPF_UMP_INGRESS_FIFO_PTRS_UPDATE_WRPTR (1UL<<31) 17631 u32_t unused_11; 17632 17633 u32_t mcpf_ump_egress_packet_sa_0; 17634 #define MCPF_UMP_EGRESS_PACKET_SA_0_EGRESS_SA (0xffffUL<<0) 17635 17636 u32_t mcpf_ump_egress_packet_sa_1; 17637 #define MCPF_UMP_EGRESS_PACKET_SA_1_EGRESS_SA (0xffffffffUL<<0) 17638 17639 u32_t mcpf_ump_ingress_burst_command; 17640 #define MCPF_UMP_INGRESS_BURST_COMMAND_INGRESS_DMA_START (1UL<<0) 17641 #define MCPF_UMP_INGRESS_BURST_COMMAND_INGRESS_PORT (1UL<<1) 17642 #define MCPF_UMP_INGRESS_BURST_COMMAND_DMA_LENGTH (0x7ffUL<<2) 17643 #define MCPF_UMP_INGRESS_BURST_COMMAND_RBUF_OFFSET (0x3fffUL<<16) 17644 17645 u32_t mcpf_ump_ingress_rbuf_cluster; 17646 #define MCPF_UMP_INGRESS_RBUF_CLUSTER_RBUF_CLUSTER (0x1ffffffUL<<0) 17647 17648 u32_t mcpf_ump_ingress_vlan; 17649 #define MCPF_UMP_INGRESS_VLAN_INGRESS_VLAN_TAG (0xffffUL<<0) 17650 #define MCPF_UMP_INGRESS_VLAN_VLAN_INS (1UL<<16) 17651 #define MCPF_UMP_INGRESS_VLAN_VLAN_DEL (1UL<<17) 17652 17653 u32_t mcpf_ump_ingress_burst_status; 17654 #define MCPF_UMP_INGRESS_BURST_STATUS_RESULT (0x3UL<<0) 17655 #define MCPF_UMP_INGRESS_BURST_STATUS_RESULT_BUSY (0UL<<0) 17656 #define MCPF_UMP_INGRESS_BURST_STATUS_RESULT_DONE (1UL<<0) 17657 #define MCPF_UMP_INGRESS_BURST_STATUS_RESULT_ERR (2UL<<0) 17658 #define MCPF_UMP_INGRESS_BURST_STATUS_RESULT_ERR1 (3UL<<0) 17659 17660 u32_t mcpf_ump_egress_burst_command; 17661 #define MCPF_UMP_EGRESS_BURST_COMMAND_EGRESS_DMA_START (1UL<<0) 17662 #define MCPF_UMP_EGRESS_BURST_COMMAND_EGRESS_PORT (1UL<<1) 17663 #define MCPF_UMP_EGRESS_BURST_COMMAND_DMA_LENGTH (0x7ffUL<<2) 17664 #define MCPF_UMP_EGRESS_BURST_COMMAND_TPBUF_OFFSET (0x1fffUL<<16) 17665 17666 u32_t mcpf_ump_egress_vlan; 17667 #define MCPF_UMP_EGRESS_VLAN_EGRESS_VLAN_TAG (0xffffUL<<0) 17668 #define MCPF_UMP_EGRESS_VLAN_VLAN_INS (1UL<<16) 17669 #define MCPF_UMP_EGRESS_VLAN_VLAN_DEL (1UL<<17) 17670 17671 u32_t mcpf_ump_egress_burst_status; 17672 #define MCPF_UMP_EGRESS_BURST_STATUS_RESULT (0x3UL<<0) 17673 #define MCPF_UMP_EGRESS_BURST_STATUS_RESULT_BUSY (0UL<<0) 17674 #define MCPF_UMP_EGRESS_BURST_STATUS_RESULT_DONE (1UL<<0) 17675 #define MCPF_UMP_EGRESS_BURST_STATUS_RESULT_ERR0 (2UL<<0) 17676 #define MCPF_UMP_EGRESS_BURST_STATUS_RESULT_RSVD (3UL<<0) 17677 17678 u32_t mcpf_ump_egress_statistic; 17679 #define MCPF_UMP_EGRESS_STATISTIC_EGRESS_GOOD_CNT (0xffffUL<<0) 17680 #define MCPF_UMP_EGRESS_STATISTIC_EGRESS_ERROR_CNT (0xffUL<<16) 17681 #define MCPF_UMP_EGRESS_STATISTIC_EGRESS_DROP_CNT (0xffUL<<24) 17682 17683 u32_t mcpf_ump_ingress_statistic; 17684 #define MCPF_UMP_INGRESS_STATISTIC_INGRESS_PKT_CNT (0xffffUL<<0) 17685 17686 u32_t mcpf_ump_arb_cmd; 17687 #define MCPF_UMP_ARB_CMD_UMP_ID (0x7UL<<0) 17688 #define MCPF_UMP_ARB_CMD_UMP_ARB_DISABLE (1UL<<4) 17689 #define MCPF_UMP_ARB_CMD_UMP_ARB_START (1UL<<5) 17690 #define MCPF_UMP_ARB_CMD_UMP_ARB_BYPASS (1UL<<6) 17691 #define MCPF_UMP_ARB_CMD_UMP_ARB_AUTOBYPASS (1UL<<7) 17692 #define MCPF_UMP_ARB_CMD_UMP_ARB_TOKEN_IPG (0x1fUL<<8) 17693 #define MCPF_UMP_ARB_CMD_UMP_ARB_TOKEN_VALID (1UL<<13) 17694 #define MCPF_UMP_ARB_CMD_UMP_ARB_FC_DISABLE (1UL<<15) 17695 #define MCPF_UMP_ARB_CMD_UMP_ARB_TIMEOUT (0xffffUL<<16) 17696 u32_t unused_12[3]; 17697 17698 u32_t mcpf_ump_egress_statistic_ac; 17699 #define MCPF_UMP_EGRESS_STATISTIC_AC_EGRESS_GOOD_CNT (0xffffUL<<0) 17700 #define MCPF_UMP_EGRESS_STATISTIC_AC_EGRESS_ERROR_CNT (0xffUL<<16) 17701 #define MCPF_UMP_EGRESS_STATISTIC_AC_EGRESS_DROP_CNT (0xffUL<<24) 17702 17703 u32_t mcpf_ump_ingress_statistic_ac; 17704 #define MCPF_UMP_INGRESS_STATISTIC_AC_INGRESS_PKT_CNT (0xffffUL<<0) 17705 17706 u32_t mcpf_ump_event; 17707 #define MCPF_UMP_EVENT_INGRESS_RDY_EVENT (1UL<<0) 17708 #define MCPF_UMP_EVENT_EGRESS_RDY_EVENT (1UL<<1) 17709 #define MCPF_UMP_EVENT_INGRESSBURST_DONE_EVENT (1UL<<2) 17710 #define MCPF_UMP_EVENT_EGRESSBURST_DONE_EVENT (1UL<<3) 17711 #define MCPF_UMP_EVENT_EGRESS_FRAME_DROP_EVENT (1UL<<4) 17712 #define MCPF_UMP_EVENT_INGRESS_RDY_EVENT_EN (1UL<<16) 17713 #define MCPF_UMP_EVENT_EGRESS_RDY_EVENT_EN (1UL<<17) 17714 #define MCPF_UMP_EVENT_INGRESSBURST_DONE_EVENT_EN (1UL<<18) 17715 #define MCPF_UMP_EVENT_EGRESSBURST_DONE_EVENT_EN (1UL<<19) 17716 #define MCPF_UMP_EVENT_EGRESS_FRAME_DROP_EVENT_EN (1UL<<20) 17717 u32_t unused_13[4033]; 17718 17719 u32_t mcpf_ump_egress_fifo_flat_space[1920]; 17720 u32_t unused_14[128]; 17721 u32_t mcpf_ump_ingress_fifo_flat_space[768]; 17722 } mcp_fio_xi_t; 17723 17724 17725 17726 17727 17728 17729 17730 /* 17731 * msqe_b definition 17732 */ 17733 typedef struct msqe_b 17734 { 17735 u8_t msqe_cmd_type; 17736 u8_t msqe_retx_num; 17737 u16_t msqe_ctx_index; 17738 u32_t msqe_tcp_seq; 17739 } msqe_b_t; 17740 17741 17742 17743 /* 17744 * msqe_b definition 17745 */ 17746 typedef struct msqe_b_xi 17747 { 17748 u8_t msqe_cmd_type; 17749 u8_t msqe_retx_num; 17750 u16_t msqe_ctx_index; 17751 u32_t msqe_tcp_seq; 17752 } msqe_b_xi_t; 17753 17754 17755 /* 17756 * msqe_l definition 17757 */ 17758 typedef struct msqe_l 17759 { 17760 u16_t msqe_ctx_index; 17761 u8_t msqe_retx_num; 17762 u8_t msqe_cmd_type; 17763 u32_t msqe_tcp_seq; 17764 } msqe_l_t; 17765 17766 17767 17768 /* 17769 * msqe_l definition 17770 */ 17771 typedef struct msqe_l_xi 17772 { 17773 u16_t msqe_ctx_index; 17774 u8_t msqe_retx_num; 17775 u8_t msqe_cmd_type; 17776 u32_t msqe_tcp_seq; 17777 } msqe_l_xi_t; 17778 17779 17780 /* 17781 * msqe select 17782 */ 17783 #if defined(LITTLE_ENDIAN) 17784 typedef msqe_l_t msqe_t; 17785 typedef msqe_l_xi_t msqe_xi_t; 17786 #elif defined(BIG_ENDIAN) 17787 typedef msqe_b_t msqe_t; 17788 typedef msqe_b_xi_t msqe_xi_t; 17789 #endif 17790 17791 17792 /* 17793 * msq_context_b definition 17794 */ 17795 typedef struct msq_context_b 17796 { 17797 u8_t msq_ctx_type; 17798 17799 u8_t msq_ctx_size; 17800 u8_t msq_pidx; 17801 u8_t msq_cidx; 17802 u32_t msq_joe; 17803 msqe_b_t msq_q[15]; 17804 } msq_context_b_t; 17805 17806 17807 17808 /* 17809 * msq_context_b definition 17810 */ 17811 typedef struct msq_context_b_xi 17812 { 17813 u8_t msq_ctx_type; 17814 #define MSQ_CTX_TYPE_TYPE (0xf<<4) 17815 #define MSQ_CTX_TYPE_TYPE_EMPTY (0<<4) 17816 #define MSQ_CTX_TYPE_TYPE_L2 (1<<4) 17817 #define MSQ_CTX_TYPE_TYPE_TCP (2<<4) 17818 #define MSQ_CTX_TYPE_TYPE_L5 (3<<4) 17819 #define MSQ_CTX_TYPE_TYPE_L2_BD_CHN (4<<4) 17820 #define MSQ_CTX_TYPE_TYPE_CP_MSG (5<<4) 17821 17822 u8_t msq_ctx_size; 17823 u8_t msq_pidx; 17824 u8_t msq_cidx; 17825 u32_t msq_joe; 17826 msqe_b_xi_t msq_q[15]; 17827 } msq_context_b_xi_t; 17828 17829 17830 /* 17831 * msq_context_l definition 17832 */ 17833 typedef struct msq_context_l 17834 { 17835 u8_t msq_cidx; 17836 u8_t msq_pidx; 17837 u8_t msq_ctx_size; 17838 u8_t msq_ctx_type; 17839 17840 u32_t msq_joe; 17841 msqe_l_t msq_q[15]; 17842 } msq_context_l_t; 17843 17844 17845 17846 /* 17847 * msq_context_l definition 17848 */ 17849 typedef struct msq_context_l_xi 17850 { 17851 u8_t msq_cidx; 17852 u8_t msq_pidx; 17853 u8_t msq_ctx_size; 17854 u8_t msq_ctx_type; 17855 #define MSQ_CTX_TYPE_TYPE (0xf<<4) 17856 #define MSQ_CTX_TYPE_TYPE_EMPTY (0<<4) 17857 #define MSQ_CTX_TYPE_TYPE_L2 (1<<4) 17858 #define MSQ_CTX_TYPE_TYPE_TCP (2<<4) 17859 #define MSQ_CTX_TYPE_TYPE_L5 (3<<4) 17860 #define MSQ_CTX_TYPE_TYPE_L2_BD_CHN (4<<4) 17861 #define MSQ_CTX_TYPE_TYPE_CP_MSG (5<<4) 17862 17863 u32_t msq_joe; 17864 msqe_l_xi_t msq_q[15]; 17865 } msq_context_l_xi_t; 17866 17867 17868 /* 17869 * msq_context select 17870 */ 17871 #if defined(LITTLE_ENDIAN) 17872 typedef msq_context_l_t msq_context_t; 17873 typedef msq_context_l_xi_t msq_context_xi_t; 17874 #elif defined(BIG_ENDIAN) 17875 typedef msq_context_b_t msq_context_t; 17876 typedef msq_context_b_xi_t msq_context_xi_t; 17877 #endif 17878 17879 17880 #define ROFFSET(_field) \ 17881 ((u32_t) (((u8_t *) &(((reg_space_t *) 0)->_field)) - ((u8_t *) 0))) 17882 17883 /* 17884 * TX header Q and payload Q 17885 */ 17886 #define HDRQ_NBYTES (1<<13) 17887 #define HDRQ_MASK (u16_t)(HDRQ_NBYTES - 1) 17888 #define PLDQ_NBYTES (1<<13) 17889 #define PLDQ_MASK (u32_t)(PLDQ_NBYTES - 1) 17890 17891 17892 #endif 17893 17894