1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, v.1, (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://opensource.org/licenses/CDDL-1.0. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2014-2017 Cavium, Inc. 24 * The contents of this file are subject to the terms of the Common Development 25 * and Distribution License, v.1, (the "License"). 26 27 * You may not use this file except in compliance with the License. 28 29 * You can obtain a copy of the License at available 30 * at http://opensource.org/licenses/CDDL-1.0 31 32 * See the License for the specific language governing permissions and 33 * limitations under the License. 34 */ 35 36 /**************************************************************************** 37 * 38 * Name: nvm_cfg.h 39 * 40 * Description: NVM config file - Generated file from nvm cfg excel. 41 * DO NOT MODIFY !!! 42 * 43 * Created: 3/15/2017 44 * 45 ****************************************************************************/ 46 47 #ifndef NVM_CFG_H 48 #define NVM_CFG_H 49 50 #define NVM_CFG_version 0x81819 51 52 #define NVM_CFG_new_option_seq 22 53 54 #define NVM_CFG_removed_option_seq 1 55 56 #define NVM_CFG_updated_value_seq 4 57 58 struct nvm_cfg_mac_address 59 { 60 u32 mac_addr_hi; 61 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF 62 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0 63 u32 mac_addr_lo; 64 }; 65 66 /****************************************** 67 * nvm_cfg1 structs 68 ******************************************/ 69 struct nvm_cfg1_glob 70 { 71 u32 generic_cont0; /* 0x0 */ 72 #define NVM_CFG1_GLOB_BOARD_SWAP_MASK 0x0000000F 73 #define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET 0 74 #define NVM_CFG1_GLOB_BOARD_SWAP_NONE 0x0 75 #define NVM_CFG1_GLOB_BOARD_SWAP_PATH 0x1 76 #define NVM_CFG1_GLOB_BOARD_SWAP_PORT 0x2 77 #define NVM_CFG1_GLOB_BOARD_SWAP_BOTH 0x3 78 #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0 79 #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4 80 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0 81 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1 82 #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2 83 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3 84 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4 85 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5 86 #define NVM_CFG1_GLOB_MF_MODE_BD 0x6 87 #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7 88 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK 0x00001000 89 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_OFFSET 12 90 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED 0x0 91 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_ENABLED 0x1 92 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_MASK 0x001FE000 93 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_OFFSET 13 94 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_MASK 0x1FE00000 95 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_OFFSET 21 96 #define NVM_CFG1_GLOB_ENABLE_SRIOV_MASK 0x20000000 97 #define NVM_CFG1_GLOB_ENABLE_SRIOV_OFFSET 29 98 #define NVM_CFG1_GLOB_ENABLE_SRIOV_DISABLED 0x0 99 #define NVM_CFG1_GLOB_ENABLE_SRIOV_ENABLED 0x1 100 #define NVM_CFG1_GLOB_ENABLE_ATC_MASK 0x40000000 101 #define NVM_CFG1_GLOB_ENABLE_ATC_OFFSET 30 102 #define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED 0x0 103 #define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED 0x1 104 #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_MASK 0x80000000 105 #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_OFFSET 31 106 #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_DISABLED 0x0 107 #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_ENABLED 0x1 108 u32 engineering_change[3]; /* 0x4 */ 109 u32 manufacturing_id; /* 0x10 */ 110 u32 serial_number[4]; /* 0x14 */ 111 u32 pcie_cfg; /* 0x24 */ 112 #define NVM_CFG1_GLOB_PCI_GEN_MASK 0x00000003 113 #define NVM_CFG1_GLOB_PCI_GEN_OFFSET 0 114 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN1 0x0 115 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN2 0x1 116 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN3 0x2 117 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_MASK 0x00000004 118 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_OFFSET 2 119 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_DISABLED 0x0 120 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_ENABLED 0x1 121 #define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK 0x00000018 122 #define NVM_CFG1_GLOB_ASPM_SUPPORT_OFFSET 3 123 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED 0x0 124 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_DISABLED 0x1 125 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED 0x2 126 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_DISABLED 0x3 127 #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_MASK 0x00000020 128 #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_OFFSET 5 129 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK 0x000003C0 130 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_OFFSET 6 131 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_MASK 0x00001C00 132 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_OFFSET 10 133 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_HW 0x0 134 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_0DB 0x1 135 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_3_5DB 0x2 136 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_6_0DB 0x3 137 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_MASK 0x001FE000 138 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_OFFSET 13 139 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_MASK 0x1FE00000 140 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_OFFSET 21 141 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK 0x60000000 142 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_OFFSET 29 143 /* Set the duration, in seconds, fan failure signal should be 144 sampled */ 145 #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_MASK 0x80000000 146 #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_OFFSET 31 147 u32 mgmt_traffic; /* 0x28 */ 148 #define NVM_CFG1_GLOB_RESERVED60_MASK 0x00000001 149 #define NVM_CFG1_GLOB_RESERVED60_OFFSET 0 150 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_MASK 0x000001FE 151 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_OFFSET 1 152 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_MASK 0x0001FE00 153 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_OFFSET 9 154 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_MASK 0x01FE0000 155 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_OFFSET 17 156 #define NVM_CFG1_GLOB_SIDEBAND_MODE_MASK 0x06000000 157 #define NVM_CFG1_GLOB_SIDEBAND_MODE_OFFSET 25 158 #define NVM_CFG1_GLOB_SIDEBAND_MODE_DISABLED 0x0 159 #define NVM_CFG1_GLOB_SIDEBAND_MODE_RMII 0x1 160 #define NVM_CFG1_GLOB_SIDEBAND_MODE_SGMII 0x2 161 #define NVM_CFG1_GLOB_AUX_MODE_MASK 0x78000000 162 #define NVM_CFG1_GLOB_AUX_MODE_OFFSET 27 163 #define NVM_CFG1_GLOB_AUX_MODE_DEFAULT 0x0 164 #define NVM_CFG1_GLOB_AUX_MODE_SMBUS_ONLY 0x1 165 /* Indicates whether external thermal sonsor is available */ 166 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_MASK 0x80000000 167 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_OFFSET 31 168 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_DISABLED 0x0 169 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ENABLED 0x1 170 u32 core_cfg; /* 0x2C */ 171 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF 172 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0 173 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0 174 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1 175 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2 176 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3 177 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4 178 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5 179 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xB 180 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xC 181 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD 182 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE 183 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xF 184 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_MASK 0x00000100 185 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_OFFSET 8 186 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_DISABLED 0x0 187 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_ENABLED 0x1 188 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_MASK 0x00000200 189 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_OFFSET 9 190 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_DISABLED 0x0 191 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_ENABLED 0x1 192 #define NVM_CFG1_GLOB_MPS10_CORE_ADDR_MASK 0x0003FC00 193 #define NVM_CFG1_GLOB_MPS10_CORE_ADDR_OFFSET 10 194 #define NVM_CFG1_GLOB_MPS25_CORE_ADDR_MASK 0x03FC0000 195 #define NVM_CFG1_GLOB_MPS25_CORE_ADDR_OFFSET 18 196 #define NVM_CFG1_GLOB_AVS_MODE_MASK 0x1C000000 197 #define NVM_CFG1_GLOB_AVS_MODE_OFFSET 26 198 #define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP 0x0 199 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_CFG 0x1 200 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_OTP 0x2 201 #define NVM_CFG1_GLOB_AVS_MODE_DISABLED 0x3 202 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_MASK 0x60000000 203 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_OFFSET 29 204 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_DISABLED 0x0 205 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_ENABLED 0x1 206 #define NVM_CFG1_GLOB_DCI_SUPPORT_MASK 0x80000000 207 #define NVM_CFG1_GLOB_DCI_SUPPORT_OFFSET 31 208 #define NVM_CFG1_GLOB_DCI_SUPPORT_DISABLED 0x0 209 #define NVM_CFG1_GLOB_DCI_SUPPORT_ENABLED 0x1 210 u32 e_lane_cfg1; /* 0x30 */ 211 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F 212 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0 213 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0 214 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4 215 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00 216 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8 217 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000 218 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12 219 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000 220 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16 221 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000 222 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20 223 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000 224 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24 225 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000 226 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28 227 u32 e_lane_cfg2; /* 0x34 */ 228 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001 229 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0 230 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002 231 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1 232 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004 233 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2 234 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008 235 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3 236 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010 237 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4 238 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020 239 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5 240 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040 241 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6 242 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080 243 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7 244 #define NVM_CFG1_GLOB_SMBUS_MODE_MASK 0x00000F00 245 #define NVM_CFG1_GLOB_SMBUS_MODE_OFFSET 8 246 #define NVM_CFG1_GLOB_SMBUS_MODE_DISABLED 0x0 247 #define NVM_CFG1_GLOB_SMBUS_MODE_100KHZ 0x1 248 #define NVM_CFG1_GLOB_SMBUS_MODE_400KHZ 0x2 249 #define NVM_CFG1_GLOB_NCSI_MASK 0x0000F000 250 #define NVM_CFG1_GLOB_NCSI_OFFSET 12 251 #define NVM_CFG1_GLOB_NCSI_DISABLED 0x0 252 #define NVM_CFG1_GLOB_NCSI_ENABLED 0x1 253 /* Maximum advertised pcie link width */ 254 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_MASK 0x000F0000 255 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_OFFSET 16 256 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_BB_16_LANES 0x0 257 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_1_LANE 0x1 258 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_2_LANES 0x2 259 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_4_LANES 0x3 260 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_8_LANES 0x4 261 /* ASPM L1 mode */ 262 #define NVM_CFG1_GLOB_ASPM_L1_MODE_MASK 0x00300000 263 #define NVM_CFG1_GLOB_ASPM_L1_MODE_OFFSET 20 264 #define NVM_CFG1_GLOB_ASPM_L1_MODE_FORCED 0x0 265 #define NVM_CFG1_GLOB_ASPM_L1_MODE_DYNAMIC_LOW_LATENCY 0x1 266 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_MASK 0x01C00000 267 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_OFFSET 22 268 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_DISABLED 0x0 269 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_I2C 0x1 270 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_ONLY 0x2 271 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_SMBUS 0x3 272 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_MASK 0x06000000 273 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_OFFSET 25 274 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_DISABLE 0x0 275 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_INTERNAL 0x1 276 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_EXTERNAL 0x2 277 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_BOTH 0x3 278 /* Set the PLDM sensor modes */ 279 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_MASK 0x38000000 280 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_OFFSET 27 281 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_INTERNAL 0x0 282 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_EXTERNAL 0x1 283 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_BOTH 0x2 284 /* Enable VDM interface */ 285 #define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_MASK 0x40000000 286 #define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_OFFSET 30 287 #define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_DISABLED 0x0 288 #define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_ENABLED 0x1 289 /* ROL enable */ 290 #define NVM_CFG1_GLOB_RESET_ON_LAN_MASK 0x80000000 291 #define NVM_CFG1_GLOB_RESET_ON_LAN_OFFSET 31 292 #define NVM_CFG1_GLOB_RESET_ON_LAN_DISABLED 0x0 293 #define NVM_CFG1_GLOB_RESET_ON_LAN_ENABLED 0x1 294 u32 f_lane_cfg1; /* 0x38 */ 295 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F 296 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0 297 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0 298 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4 299 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00 300 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8 301 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000 302 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12 303 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000 304 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16 305 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000 306 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20 307 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000 308 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24 309 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000 310 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28 311 u32 f_lane_cfg2; /* 0x3C */ 312 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001 313 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0 314 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002 315 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1 316 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004 317 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2 318 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008 319 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3 320 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010 321 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4 322 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020 323 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5 324 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040 325 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6 326 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080 327 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7 328 /* Control the period between two successive checks */ 329 #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_MASK 0x0000FF00 330 #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_OFFSET 8 331 /* Set shutdown temperature */ 332 #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_MASK 0x00FF0000 333 #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_OFFSET 16 334 /* Set max. count for over operational temperature */ 335 #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_MASK 0xFF000000 336 #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_OFFSET 24 337 u32 mps10_preemphasis; /* 0x40 */ 338 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF 339 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0 340 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00 341 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8 342 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000 343 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16 344 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000 345 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24 346 u32 mps10_driver_current; /* 0x44 */ 347 #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF 348 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0 349 #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00 350 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8 351 #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000 352 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16 353 #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000 354 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24 355 u32 mps25_preemphasis; /* 0x48 */ 356 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF 357 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0 358 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00 359 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8 360 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000 361 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16 362 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000 363 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24 364 u32 mps25_driver_current; /* 0x4C */ 365 #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF 366 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0 367 #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00 368 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8 369 #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000 370 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16 371 #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000 372 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24 373 u32 pci_id; /* 0x50 */ 374 #define NVM_CFG1_GLOB_VENDOR_ID_MASK 0x0000FFFF 375 #define NVM_CFG1_GLOB_VENDOR_ID_OFFSET 0 376 /* Set caution temperature */ 377 #define NVM_CFG1_GLOB_CAUTION_THRESHOLD_TEMPERATURE_MASK 0x00FF0000 378 #define NVM_CFG1_GLOB_CAUTION_THRESHOLD_TEMPERATURE_OFFSET 16 379 /* Set external thermal sensor I2C address */ 380 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_MASK 0xFF000000 381 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_OFFSET 24 382 u32 pci_subsys_id; /* 0x54 */ 383 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFF 384 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_OFFSET 0 385 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_MASK 0xFFFF0000 386 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_OFFSET 16 387 u32 bar; /* 0x58 */ 388 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_MASK 0x0000000F 389 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_OFFSET 0 390 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_DISABLED 0x0 391 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2K 0x1 392 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4K 0x2 393 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8K 0x3 394 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16K 0x4 395 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32K 0x5 396 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_64K 0x6 397 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_128K 0x7 398 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_256K 0x8 399 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_512K 0x9 400 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_1M 0xA 401 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2M 0xB 402 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4M 0xC 403 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8M 0xD 404 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16M 0xE 405 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32M 0xF 406 /* BB VF BAR2 size */ 407 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_MASK 0x000000F0 408 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_OFFSET 4 409 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_DISABLED 0x0 410 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4K 0x1 411 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8K 0x2 412 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16K 0x3 413 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32K 0x4 414 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64K 0x5 415 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_128K 0x6 416 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_256K 0x7 417 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_512K 0x8 418 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_1M 0x9 419 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_2M 0xA 420 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4M 0xB 421 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8M 0xC 422 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16M 0xD 423 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32M 0xE 424 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64M 0xF 425 /* BB BAR2 size (global) */ 426 #define NVM_CFG1_GLOB_BAR2_SIZE_MASK 0x00000F00 427 #define NVM_CFG1_GLOB_BAR2_SIZE_OFFSET 8 428 #define NVM_CFG1_GLOB_BAR2_SIZE_DISABLED 0x0 429 #define NVM_CFG1_GLOB_BAR2_SIZE_64K 0x1 430 #define NVM_CFG1_GLOB_BAR2_SIZE_128K 0x2 431 #define NVM_CFG1_GLOB_BAR2_SIZE_256K 0x3 432 #define NVM_CFG1_GLOB_BAR2_SIZE_512K 0x4 433 #define NVM_CFG1_GLOB_BAR2_SIZE_1M 0x5 434 #define NVM_CFG1_GLOB_BAR2_SIZE_2M 0x6 435 #define NVM_CFG1_GLOB_BAR2_SIZE_4M 0x7 436 #define NVM_CFG1_GLOB_BAR2_SIZE_8M 0x8 437 #define NVM_CFG1_GLOB_BAR2_SIZE_16M 0x9 438 #define NVM_CFG1_GLOB_BAR2_SIZE_32M 0xA 439 #define NVM_CFG1_GLOB_BAR2_SIZE_64M 0xB 440 #define NVM_CFG1_GLOB_BAR2_SIZE_128M 0xC 441 #define NVM_CFG1_GLOB_BAR2_SIZE_256M 0xD 442 #define NVM_CFG1_GLOB_BAR2_SIZE_512M 0xE 443 #define NVM_CFG1_GLOB_BAR2_SIZE_1G 0xF 444 /* Set the duration, in seconds, fan failure signal should be 445 sampled */ 446 #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_MASK 0x0000F000 447 #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_OFFSET 12 448 /* This field defines the board total budget for bar2 when disabled 449 the regular bar size is used. */ 450 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_MASK 0x00FF0000 451 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_OFFSET 16 452 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_DISABLED 0x0 453 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64K 0x1 454 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128K 0x2 455 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256K 0x3 456 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512K 0x4 457 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1M 0x5 458 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_2M 0x6 459 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_4M 0x7 460 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_8M 0x8 461 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_16M 0x9 462 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_32M 0xA 463 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64M 0xB 464 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128M 0xC 465 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256M 0xD 466 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512M 0xE 467 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1G 0xF 468 /* Enable/Disable Crash dump triggers */ 469 #define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_MASK 0xFF000000 470 #define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_OFFSET 24 471 u32 mps10_txfir_main; /* 0x5C */ 472 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF 473 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0 474 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00 475 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8 476 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000 477 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16 478 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000 479 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24 480 u32 mps10_txfir_post; /* 0x60 */ 481 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF 482 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0 483 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00 484 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8 485 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000 486 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16 487 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000 488 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24 489 u32 mps25_txfir_main; /* 0x64 */ 490 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF 491 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0 492 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00 493 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8 494 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000 495 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16 496 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000 497 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24 498 u32 mps25_txfir_post; /* 0x68 */ 499 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF 500 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0 501 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00 502 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8 503 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000 504 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16 505 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000 506 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24 507 u32 manufacture_ver; /* 0x6C */ 508 #define NVM_CFG1_GLOB_MANUF0_VER_MASK 0x0000003F 509 #define NVM_CFG1_GLOB_MANUF0_VER_OFFSET 0 510 #define NVM_CFG1_GLOB_MANUF1_VER_MASK 0x00000FC0 511 #define NVM_CFG1_GLOB_MANUF1_VER_OFFSET 6 512 #define NVM_CFG1_GLOB_MANUF2_VER_MASK 0x0003F000 513 #define NVM_CFG1_GLOB_MANUF2_VER_OFFSET 12 514 #define NVM_CFG1_GLOB_MANUF3_VER_MASK 0x00FC0000 515 #define NVM_CFG1_GLOB_MANUF3_VER_OFFSET 18 516 #define NVM_CFG1_GLOB_MANUF4_VER_MASK 0x3F000000 517 #define NVM_CFG1_GLOB_MANUF4_VER_OFFSET 24 518 /* Select package id method */ 519 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_MASK 0x40000000 520 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_OFFSET 30 521 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_NVRAM 0x0 522 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_IO_PINS 0x1 523 #define NVM_CFG1_GLOB_RECOVERY_MODE_MASK 0x80000000 524 #define NVM_CFG1_GLOB_RECOVERY_MODE_OFFSET 31 525 #define NVM_CFG1_GLOB_RECOVERY_MODE_DISABLED 0x0 526 #define NVM_CFG1_GLOB_RECOVERY_MODE_ENABLED 0x1 527 u32 manufacture_time; /* 0x70 */ 528 #define NVM_CFG1_GLOB_MANUF0_TIME_MASK 0x0000003F 529 #define NVM_CFG1_GLOB_MANUF0_TIME_OFFSET 0 530 #define NVM_CFG1_GLOB_MANUF1_TIME_MASK 0x00000FC0 531 #define NVM_CFG1_GLOB_MANUF1_TIME_OFFSET 6 532 #define NVM_CFG1_GLOB_MANUF2_TIME_MASK 0x0003F000 533 #define NVM_CFG1_GLOB_MANUF2_TIME_OFFSET 12 534 /* Max MSIX for Ethernet in default mode */ 535 #define NVM_CFG1_GLOB_MAX_MSIX_MASK 0x03FC0000 536 #define NVM_CFG1_GLOB_MAX_MSIX_OFFSET 18 537 /* PF Mapping */ 538 #define NVM_CFG1_GLOB_PF_MAPPING_MASK 0x0C000000 539 #define NVM_CFG1_GLOB_PF_MAPPING_OFFSET 26 540 #define NVM_CFG1_GLOB_PF_MAPPING_CONTINUOUS 0x0 541 #define NVM_CFG1_GLOB_PF_MAPPING_FIXED 0x1 542 #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_MASK 0x30000000 543 #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_OFFSET 28 544 #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_DISABLED 0x0 545 #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_TI 0x1 546 u32 led_global_settings; /* 0x74 */ 547 #define NVM_CFG1_GLOB_LED_SWAP_0_MASK 0x0000000F 548 #define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET 0 549 #define NVM_CFG1_GLOB_LED_SWAP_1_MASK 0x000000F0 550 #define NVM_CFG1_GLOB_LED_SWAP_1_OFFSET 4 551 #define NVM_CFG1_GLOB_LED_SWAP_2_MASK 0x00000F00 552 #define NVM_CFG1_GLOB_LED_SWAP_2_OFFSET 8 553 #define NVM_CFG1_GLOB_LED_SWAP_3_MASK 0x0000F000 554 #define NVM_CFG1_GLOB_LED_SWAP_3_OFFSET 12 555 /* Max. continues operating temperature */ 556 #define NVM_CFG1_GLOB_MAX_CONT_OPERATING_TEMP_MASK 0x00FF0000 557 #define NVM_CFG1_GLOB_MAX_CONT_OPERATING_TEMP_OFFSET 16 558 /* GPIO which triggers run-time port swap according to the map 559 specified in option 205 */ 560 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_MASK 0xFF000000 561 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_OFFSET 24 562 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_NA 0x0 563 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO0 0x1 564 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO1 0x2 565 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO2 0x3 566 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO3 0x4 567 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO4 0x5 568 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO5 0x6 569 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO6 0x7 570 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO7 0x8 571 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO8 0x9 572 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO9 0xA 573 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO10 0xB 574 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO11 0xC 575 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO12 0xD 576 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO13 0xE 577 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO14 0xF 578 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO15 0x10 579 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO16 0x11 580 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO17 0x12 581 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO18 0x13 582 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO19 0x14 583 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO20 0x15 584 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO21 0x16 585 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO22 0x17 586 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO23 0x18 587 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO24 0x19 588 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO25 0x1A 589 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO26 0x1B 590 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO27 0x1C 591 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO28 0x1D 592 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO29 0x1E 593 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO30 0x1F 594 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO31 0x20 595 u32 generic_cont1; /* 0x78 */ 596 #define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK 0x000003FF 597 #define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET 0 598 #define NVM_CFG1_GLOB_LANE0_SWAP_MASK 0x00000C00 599 #define NVM_CFG1_GLOB_LANE0_SWAP_OFFSET 10 600 #define NVM_CFG1_GLOB_LANE1_SWAP_MASK 0x00003000 601 #define NVM_CFG1_GLOB_LANE1_SWAP_OFFSET 12 602 #define NVM_CFG1_GLOB_LANE2_SWAP_MASK 0x0000C000 603 #define NVM_CFG1_GLOB_LANE2_SWAP_OFFSET 14 604 #define NVM_CFG1_GLOB_LANE3_SWAP_MASK 0x00030000 605 #define NVM_CFG1_GLOB_LANE3_SWAP_OFFSET 16 606 /* Enable option 195 - Overriding the PCIe Preset value */ 607 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_MASK 0x00040000 608 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_OFFSET 18 609 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_DISABLED 0x0 610 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_ENABLED 0x1 611 /* PCIe Preset value - applies only if option 194 is enabled */ 612 #define NVM_CFG1_GLOB_PCIE_PRESET_VALUE_MASK 0x00780000 613 #define NVM_CFG1_GLOB_PCIE_PRESET_VALUE_OFFSET 19 614 /* Port mapping to be used when the run-time GPIO for port-swap is 615 defined and set. */ 616 #define NVM_CFG1_GLOB_RUNTIME_PORT0_SWAP_MAP_MASK 0x01800000 617 #define NVM_CFG1_GLOB_RUNTIME_PORT0_SWAP_MAP_OFFSET 23 618 #define NVM_CFG1_GLOB_RUNTIME_PORT1_SWAP_MAP_MASK 0x06000000 619 #define NVM_CFG1_GLOB_RUNTIME_PORT1_SWAP_MAP_OFFSET 25 620 #define NVM_CFG1_GLOB_RUNTIME_PORT2_SWAP_MAP_MASK 0x18000000 621 #define NVM_CFG1_GLOB_RUNTIME_PORT2_SWAP_MAP_OFFSET 27 622 #define NVM_CFG1_GLOB_RUNTIME_PORT3_SWAP_MAP_MASK 0x60000000 623 #define NVM_CFG1_GLOB_RUNTIME_PORT3_SWAP_MAP_OFFSET 29 624 u32 mbi_version; /* 0x7C */ 625 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF 626 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0 627 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00 628 #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8 629 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000 630 #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16 631 /* If set to other than NA, 0 - Normal operation, 1 - Thermal event 632 occurred */ 633 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_MASK 0xFF000000 634 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_OFFSET 24 635 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_NA 0x0 636 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO0 0x1 637 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO1 0x2 638 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO2 0x3 639 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO3 0x4 640 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO4 0x5 641 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO5 0x6 642 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO6 0x7 643 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO7 0x8 644 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO8 0x9 645 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO9 0xA 646 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO10 0xB 647 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO11 0xC 648 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO12 0xD 649 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO13 0xE 650 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO14 0xF 651 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO15 0x10 652 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO16 0x11 653 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO17 0x12 654 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO18 0x13 655 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO19 0x14 656 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO20 0x15 657 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO21 0x16 658 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO22 0x17 659 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO23 0x18 660 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO24 0x19 661 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO25 0x1A 662 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO26 0x1B 663 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO27 0x1C 664 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO28 0x1D 665 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO29 0x1E 666 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO30 0x1F 667 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO31 0x20 668 u32 mbi_date; /* 0x80 */ 669 u32 misc_sig; /* 0x84 */ 670 /* Define the GPIO mapping to switch i2c mux */ 671 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_MASK 0x000000FF 672 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_OFFSET 0 673 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_MASK 0x0000FF00 674 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_OFFSET 8 675 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__NA 0x0 676 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO0 0x1 677 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO1 0x2 678 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO2 0x3 679 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO3 0x4 680 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO4 0x5 681 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO5 0x6 682 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO6 0x7 683 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO7 0x8 684 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO8 0x9 685 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO9 0xA 686 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO10 0xB 687 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO11 0xC 688 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO12 0xD 689 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO13 0xE 690 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO14 0xF 691 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO15 0x10 692 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO16 0x11 693 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO17 0x12 694 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO18 0x13 695 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO19 0x14 696 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO20 0x15 697 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO21 0x16 698 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO22 0x17 699 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO23 0x18 700 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO24 0x19 701 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO25 0x1A 702 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO26 0x1B 703 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO27 0x1C 704 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO28 0x1D 705 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO29 0x1E 706 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO30 0x1F 707 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31 0x20 708 /* Interrupt signal used for SMBus/I2C management interface 709 710 0 = Interrupt event occurred 711 1 = Normal 712 */ 713 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_MASK 0x00FF0000 714 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_OFFSET 16 715 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_NA 0x0 716 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO0 0x1 717 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO1 0x2 718 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO2 0x3 719 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO3 0x4 720 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO4 0x5 721 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO5 0x6 722 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO6 0x7 723 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO7 0x8 724 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO8 0x9 725 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO9 0xA 726 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO10 0xB 727 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO11 0xC 728 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO12 0xD 729 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO13 0xE 730 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO14 0xF 731 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO15 0x10 732 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO16 0x11 733 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO17 0x12 734 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO18 0x13 735 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO19 0x14 736 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO20 0x15 737 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO21 0x16 738 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO22 0x17 739 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO23 0x18 740 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO24 0x19 741 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO25 0x1A 742 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO26 0x1B 743 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO27 0x1C 744 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO28 0x1D 745 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO29 0x1E 746 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO30 0x1F 747 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO31 0x20 748 /* Set aLOM FAN on GPIO */ 749 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_MASK 0xFF000000 750 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_OFFSET 24 751 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_NA 0x0 752 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO0 0x1 753 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO1 0x2 754 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO2 0x3 755 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO3 0x4 756 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO4 0x5 757 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO5 0x6 758 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO6 0x7 759 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO7 0x8 760 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO8 0x9 761 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO9 0xA 762 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO10 0xB 763 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO11 0xC 764 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO12 0xD 765 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO13 0xE 766 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO14 0xF 767 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO15 0x10 768 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO16 0x11 769 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO17 0x12 770 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO18 0x13 771 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO19 0x14 772 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO20 0x15 773 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO21 0x16 774 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO22 0x17 775 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO23 0x18 776 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO24 0x19 777 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO25 0x1A 778 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO26 0x1B 779 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO27 0x1C 780 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO28 0x1D 781 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO29 0x1E 782 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO30 0x1F 783 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO31 0x20 784 u32 device_capabilities; /* 0x88 */ 785 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1 786 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2 787 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4 788 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8 789 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP 0x10 790 u32 power_dissipated; /* 0x8C */ 791 #define NVM_CFG1_GLOB_POWER_DIS_D0_MASK 0x000000FF 792 #define NVM_CFG1_GLOB_POWER_DIS_D0_OFFSET 0 793 #define NVM_CFG1_GLOB_POWER_DIS_D1_MASK 0x0000FF00 794 #define NVM_CFG1_GLOB_POWER_DIS_D1_OFFSET 8 795 #define NVM_CFG1_GLOB_POWER_DIS_D2_MASK 0x00FF0000 796 #define NVM_CFG1_GLOB_POWER_DIS_D2_OFFSET 16 797 #define NVM_CFG1_GLOB_POWER_DIS_D3_MASK 0xFF000000 798 #define NVM_CFG1_GLOB_POWER_DIS_D3_OFFSET 24 799 u32 power_consumed; /* 0x90 */ 800 #define NVM_CFG1_GLOB_POWER_CONS_D0_MASK 0x000000FF 801 #define NVM_CFG1_GLOB_POWER_CONS_D0_OFFSET 0 802 #define NVM_CFG1_GLOB_POWER_CONS_D1_MASK 0x0000FF00 803 #define NVM_CFG1_GLOB_POWER_CONS_D1_OFFSET 8 804 #define NVM_CFG1_GLOB_POWER_CONS_D2_MASK 0x00FF0000 805 #define NVM_CFG1_GLOB_POWER_CONS_D2_OFFSET 16 806 #define NVM_CFG1_GLOB_POWER_CONS_D3_MASK 0xFF000000 807 #define NVM_CFG1_GLOB_POWER_CONS_D3_OFFSET 24 808 u32 efi_version; /* 0x94 */ 809 u32 multi_network_modes_capability; /* 0x98 */ 810 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X10G 0x1 811 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X25G 0x2 812 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X25G 0x4 813 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X25G 0x8 814 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X40G 0x10 815 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X40G 0x20 816 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X50G 0x40 817 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_BB_1X100G 0x80 818 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X10G 0x100 819 u32 nvm_cfg_version; /* 0x9C */ 820 u32 nvm_cfg_new_option_seq; /* 0xA0 */ 821 u32 nvm_cfg_removed_option_seq; /* 0xA4 */ 822 u32 nvm_cfg_updated_value_seq; /* 0xA8 */ 823 u32 extended_serial_number[8]; /* 0xAC */ 824 u32 oem1_number[8]; /* 0xCC */ 825 u32 oem2_number[8]; /* 0xEC */ 826 u32 mps25_active_txfir_pre; /* 0x10C */ 827 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_PRE_MASK 0x000000FF 828 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_PRE_OFFSET 0 829 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_PRE_MASK 0x0000FF00 830 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_PRE_OFFSET 8 831 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_PRE_MASK 0x00FF0000 832 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_PRE_OFFSET 16 833 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_PRE_MASK 0xFF000000 834 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_PRE_OFFSET 24 835 u32 mps25_active_txfir_main; /* 0x110 */ 836 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_MAIN_MASK 0x000000FF 837 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_MAIN_OFFSET 0 838 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_MAIN_MASK 0x0000FF00 839 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_MAIN_OFFSET 8 840 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_MAIN_MASK 0x00FF0000 841 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_MAIN_OFFSET 16 842 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_MAIN_MASK 0xFF000000 843 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_MAIN_OFFSET 24 844 u32 mps25_active_txfir_post; /* 0x114 */ 845 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_POST_MASK 0x000000FF 846 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_POST_OFFSET 0 847 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_POST_MASK 0x0000FF00 848 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_POST_OFFSET 8 849 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_POST_MASK 0x00FF0000 850 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_POST_OFFSET 16 851 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_POST_MASK 0xFF000000 852 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_POST_OFFSET 24 853 u32 features; /* 0x118 */ 854 /* Set the Aux Fan on temperature */ 855 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_VALUE_MASK 0x000000FF 856 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_VALUE_OFFSET 0 857 /* Set NC-SI package ID */ 858 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_MASK 0x0000FF00 859 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_OFFSET 8 860 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_NA 0x0 861 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO0 0x1 862 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO1 0x2 863 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO2 0x3 864 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO3 0x4 865 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO4 0x5 866 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO5 0x6 867 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO6 0x7 868 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO7 0x8 869 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO8 0x9 870 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO9 0xA 871 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO10 0xB 872 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO11 0xC 873 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO12 0xD 874 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO13 0xE 875 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO14 0xF 876 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO15 0x10 877 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO16 0x11 878 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO17 0x12 879 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO18 0x13 880 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO19 0x14 881 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO20 0x15 882 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO21 0x16 883 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO22 0x17 884 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO23 0x18 885 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO24 0x19 886 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO25 0x1A 887 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO26 0x1B 888 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO27 0x1C 889 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO28 0x1D 890 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO29 0x1E 891 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO30 0x1F 892 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO31 0x20 893 /* PMBUS Clock GPIO */ 894 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_MASK 0x00FF0000 895 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_OFFSET 16 896 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_NA 0x0 897 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO0 0x1 898 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO1 0x2 899 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO2 0x3 900 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO3 0x4 901 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO4 0x5 902 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO5 0x6 903 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO6 0x7 904 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO7 0x8 905 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO8 0x9 906 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO9 0xA 907 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO10 0xB 908 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO11 0xC 909 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO12 0xD 910 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO13 0xE 911 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO14 0xF 912 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO15 0x10 913 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO16 0x11 914 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO17 0x12 915 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO18 0x13 916 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO19 0x14 917 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO20 0x15 918 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO21 0x16 919 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO22 0x17 920 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO23 0x18 921 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO24 0x19 922 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO25 0x1A 923 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO26 0x1B 924 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO27 0x1C 925 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO28 0x1D 926 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO29 0x1E 927 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO30 0x1F 928 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO31 0x20 929 /* PMBUS Data GPIO */ 930 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_MASK 0xFF000000 931 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_OFFSET 24 932 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_NA 0x0 933 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO0 0x1 934 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO1 0x2 935 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO2 0x3 936 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO3 0x4 937 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO4 0x5 938 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO5 0x6 939 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO6 0x7 940 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO7 0x8 941 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO8 0x9 942 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO9 0xA 943 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO10 0xB 944 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO11 0xC 945 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO12 0xD 946 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO13 0xE 947 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO14 0xF 948 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO15 0x10 949 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO16 0x11 950 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO17 0x12 951 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO18 0x13 952 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO19 0x14 953 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO20 0x15 954 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO21 0x16 955 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO22 0x17 956 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO23 0x18 957 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO24 0x19 958 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO25 0x1A 959 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO26 0x1B 960 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO27 0x1C 961 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO28 0x1D 962 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO29 0x1E 963 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO30 0x1F 964 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO31 0x20 965 u32 tx_rx_eq_25g_hlpc; /* 0x11C */ 966 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_HLPC_MASK 0x000000FF 967 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_HLPC_OFFSET 0 968 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_HLPC_MASK 0x0000FF00 969 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_HLPC_OFFSET 8 970 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_HLPC_MASK 0x00FF0000 971 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_HLPC_OFFSET 16 972 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_HLPC_MASK 0xFF000000 973 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_HLPC_OFFSET 24 974 u32 tx_rx_eq_25g_llpc; /* 0x120 */ 975 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_LLPC_MASK 0x000000FF 976 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_LLPC_OFFSET 0 977 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_LLPC_MASK 0x0000FF00 978 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_LLPC_OFFSET 8 979 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_LLPC_MASK 0x00FF0000 980 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_LLPC_OFFSET 16 981 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_LLPC_MASK 0xFF000000 982 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_LLPC_OFFSET 24 983 u32 tx_rx_eq_25g_ac; /* 0x124 */ 984 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_AC_MASK 0x000000FF 985 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_AC_OFFSET 0 986 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_AC_MASK 0x0000FF00 987 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_AC_OFFSET 8 988 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_AC_MASK 0x00FF0000 989 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_AC_OFFSET 16 990 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_AC_MASK 0xFF000000 991 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_AC_OFFSET 24 992 u32 tx_rx_eq_10g_pc; /* 0x128 */ 993 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_PC_MASK 0x000000FF 994 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_PC_OFFSET 0 995 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_PC_MASK 0x0000FF00 996 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_PC_OFFSET 8 997 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_PC_MASK 0x00FF0000 998 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_PC_OFFSET 16 999 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_PC_MASK 0xFF000000 1000 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_PC_OFFSET 24 1001 u32 tx_rx_eq_10g_ac; /* 0x12C */ 1002 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_AC_MASK 0x000000FF 1003 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_AC_OFFSET 0 1004 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_AC_MASK 0x0000FF00 1005 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_AC_OFFSET 8 1006 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_AC_MASK 0x00FF0000 1007 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_AC_OFFSET 16 1008 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_AC_MASK 0xFF000000 1009 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_AC_OFFSET 24 1010 u32 tx_rx_eq_1g; /* 0x130 */ 1011 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_1G_MASK 0x000000FF 1012 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_1G_OFFSET 0 1013 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_1G_MASK 0x0000FF00 1014 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_1G_OFFSET 8 1015 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_1G_MASK 0x00FF0000 1016 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_1G_OFFSET 16 1017 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_1G_MASK 0xFF000000 1018 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_1G_OFFSET 24 1019 u32 tx_rx_eq_25g_bt; /* 0x134 */ 1020 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_BT_MASK 0x000000FF 1021 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_BT_OFFSET 0 1022 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_BT_MASK 0x0000FF00 1023 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_BT_OFFSET 8 1024 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_BT_MASK 0x00FF0000 1025 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_BT_OFFSET 16 1026 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_BT_MASK 0xFF000000 1027 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_BT_OFFSET 24 1028 u32 tx_rx_eq_10g_bt; /* 0x138 */ 1029 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_BT_MASK 0x000000FF 1030 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_BT_OFFSET 0 1031 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_BT_MASK 0x0000FF00 1032 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_BT_OFFSET 8 1033 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_BT_MASK 0x00FF0000 1034 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_BT_OFFSET 16 1035 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_BT_MASK 0xFF000000 1036 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_BT_OFFSET 24 1037 u32 generic_cont4; /* 0x13C */ 1038 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_MASK 0x000000FF 1039 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_OFFSET 0 1040 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_NA 0x0 1041 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO0 0x1 1042 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO1 0x2 1043 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO2 0x3 1044 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO3 0x4 1045 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO4 0x5 1046 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO5 0x6 1047 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO6 0x7 1048 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO7 0x8 1049 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO8 0x9 1050 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO9 0xA 1051 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO10 0xB 1052 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO11 0xC 1053 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO12 0xD 1054 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO13 0xE 1055 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO14 0xF 1056 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO15 0x10 1057 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO16 0x11 1058 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO17 0x12 1059 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO18 0x13 1060 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO19 0x14 1061 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO20 0x15 1062 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO21 0x16 1063 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO22 0x17 1064 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO23 0x18 1065 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO24 0x19 1066 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO25 0x1A 1067 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO26 0x1B 1068 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO27 0x1C 1069 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO28 0x1D 1070 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO29 0x1E 1071 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO30 0x1F 1072 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO31 0x20 1073 u32 preboot_debug_mode_std; /* 0x140 */ 1074 u32 preboot_debug_mode_ext; /* 0x144 */ 1075 u32 reserved[56]; /* 0x148 */ 1076 }; 1077 1078 struct nvm_cfg1_path 1079 { 1080 u32 reserved[1]; /* 0x0 */ 1081 }; 1082 1083 struct nvm_cfg1_port 1084 { 1085 u32 reserved__m_relocated_to_option_123; /* 0x0 */ 1086 u32 reserved__m_relocated_to_option_124; /* 0x4 */ 1087 u32 generic_cont0; /* 0x8 */ 1088 #define NVM_CFG1_PORT_LED_MODE_MASK 0x000000FF 1089 #define NVM_CFG1_PORT_LED_MODE_OFFSET 0 1090 #define NVM_CFG1_PORT_LED_MODE_MAC1 0x0 1091 #define NVM_CFG1_PORT_LED_MODE_PHY1 0x1 1092 #define NVM_CFG1_PORT_LED_MODE_PHY2 0x2 1093 #define NVM_CFG1_PORT_LED_MODE_PHY3 0x3 1094 #define NVM_CFG1_PORT_LED_MODE_MAC2 0x4 1095 #define NVM_CFG1_PORT_LED_MODE_PHY4 0x5 1096 #define NVM_CFG1_PORT_LED_MODE_PHY5 0x6 1097 #define NVM_CFG1_PORT_LED_MODE_PHY6 0x7 1098 #define NVM_CFG1_PORT_LED_MODE_MAC3 0x8 1099 #define NVM_CFG1_PORT_LED_MODE_PHY7 0x9 1100 #define NVM_CFG1_PORT_LED_MODE_PHY8 0xA 1101 #define NVM_CFG1_PORT_LED_MODE_PHY9 0xB 1102 #define NVM_CFG1_PORT_LED_MODE_MAC4 0xC 1103 #define NVM_CFG1_PORT_LED_MODE_PHY10 0xD 1104 #define NVM_CFG1_PORT_LED_MODE_PHY11 0xE 1105 #define NVM_CFG1_PORT_LED_MODE_PHY12 0xF 1106 #define NVM_CFG1_PORT_LED_MODE_BREAKOUT 0x10 1107 #define NVM_CFG1_PORT_ROCE_PRIORITY_MASK 0x0000FF00 1108 #define NVM_CFG1_PORT_ROCE_PRIORITY_OFFSET 8 1109 #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000 1110 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16 1111 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0 1112 #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1 1113 #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2 1114 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3 1115 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000 1116 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20 1117 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1 1118 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2 1119 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4 1120 /* GPIO for HW reset the PHY. In case it is the same for all ports, 1121 need to set same value for all ports */ 1122 #define NVM_CFG1_PORT_EXT_PHY_RESET_MASK 0xFF000000 1123 #define NVM_CFG1_PORT_EXT_PHY_RESET_OFFSET 24 1124 #define NVM_CFG1_PORT_EXT_PHY_RESET_NA 0x0 1125 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO0 0x1 1126 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO1 0x2 1127 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO2 0x3 1128 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO3 0x4 1129 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO4 0x5 1130 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO5 0x6 1131 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO6 0x7 1132 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO7 0x8 1133 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO8 0x9 1134 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO9 0xA 1135 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO10 0xB 1136 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO11 0xC 1137 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO12 0xD 1138 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO13 0xE 1139 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO14 0xF 1140 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO15 0x10 1141 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO16 0x11 1142 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO17 0x12 1143 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO18 0x13 1144 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO19 0x14 1145 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO20 0x15 1146 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO21 0x16 1147 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO22 0x17 1148 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO23 0x18 1149 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO24 0x19 1150 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO25 0x1A 1151 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO26 0x1B 1152 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO27 0x1C 1153 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO28 0x1D 1154 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO29 0x1E 1155 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO30 0x1F 1156 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO31 0x20 1157 u32 pcie_cfg; /* 0xC */ 1158 #define NVM_CFG1_PORT_RESERVED15_MASK 0x00000007 1159 #define NVM_CFG1_PORT_RESERVED15_OFFSET 0 1160 u32 features; /* 0x10 */ 1161 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_MASK 0x00000001 1162 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_OFFSET 0 1163 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_DISABLED 0x0 1164 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_ENABLED 0x1 1165 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_MASK 0x00000002 1166 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_OFFSET 1 1167 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_DISABLED 0x0 1168 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_ENABLED 0x1 1169 u32 speed_cap_mask; /* 0x14 */ 1170 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1171 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1172 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1173 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1174 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1175 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1176 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1177 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1178 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1179 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1180 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1181 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1182 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1183 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1184 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1185 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1186 u32 link_settings; /* 0x18 */ 1187 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F 1188 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0 1189 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0 1190 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1 1191 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2 1192 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4 1193 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5 1194 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6 1195 #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7 1196 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070 1197 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4 1198 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1 1199 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2 1200 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4 1201 #define NVM_CFG1_PORT_MFW_LINK_SPEED_MASK 0x00000780 1202 #define NVM_CFG1_PORT_MFW_LINK_SPEED_OFFSET 7 1203 #define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG 0x0 1204 #define NVM_CFG1_PORT_MFW_LINK_SPEED_1G 0x1 1205 #define NVM_CFG1_PORT_MFW_LINK_SPEED_10G 0x2 1206 #define NVM_CFG1_PORT_MFW_LINK_SPEED_25G 0x4 1207 #define NVM_CFG1_PORT_MFW_LINK_SPEED_40G 0x5 1208 #define NVM_CFG1_PORT_MFW_LINK_SPEED_50G 0x6 1209 #define NVM_CFG1_PORT_MFW_LINK_SPEED_BB_100G 0x7 1210 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK 0x00003800 1211 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET 11 1212 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG 0x1 1213 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX 0x2 1214 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX 0x4 1215 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_MASK 0x00004000 1216 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_OFFSET 14 1217 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_DISABLED 0x0 1218 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_ENABLED 0x1 1219 #define NVM_CFG1_PORT_AN_25G_50G_OUI_MASK 0x00018000 1220 #define NVM_CFG1_PORT_AN_25G_50G_OUI_OFFSET 15 1221 #define NVM_CFG1_PORT_AN_25G_50G_OUI_CONSORTIUM 0x0 1222 #define NVM_CFG1_PORT_AN_25G_50G_OUI_BAM 0x1 1223 #define NVM_CFG1_PORT_FEC_FORCE_MODE_MASK 0x000E0000 1224 #define NVM_CFG1_PORT_FEC_FORCE_MODE_OFFSET 17 1225 #define NVM_CFG1_PORT_FEC_FORCE_MODE_NONE 0x0 1226 #define NVM_CFG1_PORT_FEC_FORCE_MODE_FIRECODE 0x1 1227 #define NVM_CFG1_PORT_FEC_FORCE_MODE_RS 0x2 1228 #define NVM_CFG1_PORT_FEC_FORCE_MODE_AUTO 0x7 1229 #define NVM_CFG1_PORT_FEC_AN_MODE_MASK 0x00700000 1230 #define NVM_CFG1_PORT_FEC_AN_MODE_OFFSET 20 1231 #define NVM_CFG1_PORT_FEC_AN_MODE_NONE 0x0 1232 #define NVM_CFG1_PORT_FEC_AN_MODE_10G_FIRECODE 0x1 1233 #define NVM_CFG1_PORT_FEC_AN_MODE_25G_FIRECODE 0x2 1234 #define NVM_CFG1_PORT_FEC_AN_MODE_10G_AND_25G_FIRECODE 0x3 1235 #define NVM_CFG1_PORT_FEC_AN_MODE_25G_RS 0x4 1236 #define NVM_CFG1_PORT_FEC_AN_MODE_25G_FIRECODE_AND_RS 0x5 1237 #define NVM_CFG1_PORT_FEC_AN_MODE_ALL 0x6 1238 #define NVM_CFG1_PORT_SMARTLINQ_MODE_MASK 0x00800000 1239 #define NVM_CFG1_PORT_SMARTLINQ_MODE_OFFSET 23 1240 #define NVM_CFG1_PORT_SMARTLINQ_MODE_DISABLED 0x0 1241 #define NVM_CFG1_PORT_SMARTLINQ_MODE_ENABLED 0x1 1242 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_MASK 0x01000000 1243 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_OFFSET 24 1244 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_DISABLED 0x0 1245 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_ENABLED 0x1 1246 u32 phy_cfg; /* 0x1C */ 1247 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK 0x0000FFFF 1248 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET 0 1249 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_HIGIG 0x1 1250 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_SCRAMBLER 0x2 1251 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_FIBER 0x4 1252 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_CL72_AN 0x8 1253 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_FEC_AN 0x10 1254 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_MASK 0x00FF0000 1255 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_OFFSET 16 1256 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_BYPASS 0x0 1257 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR 0x2 1258 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR2 0x3 1259 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR4 0x4 1260 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XFI 0x8 1261 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SFI 0x9 1262 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_1000X 0xB 1263 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SGMII 0xC 1264 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLAUI 0x11 1265 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLPPI 0x12 1266 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CAUI 0x21 1267 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CPPI 0x22 1268 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_25GAUI 0x31 1269 #define NVM_CFG1_PORT_AN_MODE_MASK 0xFF000000 1270 #define NVM_CFG1_PORT_AN_MODE_OFFSET 24 1271 #define NVM_CFG1_PORT_AN_MODE_NONE 0x0 1272 #define NVM_CFG1_PORT_AN_MODE_CL73 0x1 1273 #define NVM_CFG1_PORT_AN_MODE_CL37 0x2 1274 #define NVM_CFG1_PORT_AN_MODE_CL73_BAM 0x3 1275 #define NVM_CFG1_PORT_AN_MODE_BB_CL37_BAM 0x4 1276 #define NVM_CFG1_PORT_AN_MODE_BB_HPAM 0x5 1277 #define NVM_CFG1_PORT_AN_MODE_BB_SGMII 0x6 1278 u32 mgmt_traffic; /* 0x20 */ 1279 #define NVM_CFG1_PORT_RESERVED61_MASK 0x0000000F 1280 #define NVM_CFG1_PORT_RESERVED61_OFFSET 0 1281 u32 ext_phy; /* 0x24 */ 1282 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_MASK 0x000000FF 1283 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_OFFSET 0 1284 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE 0x0 1285 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM8485X 0x1 1286 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK 0x0000FF00 1287 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_OFFSET 8 1288 /* EEE power saving mode */ 1289 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK 0x00FF0000 1290 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET 16 1291 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED 0x0 1292 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED 0x1 1293 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE 0x2 1294 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY 0x3 1295 u32 mba_cfg1; /* 0x28 */ 1296 #define NVM_CFG1_PORT_PREBOOT_OPROM_MASK 0x00000001 1297 #define NVM_CFG1_PORT_PREBOOT_OPROM_OFFSET 0 1298 #define NVM_CFG1_PORT_PREBOOT_OPROM_DISABLED 0x0 1299 #define NVM_CFG1_PORT_PREBOOT_OPROM_ENABLED 0x1 1300 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_MASK 0x00000006 1301 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_OFFSET 1 1302 #define NVM_CFG1_PORT_MBA_DELAY_TIME_MASK 0x00000078 1303 #define NVM_CFG1_PORT_MBA_DELAY_TIME_OFFSET 3 1304 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_MASK 0x00000080 1305 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_OFFSET 7 1306 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_S 0x0 1307 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_B 0x1 1308 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_MASK 0x00000100 1309 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_OFFSET 8 1310 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_DISABLED 0x0 1311 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_ENABLED 0x1 1312 #define NVM_CFG1_PORT_RESERVED5_MASK 0x0001FE00 1313 #define NVM_CFG1_PORT_RESERVED5_OFFSET 9 1314 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_MASK 0x001E0000 1315 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_OFFSET 17 1316 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_AUTONEG 0x0 1317 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_1G 0x1 1318 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_10G 0x2 1319 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_25G 0x4 1320 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_40G 0x5 1321 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_50G 0x6 1322 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_BB_100G 0x7 1323 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_MASK 0x00E00000 1324 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_OFFSET 21 1325 #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_MASK 0x01000000 1326 #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_OFFSET 24 1327 #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_DISABLED 0x0 1328 #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_ENABLED 0x1 1329 u32 mba_cfg2; /* 0x2C */ 1330 #define NVM_CFG1_PORT_RESERVED65_MASK 0x0000FFFF 1331 #define NVM_CFG1_PORT_RESERVED65_OFFSET 0 1332 #define NVM_CFG1_PORT_RESERVED66_MASK 0x00010000 1333 #define NVM_CFG1_PORT_RESERVED66_OFFSET 16 1334 #define NVM_CFG1_PORT_PREBOOT_LINK_UP_DELAY_MASK 0x01FE0000 1335 #define NVM_CFG1_PORT_PREBOOT_LINK_UP_DELAY_OFFSET 17 1336 u32 vf_cfg; /* 0x30 */ 1337 #define NVM_CFG1_PORT_RESERVED8_MASK 0x0000FFFF 1338 #define NVM_CFG1_PORT_RESERVED8_OFFSET 0 1339 #define NVM_CFG1_PORT_RESERVED6_MASK 0x000F0000 1340 #define NVM_CFG1_PORT_RESERVED6_OFFSET 16 1341 struct nvm_cfg_mac_address lldp_mac_address; /* 0x34 */ 1342 u32 led_port_settings; /* 0x3C */ 1343 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_MASK 0x000000FF 1344 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_OFFSET 0 1345 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_MASK 0x0000FF00 1346 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_OFFSET 8 1347 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_MASK 0x00FF0000 1348 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_OFFSET 16 1349 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G 0x1 1350 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G 0x2 1351 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_25G 0x4 1352 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_25G 0x8 1353 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_40G 0x8 1354 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_40G 0x10 1355 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_50G 0x10 1356 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_50G 0x20 1357 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_100G 0x40 1358 u32 transceiver_00; /* 0x40 */ 1359 /* Define for mapping of transceiver signal module absent */ 1360 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK 0x000000FF 1361 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_OFFSET 0 1362 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_NA 0x0 1363 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO0 0x1 1364 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO1 0x2 1365 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO2 0x3 1366 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO3 0x4 1367 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO4 0x5 1368 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO5 0x6 1369 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO6 0x7 1370 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO7 0x8 1371 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO8 0x9 1372 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO9 0xA 1373 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO10 0xB 1374 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO11 0xC 1375 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO12 0xD 1376 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO13 0xE 1377 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO14 0xF 1378 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO15 0x10 1379 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO16 0x11 1380 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO17 0x12 1381 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO18 0x13 1382 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO19 0x14 1383 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO20 0x15 1384 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO21 0x16 1385 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO22 0x17 1386 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO23 0x18 1387 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO24 0x19 1388 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO25 0x1A 1389 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO26 0x1B 1390 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO27 0x1C 1391 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO28 0x1D 1392 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO29 0x1E 1393 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO30 0x1F 1394 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO31 0x20 1395 /* Define the GPIO mux settings to switch i2c mux to this port */ 1396 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_MASK 0x00000F00 1397 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_OFFSET 8 1398 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK 0x0000F000 1399 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_OFFSET 12 1400 u32 device_ids; /* 0x44 */ 1401 #define NVM_CFG1_PORT_ETH_DID_SUFFIX_MASK 0x000000FF 1402 #define NVM_CFG1_PORT_ETH_DID_SUFFIX_OFFSET 0 1403 #define NVM_CFG1_PORT_FCOE_DID_SUFFIX_MASK 0x0000FF00 1404 #define NVM_CFG1_PORT_FCOE_DID_SUFFIX_OFFSET 8 1405 #define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_MASK 0x00FF0000 1406 #define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_OFFSET 16 1407 #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_MASK 0xFF000000 1408 #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_OFFSET 24 1409 u32 board_cfg; /* 0x48 */ 1410 /* This field defines the board technology 1411 (backpane,transceiver,external PHY) */ 1412 #define NVM_CFG1_PORT_PORT_TYPE_MASK 0x000000FF 1413 #define NVM_CFG1_PORT_PORT_TYPE_OFFSET 0 1414 #define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED 0x0 1415 #define NVM_CFG1_PORT_PORT_TYPE_MODULE 0x1 1416 #define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE 0x2 1417 #define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY 0x3 1418 #define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE 0x4 1419 /* This field defines the GPIO mapped to tx_disable signal in SFP */ 1420 #define NVM_CFG1_PORT_TX_DISABLE_MASK 0x0000FF00 1421 #define NVM_CFG1_PORT_TX_DISABLE_OFFSET 8 1422 #define NVM_CFG1_PORT_TX_DISABLE_NA 0x0 1423 #define NVM_CFG1_PORT_TX_DISABLE_GPIO0 0x1 1424 #define NVM_CFG1_PORT_TX_DISABLE_GPIO1 0x2 1425 #define NVM_CFG1_PORT_TX_DISABLE_GPIO2 0x3 1426 #define NVM_CFG1_PORT_TX_DISABLE_GPIO3 0x4 1427 #define NVM_CFG1_PORT_TX_DISABLE_GPIO4 0x5 1428 #define NVM_CFG1_PORT_TX_DISABLE_GPIO5 0x6 1429 #define NVM_CFG1_PORT_TX_DISABLE_GPIO6 0x7 1430 #define NVM_CFG1_PORT_TX_DISABLE_GPIO7 0x8 1431 #define NVM_CFG1_PORT_TX_DISABLE_GPIO8 0x9 1432 #define NVM_CFG1_PORT_TX_DISABLE_GPIO9 0xA 1433 #define NVM_CFG1_PORT_TX_DISABLE_GPIO10 0xB 1434 #define NVM_CFG1_PORT_TX_DISABLE_GPIO11 0xC 1435 #define NVM_CFG1_PORT_TX_DISABLE_GPIO12 0xD 1436 #define NVM_CFG1_PORT_TX_DISABLE_GPIO13 0xE 1437 #define NVM_CFG1_PORT_TX_DISABLE_GPIO14 0xF 1438 #define NVM_CFG1_PORT_TX_DISABLE_GPIO15 0x10 1439 #define NVM_CFG1_PORT_TX_DISABLE_GPIO16 0x11 1440 #define NVM_CFG1_PORT_TX_DISABLE_GPIO17 0x12 1441 #define NVM_CFG1_PORT_TX_DISABLE_GPIO18 0x13 1442 #define NVM_CFG1_PORT_TX_DISABLE_GPIO19 0x14 1443 #define NVM_CFG1_PORT_TX_DISABLE_GPIO20 0x15 1444 #define NVM_CFG1_PORT_TX_DISABLE_GPIO21 0x16 1445 #define NVM_CFG1_PORT_TX_DISABLE_GPIO22 0x17 1446 #define NVM_CFG1_PORT_TX_DISABLE_GPIO23 0x18 1447 #define NVM_CFG1_PORT_TX_DISABLE_GPIO24 0x19 1448 #define NVM_CFG1_PORT_TX_DISABLE_GPIO25 0x1A 1449 #define NVM_CFG1_PORT_TX_DISABLE_GPIO26 0x1B 1450 #define NVM_CFG1_PORT_TX_DISABLE_GPIO27 0x1C 1451 #define NVM_CFG1_PORT_TX_DISABLE_GPIO28 0x1D 1452 #define NVM_CFG1_PORT_TX_DISABLE_GPIO29 0x1E 1453 #define NVM_CFG1_PORT_TX_DISABLE_GPIO30 0x1F 1454 #define NVM_CFG1_PORT_TX_DISABLE_GPIO31 0x20 1455 u32 mnm_10g_cap; /* 0x4C */ 1456 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1457 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1458 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1459 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1460 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1461 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1462 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1463 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1464 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1465 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1466 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1467 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1468 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1469 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1470 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1471 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1472 u32 mnm_10g_ctrl; /* 0x50 */ 1473 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_MASK 0x0000000F 1474 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_OFFSET 0 1475 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_AUTONEG 0x0 1476 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_1G 0x1 1477 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_10G 0x2 1478 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_25G 0x4 1479 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_40G 0x5 1480 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_50G 0x6 1481 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_BB_100G 0x7 1482 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_MASK 0x000000F0 1483 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_OFFSET 4 1484 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_AUTONEG 0x0 1485 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_1G 0x1 1486 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_10G 0x2 1487 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_25G 0x4 1488 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_40G 0x5 1489 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_50G 0x6 1490 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_BB_100G 0x7 1491 /* This field defines the board technology 1492 (backpane,transceiver,external PHY) */ 1493 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MASK 0x0000FF00 1494 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_OFFSET 8 1495 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_UNDEFINED 0x0 1496 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE 0x1 1497 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_BACKPLANE 0x2 1498 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_EXT_PHY 0x3 1499 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE_SLAVE 0x4 1500 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1501 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_OFFSET 16 1502 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_BYPASS 0x0 1503 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR 0x2 1504 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR2 0x3 1505 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR4 0x4 1506 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XFI 0x8 1507 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SFI 0x9 1508 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_1000X 0xB 1509 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SGMII 0xC 1510 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLAUI 0x11 1511 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLPPI 0x12 1512 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CAUI 0x21 1513 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CPPI 0x22 1514 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_25GAUI 0x31 1515 #define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_MASK 0xFF000000 1516 #define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_OFFSET 24 1517 u32 mnm_10g_misc; /* 0x54 */ 1518 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_MASK 0x00000007 1519 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_OFFSET 0 1520 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_NONE 0x0 1521 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_FIRECODE 0x1 1522 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_RS 0x2 1523 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_AUTO 0x7 1524 u32 mnm_25g_cap; /* 0x58 */ 1525 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1526 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1527 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1528 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1529 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1530 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1531 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1532 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1533 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1534 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1535 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1536 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1537 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1538 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1539 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1540 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1541 u32 mnm_25g_ctrl; /* 0x5C */ 1542 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_MASK 0x0000000F 1543 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_OFFSET 0 1544 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_AUTONEG 0x0 1545 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_1G 0x1 1546 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_10G 0x2 1547 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_25G 0x4 1548 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_40G 0x5 1549 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_50G 0x6 1550 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_BB_100G 0x7 1551 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_MASK 0x000000F0 1552 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_OFFSET 4 1553 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_AUTONEG 0x0 1554 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_1G 0x1 1555 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_10G 0x2 1556 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_25G 0x4 1557 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_40G 0x5 1558 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_50G 0x6 1559 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_BB_100G 0x7 1560 /* This field defines the board technology 1561 (backpane,transceiver,external PHY) */ 1562 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MASK 0x0000FF00 1563 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_OFFSET 8 1564 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_UNDEFINED 0x0 1565 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE 0x1 1566 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_BACKPLANE 0x2 1567 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_EXT_PHY 0x3 1568 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE_SLAVE 0x4 1569 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1570 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_OFFSET 16 1571 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_BYPASS 0x0 1572 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR 0x2 1573 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR2 0x3 1574 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR4 0x4 1575 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XFI 0x8 1576 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SFI 0x9 1577 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_1000X 0xB 1578 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SGMII 0xC 1579 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLAUI 0x11 1580 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLPPI 0x12 1581 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CAUI 0x21 1582 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CPPI 0x22 1583 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_25GAUI 0x31 1584 #define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_MASK 0xFF000000 1585 #define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_OFFSET 24 1586 u32 mnm_25g_misc; /* 0x60 */ 1587 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_MASK 0x00000007 1588 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_OFFSET 0 1589 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_NONE 0x0 1590 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_FIRECODE 0x1 1591 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_RS 0x2 1592 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_AUTO 0x7 1593 u32 mnm_40g_cap; /* 0x64 */ 1594 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1595 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1596 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1597 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1598 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1599 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1600 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1601 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1602 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1603 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1604 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1605 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1606 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1607 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1608 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1609 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1610 u32 mnm_40g_ctrl; /* 0x68 */ 1611 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_MASK 0x0000000F 1612 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_OFFSET 0 1613 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_AUTONEG 0x0 1614 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_1G 0x1 1615 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_10G 0x2 1616 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_25G 0x4 1617 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_40G 0x5 1618 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_50G 0x6 1619 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_BB_100G 0x7 1620 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_MASK 0x000000F0 1621 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_OFFSET 4 1622 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_AUTONEG 0x0 1623 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_1G 0x1 1624 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_10G 0x2 1625 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_25G 0x4 1626 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_40G 0x5 1627 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_50G 0x6 1628 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_BB_100G 0x7 1629 /* This field defines the board technology 1630 (backpane,transceiver,external PHY) */ 1631 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MASK 0x0000FF00 1632 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_OFFSET 8 1633 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_UNDEFINED 0x0 1634 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE 0x1 1635 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_BACKPLANE 0x2 1636 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_EXT_PHY 0x3 1637 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE_SLAVE 0x4 1638 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1639 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_OFFSET 16 1640 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_BYPASS 0x0 1641 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR 0x2 1642 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR2 0x3 1643 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR4 0x4 1644 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XFI 0x8 1645 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SFI 0x9 1646 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_1000X 0xB 1647 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SGMII 0xC 1648 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLAUI 0x11 1649 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLPPI 0x12 1650 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CAUI 0x21 1651 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CPPI 0x22 1652 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_25GAUI 0x31 1653 #define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_MASK 0xFF000000 1654 #define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_OFFSET 24 1655 u32 mnm_40g_misc; /* 0x6C */ 1656 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_MASK 0x00000007 1657 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_OFFSET 0 1658 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_NONE 0x0 1659 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_FIRECODE 0x1 1660 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_RS 0x2 1661 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_AUTO 0x7 1662 u32 mnm_50g_cap; /* 0x70 */ 1663 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1664 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1665 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1666 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1667 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1668 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1669 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1670 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1671 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1672 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1673 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1674 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1675 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1676 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1677 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1678 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1679 u32 mnm_50g_ctrl; /* 0x74 */ 1680 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_MASK 0x0000000F 1681 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_OFFSET 0 1682 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_AUTONEG 0x0 1683 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_1G 0x1 1684 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_10G 0x2 1685 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_25G 0x4 1686 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_40G 0x5 1687 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_50G 0x6 1688 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_BB_100G 0x7 1689 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_MASK 0x000000F0 1690 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_OFFSET 4 1691 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_AUTONEG 0x0 1692 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_1G 0x1 1693 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_10G 0x2 1694 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_25G 0x4 1695 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_40G 0x5 1696 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_50G 0x6 1697 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_BB_100G 0x7 1698 /* This field defines the board technology 1699 (backpane,transceiver,external PHY) */ 1700 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MASK 0x0000FF00 1701 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_OFFSET 8 1702 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_UNDEFINED 0x0 1703 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE 0x1 1704 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_BACKPLANE 0x2 1705 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_EXT_PHY 0x3 1706 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE_SLAVE 0x4 1707 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1708 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_OFFSET 16 1709 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_BYPASS 0x0 1710 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR 0x2 1711 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR2 0x3 1712 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR4 0x4 1713 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XFI 0x8 1714 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SFI 0x9 1715 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_1000X 0xB 1716 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SGMII 0xC 1717 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLAUI 0x11 1718 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLPPI 0x12 1719 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CAUI 0x21 1720 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CPPI 0x22 1721 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_25GAUI 0x31 1722 #define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_MASK 0xFF000000 1723 #define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_OFFSET 24 1724 u32 mnm_50g_misc; /* 0x78 */ 1725 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_MASK 0x00000007 1726 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_OFFSET 0 1727 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_NONE 0x0 1728 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_FIRECODE 0x1 1729 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_RS 0x2 1730 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_AUTO 0x7 1731 u32 mnm_100g_cap; /* 0x7C */ 1732 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_MASK 0x0000FFFF 1733 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_OFFSET 0 1734 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_1G 0x1 1735 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_10G 0x2 1736 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_25G 0x8 1737 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_40G 0x10 1738 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_50G 0x20 1739 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_BB_100G 0x40 1740 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_MASK 0xFFFF0000 1741 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_OFFSET 16 1742 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_1G 0x1 1743 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_10G 0x2 1744 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_25G 0x8 1745 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_40G 0x10 1746 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_50G 0x20 1747 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_BB_100G 0x40 1748 u32 mnm_100g_ctrl; /* 0x80 */ 1749 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_MASK 0x0000000F 1750 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_OFFSET 0 1751 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_AUTONEG 0x0 1752 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_1G 0x1 1753 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_10G 0x2 1754 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_25G 0x4 1755 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_40G 0x5 1756 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_50G 0x6 1757 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_BB_100G 0x7 1758 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_MASK 0x000000F0 1759 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_OFFSET 4 1760 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_AUTONEG 0x0 1761 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_1G 0x1 1762 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_10G 0x2 1763 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_25G 0x4 1764 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_40G 0x5 1765 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_50G 0x6 1766 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_BB_100G 0x7 1767 /* This field defines the board technology 1768 (backpane,transceiver,external PHY) */ 1769 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MASK 0x0000FF00 1770 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_OFFSET 8 1771 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_UNDEFINED 0x0 1772 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE 0x1 1773 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_BACKPLANE 0x2 1774 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_EXT_PHY 0x3 1775 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE_SLAVE 0x4 1776 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1777 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_OFFSET 16 1778 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_BYPASS 0x0 1779 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR 0x2 1780 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR2 0x3 1781 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR4 0x4 1782 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XFI 0x8 1783 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SFI 0x9 1784 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_1000X 0xB 1785 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SGMII 0xC 1786 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLAUI 0x11 1787 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLPPI 0x12 1788 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CAUI 0x21 1789 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CPPI 0x22 1790 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_25GAUI 0x31 1791 #define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_MASK 0xFF000000 1792 #define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_OFFSET 24 1793 u32 mnm_100g_misc; /* 0x84 */ 1794 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_MASK 0x00000007 1795 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_OFFSET 0 1796 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_NONE 0x0 1797 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_FIRECODE 0x1 1798 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_RS 0x2 1799 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_AUTO 0x7 1800 u32 temperature; /* 0x88 */ 1801 #define NVM_CFG1_PORT_PHY_MODULE_DEAD_TEMP_TH_MASK 0x000000FF 1802 #define NVM_CFG1_PORT_PHY_MODULE_DEAD_TEMP_TH_OFFSET 0 1803 #define NVM_CFG1_PORT_PHY_MODULE_ALOM_FAN_ON_TEMP_TH_MASK 0x0000FF00 1804 #define NVM_CFG1_PORT_PHY_MODULE_ALOM_FAN_ON_TEMP_TH_OFFSET 8 1805 u32 reserved[115]; /* 0x8C */ 1806 }; 1807 1808 struct nvm_cfg1_func 1809 { 1810 struct nvm_cfg_mac_address mac_address; /* 0x0 */ 1811 u32 rsrv1; /* 0x8 */ 1812 #define NVM_CFG1_FUNC_RESERVED1_MASK 0x0000FFFF 1813 #define NVM_CFG1_FUNC_RESERVED1_OFFSET 0 1814 #define NVM_CFG1_FUNC_RESERVED2_MASK 0xFFFF0000 1815 #define NVM_CFG1_FUNC_RESERVED2_OFFSET 16 1816 u32 rsrv2; /* 0xC */ 1817 #define NVM_CFG1_FUNC_RESERVED3_MASK 0x0000FFFF 1818 #define NVM_CFG1_FUNC_RESERVED3_OFFSET 0 1819 #define NVM_CFG1_FUNC_RESERVED4_MASK 0xFFFF0000 1820 #define NVM_CFG1_FUNC_RESERVED4_OFFSET 16 1821 u32 device_id; /* 0x10 */ 1822 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_MASK 0x0000FFFF 1823 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_OFFSET 0 1824 #define NVM_CFG1_FUNC_RESERVED77_MASK 0xFFFF0000 1825 #define NVM_CFG1_FUNC_RESERVED77_OFFSET 16 1826 u32 cmn_cfg; /* 0x14 */ 1827 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_MASK 0x00000007 1828 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_OFFSET 0 1829 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_PXE 0x0 1830 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_ISCSI_BOOT 0x3 1831 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_FCOE_BOOT 0x4 1832 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_NONE 0x7 1833 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK 0x0007FFF8 1834 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_OFFSET 3 1835 #define NVM_CFG1_FUNC_PERSONALITY_MASK 0x00780000 1836 #define NVM_CFG1_FUNC_PERSONALITY_OFFSET 19 1837 #define NVM_CFG1_FUNC_PERSONALITY_ETHERNET 0x0 1838 #define NVM_CFG1_FUNC_PERSONALITY_ISCSI 0x1 1839 #define NVM_CFG1_FUNC_PERSONALITY_FCOE 0x2 1840 #define NVM_CFG1_FUNC_PERSONALITY_ROCE 0x3 1841 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK 0x7F800000 1842 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET 23 1843 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK 0x80000000 1844 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_OFFSET 31 1845 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_DISABLED 0x0 1846 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_ENABLED 0x1 1847 u32 pci_cfg; /* 0x18 */ 1848 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK 0x0000007F 1849 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET 0 1850 /* AH VF BAR2 size */ 1851 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_MASK 0x00003F80 1852 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_OFFSET 7 1853 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_DISABLED 0x0 1854 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4K 0x1 1855 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8K 0x2 1856 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16K 0x3 1857 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32K 0x4 1858 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64K 0x5 1859 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_128K 0x6 1860 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_256K 0x7 1861 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_512K 0x8 1862 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_1M 0x9 1863 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_2M 0xA 1864 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4M 0xB 1865 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8M 0xC 1866 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16M 0xD 1867 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32M 0xE 1868 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64M 0xF 1869 #define NVM_CFG1_FUNC_BAR1_SIZE_MASK 0x0003C000 1870 #define NVM_CFG1_FUNC_BAR1_SIZE_OFFSET 14 1871 #define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED 0x0 1872 #define NVM_CFG1_FUNC_BAR1_SIZE_64K 0x1 1873 #define NVM_CFG1_FUNC_BAR1_SIZE_128K 0x2 1874 #define NVM_CFG1_FUNC_BAR1_SIZE_256K 0x3 1875 #define NVM_CFG1_FUNC_BAR1_SIZE_512K 0x4 1876 #define NVM_CFG1_FUNC_BAR1_SIZE_1M 0x5 1877 #define NVM_CFG1_FUNC_BAR1_SIZE_2M 0x6 1878 #define NVM_CFG1_FUNC_BAR1_SIZE_4M 0x7 1879 #define NVM_CFG1_FUNC_BAR1_SIZE_8M 0x8 1880 #define NVM_CFG1_FUNC_BAR1_SIZE_16M 0x9 1881 #define NVM_CFG1_FUNC_BAR1_SIZE_32M 0xA 1882 #define NVM_CFG1_FUNC_BAR1_SIZE_64M 0xB 1883 #define NVM_CFG1_FUNC_BAR1_SIZE_128M 0xC 1884 #define NVM_CFG1_FUNC_BAR1_SIZE_256M 0xD 1885 #define NVM_CFG1_FUNC_BAR1_SIZE_512M 0xE 1886 #define NVM_CFG1_FUNC_BAR1_SIZE_1G 0xF 1887 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK 0x03FC0000 1888 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_OFFSET 18 1889 /* Hide function in npar mode */ 1890 #define NVM_CFG1_FUNC_FUNCTION_HIDE_MASK 0x04000000 1891 #define NVM_CFG1_FUNC_FUNCTION_HIDE_OFFSET 26 1892 #define NVM_CFG1_FUNC_FUNCTION_HIDE_DISABLED 0x0 1893 #define NVM_CFG1_FUNC_FUNCTION_HIDE_ENABLED 0x1 1894 /* AH BAR2 size (per function) */ 1895 #define NVM_CFG1_FUNC_BAR2_SIZE_MASK 0x78000000 1896 #define NVM_CFG1_FUNC_BAR2_SIZE_OFFSET 27 1897 #define NVM_CFG1_FUNC_BAR2_SIZE_DISABLED 0x0 1898 #define NVM_CFG1_FUNC_BAR2_SIZE_1M 0x5 1899 #define NVM_CFG1_FUNC_BAR2_SIZE_2M 0x6 1900 #define NVM_CFG1_FUNC_BAR2_SIZE_4M 0x7 1901 #define NVM_CFG1_FUNC_BAR2_SIZE_8M 0x8 1902 #define NVM_CFG1_FUNC_BAR2_SIZE_16M 0x9 1903 #define NVM_CFG1_FUNC_BAR2_SIZE_32M 0xA 1904 #define NVM_CFG1_FUNC_BAR2_SIZE_64M 0xB 1905 #define NVM_CFG1_FUNC_BAR2_SIZE_128M 0xC 1906 #define NVM_CFG1_FUNC_BAR2_SIZE_256M 0xD 1907 #define NVM_CFG1_FUNC_BAR2_SIZE_512M 0xE 1908 #define NVM_CFG1_FUNC_BAR2_SIZE_1G 0xF 1909 struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr; /* 0x1C */ 1910 struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr; /* 0x24 */ 1911 u32 preboot_generic_cfg; /* 0x2C */ 1912 #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_MASK 0x0000FFFF 1913 #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_OFFSET 0 1914 #define NVM_CFG1_FUNC_PREBOOT_VLAN_MASK 0x00010000 1915 #define NVM_CFG1_FUNC_PREBOOT_VLAN_OFFSET 16 1916 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_MASK 0x001E0000 1917 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_OFFSET 17 1918 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_ETHERNET 0x1 1919 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_FCOE 0x2 1920 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_ISCSI 0x4 1921 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_RDMA 0x8 1922 u32 features; /* 0x30 */ 1923 /* RDMA protocol enablement */ 1924 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_MASK 0x00000003 1925 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_OFFSET 0 1926 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_NONE 0x0 1927 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_ROCE 0x1 1928 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_IWARP 0x2 1929 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_BOTH 0x3 1930 u32 reserved[7]; /* 0x34 */ 1931 }; 1932 1933 struct nvm_cfg1 1934 { 1935 struct nvm_cfg1_glob glob; /* 0x0 */ 1936 struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX]; /* 0x228 */ 1937 struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX]; /* 0x230 */ 1938 struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX]; /* 0xB90 */ 1939 }; 1940 1941 /****************************************** 1942 * nvm_cfg structs 1943 ******************************************/ 1944 enum nvm_cfg_sections 1945 { 1946 NVM_CFG_SECTION_NVM_CFG1, 1947 NVM_CFG_SECTION_MAX 1948 }; 1949 1950 struct nvm_cfg 1951 { 1952 u32 num_sections; 1953 u32 sections_offset[NVM_CFG_SECTION_MAX]; 1954 struct nvm_cfg1 cfg1; 1955 }; 1956 1957 #endif /* NVM_CFG_H */ 1958